Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp.

963966
Built-in Self-Test Implementation for an Analog-to-Digital Converter
Kwisung Yoo, Minho Kwon, Geumhwan Bahng, Sangyun Hwang, Hoon Lee,
Jungyoon Lee, Daesik Seo, Jaeseok Kim, Sungho Kang and Gunhee Han

Department of Electrical and Electronic Engineering, Yonsei University, Seoul 129-742

(Received 23 April 2002)
As integrated circuit fabrication techniques advance, a complex system can be integrated on
a single chip: namely, a system-on-a-chip (SOC). A SOC consists of many intellectual property
(IP) building blocks, including analog-to-digital converters (ADCs) and digital-to-analog converters
(DACs) which should provide certain built-in self-test (BIST) scheme to minimize the testing cost.
Due to the analog nature of ADCs and DACs, digital BIST schemes are not applicable. This paper
proposes a simple ADC BIST scheme based on a ramp test. The proposed BIST scheme is veried
by simulation with a 6-bit pipelined ADC. Simulation results show that the proposed ADC BIST
scheme can detect not only catastrophic faults but also some parametric faults. The total gate
count of the proposed BIST circuit is about 150.
PACS numbers: 85.40.Qx
Keywords: BIST, ADC BIST
I. INTRODUCTION
As IC fabrication techniques have been improved, a
complex system can be implemented on a chip. The
test cost of a SOC often overwhelms the design and
the fabrication cost due to the complexity of the imple-
mented system [1,2]. Because the price of the automatic
test equipment drastically increases as the system speed
and complexity increases, various Built-In-Self-Testing
(BIST) techniques have been introduced to reduce the
test cost [38]. Most of the reported BIST schemes are
limited to a digital system and a memory. Few analog
BIST schemes have been reported [912] and this eld is
still in its primitive stage. The absence of compact cir-
cuits to measure analog value and the fuzzyness of the
criterion make the analog BIST challenged.
ADCs and DACs are commonly included in a SOC.
ADC/DAC BIST is becoming a bottleneck of the SOC
testing, though. Most of the reported ADC/DAC
schemes require large overhead while the eciency is low
[1316]. Common ADC testing involves measuring eec-
tive resolution and histogram with sinusoidal test input
signal.
This dynamic testing requires Digital Signal Proces-
sor (DSP) for calculating Fast Fourier Transform (FFT)
or accumulators and memories which require large over-
head. Measurement of the Integral Nonlinearity (INL)
error and the Dierential Nonlinearity (DNL) error with
ramp test signal is the other ADC testing method which
is suitable for BIST due to the small overhead.

E-mail: [email protected]; Fax: +82-2-312-4584

Although the ADC is an analog block, the output of
ADC is digital. This property provides possibility to
implement ADC BIST scheme with compact digital cir-
cuit. This paper proposes a simple ADC BIST scheme.
Section II proposes the ADC BIST scheme and its im-
plementation, section III provides verication results of
the proposed scheme through simulation.
II. ADC BIST SCHEME AND
IMPLEMENTATION
The proposed BIST system is depicted in Figure 1.
As the analog test signal is applied to ADCs input, the
ADC generates digital code corresponding to the input
signal. Only with digital code, the error detector decides
whether the ADC has any fault or not.
The ramp signal generator should have higher linearity
Fig. 1. BIST block diagram.
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-964- Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002
Fig. 2. Error denition.
than the ADC under test [17]. A high linearity ramp sig-
nal generator using Switched-Capacitor (SC) circuit was
reported in [18]. The ramp test signal can be supplied
by external equipment and shared by many ADCs under
testing in parallel. The ramp test signal varies within
dynamic range of ADC for proper operation and should
be increased by 1 LSB per clock. Since the analog input
is increased by 1 LSB per clock, the ADC output should
be increased by 1 LSB per sample. If there exists any
fault then the ADC output may be not increased by 1
LSB per sample.
Four types of errors are dened as in Table 1 and de-
picted in Figure 2 to detect faulty circuits. Here x(n) is
ADC output code for n
th
sample.
If the magnitude of two consecutive sample dierence,
x(n) x(n 1) is greater than 1 LSB then it means
that the ADC output increases more than 1 LSB while
the input signal is increased by 1 LSB. The ADC can be
considered to be faulty, namely missing code error. If the
sign bit of the dierence is negative, then it means that
the ADC output decreases even while the input signal
is monotonically increased. This type of fault is dened
as monotonocity error. If the ADC generates sample of
same value more than 3 consecutive samples, x(n1) =
x(n) = x(n + 1), it means that ADC output is kept
constant even while the input signal is increased by 3
LSBs. This fault corresponds to the DNL error. Ideally,
if two consecutive samples output are identical then ADC
under test can be considered as faulty circuit. However,
due to some uncertainty in analog circuits, the boundary
of the DNL error should be relaxed at least to 3 samples.
The INL/gain error is dened by the dierence be-
tween the ADCs output and the ideal output that is
obtained by counting the clocks in the ramp signal gen-
erator. The INL/gain error can be caused either by the
Table 1. Error denition.
Denition
Missing code error x(n) x(n 1) 2LSB
Monotonocity error x(n) x(n 1) < 0
DNL error x(n 1) = x(n) = x(n + 1)
INL/gain error ideal(n) x(n) > boundary
nonlinearity or by the gain error of the ADC under test.
Figure 3 shows the block diagram of the proposed er-
ror detector. Assuming that the counter/register loads
the ADC output which means previous sample at phase

4
, the dierence between the ADC output and the
counter/register output is calculated at phase
1
. If the
counter/register output and ADC output are identical
then ip-op 3 is set to 0 at phase
3
. If next sample is
identical with previous two samples then the ip-op 4
is set to 1 at phase
2
. This means that the INL error
occurs. The ip-op 3 should be initially set to 1 for
proper operation.
If the subtractor output except LSB has any 1, it
means that the dierence of two consecutive samples is
more than 1 LSB. Therefore, ORing of all output bits
except LSB detects the missing code error.
If there is underow in the subtractor output, it means
that the present sample is lesser than the previous sam-
ple. Therefore, monotonocity error can be detected with
sign bit of subtractor output.
The counter/register is initially reset and counts the
clock in ramp signal generator for the INL/gain er-
ror detection. This means that the counter repre-
sents ideal ADC output in the INL/gain error detec-
tion mode. If the dierence between the ADC output
and the counter/register exceeds certain limit (2
m
) in
the INL/gain error detection mode, then it means that
there exists the INL error or the gain error. This bound-
ary is checked by ORing of upper (N m) bits in the
subtractor output.
III. SIMULATION RESULT
Fig. 3. Error detector.
Built-in Self-Test Implementation for an Analog-to-Digital Converter Kwisung Yoo et al. -965-
Table 2. Result of simulation.
Type of error observed Result of BIST
Cause of fault Missing Monoto- Missing Monoto-
code nocity
DNL
code nocity
DNL
TC1 Normal circuit
TC2 Oset
TC3 Oset
TC4 Gain
TC5 Gain & oset
TC6 Open
Short
TC7
(internal node)

TC8 Short (VSS)
TC9 Short (VDD)
TC10 Short (VDD)
Fig. 4. Simulation example of TCs.
The proposed scheme is veried by the simulation with
6 bit pipelined ADC. Various test circuits that have ar-
bitrary faults are simulated. These test circuits include
both catastrophic faults such as open or short and para-
metric faults such as an amplier gain error and a com-
parator oset error. Figure 4 shows the examples of sim-
ulation results. The topmost gure shows the input and
the output of the ADC under test. The output of the
ADC is converted to analog value with an ideal DAC for
comparison purpose. The middle gure shows the ADC
quantization error. The bottom gure shows the result
of the error detector that is observed at the input node
of each ip-op. Any pulse in bottom gure represents
corresponding errors.
The test ADC is designed to have dynamic range from
1 to 1, and oset binary code output to simplify the
simulation. That is, 1 LSB corresponds to 31.25 mV.
Thus, if absolute value of ADCs quantization error is
greater than this value, then the ADC is considered as a
faulty circuit.
Table 2 summarizes examples of simulation results.
Besides of the example circuits shown in Table 2, var-
ious test circuits are simulated and the proposed BIST
successfully detected faulty circuits that can be identied
by a person. Though, certain circuits that have minor
faults pass the BIST and inspection by a person as well.
IV. CONCLUSION
This paper proposes a compact ADC BIST scheme
whose gate count is only about 150. Extensive simu-
lation results proved that the proposed BIST scheme
detects most of faulty ADCs that can be identied by
person. Due to noise or any uncertainty in real circuits,
the test should be performed several times and nal deci-
sion should be made by BIST controller. Several circuits
with minor faults pass the BIST and human inspection.
These faults can be detected by more complex BIST the
with price of overhead.
ACKNOWLEDGMENTS
This work was supported by a Korea Research Foun-
dation grant (KRF 2000-042-E00029). CAD tools were
supported by IC Design Education center.
-966- Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002
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