ISSN (Online) : 2319 - 8753

ISSN (Print) : 2347 - 6710

International Journal of Innovative Research in Science, Engineering and Technology
Volume 3, Speci al I ssue 3, March 2014
2014 IEEE International Conference on Innovations in Engineering and Technology (ICIET14)
On 21
st
& 22
nd
March Organized by
K.L.N. College of Engineering, Madurai, Tamil Nadu, India
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1435

Area Efficient Digital Comparator
Design Using Pseudo NMOS and Pass
Transistor Logic

Udayakumar M
1
, Kumar P
2

Department of Electronics and Communication Engineering, K. S. Rangasamy College of
technology, Tiruchengode, Namakkal, Tamilnadu, India.
Department of Electronics and Communication Engineering, K. S. Rangasamy College of
technology, Tiruchengode, Namakkal, Tamilnadu, India.
ABSTRACT- Comparators are one of the most key
design elements for a large number of applications. This
paper presents wide-range, area efficient and high-speed
comparator using pseudo nMOS and pass transistor logic.
The conventional CMOS design requires more number of
transistors than pseudo nMOS and pass transistor logic.
Hence the transistor count of a design can be reduced by
using pseudo nMOS and pass transistor logic instead of
conventional CMOS. The working operation of the
comparator based on a novel scalable parallel prefix
structure. The comparison starts from most significant bits
(MSB) of each sequence, if the MSB bit of two different
sequences is equal that time only the comparison
operation moves towards the least significant bit (LSB).
This method helps to minimize the dynamic power
dissipation by eliminating unwanted transitions in a
parallel prefix structure. Then the N-bit comparison result
will be generated after [log4N+ log16N+ 4] CMOS
gate delays. This comparator is designed by
interconnecting CMOS gates with a maximum number of
fan-in and fan-out of five and four, respectively, not
depending on comparator bitwidth. This comparator plays
a role for high speed and power efficiency for large
bitwidth.

KEY WORDS- Bitwise competition logic, Pass
transistor logic, pseudo nMOS logic.
I. INTRODUCTION
OMPARATORS are one of the most important
design elements for a large number of applications
such as scientific computation, test circuit applications [1]
and general purpose processor components [2], [3]. The
comparator logic design is straightforward; the wide use
of comparators in high-performance systems having a
great prominence on performance and power consumption
optimizations.
The specialized arithmetic units are used for large
comparisons, along with custom logic circuits. The
comparator designs also use subtractors in the form of flat
adder components, but this type of designs are commonly
slow and area-demand, even when implemented using fast
adders [4]. The comparator designs using a hierarchical
prefix tree structure composed of 2-b comparators
minimize comparison delays and improve scalability [9].
While comparing wide operands, the delay and area of
these designs are high.
Pipelining is used to reduce power consumption and
improve the speed and also minimize the switching
transitions with respect to the actual input operands bit
values [7]. One comparator design uses all-N-transistor
circuits for compensating high fan-in with high pipeline
throughput [8].The multiplexer based comparator
architectures have two stages, the operation of the two
stages be followed. The first stage has eight modules for
8-bit comparison, this module results are given as an input
to the priority encoder. The second stage has 8-to-1
multiplexer to select the suitable result from the first stage
[13]. In this architecture, two-phase domino clocking is
used to execute both stages in one clock cycle. Here the
design highly affected to race conditions when operations
present on the rising and falling clock edges, this
operation limits the operating speed and jitter margin.
Some comparator architectures save power by using
novel ripple-based structures. This type of architectures
incorporates wide-range ripple-carry adders [16]. Here the
novel ripple-based structure eliminates unwanted
computations dynamically. Compute-on-demand
comparators compare a pair of binary numbers single bit
at a time, moving from the MSB to the LSB. If the
compared bits are equal it enables the comparison of the
next bit else represents the final comparison decision. All
bits of greater significance are equal then only the next
comparison cell gets activated. Although these designs
C
Area Efficient Digital Comparator Design Using Pseudo nMOS and
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1436

reduce switching, they suffer from long worst case
comparison delays for large worst case operands.
Some comparator architecture does not have any
arithmetic operations. This type of architecture can reduce
the long delays affected by bitwise ripple designs. The
larger number can be found by determining which
operand possesses the 1 bit at LSB after pre-encoding,
before supplying the numbers to bitwise competition logic
(BCL) structure [17]. The BCL structure dismemberment
the operands into 8-bit blocks, after that the result for
each block is input into a multiplexer to find the final
comparison decision. So the BCL-based design has a low
transistor count. So this design has the potential for low
power consumption. In this BCL structure, the pre-
encoder logic modules limit the maximum operating
frequency being achieved. In addition, to enable the BCL
unit some special control logic is needed. It switches
dynamically in a synchronized fashion, thus considerably
increase the power consumption and lowering the
operating frequency.
To reduce the number of transistors required for the
previous designs, this paper influence pass transistor logic
and pseudo nMOS logic cells to architect fast,scalable,
wide-range, power-efficient and area efficient algorithmic
comparators.
II.ARCHITECTURAL OVERVIEWOF THE COMPARATOR
The comparison resolution module in Fig.1 is a novel
MSB-to-LSB parallel-prefix tree structure that performs a
bitwise comparison of two N-bit operands A and B,
denoted as A
N1
, A
N2
, . . ., A
0
and B
N1
, B
N2
, . . ., B
0
,
where the index range from N1 for the MSB to 0 for the
LSB. The comparison resolution module performs the
bitwise comparison operation asynchronously from left to
right, such that the computation of comparison logic is
triggered only if all bits of greater significance are equal.

Fig. 1. Block diagramof proposed comparator architecture, consisting of
a comparison resolution module connected to a decision module [5].
The bitwise comparison results are stored into two N-
bit buses using parallel prefix structure. The two buses are
the left bus and the right bus, each of which store the
partial comparison result as each bit position is evaluated,
such that
ifA
x
>B
x
, then left
x
=1 and right
x
=0.
ifA
x
<B
x
, then left
x
=0 and right
x
=1.
ifA
x
=B
x
, then left
x
=0 and right
x
=0.
In this, to reduce switching activities, if the bitwise
comparison is not equal, the bitwise comparison of all the
bits of lower significance is terminated and all such
positions are set to zero on both buses. Hence, there is
never more than one high bit on either bus.The decision
module uses NOR-NAND networks to output the final
comparison decision based on all of the bits on the left
bus producing the Lbbit and all of the bits on the right bus
producing the Rbbit. If LbRb=00, then A =B, if LbRb=
10 then A > B, if LbRb=01 then A < B, and LbRb=11 is
not possible.
A 4-b comparison of input operands A =1000 and B =
0101 is illustrated in Fig. 2. In the first step, a parallel
prefix tree structure generates the encoded data on the left
bus and right bus for each pair of corresponding bits from
A and B. In this example, A
3
=1 and B
3
=0 encodes as
Lb
3
=1 and Rb
3
= 0. At this point, wherethe bits are
unequal, the comparison terminates and a final
comparison decision can be made based on the first bit
evaluated.

Fig. 2.Example 4-bit comparison.
The parallel prefix structure fixes all bits of lower
significance of left and right bus to 0, regardless of the
remaining bit values in the operands. In the second step,
the OR-networks perform the bus OR-scans, resulting in 0
and 1, respectively, and the final comparison decision is
A> B.
Area Efficient Digital Comparator Design Using Pseudo nMOS and
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1437

The structure is sectioned into five hierarchical
prefixing sets, as shown in Fig. 3, with the associated
symbolic representations in Tables I and II. Here each
group performs a specific function. The output of each
group is given as an input to the next group.At last the
fifth group produces the output on the left bus and the
right bus.
TABLE I
SYMBOLSAND DEFINITIONS [5].
Symbol (Cells) Definition
N Operand bitwidth
A First input operand
B Second input operand
R
b
Right bus result bit
L
b
Left bus result bit
Bitwise AND
Bitwise OR
CMP{} Complement function of set
In this design all cells are operating in parallelwhich
increases the operating speed. This prefixing set structure
bounds the components fan-in and fan-out regardless of
comparator bitwidth and eliminates heavily loaded global
signals with parasitic components, thus improving the
operating speed and reducing power consumption.
TABLE II
LOGIC GATE REPRESENTATIONS OF SYMBOLSUSED IN Fig. 3 [6].

III. DESIGN DETAILSOF THE COMPARATOR
The comparator design is based on using a novel
parallel prefix tree.
The -type cells in group 1 compare the N-bit operands
A and B bit-by-bit. These cells provide a termination flag
T
x
to cells in groups 2 and 4, indicating whether the
computation should terminate. These cells compute
(where 0 x N 1)
:T
x
=A
x
B
x
. (1).
The
2
-type cells in group 2 combine the termination
flags for each of the four -type cells from group 1to limit
the fan-in and fan-out to a maximum of four. If all the
inputs to the
2
-type cells are 0s, then continue the
comparisons for bits of lesser significance else
comparison gets terminated, and then final decision can
be made. For 0 n N/41, there is a total of N/4
2
-type
cells, all functioning in parallel

2
:W
2,m
=CMP( T
I
4n+3
I=4n
). (2).
The
3
-type cells in Group 3are very similar to
2
-type
cells, but ithas more logic levels, different inputs. A
3
-
type cell doesnt provide any comparison functionality.
These cells only limit the fan-in and fan-out irrespective
of operand bitwidth.Group 3 provides functionality
similar to group 2to continue or terminate the bitwise
comparison activity. If the comparison is terminated,
group 3 signals group 4 to set the left bus and right bus
bits to 0 for all bits of least significance.For 0 n N/4
1, there is a total of N/4
3
-type cells per level, with cell
function as

3
:W
3,m
=CMP( W
2,I
n
I=0
). (3).
Group 4 consists of -type cells. The outputs of these
cells control the selection line of -type cells in group 5.
The comparison outcomes from group 1 gives
information about the more significant bits to the -type
cells,which compute (0 x N 1)
:Z
k
= W
3, x/ 4-1Tx
I
i

x-1
=4x/ 4-1
. (4).
In the -type cells the number of inputs increases from
left to right in each partition, finishes with a fan-in of five.
Thus, the -type cells in group 4 determine whether group
5 propagates the bitwise comparison codes. The N -type
cells in group 5 produce the outputs to left and right bit
bus. One input of -type cell is (A
x
, B
x
) and the other is
hardwired to 00. The select control input is based on the
-type cell output from group 4. The 2-bits can be defined
as the left-bit code (A
x
) and the right-bit code (B
x
). All
left-bit codes and all right-bit codes combine to form the
left bus and the right bus, respectively. The output of -
type cells
x
1,0
denotes the greater-than, less-than, or
equal to final comparison decision

f
x
1,0
_
00, for A
x
=B
x
01, for A
x
<B
x
10, for A
x
>B
x
(5).
Essentially, the 2-b code
x
1,0
can be realized by OR-ing
all left bits and all right bits separately, as shown in the
decision module (Figs. 1 and 2), using an OR-gate
network in the form of NOR-NAND gates yielding a
more optimum gate structure
Area Efficient Digital Comparator Design Using Pseudo nMOS and
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1438

I0
1,]
1
= f
x
1
4j+3
x=4j
(6). R0
1,]
0
= f
x
0
4j+3
x=4j
(7).

Fig. 3. Implementation details of the comparison resolution module (groups 1 through 5) and the decision module [5].

The power 1 and 0 in (6) and (7) denote the addition
of the left and right bits, respectively, and the suffix 1
denotes the first level of OR-logic in the decision module
that receives data directly from group 5.
IV. RESULTS AND DISCUSSION
This section analyzes the area (in number of
transistors), operating speed, and power requirements of
our proposed comparator architecture and calculates the
number of logic levels required for an N-bit comparator
based on simple logic gates.
A. Area Calculation
The total number of cells required is derived and use
Table 4.1 to translate the cell counts into transistors for an
N-bit comparator. Based on (1)(7), the number of E
CRM

cells required for the comparison resolution module and
the numbers of E
DM
cells in the decision module is,
respectively
E
CRM
=(N) +(
N
4

2
) +( log16N
N
4

3
) +(N ) +
(N ). (8).
E
DM
=2 N
x
/ 4
Iog4N
x=1
(9).
Table III shows the total number of cells and the required
number of levels per group for various comparator
bitwidths based on (8) and (9). The cell counts in Table III,
along with the number of transistors per cell type (Table
II), allow us to derive the total number of transistors for
various bitwidths (Table IV). The results show an
approximate linear growth in comparator size as a function
of bitwidth.
B. Input-Output Delay
This section analyzes the critical path delay of the
proposed comparator with N-bit inputs. The delay
DELAY
CRM
for the comparison resolution module is









Area Efficient Digital Comparator Design Using Pseudo nMOS and
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1439

TABLE III
TOTAL NUMBER OF CELLS AND CIRCUIT LEVELS IN EACH GROUP FOR VARIOUS COMPARATOR BITWIDTHS.
Size of the
Comparator
Group 1 Group 2 Group 3 Group 4 Group 5
Cells Levels Cells Levels Cells Levels Cells Levels Cells Levels
16-b 16 1 4
2
1 4
3
1 16 1 16 1
32-b 32 1 8
2
1 8
3
1 32 1 32 1
64-b 64 1 16
2
1 16
3
1 64 1 64 1

TABLE IV
TOTAL NUMBER OF TRANSISTORS FOR VARIOUS COMPARATOR BITWIDTHS.




DELAY
CRM
=D
group1
+D
group2
+D
group3
+D
group4
+
D
group5
.(10).
All terms, except the third, on the right-hand side of (10)
entail a single gate delay D
U
, resulting in
DELAY
CRM
=D
U
+D
U
+( log
16
(N) )D
U
+D
U
+D
U

=4D
U
+( log16 (N) ) D
U
(11).
The delay DELAY
DM
for the decision modules NOR-
NAND gate network is
DELAY
DM
=(log
4
(N)) D
U
. (12).
The total comparator delay DELAY
T
from input to output
for an N-bit comparator is
D
T
=4D
U
+( log
16
(N) ) D
U
+( log
4
(N) )D
U
. (13).

Fig. 4.Maximuminput-output delay versus input bitwidth.
The maximum total input-to-output delay versus input
bitwidth for the proposed comparator is shown in Fig. 4.
The graph (Fig.4) shows that the delay is increased
linearly with respect to the comparator bit size. This
comparator offers a 33% speed advantage over the design
in [15] and 59% speed advantage over the design in [13].
V. RESULT COMPARISON
To evaluate the functionality and performance of this
comparator, the complete design is simulated with various
inputs using the T-Spice simulator with 0.15m-TSMC
digital CMOS technology. The worst case delay of this
comparator is calculated by turn on the maximum number
of cells, including all the lower significant cells. Here the
objective is to increase the operating speedand reduce the
transistor counts. Themaximum measured cell delay was

0.0847 ns for the -type cell with a maximum fan-in
offive and a maximum fan-out of one. This comparator is
evaluated with conventional CMOS comparator design,
whose structures represent recently proposed topologies
and circuits targeted for high-speed operation and power
savings. Simulation results for 64-b comparator and
reported results for conventional CMOS comparator
design and proposed comparator design are shown in
Table V. The maximum total input-to-output delay versus
input bitwidth for our comparator is shown in Fig. 4. The
simulation results closely match the analytical model in
Table IV.








0 10 20 30 40 50 60 70
0.4
0.5
0.6
0.7
0.8
0.9
1
Comparator bit size (bits)
I
n
p
u
t
-
o
u
t
p
u
t

d
e
l
a
y

(
n
s
)
Size of the
Comparator
Number of Transistors
Group 1 Group 2 Group 3 Group 4 Group 5 Total
16-b 16 6 4 5 4 5 16 16 16 10 552
32-b 32 6 8 5 4 5 32 16 32 10 1084
64-b 64 6 16 5 4 5 64 16 64 10 2148
Area Efficient Digital Comparator Design Using Pseudo nMOS and
M.R. Thansekhar and N. Balaji (Eds.): ICIET14 1440

TABLE V
RESULTS COMPARISON BETWEEN EXISTING AND PROPOSED DESIGN.
Comparator Type
(Technology)
Transistor Count Maximum Input-
Output Delay
Salehet al. [5]
(150nm)
4000
(64-bit)
0.86ns
Proposed
comparator (150
nm)
2210
(64-bit)
0.89ns
VI. CONCLUSION
This work proposed a high-speed, low-power and area-
efficient comparator using parallel prefix structure
consisting of the comparison resolution module and the
decision module. These modules are designed using
simple logic gateswith a maximum fan-in of 5 and fan-out
of 4, independent of the input bitwidth. The cells used in
this comparator are designed using pass transistor logic
and pseudo nMOS logic. These logic styles reduce the
number of transistors required in the design. Leveraging
the parallel prefix tree structure for the comparator design
is novel in that this design performs the comparison
operation from the MSB to the LSB, using parallel
operation. In this design, all cells are locally
interconnected, which avoids the need for large cell
drivers, thus balancing all cells to a uniform transistor
size. This comparator is designed in Tanner EDA tool
using 180nm digital CMOS technology and simulated
using T-Spice simulation tool.

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