Design of arithmetic circuits using novel high speed

and energy efficient full adder

Patel Konarkkumar Dilipbhai
MTECH- VLSI Design
VIT Uniersit!" Chennai
Chennai" In#ia
konark$%&'&(gmail)*om
Pro+,-)-nita -ngeline
MTECH- VLSI Design
VIT Uniersit!" Chennai
Chennai" In#ia
anitaangeline)a(it)a*)in
Abstract Full adders are important elements in applications
such as ALU operation in DSP architectures and
microprocessors. In this paper, we propose a technique to build
a full adder usin no!el "#$ and "%#$ ates in combination
with e&istin ones. Proposed full adders consistentl' consume
less power and ha!e more speed compared with the earlier full
adder desin and the con!entional ()*transistor +,#S adder.
For comparison we added other full adders desin with hiher
ate count. The simulation results is based on
180nm technology.

Ke!.or#s/*arr! sele*t a##er" noel a##er" po.er #ela!
pro#u*t
I) I0T12DUCTI20
The *onentional +ull a##er usuall! re+erre# stati*
CM2S that uses &3 transistors) The transmission gate4T56
base# #esign has +ull oltage s.ing .ith &7 transistor *ount
but the transistor *ount is still large .hi*h ultimatel! *reates
more po.er #issipation) 8urther re#u*tion in #esign is #one
.ith +ull a##er #esign .hi*h *ontains $% transistors )In this
#esign" .e emplo!e# an inerter to generate the *omplement
o+ 4- 96) This #esign also has +ull s.ing operations) This
#esign .as +urther improe# .ith $:-transistor +ull a##er
#esign) The *ost o+ t.o more a##itional transistors" this
#esign eliminates the inerter +rom *riti*al path) This aoi#s
short *ir*uit po.er *onsumption in lo. po.er operation) The
$7 transistor base# #esign has lo.est output oltage s.ing as
.ell as the po.er #riing *apabilit! o+ this #esign in *as*a#e
stage is er! poor )It take mu*h time to *omplete the
operation)
Mainl! in CM2S *ir*uits three ma;or *omponents in
po.er *onsumption -. D'namic Power this is #ue to
*apa*itan*e *harging an# #is*harging #uring transistor
s.it*hing in the *ir*uit )(. Short +ircuit Power this is #ue to
short *ir*uit *urrent +lo.ing +rom groun# to po.er suppl!
.hen both PM2S net.ork an# 0M2S net.ork are 20 at
same time /. Static Power this is #ue to leakage *urrent) The
most #ominant *omponent I s #!nami* po.er it almost
*onsume o+ 37-3<= o+ total po.er) 0ote that other
*omponents are not negligible espe*iall! short *ir*uit po.er
it takes $7-$<= o+ total po.er) 1e#u*ing an! *omponents
among this .e .ill en# up .ith mu*h lo.er po.er
*onsumption" but .e al.a!s intereste# in in*reasing
+re>uen*!)
The optimi?e# metho# to #esign *arr! sele*t a##er
4CS-6 b! using propose# a##er is presente# here) The #esign
shoul# eliminate an! #egra#ation on the output oltage"
haing less #ela!" *onsume less po.er an# immune to noise
een .ith lo. oltage s.ing) In multipliers" partial pro#u*ts
an# a**umulation is implemente# using a a##ition tree" this is
*alle# the Carr! Sae -##er 4CS-6 tree) Designs +or this
CS- tree uses either *ompressors or +ull a##ers an# .ith
multiple@er #esign)
The optimi?ation o+ gates is essential in #igital *ir*uit
#esign) The gate leel mo#i+i*ation *an improe area an#
po.er e++i*ien*! )same approa*h has been in*orporate# here
in CS-) 1ipple Carr! -##ers 41C-6 has mu*h less
*ompli*ate# *ir*uits *ompare# to other a##ers) Ho.eer in
these Carr! Sele*t -##ers 4CS-6 elementar! the spee# o+
a##ition operation is limite# b! the *arr! .hi*h ripples +rom
the 4LS96 least signi+i*ant bit to the 4MS96 most signi+i*ant
bit) Carr! Sele*t -##er 4CS-6 is one o+ the +astest a##er
among the all other a##ers be*ause it uses multiple@er) So"
*arr! propagate +aster *ompare# to all other a##er)
II) EAISTI05 B21K
Before seeing the proposed full adder
design, some more designs are employed here
for comparison. The frst one, is 28T full adder,
this is a static CMOS logic design .It containing
28 transistors. This design, is as shon in !igure.
This design has full "oltage sing and it has
#u$ered sum and cout. The second approach is
2% transistor #ased on transmission gate. This
design is as shon in fgure. It contains &O'
gate, to multiple(er and one in"erter. The
multiple(er implementation is shon in fgure.
The third implementation is transmission fun full
adder hich contains )* transistors. In this
design the #asic &O' circuit re+uires one of to
,Type te(t- .age $
i/p in complementary forms. So one additional
in"erter is needed hich leads the design
implementation of &O' logic ith * transistor.
This design uses 0 CMOS #ased transmission
gate design this can gi"e full "oltage sing.
4a6 &3 transistors +ull a##er

4b6 $: transistor +ull a##er

III) P12P2SED B21K
Consi#er the logi* +un*tion o+ a +ull a##er that *an be
represente# as"
SumC 4- 96 Cin
SumC 4- 96 Cin
CoutC -)9 D Cin)4- 96
The aboe e>uation *an be re.ritten as"

SumC4- 96 ) Cin D 4- 96 )
CoutC4- 96 ) Cin D 4- 96 ) -
4*6 &7 transistor +ull a##er
So " b! minimi?ing the logi*al e@pression o+ Sum an#
Cout .e *an sa! that i+ .e #esign one A21 gate an#
multiple@er e++e*tiel! an# i+ it *onsumes less po.er an# gie
proper output then .e *an #esign a +ull a##er *ir*uit high
spee# an# energ! e++i*ient #esign) This #esign a#opts inerter
base# bu++ere# A21EA021 #esigns to eliminate the threshol#
oltage loss problem .hi*h enhan*e the #riing *apabilit! o+
the #esign +or *as*a#e# operations) The #esign su**ess+ull!
in*orporate the bu++ering *ir*uit in the #esign o+ +ull a##er" so
ultimatel! the transistor *ount is also minimi?e# .hi*h
+a*ilitates lo.er oltage an# +aster operations" again this lea#
to less energ! *onsumption
Page F &
Fiure0 proposed full adder

The A21 an# A021 gates pla! the ma;or role in arious
*ir*uits espe*iall! *ir*uits use# +or per+orming arithmeti*
operations like +ull a##ers" *ompressors)
The #esign o+ +ull a##er *onsist a lo.er number o+
transistor *ount) -**or#ing to e@pression it re>uire
A21EA021 an# multiple@er +or generating sum an# *arr!)
The #esign *ir*uit is sho.n aboe +igure)



In 1C- 4ripple *arr! a##er6 eer! +ull a##er has to .ait +or
ne@t in*oming *arr! be+ore an outgoing *arr! is generate#
+rom preious stage) 2ne e++i*ient .a! to get aroun# this
linear #epen#en*! is to anti*ipate both this possible alues o+
the *arr! at the input i)e) 7 an# $ an# ealuate this result in
a#an*e) 2n*e the real alue o+ the *arr! is re*ognise# then
the result *an be easil! sele*te# .ith the help o+ simple
multiple@er stage) The *ir*uit implementation o+ the *arr!
sele*t a##er using noel +ull a##er #esign is as sho.n in
+igure)
Fiure 0 carr' select adder 1+SA.
Page F &
VI) SIMUL-TI20 2UTPUT
8irst .e *onsi#er #i++erent stati* *ir*uits then .e
*ompare those .ith propose# a##er here .e assume that the
input oltage has +ull output oltage s.ing 4+rom VDD to
50D6)-ll the #esign is #one .ith *a#en*e simulation tool)
The #esign is *he*ke# .ith $37 nm te*hnolog!) -mong all
this #esign the propose# a##er #esign gies +ull oltage
s.ing at the output sum an# *arr!) Here note the propose#
#esign also eliminates the threshol# loss problems )the #esign
also su**ess+ull! embe#s the bu++ring *ir*uit .ithin #esign)
The #esign *onsumes lo. po.er #issipation *ompare# to
earlier a##ers the *omparison table bet.een #i++erent #esign
.ith propose# a##er is sho.n belo.)
T-9LE $
8or the gien *ir*uit the pro#u*t o+ po.er *onsumption an#
propagation #ela! is generall! *onstant this pro#u*t is po.er
#ela! 4PDP6 pro#u*t )this is one o+ the important >ualit!
matri*es to measure s.it*hing o+ #ei*e) The PDP is simpl!
the energ! *onsume# b! the *ir*uit per number o+ s.it*hing
eent) I#eal *ir*uit is one that is +ast an# *onsumes less
energ!) Table $ sho.s that the propose# #esign *onsume less
po.er *ompare# to all other multi transistor +ull a##er the
po.er #ela! pro#u*t .hi*h is e>uialent to energ! #ela! is
also minimise# in propose# +ull a##er)
T-9LE &
The obseration table & sho.s that the noel CS- takes less
energ! then *ompare# to CS- using *onentional +ull a##er
as this the transistor *ount is minimi?e# in the *ir*uit noel
base# CS-) The noel base# CS- also *onsist minimum
po.er *ompare# to *onentional one)
V) C20CLUSI20
In this paper the result sho.s that propose# +ull a##er gies
better per+orman*e *ompare# to other +ull a##er #esign .ith
+ull output oltage s.ing) -n# the operation is eri+ie# b!
*a#an*e) The #esign is also *he*ke# .ith arithmeti* *ir*uit to
*ompare the *as*a#e per+orman*e o+ the *ir*uit)
VI) 1E81E0CES
G$H Iin-+a Lin" Jin-tsung H.ang" Member" Ieee" Ming-h.a Sheu" Member"
ieee an# Cheng-*he Ho Ieee Transa*tions 2n Cir*uits -n# S!stemsK-
0oel High-spee# -n# Energ! E++i*ient $7-transistor 8ull -##er
DesignL 1egular Papers" Vol) <%" 0o) < Jear o+ publi*ation,Ma! &77M)
G&H 1ai ti.ari " Khemae;" K#esign an# anal!sis o+ lo. po.er $$ transistor
+ull a##erL Jear o+ publi*ation, Iune &7$%
GNH Mano; Kumar" San#ip -r!a" International Iournal 2+ Vlsi Design O
Communi*ation S!stems 4Vlsi*s6 Vol)&" 0o)%" KSingle 9it 8ull -##er
Design Using 3 Transistors Bith 0oel N Transistors Anor 5ateL
Jear 2+ Publi*ation, De*ember &7$$
G%H Sakshi 1a;put$" 5itan;ali" Pri!a Sharma an# 5arima -ssistant
Pro+essor" Department o+ Ele*troni*s an# Communi*ation Engineering"
Mahara;a Sura;mal Institute o+ Te*hnolog! 455SIPU6" 0e. Delhi"
In#ia K#esign o+ lo. po.er an# high spee# 9EC& &%3 e++i*ient noel
*arr! sele*t a##erL IIE-T "mar*h &7$N )
G<H I) Bang" S) 8ang" an# B) 8eng" K0e. e++i*ient #esigns +or A21 an#
A021 +un*tions on the transistor leel"L IEEE I) Soli#-State Cir*uits"
ol) &'" no) M" pp) M37PM3:" Iul) $''%)
G:H 1eto Qimmermann an# Bol+gang 8i*htner" Fellow, IEEE Lo.-Po.er
Logi* St!les, CM2S Versus Pass-Transistor Logic IEEE I2U10-L 28
S2LID-ST-TE CI1CUITS" V2L) N&" 02) M" IULJ
Page F &