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Introduction
In this lab, you will design a finite state machine to control the taillights of a 1965 Ford
Thunderbird
1
. There are three lights on each side that operate in sequence to indicate the
direction of a turn. Figure 1 shows the tail lights and Figure 2 shows the flashing
sequence for (a) left turns and (b) right turns.
ZOTTFFS
CALIFORNIA
RA RB RC LC LB LA
Copyright 2000 by Prentice Hall, Inc.
Digital Design Principles and Practices, 3/e

Figure 1. Thunderbird Tail Lights

LC (a) LB LA RA (b) RB RC
Copyright 2000 by Prentice Hall, Inc.
Digital Design Principles and Practices, 3/e

Figure 2. Flashing Sequence (shaded lights are illuminated)

1
This lab is derived from an example by John Wakerly from the 3
rd
Edition of Digital Design.
Digital Computers I: Organization and Logical Design

Lab 4: Thunderbird Turn Signal
Due: Wednesday, November 5, 2014 in class

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This lab is divided into four parts: design, VHDL entry, simulation, and implementation.
If you follow the steps of FSM design carefully and ask questions at the beginning if a
part is confusing, you will save yourself a great deal of time. As always, dont forget to
refer to the What to Turn In section at the end of this lab before you begin.
1) Design
Youve already designed one state machine, so you should be able to do this one on your
own. You may assume you have a clock operating at a few Hz available to run the FSM.
On paper, sketch a state transition diagram for your FSM. Give each state a name and
indicate the values of the six outputs LC, LB, LA, RA, RB, and RC in each state. Your
FSM should take three inputs: reset, left, and right. On reset, the FSM should enter a
state with all lights off. When you press left, you should see LA, then LA and LB, then
LA, LB, and LC, then finally all lights off again. This pattern should occur even if you
release left during the sequence. If left is still down when you return to the lights off
state, the pattern should repeat. right is similar. It is up to you to decide what to do if the
user makes left and right simultaneously true; make a choice to keep your design easy.
Indicate on your state transition diagram the input conditions that will cause transitions
between states.
Write a state table listing the next state and outputs in terms of the current state and
inputs. Then choose a state encoding. Hint: with a careful choice of encoding, your
output and next state logic can be fairly simple. Rewrite the state table using your
encoding.
At this point, you could write a set of next state and output equations as you have done in
Lab 3. Instead, we will design it in an HDL and let the synthesis tool choose the gate-
level implementation.
2) VHDL Entry
Create a new project named lab4_xx, where xx are your initials. Choose HDL for the
to-level source type, and choose the settings shown in the picture below.
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Create a new source of type VHDL Module, by right clicking the project name in the
Design window, and selecting New Source. Call this module State_Machine.
Provide inputs clk, reset, left, right, and outputs LC, LB, LA, RA, RB, RC.
Complete in the VHDL module with your own code to define your state machine.
Remember to declare any internal signals (wire or reg) as needed.
After you have finished entering your code, check your VHDL code for errors by
synthesizing your code. Synthesis will convert your VHDL code into gates and flip-
flops. Making sure your VHDL module is highlighted in the Design window, choose the
Synthesize XST option in the Processes window. Synthesis will find syntactical and
certain other errors.
Expand the Synthesize option in the Processes window and choose View Synthesis
Report. Get in the habit of reading this report; it will often warn you of troubles that
otherwise could take a long time to track down. If synthesis did not complete
successfully, the report will explain why. If it did complete successfully, you can see
what a normal successful report looks like, which will be handy when you have to debug
more complicated digital systems in the future. In particular, pay attention to whether the
synthesis tool chose to change your state encodings; this will help to understand the
schematics.
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Fix the errors in your VHDL and perform Synthesis again. Repeat until Synthesis
completes successfully and there is a green check mark next to the Synthesize option in
the Processes for Source window.
Think about the hardware that you expect your FSM to imply. You can view your
synthesized gates by selecting View RTL Schematic and View Technology Schematic
under the expanded Synthesize XST option. Select Start with a schematic of the top-
level block, and click ok. Print both of these schematics in a readable way to turn in with
your lab write-up. The RTL Schematic is the Register-Transfer-Level schematic and
shows gates and registers. Study the schematic carefully. Does it match what you
expect? It should have a state machine block with a clock, reset, inputs, and outputs,
along with some output logic. You can right click the state machine and choose View
FSM to see a state transition diagram. Does the diagram match your intent? If the
schematic contains anything you didnt want, such as latches, think about your VHDL
code and figure out how it was incorrectly written to imply the unwanted hardware.
We will discuss the details of how FPGAs work shortly. For now, take a look, and get a
general idea of how the synthesis tool changes your code into hardware. You will see a
number of flip-flops; check that the number makes sense.
You will notice that the synthesis tool might have implemented your design in hardware
differently than you would have yourself. In your write-up include a few sentences on
why these might be different than you expected.
Remember that even when your module synthesizes without errors, it does not
necessarily mean that it performs the functions you expect it to. You still need to
simulate your code to verify its functionality.
3) Simulation
Now Simulate your FSM. Click on the Simulation button in the Design window. Then
right click State_Machine and create a VHDL test bench. Call this
State_Machine_Test. A test bench skeleton will be generated for you, but you will have
to create the stimulus to test you state machine. Your simulation should convincingly
show that the FSM performs all functions correctly.
4) Hardware Implementation
Now you will map your design to the Spartan 3E FPGA as you did in Lab 2. n. First, you
will need two new files that will associate the inputs and outputs of the schematic you
drew to the switches and LED lights on the board. Go to the following URL and
download the files: top.vhd, s3.ucf, and debouncer.vdh.
http://students.cec.wustl.edu/~bracy/cse260/lab4
Refer to Lab 2 on how to add these 3 files.
Looking at s3.uf now, you can see that clock input (clk) maps to switch 0 (SW0) on the
lower right corner of the Spartan 3E board. The other three inputs (reset, left, and right)
map to the neighboring three switches, as shown in Figure 3.
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LEDs
(LC, LB, LA, RA, RB, RC)
Switches
C
L
K
R
e
s
e
t
R
i
g
h
t
L
e
f
t
Figure 3. Spartan 3E inputs and outputs
Notice that you will need to manually toggle the clock using switch 0 (SW0). Each time
you move it, you get a clock edge. Also be sure to reset your FSM when you begin. The
outputs (LC, LB, LA, RA, RB, and RC) map to six of the LEDs just above the switches.
The component identity and the corresponding FPGA pin number are written in silk
screen (white ink) on the Spartan 3E board above or below each board component.
If you have forgotten how to load your program on the FPGA, please refer to Lab 2.
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After you have successfully loaded your FSM onto the FPGA, reset the FSM, by turning
switch 1 (SW1) ON, and toggling the clock (SW0). Your FSM should now be in the reset
state and all the LEDs should be off. Now switch left (SW3) HIGH and toggle the clock
by pushing SW0 on and off. Toggle the clock until it finishes going through the correct
states in your FSM. Do the same for the right switch.
Note: the switches often experience a phenomenon called bounce, in which the
mechanical contacts bounce as the switch is opening or closing, creating multiple rapid
rising and falling pulses rather than a single clock edge. To keep this from happening, we
have given you a file called debouner.vhd. If you look in top.vhd. you can see that the
debouncer takes in the swt(0) signal, and outputs a signal dSwt. This is the debounced
version of the right-most switch the one youll be moving the most for this lab. We
could debounce the other signals as well, but the clk signal seems to be the most
problematic.
Another Note: the debouncer needs a real clock, so weve given it a one called clkb.
You should not use clkb in your vhdl anywhereit is not the clock that is driven by
switch 0.
Super Important Note: The debouncer needs to know whether your design is running in
simulation (making waveforms) or in synthesis (on the FPGA board) in order to work
correctly. You indicate this with a constant called operationMode. It is defaulted to 1.
When you simulate your design, make sure operationMode is set to 0. When you
synthesize your design, make sure operationMode is set to 1.
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What to Turn In
Please turn in each of the following items, clearly marked and in the following order:
1. Please indicate how many hours you spent on this lab. This will not affect your
grade, but will be helpful for calibrating the workload for next semesters labs.
2. Your paper FSM design, including a completed state transition diagram for your
FSM.
3. Printouts of your VHDL code.
4. Printouts of your simulation waveforms demonstrating that your FSM performs all
tasks correctly. Your signals need to be displayed in the following order: clk, reset,
left, right, LC, LB, LA, RA, RB, RC.
5. Write a few sentences about the RTL schematic and technology schematic and if and
how they differ from your expected hardware.
6. Briefly describe how you tested the system on the Spartan 3E board and whether it
worked according to the specifications.
Youve now implemented your first design in VHDL and your first state machine in
hardware!
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Simulation Hints
In ModelSim, you can view signals internal to your VHDL module (i.e. signals that are
not inputs or outputs to the module). To do so, begin by running your testbench on
ModelSim. View the Workspace window in the main ModelSim window. Expand the
hierarchy of the modules until you find the unit under test (UUT), your FSM module.
Double-click on the UUT, as shown below in Figure 3, to display all the signals
associated with that module in the Objects window next to it. (You may need to expand
the Objects window to view the signals.)
Restart Run -All
Figure 3
Click on the signal you would like to view in the waveform window and drag it to the
waves window (labeled wave-default). For example, you might want to view the state
signal. After you have dragged the signals you would like to view to the waves window,
you will need to resimulate. Again in the main ModelSim window, click on Restart ,
and then Run-All , as shown in Figure 3 above.
During debug, youll likely want to view several internal signals. However, on the final
waveform that you turn in, make sure to display only the required signals in the correct
order. All the signals must be readable to get full credit.
You can save the signals displayed in the Modelsim waveform by choosing File->Save.
It will list wave.do as the default filename. You can use that filename or rename it to
another .do filename. After exiting and reopening Modelsim, you can reload the signals
you saved in the .do file. First delete all of the current signals shown in the waveform by
choosing Edit->Select All. Then press the Delete key. The waveform should now show
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no signals. Then choose File->Load and reload the .do file. You will need to Restart and
Run-All to view the signal values.