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ModelSim-Altera Starter Edition - Short Tutorial

This document provides a tutorial for using ModelSim-Altera Starter Edition to simulate a mux design. It involves the following steps: 1. Creating a new project called "mux_sim" and adding the "Mux.v" and "Mux_tb.v" files. 2. Writing a testbench module in "Mux_tb.v" to apply inputs and check the output. 3. Compiling the files, simulating the design, and viewing the output waveforms to verify the mux functions as expected for different input selections.

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286 views8 pages

ModelSim-Altera Starter Edition - Short Tutorial

This document provides a tutorial for using ModelSim-Altera Starter Edition to simulate a mux design. It involves the following steps: 1. Creating a new project called "mux_sim" and adding the "Mux.v" and "Mux_tb.v" files. 2. Writing a testbench module in "Mux_tb.v" to apply inputs and check the output. 3. Compiling the files, simulating the design, and viewing the output waveforms to verify the mux functions as expected for different input selections.

Uploaded by

KarimovaRaikhanovna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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KEEE2232 Digital Design

Semester I, 2014/2015
ModelSim-Altera Starter Edition Short Tutorial


1. Open ModelSim-Altera Starter Edition.



2. Click File>>New>>Project


3. Create Project window will appear. Give project name mux_sim and browse your Project
Location to your mux folder. Then, click OK.



4. Add items to the Project window will appear. Click Add Existing File.



5. Browse to your Mux.v file. Then, click OK.



6. Next, click Create New File. Give file name Mux_tb and file type as Verilog. Then, click
OK and click Close.



7. Now, you have 2 files in your project. Mux.v and Mux_tb.v.



8. Double click Mux_tb.v and empty blank space will appear.




9. You have to write your testbench. Please write the following code.
`timescale 1ns / 1ps

module Testbench;

reg [3:0] Input0_t, Input1_t, Input2_t, Input3_t;
reg [2:0] Sel_t;
wire [3:0] Data_out_t;

Mux Mux_1(Input0_t, Input1_t, Input2_t, Input3_t, Sel_t, Data_out_t);

initial
begin

// assign values to input register
Input0_t <= 0;
Input1_t <= 1;
Input2_t <= 2;
Input3_t <= 3;

//case 0 - Input0 value should be display on output
Sel_t <= 0;
#1 $display("Data_out_t = %b", Data_out_t);

//case 1 - Input1 value should be display on output
Sel_t <= 1;
#1 $display("Data_out_t = %b", Data_out_t);

//case 2 - Input2 value should be display on output
Sel_t <= 2;
#1 $display("Data_out_t = %b", Data_out_t);

//case 3 - Input3 value should be display on output
Sel_t <= 3;
#1 $display("Data_out_t = %b", Data_out_t);

// reassign value to input register Input0 and display on output
Input0_t = 8;
Sel_t <= 0;
#1 $display("Data_out_t = %b", Data_out_t);

// reassign value to input register Input0 and display on output
Input0_t = 4;
Sel_t <= 0;
#1 $display("Data_out_t = %b", Data_out_t);

end
endmodule












10. Save the file. Now, go to Compile menu and click Compile All.



11. If no errors found and compile was succesfull, the status for both files will change to
green .



12. After that, in Project pane, change to Library tab.













13. Expand the work library and double-click Testbench.



14. Sim tab will appear. Right-click Testbench and Add to >> Wave >> All items in region.






15. Wave tab will appear in Wave pane.



16. Now, you can start the simulation by clicking Run All icon, . Another way is you can
go to Simulate menu, click Run >> Run -All














17. After the simulation, you will see the waveforms for all the signals in the Wave tab.



18. Check behavior of signals. Zoom In button and Zoom Out button is useful to check the
detail. Changing the radix of the signal from Binary to Decimal is useful as well.

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