Ece546fall12 08

Slide 1 W.
Rhett Davis NC State University ECE 546 Fall 2012

ECE 546 - VLSI Systems Design
Lecture 8: Stick Diagrams,
Sizing Complementary Gates
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikoli
Slide 2 W. Rhett Davis NC State University ECE 546 Fall 2012
Announcements
HW#3 Due Today
HW#4 Due in 1 week
Consider Attending ECE GO
Night before the Fall Engineering Career Fair
Details at http://www.ece.ncsu.edu/go/
Numbers needed for catering soon
Cisco, Harris, NSA, Northrop Grumman, Boeing
currently coming
Summary of Last Lecture
How do you extract the resistance of a wire
from a layout?
What kind of circuit model would you use for a
wire?
How do you compute delay using this model?
When computing the propagation delay of a
complex Complementary CMOS gate, how do
you build the RC tree?
Review of Last Lecture
Complementary CMOS
Pull-up Network (PUN)
must be the complement
(or dual) of the Pull-
Down Network (PDN)
Output never pulled
in 2 directions
Review of Last Lecture
Apply De-Morgans Theorem to help find
PDN and PUN
D
A
B C
Vout
C B A D F
VDD
Vout
D
B
C
A
C B A D
Todays Lecture
Stick Diagrams & Euler Paths
(Appendix D)
Sizing Complementary CMOS
Gates (6.2.1)
Finding the PUN
Use a Logic Diagram to find the DUAL
Start by drawing PDN:
Draw the nodes first
Finding the PUN
then draw the edges (transistors):
Finding the PUN
Now draw the PUN
Start with the nodes:
One each for VDD and Vout on either side
One inside each region of the PDN
Finding the PUN
Now draw the PUN
Then draw the edges
one to cross every PDN edge
Finding the PUN
Now draw the circuit
Example
Find logic diagram and PUN for
EB D C ED B A F
Standard-Cell Realization
To make a compact,
repeatable cell, wed
like to organize it as
shown here.
How to chose the
order of the inputs
(from left to right)?
Inputs (poly)
VDD
GND
Vout
pactive
nactive
Euler Paths
Euler Path a path that covers the entire
logic diagram, traversing each edge only
once
PDN: CBAD, BCAD, DABC, DACB
PUN: DBCA, DACB
Consistent Euler Path
an Euler path that exists for
both the PDN and PUN
DACB
Stick Diagram
An easy way to plan the layout of the cell
Start with the lines of poly-silicon
Use Consistent Euler Paths for ordering
D A C B
Stick Diagram
Add horizontal lines for metal lines (VDD, GND, Vout)
and active areas
D A C B
VDD
GND
Vout
pactive
nactive
Stick Diagram
Draw the PDN
Use an X to indicate a contact
Use a dot indicate a connection in the same layer
D A C B
VDD
GND
Vout
pactive
nactive
Stick Diagram
Draw the PUN (error on this slide, VDD and Vout
swapped)
VDD Vout
Then Draw the Layout
Height of cell determined by metal width and spacing
Increase fingers parameter in p-cells to eliminate contacts on
one side of the cell
In older technologies, this allowed
some savings of area as illustrated here.
In newer technologies (45nm), poly pitch
cannot be reduced, even if there are no
contacts.
Diagram Must be LVS Correct
D A C B
VDD
GND
Vout
pactive
nactive
NOT CORRECT
(short circuit)
Todays Lecture
Stick Diagrams & Euler Paths
(Appendix D)
Sizing Complementary CMOS
Gates (6.2.1)
Sizing Example
OUT = D + A (B + C)
D
A
B C
D
A
B
C
Assuming that the PMOS
has twice as much resistance
as the NMOS, size the
transistors in this example:
Fan-In Considerations
D C B A
D
C
B
A
C
L
C
3
C
2
C
1
Distributed RC model
(Elmore delay)
t
pHL
= 0.69 R
eqn
(C
1
+2C
2
+3C
3
+4C
L
)
Propagation delay deteriorates
rapidly as a function of fan-in
quadratically in the worst case.
NAND t
p
as a Function of Fan-In
Gates with a
fan-in
greater than
4 should be
avoided.
t
pL
H
t
p
(
p
s
e
c
)
fan-in
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
t
pHL
quadratic
linear
t
p
t
pLH
t
p
as a Function of Fan-Out
2 4 6 8 10 12 14 16
t
p
NOR2
t
p
(
p
s
e
c
)
eff. fan-out
All gates
have the
same drive
current.
t
p
NAND2
t
p
INV
Slope is a
function of
driving
strength
Fast Complex Gates: Technique 1
Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing
In
N C
L
C
3
C
2
C
1
In
1
In
2
In
3
M1
M2
M3
MN
Distributed RC line
M1 > M2 > M3 > > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
Transistor ordering
C
2
C
1
In
1
In
2
In
3
M1
M2
M3 C
L
C
2
C
1
In
3
In
2
In
1
M1
M2
M3 C
L
critical path critical path
charged
1
01
charged
charged
1
delay determined by time to
discharge C
L
, C
1
and C
2
delay determined by time to
discharge C
L
1
1
01
charged
discharged
discharged
Alternative logic structures
F = ABCDEFGH
Isolating fan-in from fan-out using buffer
insertion
C
L
C
L
Reducing the voltage swing
linear reduction in delay
also reduces power consumption
But the following gate is much slower!
Or requires use of sense amplifiers on the
receiving end to restore the signal level
(memory design)
t
pHL
0.69 (C
L
V
DD
)/ I
DSATn
0.69 (C
L
V
swing
)/ I
DSATn
Summary
Learned how to find the dual of a PDN with a
logic diagram
Learned how to find consistent Euler Paths
from the logic diagram and draw the stick-
diagram for the layout
Learned how to size Complementary CMOS
gates for less delay

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Rhett Davis NC State University ECE 546 Fall 2012

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