The document discusses computer performance and factors that affect it. It covers three main factors: hardware design, instruction set, and compiler. Hardware design focuses on the processor, memory technologies, and architectural enhancements. Instruction sets and compilers can also impact performance by reducing the number of instructions or steps needed. Key concepts covered include pipelining, superscalar operations, clock rate, RISC vs CISC, and the basic performance equation.
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Subject Code:cs 46 Test #:1
The document discusses computer performance and factors that affect it. It covers three main factors: hardware design, instruction set, and compiler. Hardware design focuses on the processor, memory technologies, and architectural enhancements. Instruction sets and compilers can also impact performance by reducing the number of instructions or steps needed. Key concepts covered include pipelining, superscalar operations, clock rate, RISC vs CISC, and the basic performance equation.
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DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode(cs )* Test + (, !ode- Answer for .uestion +( , Information Handled by a Computer Instructions/machine instructions Govern the transfer of information within a computer as well as between the computer and its I/O devices Specify the arithmetic and logic operations to be performed Program Data sed as operands by the instructions Source program !ncoded in binary code " # and $ %SCII and !&CDIC 'emory nit Store programs and data (wo classes of storage Primary storage )ast Programs must be stored in memory while they are being e*ecuted +arge number of semiconductor storage cells Processed in words %ddress ,%' and memory access time 'emory hierarchy " cache- main memory Secondary storage " larger and cheaper %rithmetic and +ogic nit .%+/ 'ost computer operations are e*ecuted in %+ of the processor0 www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES +oad the operands into memory " bring them to the processor " perform operation in %+ " store the result bac1 to memory or retain in the processor0 ,egisters )ast control of %+ Control nit %ll computer operations are controlled by the control unit0 (he timing signals that govern the I/O transfers are also generated by the control unit0 Control unit is usually distributed throughout the machine instead of standing alone0 Operations of a computer2 %ccept information in the form of programs and data through an input unit and store it in the memory )etch the information stored in the memory- under program control- into an %+- where the information is processed Output the processed information through an output unit Control all activities inside the machine through a control unit &asic Operational Concepts ,eview %ctivity in a computer is governed by instructions0 (o perform a tas1- an appropriate program consisting of a list of instructions is stored in the memory0 Individual instructions are brought from the memory into the processor- which e*ecutes the specified operations0 Data to be used as operands are also stored in the memory0 www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( / Performance T0e most important measure of a computer is 0ow 1uick-2 it can e3ecute pro4rams. T0ree factors affect performance( 5ardware desi4n $nstruction set #ompi-er Performance Processor time to e3ecute a pro4ram depends on t0e 0ardware in6o-6ed in t0e e3ecution of indi6idua- mac0ine instructions. Performance T0e processor and a re-ati6e-2 sma-- cac0e memor2 can be fabricated on a sin4-e inte4rated circuit c0ip. Speed #ost !emor2 mana4ement Processor #-ock #-ock7 c-ock c2c-e7 and c-ock rate T0e e3ecution of eac0 instruction is di6ided into se6era- steps7 eac0 of w0ic0 comp-etes in one c-ock c2c-e. 5ert8 & c2c-es per second 9asic Performance E1uation T & processor time re1uired to e3ecute a pro4ram t0an 0as been prepared in 0i40:-e6e- -an4ua4e N & number of actua- mac0ine -an4ua4e instructions needed to comp-ete t0e e3ecution ;note( -oop< S & a6era4e number of basic steps needed to e3ecute one mac0ine instruction. Eac0 step comp-etes in one c-ock c2c-e & c-ock rate www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES Note( t0ese are not independent to eac0 ot0er Pipe-ine and Supersca-ar Operation $nstructions are not necessari-2 e3ecuted one after anot0er. T0e 6a-ue of S doesn=t 0a6e to be t0e number of c-ock c2c-es to e3ecute one instruction. Pipe-inin4 & o6er-appin4 t0e e3ecution of successi6e instructions. Add ,7 /7 > Supersca-ar operation & mu-tip-e instruction pipe-ines are imp-emented in t0e processor. ?oa- & reduce S ;cou-d become @,A< #-ock ate $ncrease c-ock rate $mpro6e t0e inte4rated:circuit ;$#< tec0no-o42 to make t0e circuits faster educe t0e amount of processin4 done in one basic step ;0owe6er7 t0is ma2 increase t0e number of basic steps needed< $ncreases in t0at are entire-2 caused b2 impro6ements in $# tec0no-o42 affect a-- aspects of t0e processor=s operation e1ua--2 e3cept t0e time to access t0e main memor2. #$S# and $S# Tradeoff between N and S A ke2 consideration is t0e use of pipe-inin4 S is c-ose to , e6en t0ou40 t0e number of basic steps per instruction ma2 be considerab-2 -ar4er $t is muc0 easier to imp-ement efficient pipe-inin4 in processor wit0 simp-e instruction sets educed $nstruction Set #omputers ;$S#< #omp-e3 $nstruction Set #omputers ;#$S#< #ompi-er A compi-er trans-ates a 0i40:-e6e- -an4ua4e pro4ram into a se1uence of mac0ine instructions. To reduce N7 we need a suitab-e mac0ine instruction set and a compi-er t0at makes 4ood use of it. ?oa- & reduce NBS A compi-er ma2 not be desi4ned for a specific processorC 0owe6er7 a 0i40:1ua-it2 www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES compi-er is usua--2 desi4ned for7 and wit07 a specific processor. www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( > > Definition of benc0mark T0e SPE# ratin4 definition SPE# ratin4 D unnin4 time in ef computer E unnin4 time in computer under test T0e O6era-- spec ratin4 of a computer s2stem SPE# atin4 D ; F SPE# i < ,En Specification of SPE# /GGG computer s2stem HH U-trasparc ,G WES wit0 >GG !58 u-trasparc &$$ i processor Processor tec0no-o427 speed and 0ardware arc0itecture $EO or4ani8ation 7 de6ices !emor2 tec0no-o4ies 7 speed and arc0itecture En6ironment and s2stem software e6o-ution Arc0itectura- en0ancements "O EA#5 ?ENEAT$ONS www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( ) T0e bi4 endian stora4e uses -ower b2te addresses for more si4nificant b2tes and -itt-e endian stora4e uses -ower b2tes for -ess si4nificant b2tes. i) Since it is 0e3 words of of ) di4its t0e bi4 endian stora4e words are >)>I5 and >J>>5. >)>I5 D >K,* > L)K,* / L>K,* , L IK,* G D
,>>*I decima- >J>>5 D
>K,* > LJK,* / L>K,* , L >K,* G D
,>*,I decima- ii) 9i4 endian stora4e of / 9#D words of ) di4its are >)>I and >J>> and t0eir decima- 6a-ues are >)>I and >J>> iii) %itt-e endian stora4e in AS#$$ of ) di4it si4ned 0e3 word is J>)I5 and t0e decima- 6a-ue is JK,* > L>K,* / L)K,* , L IK,* G D
/,>/, decima-
iv) %itt-e endian stora4e in AS#$$ of a ) di4it 9#D word is J>)I decima- www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( J Pro4ram:#ontro--ed $EO E3amp-e !ac0ine instructions t0at can c0eck t0e state of t0e status f-a4s and transfer data( EADWA$T 9ranc0 to EADWA$T if S$N D G $nput from DATA$N to , W$TEWA$T 9ranc0 to W$TEWA$T if SOUT D G Output from , to DATAOUT Pro4ram:#ontro--ed $EO E3amp-e !emor2:!apped $EO & some memor2 address 6a-ues are used to refer to perip0era- de6ice buffer re4isters. No specia- instructions are needed. A-so use de6ice status re4isters. EADWA$T Testbit +>7 $NSTATUS 9ranc0DG EADWA$T !o6e92te DATA$N7 , www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( * www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( M www.bookspar.com | Website for students | VTU NOTES www.bookspar.com | Website for students | VTU NOTES DEPAT!ENT O" #O!PUTE S#$EN#E $NTENA% TEST & SO%UT$ONS Sub'ect #ode( Test + ( !ode- Answer for .uestion +( N $n a primiti6e computer7 t0e o6erf-ow bit is not automatica--2 set w0en a /=s comp-ementar2 addE subtract operation is done. Write a pseudo code for detectin4 t0e o6erf-ow condition for t0e abo6e arit0metic operation wit0 4eneric assumptions on t0e arc0itecture. Demonstrate t0e 6a-idit2 of t0e code wit0 assumed data in N bits T0e assumption is t0at t0e arc0itecture 0as #arr2 and Ne4ati6e f-a4s and $SA supportin4 t0is #onditiona- f-a4s. T0e data are in memor2 -ocations %O#A and %O#9 and 0as re4isters G: N and t0e o6erf-ow f-a4s are to be set in re4ister ) G,,,,,,, T0e t2pica- pseudo code as fo--ows( G,,,,,,, L,/M G,G,G,G, ;L< LGNJ StartOc0eck(!o6 G7 -oca ; : )) < ::::G,,G,G,GG L/,/ ;O6- !o6 ,7 -ocb Add G7, !o6 >7 G C store t0e 6a-ue for future use PNP positi6e C $f t0e resu-t is ne4ati6e c0eck for t0e addends si4n !o6 G7,C sets t0e si4n f-a4 PP NoOo6erf-ow !o6 G7 -oca PP o6erf-ow Positi6e ( !o6 G7, PNP NoOo6erf-ow !o6 o7-oca PNP o6erf-ow O6erf-ow ( !oV )7+Q"" NoOo6erf-ow ( !o6 ). +QGG End www.bookspar.com | Website for students | VTU NOTES