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Non - Intrusive BIST - Organization

This document discusses non-intrusive built-in self-test (BIST) architectures and implementations at different levels including board, device, and system levels. Non-intrusive BIST avoids manipulating the internal circuitry of the circuit under test and places the BIST circuitry externally, resulting in low area and performance overhead. It is well-suited for high-speed applications. Programmable logic devices are good for board-level BIST as the BIST circuitry can be reprogrammed. Bit-sliced BIST distributes the BIST circuitry over each bit slice of the data path. While non-intrusive BIST provides benefits like low overhead and vertical testability, it may have low

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Raghavendra Mattur
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54 views7 pages

Non - Intrusive BIST - Organization

This document discusses non-intrusive built-in self-test (BIST) architectures and implementations at different levels including board, device, and system levels. Non-intrusive BIST avoids manipulating the internal circuitry of the circuit under test and places the BIST circuitry externally, resulting in low area and performance overhead. It is well-suited for high-speed applications. Programmable logic devices are good for board-level BIST as the BIST circuitry can be reprogrammed. Bit-sliced BIST distributes the BIST circuitry over each bit slice of the data path. While non-intrusive BIST provides benefits like low overhead and vertical testability, it may have low

Uploaded by

Raghavendra Mattur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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C.

Stroud 11/06 Non-Intrusive BIST 1


Non
Non
-
-
Intrusive BIST
Intrusive BIST
-
-
Organization
Organization
Architecture Implementations Architecture Implementations
Board Board- -level level
Device Device- -level level
System System- -level level
Vertical Testability Vertical Testability
Benefits and Limitations Benefits and Limitations
C. Stroud 11/06 Non-Intrusive BIST 2
Non
Non
-
-
Intrusive BIST
Intrusive BIST
Architectures avoid manipulation of internal CUT circuitry Architectures avoid manipulation of internal CUT circuitry
BIST circuitry is external to CUT BIST circuitry is external to CUT
Low performance penalty Low performance penalty
Good for high speed applications Good for high speed applications
C. Stroud 11/06 Non-Intrusive BIST 3
Board
Board
-
-
Level Implementations
Level Implementations
Programmable logic devices Programmable logic devices
( (FPGAs FPGAs & & CPLDs CPLDs) are excellent ) are excellent
devices for board devices for board- -level BIST level BIST
Reprogram with BIST circuitry Reprogram with BIST circuitry
for testing for testing
Reprogram for system function Reprogram for system function
during operation during operation
No area overhead or performance No area overhead or performance
penalty penalty
Must store configuration data to Must store configuration data to
reprogram PLD reprogram PLD
Provide TPG, MISR, & BIST Provide TPG, MISR, & BIST
control for board control for board- -level STUMPS level STUMPS
C. Stroud 11/06 Non-Intrusive BIST 4
Device
Device
-
-
Level Implementations
Level Implementations
TPG & MISR can be shared TPG & MISR can be shared
Loopback mechanism needed Loopback mechanism needed
Good for data path circuitry Good for data path circuitry
Control circuitry tested via Control circuitry tested via
multiple test sessions multiple test sessions
C. Stroud 11/06 Non-Intrusive BIST 5
Bit
Bit
-
-
Sliced BIST Circuit Design
Sliced BIST Circuit Design
One bit One bit- -slice per bit in data path slice per bit in data path
Additional XOR gates for LFSR polynomial Additional XOR gates for LFSR polynomial
Optional flip Optional flip- -flops for pipelining high speed applications flops for pipelining high speed applications
C. Stroud 11/06 Non-Intrusive BIST 6
System
System
-
-
Level Implementation & Testing
Level Implementation & Testing
C. Stroud 11/06 Non-Intrusive BIST 7
Non
Non
-
-
Intrusive BIST Summary
Intrusive BIST Summary
Benefits
Benefits
Low area overhead Low area overhead
Low performance penalty Low performance penalty
Good for high speed applications Good for high speed applications
Vertical testability for device through system Vertical testability for device through system- -level testing level testing
Limitations
Limitations
Low fault coverage for many applications Low fault coverage for many applications
Fault simulation may be lengthy Fault simulation may be lengthy
But necessary to determine fault coverage But necessary to determine fault coverage

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