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D06A Prog Logice Devices (GALs)

This document provides instructions for an experiment involving programmable logic devices (PLDs). It includes: 1) An overview of the equipment needed, including a PC with programming software, PLD chip, and accessories. 2) Description of three areas to design PLD circuits: combinational logic, synchronous sequential logic, and asynchronous sequential logic. 3) Step-by-step procedures for designing each type of circuit using equations or state tables in a PLD programming tool, simulating the design, and programming and testing the circuit on a PLD chip. The examples provided are a 7-segment decoder, 3-bit counter, and 2-input sequence detector.

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0% found this document useful (0 votes)
145 views13 pages

D06A Prog Logice Devices (GALs)

This document provides instructions for an experiment involving programmable logic devices (PLDs). It includes: 1) An overview of the equipment needed, including a PC with programming software, PLD chip, and accessories. 2) Description of three areas to design PLD circuits: combinational logic, synchronous sequential logic, and asynchronous sequential logic. 3) Step-by-step procedures for designing each type of circuit using equations or state tables in a PLD programming tool, simulating the design, and programming and testing the circuit on a PLD chip. The examples provided are a 7-segment decoder, 3-bit counter, and 2-input sequence detector.

Uploaded by

P_lee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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D06 Programmable Logic Devices

D06A - Programmable Logic Devices (GAL20V8)


1 Equime!"
PC with Programmer software and Programmer Box (LEAPER Universal IC Writer)
PC with IDE (WinCUPL Win!I") #Integrated Develo$ment Environment%
Digital &rainer
'AL()*+ Integrated Cir,-it
PLD()*+ Box (allows .anana leads to ,onne,t to IC)
/0!egment De,oder Box
(x 1mm .anana leads
2 .ag of (mm .anana leads
IMPORTANT: YOUR OWN USB Drive or other remova.le storage devi,e3 &his is
not re4-ired .-t it will .e hel$f-l as 5les need to .e shifted .etween ,om$-ters3
2 E#erime!" $vervie%
Com$lete $ro.lems within three areas of $ossi.le a$$li,ation for a sim$le PLD6
,om.inational logi, s7n,hrono-s se4-ential logi, and as7n,hrono-s se4-ential logi,3
& Proce'ure
3.1 Starting WinCUPL
23 8$en WinCUPL from start menu > Programs > Atmel > Atmel WinCUP >
WinCUP or sear,h windows for 9WinCUPL3exe:
(3 Create a new Pro;e,t (<ile = >ew = Pro;e,t)
?3 IMPORTANT: In the dialog .ox that a$$ears enter an a$$ro$riate name (e3g3
de,oder?to/) and enter the devi,e as g!"v#a3 &he other 5elds ,an .e left as
the7 are3
13 A $o$-$ will as@ how man7 in$-t $ins o-t$-t $ins and $innodes are re4-ired for
the $ro;e,t3 Enter a$$ro$riate val-es to the $ro.lem or leave them ) (this ,an
alwa7s .e ,hanged later A a ,ode tem$late is ,reated from the val-es entered)3
B3 Co- are now read7 to ,ode3
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D06 Programmable Logic Devices
3.2 COMBINATIONAL DESIGN
&,2,1 -ombi!a"io!al Desig! .si!g Equa"io!s (Deco'e&"o/)
Create a de,oder for a ?0.it .inar7 in$-t to /0segment dis$la7 o-t$-t3
Prep:
23 Com$lete the tr-th ta.le3
(3 Create e4-ations for ea,h of the o-t$-ts from the tr-th ta.le or .7 -sing
@arna-gh ma$s3
Trut$ Ta%le
n INPUT
P Q R
OUTPUTS
a b c d e f g
Output Equations
0 0 0 0 1 1 1 1 1 1 0 a =!P!Q!R+!PQ!R+
1 0 0 1 0 1 1 0 0 0 0 b =
2 0 1 0 1 1 0 1 1 0 1 c =
3 0 1 1 d =
4 1 0 0 e =
5 1 0 1 f =
6 1 1 0 g =
7 1 1 1

Q
P
R
Binary Input
7-Seg
Outputs
a
d
3-bit Binary
to 7-Seg
DECODER
b
c
e
f
g
GND
g
msb = 4
nused !"#c$
%
&
'
4
&%
%&
&(
%)
&7
&*
&+
&,
GAL20V8
-DD
NDg
%4
,-
)-
In Lab:
23 Write Code for the De,oder in WinCUPL #See A&&en'i( A )or $el&%3
DE ?0.it BI>ARC to F0!E' DEC8DERED
DEEEEEEEEEEEEEEEEEEEEEEEEEEEEEED
DE Pins ED
DEEEEEED
Pin ( G PH DE ms. of .inar7 in$-t ED
Pin ? G
Pin#2B33(2% G #a.,defg%H
DE E4-ations ED DE F G A>D I G 8R J G I>*ER&
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D06 Programmable Logic Devices
DEEEEEEEEEEED
P G
(3 !im-late the De,oder in Win!im #See A&&en'i( B )or $el&%3
?3 Program a 'AL()*+ with 7o-r ,om$iled ,ode #See A&&en'i( C )or $el&%3
13 *erif7 the $rogram wor@s on the 'AL()*+ .7 ,onne,ting to the /0segment dis$la73
a3 Conne,t wires .etween the o-t$-t $ins 7o- de5ned and the /0seg dis$la7 .ox3
.3 Power the 'AL()*+ .ox with 2B* and gro-nd A ens-re the ,ommon gro-nd is
,onne,ted to the /0seg dis$la7 .ox and the 'AL()*+ .ox or it will not wor@3
,3 Use the digital trainer swit,hes as in$-ts (ens-re it is t-rned on)3
d3 Use a digital 92: from the digital trainer to sele,t whi,h digit of the /0seg
dis$la7 .ox is to .e ena.led3
&,2,2 -ombi!a"io!al Desig! .si!g 0ables (Deco'e1"o/)
Create a De,oder for a 10.it .inar7 in$-t to /0segment dis$la7 o-t$-t3
Prep:
23 Com$lete the tr-th ta.le ('o not ,reate o-t$-t e4-ations for this 4-estion)3
Trut$ Ta%le
n INPUT
P Q R S
OUTPUTS
a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 1 0 1 0
B 1 0 1 1
C 1 1 0 0
D 1 1 0 1
E 1 1 1 0
F 1 1 1 1 1 0 0 0 1 1 1
Note: &he /0segment dis$la7 dis$la7s hex re$resentation3
(evise') Augus" 200* Page &+1&
D06 Programmable Logic Devices

Q
P
R
Binary Input
7-Seg
Outputs
a
d
4-bit Binary
to 7-Seg
DECODER
b
c
e
f
g
GND
g
msb = 4
nused !"#c$
%
&
'
4
&%
&,
&7
&+
&(
&*
%)
%& GAL20V8
-DD
NDg
%4
,-
)-
S
,
In Lab:
23 Create a new $ro;e,t (De,oder1to/) and write a$$ro$riate $in de5nitions3
(3 Write ,ode for the 10.it de,oder -sing ta.les (see .elow)3
?3 !im-late the de,oder in Win!I"3
13 Program and test the de,oder on a 'AL()*+ IC3
Co'e )or ta%les *a)ter &in 'e+nitions,
DE De,larations ED
DEEEEEEEEEEEEED
<ield Binar71 G #P K R !%H
<ield !eg/ G #a . , d e f g%H
DE E4-ations ED
DEEEEEEEEEEED
&a.le Binar71 G= !eg/
L
9.:)))) G= 9.:2222222)H
9.:)))2 G=
DDand so on
-.
(evise') Augus" 200* Page 1+1&
D06 Programmable Logic Devices
3.3 SYNCHRONOUS CIRCUIT DESIGN
&,&,1 .si!g Equa"io!s (-ou!"er&)
Design a /0%it Binar1 Counter *ABC, Using D0T1&e 2i&02o&s
Prep:
23 Create Mi$0Mo$ e4-ations from state0transition ta.le (,an -se @arna-gh ma$s)3
(3 Create ,om.inational e4-ations for the additional o-t$-ts3
n
State
D-FlipFlop Equations Present Ne(t
A ! A""!" A= D
A
= !ABC + A!B!C + A!BC + ABC
0 0 0 0 0 0 1
1 0 0 1 0 1 0
2 0 1 0 0 1 1
B= D
B
=
3 0 1 1 1 0 0
4 1 0 0 1 0 1
5 1 0 1 1 1 0
C= D
C
=
6 1 1 0 1 1 1
7 1 1 1 0 0 0
A''itional Out&uts
&he ,o-nter is also to have the following o-t$-ts
3
"
when ,o-nt G ) 3
"
G
3
456
when ,o-nt G B or N or / 3
456
G
3
6
when the ,o-nt G 222
.
3
6
G

!#unter
Output
.
/)
3-bit Binary
COUNER
B
!
/,+7
/7
GND
g
!"#c$
&
&%
&,
&7
&+
&(
&*
%)
GAL20V8
-DD
NDg
%4
,-
)-
State
Outputs
In Lab:
23 Create a new $ro;e,t (Co-nter?) and write a$$ro$riate $in de5nitions3
(3 Code Boolean e4-ations for Mi$Mo$ in$-ts and additional o-t$-ts3
Note: &he D in$-t of Mi$Mo$ A (A
D
G A:) is A7D A where A is a Mi$Mo$ o-t$-t $in3
<or exam$le6
A3D G JAFBFC I AFJBFJC I
?3 !im-late the ,o-nter in Win!I"
13 Program and test the Co-nter on a 'AL()*+ IC3
(evise') Augus" 200* Page 2+1&
D06 Programmable Logic Devices
&,&,2 .si!g 3"a"e-4ac5i!e 0able (.Do%!-ou!"&)
Design a /0%it U&8Do9n Counter Using WinCUP S1n:$ronous State0Ma:$ine
Design 3
;el& in se:tion 1.1.30 State Machine Syntax o) t$e CUP Re)eren:e Manual *$el& menu in
WinCu&l,7

!#unter
Output
.
3-bit Binary
U!"Do#n
COUNER
B
!
GND
g
!"#c$
&
&%
&,
&7
&+
GAL20V8
-DD
NDg
%4
,-
)-
= p
0 = D#1n
%
In Lab:
23 Create a new $ro;e,t (U$DownCo-nt?) and write a$$ro$riate $in de5nitions3
(3 Code a state ma,hine for the ,o-nter (see .elow for s7ntax)
?3 !im-late the ,o-nter in Win!im
13 Program and test the ,o-nter on a 'AL()*+ IC3
State Ma:$ine S1nta( *a)ter &in 'e+nitions,
DE gro-$ the ,o-nter Mi$Mo$ o-t$-ts into a 5eld ED
5eld ,o-nt G #A B C%H
8< De+ne Counter States *1ou nee' # states,<8
Ode5ne !) 9.:)))H
Ode5ne !2 9.:))2H
DE &ransition &a.le ED
!e4-en,ed ,o-nt
L
$resent !) if U next !2H
if JU next !/H
$resent s2 if U next s(H
if JU next s2H
P
(evise') Augus" 200* Page 6+1&
!tat
e
7
2
7
(
4
)
4
2
4
(
)
)
2
)2
2
4
?
)
2 Out&ut =>uations
Q2 G
Q( G
ABG))
4
)
4
2 4
(
)2R22R
2)
Q
(
4
?
ABG))
ABG2)R2
2))
ABG)2
D06 Programmable Logic Devices
3.4 ASYNCHRONOUS SEUENTIAL CIRCUIT DESIGN !ABS"#D"t$
Buil' an as1n:$ronous !0in&ut *AB, se>uen:e 'ete:tor *9it$ %ot$ in&uts
starting as ",3
&he se4-en,e to as7n,hrono-sl7 dete,t is AB ? ""@ "A@ AA
Prep:
23 Com$lete the s7stem model diagram3
(3 Constr-,t next state e4-ations3
?3 Constr-,t e4-ations for the two o-t$-ts (Q2 Q()3
Out&ut Des:ri&tions
Q2 is to go tr-e whenever ABG22
Q( is to .e tr-e when AB G22 $rovided that AB has gone thro-gh the se4-en,e AB G
)))222
Transition Ta%le
Prese
nt
State
(7
2
7
(
)
Ne(t State (7
2
7
(
) Ne(t State =>uations
In$-ts
AB G )) )2 22
2)
7
2
G J7
2
J7
(
JAJB R 7
2
J7
(
JAJB R
4
)
G )) 7
2
7
(
G 2) )) ))
))
4
2
G 2) 7
2
7
(
G 2) 22 ))
))
7
(
G
4
(
G 22 7
2
7
(
G
4
?
G )2 7
2
7
(
G
In Lab:
23 Create a new $ro;e,t (AB!e4Det) and write a$$ro$riate $in de5nitions3
(3 Code the se4-en,e dete,tor -sing feed.a,@3
&o im$lement the s7stem as7n,hrono-sl7 a Mi$Mo$ that is not ,lo,@ed is needed
#e3g3 R!0Mi$ Mo$s%3 A R!0Mi$Mo$ is not $art of the 'AL()*+ hardware so it has to
.e ,onstr-,ted -sing feed.a,@ as indi,ated in the >ext !tate E4-ations shown
a.ove3
(evise') Augus" 200* Page /+1&
D06 Programmable Logic Devices
?3 !im-late in Win!im
13 Program and test the se4-en,e dete,tor on a 'AL()*+ IC3
(evise') Augus" 200* Page 8+1&
D06 Programmable Logic Devices
1 Ae!'i# A 6asic 7i!-.PL -o'e
&his a$$endix will -se the 5rst $ro.lem (De,ode?to/) for ,ontent3
At the to$ of the ,ode 5le $h7si,al devi,e $ins need to .e assigned names3 Refer to the
devi,e s$e,i5,ation do,-ment as to whi,h $ins ,an .e -sed as in$-ts o-t$-ts and Mi$0
Mo$ o-t$-ts3
Pin de5nitions ,an .e as follows6 (Note: WinCUPL is ,ase0sensitive)
!"n#$%&!
P'n 2 = A(
P'n 3 = B(
P'n 4 = C(
!)$%#$%&!
P'n 16 = a(
and &* *n
&his ,ode ,an also .e done a short0hand wa76
!"n#$%&!
P'n +2,,4- = +A. B. C-(
8n,e the $ins have .een given names it is eas7 to write e4-ations for the o-t$-t $ins3
&o assign Boolean e4-ations to the o-t$-t $ins WinCUPl s7ntax for Boolean o$erators
,an .e -sed3
! = 'n/e0%( 1 = A2D( 3 = )R( 4 = 5)R(
)$%#$% Enab6e *f )$%#$% 7 = 7,)E
!o an exam$le of an o-t$-t e4-ation6
!E8$a%'*n&!
a = A1!B1!C 3 9A 3 B4!C:(
a = 9A and n*%B and n*%C: *0 9A *0 9B ;*0 n*%C::
P-lling this all together as a ,om$lete PLD 5le6
!F'6e <eade0& 9a$%*=gene0a%ed: !
!"n#$%&!
P'n +2,,4- = +A. B. C-(
!)$%#$%&!
P'n 16 = a(
!E8$a%'*n&!
a = A1!B1!C 3 9A 3 B4!C:(
When ,om$lete ,om$ile the 5le .7 sele,ting device dependent compile3 An
-ns-,,essf-l ,om$ile indi,ates s7ntax errors3 A s-,,essf-ll7 ,om$ile indi,ates no
s7ntax errors in 7o-r ,ode and 7o- ,an move onto testing (,om$iling will onl7 wor@ if
the devi,e in the 5le header is ,orre,t)3
(evise') Augus" 200* Page *+1&
D06 Programmable Logic Devices
;int: Alwa7s loo@ at the 5rst error in the list as solving it ,an often 5x all the errors3
Alwa7s ,he,@ the line a.ove the error as a $ro.lem there ,an ,a-se misleading errors3
<or exam$le a missing semi,olon on an a.ove line will ,a-se an error on the line
.elow3
(evise') Augus" 200* Page 10+1&
D06 Programmable Logic Devices
2 Ae!'i# 6 8o% "o simula"e i! 7i!3im
&he a$$li,ation -sed in this t-torial is a sim$le inverter3
1. After ,reating saving and ,om$iling a 5le in WinC-$l ,li,@ the WinSim %utton3
2. 8n,e Win!im o$ens go to the men- File and ,li,@ New.
3. Cli,@ the .-tton Design File and 5nd the 3$ld 5le written in WinC-$l
4. 8n,e sele,ted this sho-ld 5ll in the Design Pro$erties a-tomati,all7 ,li,@ OK
5. 'o to the Signal men- and sele,t Add Signal3
. Add the signals 7o- wish to see sim-lated .7 sele,ting them from the dro$0down
men- and $ressing OK3
!. When all desired signals are added $ress Done3
". 'o to the Signal men- and sele,t Add #ecto$3
%. Enter the n-m.er of ve,tors 7o- wish to sim-late for (n-m.er of ,ases to view)3
Cli,@ OK.
1&. Rig$t0:li:B on the ve,tor ,ells to set to desired sim-lation val-e3
>ote6 the Set '(ole Signal o$tion A this is ver7 -sef-l3 &r7 all the o$tions to see what
the7 do3
11. <or .asi, -se drive the in$-ts to wanted val-e () or 2)
12. Leave the o-t$-ts as sim-lator determined (E)3
13. Press the sim-late .-tton to attem$t to sim-late3
Note: Not all a&&li:ations :an %e simulate'.
(evise') Augus" 200* Page 11+1&
Be)ore
Simulation
A)ter
Simulation
D06 Programmable Logic Devices
NOTE: WinSim is not case sensitie! i" yo# hae t$o si%na&s o" 'i(erent case
it $i&& not $or) *e.%. t$o 'i(erent si%na&s ca&&e' +a, - +., $i&& not
sim#&ate/.
(evise') Augus" 200* Page 12+1&
D06 Programmable Logic Devices
6 Ae!'i# - Programmi!g a GAL20V8
When a 3PLD 5le is ,om$iled in WinCUPL a 3;ed 5le of the same name sho-ld .e
$rod-,ed3 &his 3;ed 5le ,an .e -sed to $rogram a 'AL()*+a ,hi$3
%.1 S"t&' !(n)* n""+"+ t( ," +(n" (n-" '"r )(gin$
T$is se:tion is out o) 'ate7 Onl1 use t$is as a gui'eC
&o $rogram the ,hi$ -se a LEAPER Universal Writer Box3 When the .ox is 5rst t-rned on
drivers m-st .e installedH follow the driver install wiSard to install from a s$e,i5,
lo,ation3 &he drivers are lo,ated in6 ):*+$og$am Files*,nive$sal -) '$ite$*D$ive$
8n,e the drivers are installed o$en the $rogram 9Universal IC Writer: from the start
men-3
In the 9Universal IC Writer: software
sele,t the $rogrammer 9t7$e:
* "an-fa,t-re G LA&&ICE
* &7$e >-m.er G 'AL()*+B(DIP) #not a t7$o it is B%
%.2 Pr(gra..ing t/" -/i'
Insert the ,hi$ into the LEAPER Universal Writer -nit A ens-re the ,hi$ is $la,ed in the
,orre,t orientation and is se,-rel7 lo,@ed in (-se the diagram on the -nit to orientate
,orre,tl7)3
Ens-re 7o- have a,,ess to 7o-r 3;ed 5le that 7o- wish to $rogram3
Press the 9Load: .-tton
<ind 7o-r 3;ed 5le3
!ele,t 9Ces: A i3e3 De.a/lt F/se to &.
Press 8T
Ens-re that 9Erase: 9Che,@: 9Prog: and 9*erif7: are ,he,@ed to r-n3
Ens-re that 9Prot: is not :$e:Be' to r-n3
Press the green arrow .-tton in the .ottom right ,orner to $rogram the ,hi$3
(evise') Augus" 200* Page 1&+1&

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