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Introduction To PLLS: Behzad Razavi Electrical Engineering Department University of California, Los Angeles

This document provides an introduction and overview of phase-locked loops (PLLs). It discusses the need for frequency synthesis when a local oscillator frequency is not exactly what is needed. It also describes the basic components of a PLL, including the phase detector, voltage-controlled oscillator (VCO), and charge pump. The document outlines the PLL design procedure and discusses non-idealities that can occur in the phase frequency detector and charge pump components. It provides examples of simulated PLL behavior for different component values.

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123 views30 pages

Introduction To PLLS: Behzad Razavi Electrical Engineering Department University of California, Los Angeles

This document provides an introduction and overview of phase-locked loops (PLLs). It discusses the need for frequency synthesis when a local oscillator frequency is not exactly what is needed. It also describes the basic components of a PLL, including the phase detector, voltage-controlled oscillator (VCO), and charge pump. The document outlines the PLL design procedure and discusses non-idealities that can occur in the phase frequency detector and charge pump components. It provides examples of simulated PLL behavior for different component values.

Uploaded by

girishknath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1

Introduction to PLLs
Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles
2
Outline
Need for Frequency Synthesis
Phase Detector
Type I and II PLLs
PFD/Charge Pump Nonidealities
PLL Design Procedure
3
The Need for RF Synthesis
What happens if the LO
freq is not exactly what we
want?
Need a freq. synthesizer:
4
Mathematical Model of VCO
What happens if a small
sine appears on Vcont?
5
Phase Detector
6
Problem of Phase Alignment
Loop is locked if phase difference is constant.
7
Example
Ripple modulates VCO,
producing sidebands.
8
Response to Frequency Step
9
Response to Phase Step
10
Phase and Frequency Settling
11
PLL Dynamics
How do we compute the time or frequency
response of a PLL?
12
Type I PLL
Trade-offs among stability,
ripple, and phase offset
Limited capture range
Why is this better than a piece
of wire?
13
Frequency Multiplication
Voltage Type
Phase or Freq Type
How do these change for this type of loop:
14
Aided Acquisition
15
PFD Implementation
Reset pulses are ~ 5 gate delays
wide.
Reset pulses are necessary to
avoid dead zone.
16
PFD and Charge Pump
Infinite gain yields zero phase
offset.
Q
A
and Q
B
are called Up and
Down pulses, respectively.
17
PFD/CP/Capacitor Behavior
18
First Attempt to Close the Loop
19
Type II (Charge-Pump) PLL
20
Frequency Multiplication Revisited
21
PFD/CP Nonidealities
Skew between Up and Down
Pulses
Mismatch between Up and Down
Currents
Charge Sharing
Channel-Length Modulation
Charge Injection Mismatch
22
Problem of Skew
23
Up and Down Current Mismatch
Produces both ripple and phase offset.
24
Channel-Length Modulation
Ix
Vx
W/L
N
=10 um/60 nm
W/L
N
=20 um/120 nm
25
Reduction of Channel-Length Modulation
[Lee, Elec. Let., Nov. 00]
[Terrovitis, ISSCC04]
26
Reduction of Both Mismatches
[Wakayama, US Patent 7,057,465 B2]
(Also, see Gierkink, ISSCC08]
27
Addition of Second Capacitor
C
2
can reach 0.2Cp with little degradation in
settling behavior.
But imposes an upper bound on Rp.
28
PLL Design Procedure
Design VCO for frequency range of interest
and obtain K
VCO
.
Set the loop bandwidth to one-tenth of
input frequency:
(Loop BW ~ 2.5
n
for = 1.)
Select a charge pump current (tens of
microamps to some milliamps).
Set the damping factor to 1 and compute
Rp and Cp.
29
Charge Pump Design
Select W/L of current sources for an overdrive of about
50-100 mV.
Choose L such that mismatch due to channel- length
modulation remains below 10-20%.
Choose switch dimensions for a headroom consumption
of 20-30 mV.
If mismatch due to channel-length modulation results in
excessive jitter or sidebands:
(a) Increase C
2
and Cp (BW goes down).
(b) Use one of the circuit techniques to reduce
effect of channel-length modulation.
M=4
K
VCO
=148 MHz/V
235 MHz
Ip=0.5 mA
30
Simulated Behavior
R
p
=3 k
Cp=25 p
C
2
=2.5 p
R
p
=1.5 k
Cp=25 p
C
2
=2.5 p
R
p
=1.5 k
Cp=25 p
C
2
=5 p
R
p
=3 k
Cp=25 p
C
2
=5 p
R
p
=6 k
Cp=25 p
C
2
=5 p
R
p
=12 k
Cp=25 p
C
2
=5 p

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