Timing Analysis of a Source Synchronous

Interface Using ALTLVDS

Version 1.0 Page 1 of 6 Q307
A source synchronous interface is one where clock and data are sent together and the transmit
clock is used to cature the data at the recei!er. "here are two tyes of source synchronous
interfaces in an Altera
#
$trati%
#
and $trati% && 'P(A. "here is one that uses a dedicated
transcei!er like the A)")V*$ +lock and one that uses (P&, -general urose &,.. /oth tyes of
interfaces are a common in 'P(A designs. 0owe!er1 each re2uires uni2ue methodology for
analy3ing timing to determine margin. "his aer will focus on timing analysis using A)")V*$
transcei!ers. "he A)")V*$ +lock only e%ists in the $trati% family of 'P(As1 thus only alies to
$trati%1 $trati% && and $trati% &&& designs using the A)")V*$ +lock.
1
"he (P&, should +e used for
e!ery interface not using A)")V*$4 this method is discussed in other aers osted on the Altera
forum -"a+le 1..
"a+le 1
5"iming Analysis of $ource $ynchronous ,ututs6
htt788www.alteraforum.com8forum8attachment.h9attachmentid:30;d:117<03==1>
5?entering the ?lock in the *ata Valid @indow for $ource $ynchronous &nuts6
htt788www.alteraforum.com8forum8attachment.h9attachmentid:31;d:117<03=33>
Altera carefully designed the A)")V*$ +lock in the $trati% family so it would +e easy to close
timing. &n fact1 the interface is guaranteed to work at seeds +eyond 1.0 (+s in $trati% &&&
de!ices without much effort. 0a!ing a system work theoretically and showing it will work in a real
system are different challenges. "he methodology re2uired to analy3e A)")V*$ timing will +e
shown in the first section.
"he second section will touch on the ro+lem of trace mismatch. ,n a real P?/1 it can +e difficult
to erfectly match e!ery data +it and clock +it. A trace mismatch can negati!ely imact your
timing margin. "he ro+lem of trace mismatch can +e eliminated with a technology called
*ynamic Phase Alignment -*PA.. 0owe!er1 with *PA mode1 +ecause of its dynamic nature1
there is no way to analy3e timing. "he 2uandary of not +eing a+le to do a full timing analysis is
not a ro+lem +ecause the A)")V*$ circuit in this mode is cali+rated to ideal conditions.
"he last section will focus on using the Quartus
#
&& "imeQuest "iming Analy3er and ?lassic
"iming Analy3er -"AA. to analy3e timing. Prior to Quartus && !ersion 7.11 it was difficult to get an
accurate timing analysis using "imeQuest. BCP,B"DB$EF and BCP,B"D"??$ are new
commands in Quartus && !7.1 which will make analy3ing timing with circuits that use A)")V*$
modules easy. "hese commands will +e e%lained in detail.
"his aer looks at timing analysis from a datasheet aroach. &n this case1 the 'P(A is treated
like a +lackG+o% to the +oard designer. ,nly the &8, timing of the de!ices need +e secified. ,nce
you know the &8, timing num+ers and +oard skew1 you can calculate if margin e%ists. "his
calculation can +e done +y hand initially. Hltimately1 you will use a timing analysis tool like
"imeQuest.
Margin Analysis using ALTLVDS Receiver:
Altera offers dedicated circuitry in $trati%1 $trati% && and $trati% &&& de!ices to make it easy to
achie!e high transfer seeds. "his circuitry makes it easier to achie!e a ro+ust highGseed
connection to and from the 'P(A. "he A)")V*$ +lock is hand otimi3ed during chi design to
center the samling window -$@. to the data !alid window. "he $@ can +e !iewed as the
re2uired setGu and hold window including all clock uncertainties. "he )V*$ circuitry is designed
where+y the samling window is centered to the !alid data. "his is an imortant oint that is often
o!erlooked since we are accustomed to thinking a+out the clock +eing centered to the data. "he
concet of +alancing the samling window is imortant +ecause it insures that you can always
1
?yclone
#
&1 &&1 &&& families also ha!e an A)")V*$ +lock1 +ut it is not imlemented in hard silicon
and thus uses the (P&, method.
Version 1.0 Page = of 6 Q307
cature your data if the data is resent at the ins for a time e2ual to $@. "he actual t$H and t0
num+ers are ignored in this scenario since they are guaranteed +y the $@ arameter.
"he $@ is characteri3ed across PV" and is guaranteed +y design. "his circuit has ro!en to +e
ro+ust in Altera de!ices and has +een used in hundreds of designs at seeds ranging from =00
F03 to o!er 1 (03.
'or more information on $@ characteri3ation1 contact Altera Alications and ask for
the )V*$ characteri3ation reort.
$ince the Quartus && software can not analy3e t$H and t0 for A)")V*$ +lock1 you must use the
Becei!er $kew Fargin -B$EF. e2uation to calculate timing margin.
@hen you use the A)")V*$ +lock1 you are configuring the hidden circuitry of the dedicated
transcei!er. "he Quartus && Fega@i3ard
#
PlugGin Fanager can +e used to configure the A)")V*$
+lock.
0ere is a highGle!el e%lanation of what is +eing defined when you use the Fega@i3ard PlugGin
Fanager7
1. *efine deseriali3ation factor
=. *efine clock to data relationshi
3. *efine fre2uency of the inut clock.
"here are lots of other otions1 +ut this co!ers what is haening at the most +asic le!el.
"hese arameters configure the P)). "hey also tell the A)")V*$ +lock how many +its of data will
+e resented to the core and at what clock fre2uency.
"he P)) is configured in the Fega@i3ard +y secifying the deGseriali3ation factor of the data with
resect to the data rate. 'or e%amle1 an )V*$ inut with a deGseriali3ation factor of I and a data
rate of I00 m+s results in I +its of data at a 10 ns eriod inside the 'P(A. "his also means that
the V?, is running at I00 F03 caturing 1 +it of data on e!ery clock cycle. "he clock to data
relationshi is also considered.
=
$ince the P)) will align the inut clock edge with the V?, clock edge1 the )V*$ circuitry must
adJust the clock edge so it is in the middle of the data. "he user defines the clock to data
relationshi and the Quartus && software will choose the A)")V*$ settings for all +its so that the
$@ is +alanced. "his is done once -statically. and is defined in the +it stream.
Calculating RSKM:
B$EF : H& K "??$ K $@ -you ha!e margin if B$EF is ositi!e.
2
/ased on the clock to data relationshi entered +y the user1 the internal clock will automatically
+e adJusted in I< degree increments of the +it eriod to ensure the clock is centered in the data.
'or e%amle if the clock and data are recei!eGedge aligned1 the P)) will automatically create the
shift necessary to ut the clock in the middle of the data +its.
Version 1.0 Page 3 of 6 Q307
'igure 1. $amle "iming /udget *iagram
Receiver Se! Margin "RSKM# : Fargin or slack at the recei!er cature register.
UI : Hnit inter!al
Transmitter "T$# Channel%to%Channel Se! "TCCS# : sum of all "L uncertainties.
"he timing difference +etween the fastest and slowest outut
edges on data signals1 including t?, !ariation1 clock skew1 and
Jitter. "he clock is included in the "??$ measurement and ser!es
as the time reference. /oard !ariations should also +e added to this num+er.
Receiver "R$# Sam&ling 'in(o! "S'# Re)uirement : $um of all BL re2uirements.
"he eriod of time during which the data must +e !alid in order
to cature it correctly. "he setu and hold times determine the
ideal stro+e osition within the samling window.
B$EF defines the amount of margin on a gi!en source synchronous interface for the recei!er
and is made u of $@ and "??$. $@ is guaranteed to +e +alanced +y design and is
characteri3ed across PV" to meet the secifications u+lished for each de!ice family. "??$ is
also guaranteed +y design and is Just as carefully characteri3ed in reference to the transmitter.
"he $@ arameter is e%lained in the re!ious section.
"??$ defines the a+solute skew in t?, +etween the two e%treme channels across a multiG
channel interface across PV". &n other words1 no two +its in a multiGchannel interface will ha!e a
skew greater than "??$. "his num+er includes t?, !ariation1 clock skew1 and Jitter. Altera has
taken great care on the dedicated )V*$ "L ins to closely match ackage skew so that t?,
!ariation is low. &f you are using another de!ice that doesnt characteri3e "??$1 you can calculate
"??$ yourself. "imeQuest has a con!enient way of doing this for your inuts using the
&APH"DFALD*C)AM and &APH"DF&AD*C)AM.
"??$ : -greatest difference +etween t?,. N clock skew N Jitter
"his calculated "??$ can now +e used to calculate B$EF for an Altera recei!er.
(i!en a I00 m+s )V*$ interface +etween two $trati% 'P(As you ha!e the following7
"??$ : =00 s
$@ : II0 s
H& : =.< ns
B$EF : =<00 K =00 K II0 : 1O60s
"his articular e%amle does not account for +oard trace mismatch or other clock uncertainties.
"he ro+lem of trace mismatch will +e co!ered in the ne%t section. Mou can su+tract clock
uncertainties from B$EF if you wish1 +ut this is not necessary as long as you meet the )V*$
secifications u+lished in the datasheet.
Version 1.0 Page I of 6 Q307
RSKM Summary:
B$EF is an industry standard way of calculating recei!er margin or slack for a source
synchronous interface. B$EF is e2ual to the H& G "??$ K $@. 'or $trati%1 $trati% && and $trati% &&&
de!ices1 $@ and "??$ are arameters that are carefully characteri3ed and can +e used to
model the samling window of a recei!er channel and !ariation of a transmitter channel. "his is
the only way to calculate slack on a source synchronous interface that uses the A)")V*$
recei!er +lock.
*oar( Trace Mismatch:
"he B$EF analysis a+o!e gi!es you the margin at the recei!er gi!en ideal +oard conditions. &n
realGworld systems1 there is going to +e some trace mismatch on your +oard. "here are two ways
you can account for +oard trace mismatch. &n a source synchronous interface1 you always
measure data skew with resect to the transmit clock. Hsing the clock as your reference channel1
you can take the +est and worst case conditions +etween the clock and each data channel. "he
second more essimistic aroach is to take the worst case condition on the +us and aly it to
e!ery data +it on the +us.
Hsing the B$EF e2uation you would now ha!e7
B$EF : H& K "??$ K $@ K +oard skew
(i!en a I00 m+s )V*$ interface +etween two $trati% 'P(As1 you ha!e the following7
"??$ : =00 s
$@ : II0 s
H& : =.< ns
Aow consider the +oard trace delay. "yically these num+ers are gi!en in a Fanhattan reort in
terms of length !ariation.
3
'or illustrati!e uroses1 we will simly look at skew as the time
difference +etween the clock and the data.
?lock skew is reference 0
*ata-0. : =0 s greater than clock
*ata-1. : 30 s less than clock
*ata-=. : 30 s less than clock
*ata-3. : 30 s greater than clock
"he difference +etween the worst case clock comared to data is 30 s on each side1 so +oard
skew is 60 s. "he +oard skew reduces margin so this must +e accounted for.
B$EF : =<00 K =00 K II0 K 60 : 1O00s
*ynamic Phase Alignment -*PA. is a feature in the A)")V*$ +lock that eliminates +oard trace
skew ro+lems. *PA ena+les seeds +eyond 1 (+s. &t is imossi+le to do an e%act timing
analysis when using *PA since the +oard skew factors are comensated for dynamically.
As long as you are meeting the inut re2uirements of the A)")V*$ +lock and your +oard skew
isnt greater than the H&1 timing can +e met. Please refer to the *PA section of the de!ice user
guide for more information on *PA.
Timing Analysis using Time+uest:
3
Fost +oard designers get their skew num+ers from the Fanhattan reort from the design house1
which will gi!e the !ariation in length -in inches or cm.. ,nce you ha!e the lengths you can take
the ma% and min trace length num+ers and su+tract them1 and then multily +y 166 s8inch to get
the +oard trace skew. "his is indeendent of the relationshi of the data to the clock.
Version 1.0 Page < of 6 Q307
"he BCP,B"DB$EF and BCP,B"D"??$ are two features that were added to Quartus && !7.1
software that ena+le source synchronous timing analysis when using the A)")V*$ Fegafunction.
BCP,B"DB$EF reorts the recei!er inut skew margin -B$EF. for the data in1 recei!er
channel1 and clock in each )V*$ register in the design. BCP,B"DB$EF is a "imeQuest
command that will reort Becei!er $kew Fargin -B$EF : H& K "??$G $@.. "??$ will +e
reorted as 0 s unless you secify &APH"DFALD*C)AM and &APH"DF&AD*C)AM !alues for the
data inuts. Again1 the "??$ reorted when running the BCP,B"DB$EF command is wholly
deri!ed from the &APH"DFALD*C)AM and &APH"DF&AD*C)AM you entered for the )V*$ inuts.
BCP,B"D"??$ reorts the actual transmitter channelGtoGchannel skew -"??$. for the data
outut in1 transmitter channel1 and clock in each )V*$ circuit in the design. "his reort shows
you the "??$ for the outut )V*$ channel and does not relate to the "??$ shown in the
BCP,B"DB$EF timing reort.
"he BCP,B"D"??$ !alues do not include any +oard skew. /oard skew needs to +e considered
along with the "??$ when entering an &APH"DFALD*C)AM and &APH"DF&AD*C)AM.

Summary:
A)")V*$ is a technology that makes imlementing a highGseed )V*$ channel easy. "he timing
analysis methodology is uni2ue when comared to (P&,. Hsing the B$EF method with the
"??$ and $@ arameters shows the amount of margin that is a!aila+le on an interface.
/oards skew must also +e considered. *PA can eliminate much of the trace mismatch ro+lem.
$ince the circuit is dynamically configured you cannot erform an e%act static timing analysis.
0owe!er1 if you follow the set guidelines1 you will ha!e a ro+ust relia+le interface that can
comensate for real world imerfections in trace length.
"he methodology descri+ed in this document only alies to )V*$G+ased transcei!ers in $trati%
family de!ices. "here are two e%cellent documents that descri+e timing analysis using (P&,
referred to in "a+le 1.
'inally1 the Quartus && "imeQuest timing analy3er ro!ides easy to use commands that ena+le a
user to 2uickly e%tract the source synchronous timing arameters. "hese reorts will allow a
designer to e!aluate the margin in their sourceGsynchronous interface.
Version 1.0 Page 6 of 6 Q307