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M.tech Algorithm For Vlsi Design Automation

NR Code No: 54217 / MT M.Tech. II-Semester Examinations, August / September-2007. Time: 3 hours Answer any FIVE questions All questions carry equal marks.

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315 views

M.tech Algorithm For Vlsi Design Automation

NR Code No: 54217 / MT M.Tech. II-Semester Examinations, August / September-2007. Time: 3 hours Answer any FIVE questions All questions carry equal marks.

Uploaded by

srinivas
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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NR

Code No: 54217/MT

M.Tech. II-Semester Examinations, August/September-2007.

ALGORITHMS FOR VLSI DESIGN AUTOMATION


(VLSI System Design)

Time: 3 hours Max. Marks: 60

Answer any FIVE questions


All questions carry equal marks
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1.a) Draw the sketch of Gajskis’ Y-chart and explain about the visualization
of the three design domains.
b) Using the Y-chart explain about the design methodology based on top-
down structural decomposition and bottom up layout reconstruction.

2.a) Give an example of a directed graph and explain about the same.
b) Give the adjacency list representation of the above graph.

3.a) Write an algorithm for branch and bound method.


b) Draw a graph to illustrate Integer Linear Programming.

4.a) Explain about Maximum-distance constraints.


b) Explain about the Bellman-Ford Algorithm.

5.a) Explain about ROBDD principles.


b) Give a Heuristic based on ROBDDs.

6.a) With an example explain about a simple Data Flow graph.


b) Explain about Iterative Data Flow.

7.a) Give the physical Design cycle for FPGAs and explain about the same.
b) Explain about partitioning for segmented models.

8. Write notes on any TWO:


(a) MCM technologies
(b) Chip Array based Approaches
(c) Multiple Stage Routing
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