DipTrace Tutorial

This document allows you to get started with ease by designing simple Schematic and its
PCB, pattern and component libraries, then trying different package features. The tutorial
includes step-by-step design guide and many additional insets that allow you to discover
program features. f you have any !uestions while learning the tutorial, contact our
support staff" support#diptrace.com. $e will be happy to be of assistance and gladly
answer all your !uestions. This version of tutorial was created for %ipTrace ver. &.'.'(
)build *ebruary &', &''+,.
Content
I. Creating a simple Schematic and PCB
(. -stablishing a Schematic Si.e and Placing Titles /
&. Configuring 0ibraries 1
2. %esigning a Schematic 3
/. Converting to a PCB &2
4. %esigning a PCB &/
4.( Preparing to 5oute &/
4.& 6utorouting &1
4.2 $orking with 0ayers 2'
4./ 7easuring Trace 0ength 2&
4.4 7anual 5outing
4.8 $orking with 9ias
4.1 Selecting :b;ects by Type<0ayer
2/
21
/&
4.3 Placing Te=t and >raphics //
4.+ Copper Pour
4.(' 0ocking :b;ects
4.(( %esign 9erification
4.(& %esign nformation
4.(2 Paneli.ing
/1
4'
4(
42
4/
4.(& Printing 44
8. 7anufacturing output 41
8.( %?* output 41
8.& >erber output 8'
8.2 Create @C %rill *ile for C@C 7achine %rilling 8/
II. Creating Libraries

(. %esigning a Pattern 0ibrary 84
(.( Customi.ing Pattern -ditor 84
(.& %esigning a 5esistor 88
(.2 Saving library 1&
(./ %esigning a Capacitor 12
(.4 %esigning a %P (/ Pattern 18
(.8 %esigning a %P Pattern with a 9ariable @umber of Pads 1+
(.1 Placing the Patterns 3(
&. %esigning a Component 0ibrary 3/
&.( Customi.ing Component -ditor 3/
&.& %esigning a 5esistor 38
&.2 %esigning a Capacitor 3+
&./ %esigning a 7ultipart Component +8
&.4 %esigning 9CC and >@% Symbols ('&
&.8 Asing 6dditional fields ('/
&.1 Spice Settings
&.3 Placing the Components
('1
('+
III. Using different package features
(. Connecting ((/
(.( $orking with buses and page connectors ((/
(.& $orking with net ports ((3
(.2 Connecting without wires ((3
(./ Connection manager in Schematic and PCB 0ayout (&'
&. 5eference %esignators (&(
2. Bow to find components in libraries (&4
/. -lectrical 5ule Check (&8
4. Bill :f 7aterials )B:7,
8. mporting<-=porting net-lists
1. Spice Simulation
3. Checking @et Connectivity
+. Placement features
('. *anout
((. Bierarchy
(&3
(2'
(2&
(24
(21
(/&
(/4

&
I. Creating a simple Schematic and PCB.
This part of tutorial will teach you how to create a simple schematic and its PCB )Printed
Circuit Board, using %ipTrace program.
This is a schematic that you will be creating using %ipTrace schematic capture module"
:pen %ipTrace Schematic Capture module, i.e., go to Start 6ll Programs %ipTrace
Schematic
f you run Schematic program first time, you will see the dialog bo= for graphics mode
and color scheme selection.
Cou can select graphics mode that is better for you"
(. %irect2% is the fastest mode for typical $indows PC and we recommend to use it if it
works on your system correctly and you havenDt Bigh--nd >raphics System with
:pen>0 hardware. Bowever this mode also depends on hardware<drivers<versions, so
small percent of computers )usually with very new<buggy or very outdated :S<drivers,
can have issues with it )artefacts on the screen or some ob;ects disappear,.
&. :pen>0 usually works a bit slower than %irect2%, however it is more universal for
different operating systems and less dependent on hardware<drivers. 6lso it will be the
best choice for high-end engineering<graphics stations with professional :pen>0 graphic
cards. 6nyway you can try both modes on heavy pro;ects and choose the best for you.
2. $indows >% can be used as alternate mode if both %irect2% and :pen>0 donDt work
correctly with your graphics card. t is much slower but doesnDt depend on
2
drivers<hardware<:S. 6lso this mode is enough for comfortable work on small and
medium-si.ed pro;ects.
$e will use white background as more acceptable for printing this tutorial, you can select
the scheme you want. 6lso notice that you can change color scheme or define colors you
want any time from 9iew<Colors.
The same dialog bo= will appear in PCB 0ayout module. Component -ditor and Pattern
-ditor use color settings of Schematic Capture and PCB 0ayout accordingly.
6lso we will hide design manager < properties panel to add more design space. *or our
3''=8'' tutorial resolution this is important, but if you have large resolution you can skip
this step and use design manager < properties panel. Select 9iew<Toolbars<%esign
7anager from main menu.

1. stablishing a schematic si!e and placing titles.
-stablish a schematic si.e and place a drawing frame" *ile < Title E Sheet Setup, select
F6@S 6G in the FSheet TemplateG bo=. Then go to the bottom of the screen, check the
F%isplay TitlesG and F%isplay SheetG bo=es.
@otice that you can show<hide Titles and Sheet by selecting F9iew < %isplay TitlesG and
F9iew < %isplay SheetG from main menu.
Press the F-F button until the drawing frame can be seen. @otice that FHG< FIF or mouse
wheel allow you to .oom on the schematic. f a mouse arrow points to the component or
to the selected area, the FJoomG can be achieved by pressing FHG < F-F or scrolling mouse
/
wheel. 6lso you can change .oom by selecting appropriate value from the scale bo= on
standard panel or simply typing it there.
To enter the te=t into the title field move the mouse arrow over that field )it should be
highlighted in green,, then left-click on the field to see the pop up window with *ield
Properties dialog bo=. n that dialog bo= you can type the te=t, define the alignment )0eft,
Center or 5ight, and *ont. n your case, type F6stable *lip *lopG, press F*ontG button
and set the font si.e to F(&G. Then click F:KG to close that dialog bo= to apply changes.
@otice that you can also enter multi-line te=t into the title block fields.
4
Cou may .oom on the Title Block by moving the mouse arrow on it and pressing the FHG
repeatedly or scrolling mouse wheel up. @otice that you can use FJoom $indowG tool to
.oom on the defined rectangle of the design area" click on the FJoom $indowG tool )the
second button to the left of the scale bo=,, move mouse arrow to the upper left corner of
the area that you want to .oom on, hold down the left mouse button and move the mouse
to the opposite corner and then release the mouse button. To return to the previous scale
and position, use FAndo ScaleG tool )the button on the left side of the scale bo=,.
8
>o to *ile and select LSave 6sM, type a name of the file you want to use and make sure
that it is in the needed directory. Press LSaveM.
". Configuring libraries
Before first using Schematic Capture and PCB 0ayout, you might want to setup your
libraries. >o to 0ibrary0ibrary Setup"

1
@otice that on the right side you may see a te=t F@o 0ibrary *ileG, disregard it and scroll
down using the scroll button on the right side of the F6ll 0ibrariesG bo=. 6fter scrolling
down, you will see all libraries that came with your software.
%ipTrace package has two modes to activate libraries"
(. To get libraries from a specified folder"
This mode is active if F>et 0ibraries from *olderG bo= is checked, in the upper left corner
of the F0ibrary SetupG window. To define the folder with libraries press FNG button on
the right side of folder path. 7ake sure that you find the L0ibM directory that came with
the program. 0ater, you can point to any other location )for e=ample, you may point to a
library named LmylibM which you would create to store your own symbols, but in the
beginning, before you become familiar with L0ibrariesM concept, please follow our
suggestions.
&. To activate libraries using the list"
This mode is active if F>et 0ibraries from *olderG bo= is unchecked. The list of active
libraries is enabled in this mode and you can edit it using the buttons at the right side of
this list" FOOG I adds the selected library from 6ll 0ibraries list, FNG I adds the library
from hard drive, F6rrow ApG I moves the selected library up, F6rrow %ownG I moves
the selected library down, F%elG I deletes selected libraries from 6ctive 0ibraries list.
@otice that the first mode is enabled by default.
6ll known libraries are placed automatically to 6ll 0ibraries list )on the right side of the
dialog bo=,. 6lso you can add or delete libraries from that list using F6ddG or F%eleteG
buttons.
Close the 0ibrary Setup dialog bo= and all changes, if made, will be applied to the
0ibraries panel.
f you want to move components from a design to a library, select these components,
move a mouse arrow over one of them, right-click, then select FSave to 0ibraryG. *rom
the FSave to 0ibraryG submenu you can add the selected component to active library
)shown on the left side of screen, or save them to a different library.
#. Designing a schematic
:pen Schematic Capture module and using a mouse arrow, select a library named
FTransistorG in the upper right part of the screen and click on the FTransistorsG button.
@otice that you can scroll libraries left and right using arrow buttons on the right side of
those buttons.
Scroll down the component list on the left side of the screen, to the transistor &@//'( and
click on it. That will select a symbol and allow you to move it to the schematic. 7ove the
mouse arrow to the schematic and left-click once - that will place a transistor on the
schematic. To disable a placement mode, right-click.

3
Bow to move a symbol aroundP Bold down the left mouse button on the symbol and
move it until you find a proper place for it. f you need to move several symbols you
should select them first, then drag-and-drop. To select a single symbol, left-click on it. f
you want to select several symbols, press and hold down a FCtrlG button and click on
each symbol that you want to select in your group of symbols. 6lso you can select the
group of symbols using a different way" move mouse to the upper-left corner of the
group, hold down the left mouse button, move cursor to lower-right corner and release
the mouse button )if the Ctrl key is pressed, the selection will be inverted,.
@otice that a L5eference %esignatorM of the transistor is A(. f you prefer to change it to
Q(, place a mouse arrow over the A( and right-click on it, then select a top item
)%esignator, from the submenu. $hen a dialog bo= will pop up, type a new designator, in
this case FQ(G"
$e need two transistors for our schematic, so select F&@//'(G in the component list )on
the left side, and place it in the design area - the sheet you are working on. @otice that
you donMt need to rename the second transistor to FQ&G because itMs done automatically.
f you want to rotate the symbol before placing it on the schematic, press a Space Bar or
F5G button.
+
Select a library named F%iscreteG on the library panel and find a suitable resistor.
Select 5-S/'', which designates a resistor with /'' mils of lead spacing. By the way, if
you prefer a drawing in metric units, go to F9iew < Anits < mmG.
('
Change a reference designator of your resistor to 5(. Place a mouse arrow over a resistor,
right-click on it, select top item from the submenu and change FA(G to F5(G, then click
F:KG.

$e need / resistors on the schematic. @otice that you can simply place them from a
component panel on the left, the same way you placed the Q( and Q&, but now we will
use another method. Select your resistor like in the picture above then copy it 2 times.
Cou can use & ways to copy this symbol"
(. Simply select F-dit < CopyG from the main menu, then select F-dit < PasteG 2 times or
right-click in the position where you want to place copy and FPasteG from pop-up menu.
&. The second method is named FCopy 7atri=G. Select your resistor, then F-dit < Copy
7atri=G from the main menu )or simply press FCtrlH7G,.

((
n the FCopy 7atri=G dialog bo= define the number of columns and rows )in our case F&G
columns and F&G rows to get / resistors, and spacing )in our case ( inch for columns and
'./ inch for rows,, then click F:KG. @ow you can see the resulted matri= of resistors"
7ove resistors to a proper location on your schematic and rotate by +' degrees, use a
Space Bar or F5G button to rotate a symbol. 6nother possibility to rotate is by using F-dit
< 5otateG command or right-click on the symbol and F5otateG from the submenu.
Cou can use Shift key for orthogonal moving )by single coordinate only, if necessary.
@otice that you can scroll the design by using the right mouse button or mouse wheel"
move mouse arrow to the design area, then hold down the right mouse button or mouse
wheel and scroll your design to a new position.
(&
@ow we will display component types for the transistors" select the components Q( and
Q&, then right-click on one of them and select FPropertiesG from the submenu. Click on
the tab F7arkingG in the component properties dialog bo=.
(2
Select FTypeG in the field FShowG for additional marking. This will show type of the
selected components. @otice that descriptors are already displayed and F%efaultG defines
the use of general Schematic settings for the components, so displaying 5ef%es is a
general property. Click F:KG to close the dialog bo= and display the type of transistors.
Show pin numbers by selecting F9iew < Pin @umbers < ShowG if they are not shown yet.
@otice that you can change numbers showing for selected patterns using right-click on
the pattern and FPin @umbersG from its submenu.
Cour FTypeG markings and pin numbers )B, C, -, cross over other symbol graphics, so
you should move them around. To move the te=ts around, select F9iew < Part 7arking <
7ove ToolG from main menu or simply press F*('G and then move Types and pin
numbers. 6lso you can rotate pattern markings while moving by pressing F5G or FSpaceG
key. By the way, in F9iew < Part 7arkingG submenu you can define general settings for
part markings. >eneral settings of markings are applied to all schematic parts, e=cept
ones which have their own settings )in our case the transistors have their own settings,.
@ote" you may use command F-dit < AndoG or click on the corresponding button in the
top of the schematic window if you want to go back to the previous version of schematic.
The program saves up to 4' steps. 6nd you may use L5edoM button which is a functional
opposite of LAndoM. 5emember to save the schematic" Select F*ile < SaveG from main
menu or click on the FSaveG button in upper-left side. f the schematic is still not saved,
the FSave 6sG dialog bo= will be opened to define the file name. f the file name is
already saved, you donMt need to type it again, but click on the FSaveG button or press
FCtrlHSG only. f you need to define another file name, for e=ample for backup purpose,
select F*ile < Save 6sG from the main menu.
(/
Connect the resistor 5( to the base of transistor Q(" place a mouse arrow on the bottom
tip of the resistor 5( and left-click. 7ove the mouse arrow down and right to the base of
transistor Q( and left-click to connect the wire between 5( and base of Q(.
To mirror the transistor Q&, place the mouse arrow over Q& and right-click to select *lip
and Bori.ontal"
(4
To move the resistor, place a mouse arrow over it, then left-click and hold while moving
a component around. $hen in a correct position, release the left button. Connect 5/ to
the base of Q&, 5& to FCG pin of Q( and 52 to FCG pin of Q&"
(8
@otice that the wire is not straight between 52 and Q&R move transistor Q& by placing a
mouse arrow over Q&, clicking left mouse button and holding it while moving Q& left
until the wire connecting collector 52 and collector Q& becomes a straight line. This is
not important for electrical connectivity but only from aesthetic point of view.
Select C6P(''5P and place twice. Then change A( and A& reference designators to C(
and C&. @otice that you can place the first capacitor, rename its descriptor only and then
place the second one, or use FCopyG function to create the second capacitor.
*lip C&, so the plus sign is on the right side, by placing a mouse arrow over C&, right-
click and select *lipBori.ontal.
7ove capacitors C( and C& between transistors Q( and Q( with respect to polarities"
7ove resistors a little to the top to provide more space for connections. @otice that the
wires follow the components" place left mouse arrow over resistor, hold down the left
button while moving 5( up. Select FQ&G, F52G, F5/G and related wires by placing the
mouse arrow in the upper left corner of these ob;ects, then hold down left mouse button
and move to opposite corner I all ob;ects in the rectangle will be selected when you
release the left mouse button.
(1
Connect C( )H, to collector Q(" move mouse arrow to C( )H, pin, left-click, move to the
wire between 5& )6, and Q( )C,, then left-click to connect. @otice that blue s!uares
show the selection, use right-click to clear the selection if you are in the default mode and
double right-click if you are in another mode )first click to disable the mode and the
second one to clear selection,. Connect C& to between Q( base and collector Q&.
(3
Scroll down the component list in the left side to locate the 0-% and place two
components onto your schematic. Then change reference designators to F0-%(G and
F0-%&G, rotate these symbols by selecting them and pressing F5G key or Space three
times and connect to transistors"
(+
Place a battery symbol from L%iscSSchM library. Then change battery 5ef%es and connect
the wires to complete your schematic )see on the picture below,.
f you want to move e=isting wire, move the mouse arrow over it )the net should be
highlighted and mouse arrow shows possible moving directions, then hold down the left
mouse button and move the wire to new position. @otice that if you are in FPlace $ireG
mode and click on the e=isting wire I you start to create a new wire. )FPlace $ireG mode
is enabled automatically when you try to place wire by clicking on some component pin,
also you can put on it by selecting F:b;ects < Circuit < Place $ireG or the corresponding
button on the ob;ects panel in upper side of window,. f some ob;ects are not highlighted
when you move mouse arrow over them try to right-click to turn on the default mode. f
you want to delete the wire )node to node connection, move mouse over it, right-click to
open submenu, then select %elete $ire. To delete wire segment select F%elete 0ineG
from the wire submenu. @otice that you can use FAndoG to return to the previous
version)s, of the schematic.
6dd component values" right-click on F5(G, select FPropertiesG from submenu, type
F/1kG to F9alueG field. Click on F7arkingG Tab and go to
7ain 7arkingShow9alue, then go to 6dditional 7arkingShow5ef%es and
click :K. This screen makes reference designators and component values visible"
&'
-nter the remaining component values. @otice that you can select several symbols and
define 7arking Settings for them all by opening Component Properties dialog bo= only
once.
&(
:ur battery was placed from library %iscSSch. 6ll TSch libraries contain only the
symbols without patterns )you can preview the pattern in bottom left corner before
placement the component,. f you want to convert a schematic to PCB you should attach
the related pattern first, otherwise the conversion will proceed but will show you errors
which will have to be corrected anyway" move the mouse arrow over a battery symbol,
right-click to show the submenu and select F6ttached PatternG. 6dd pattern libraries to
the dialog bo= by clicking F6ddG button in the upper-right and selecting the library on
your hard drive )by the way all standard libraries are in FO%riveU"VProgram
*ilesV%ipTraceV0ibG folder,. Select the library from a library list and the pattern from a
pattern list at the bottom-right side of the dialog bo=. The default battery pattern is
included into Fmisc.libG. %efine pin to pad connections for your component" click on the
pin name in the pin table )left side of the dialog bo=,, then type related pad number in the
FPad @umberG field or simply left-click on the pad in the related pattern graphics )middle
of the dialog bo=,.

$hen the pin to pad connection is done, click F:KG and it will close the dialog bo= and
apply changes.
@ote" some symbols may not have the attached patterns )for e=ample 9CC, >@% or
logical connectors I F@et PortsG, and that will be shown in LerrorsM during conversion to
a PCB.
:ur schematic is ready to convert to PCB. %o not forget to save it by selecting F*ile <
SaveG from the main menu, by clicking on the FSaveG button in the upper left side of
window or simply by pressing FCtrlHSG.
6lso notice that you can print or save the schematic to B7P or WP> file. Select
F*ile<PreviewG from main menu, then press FPrint 6llG to print all schematic sheets,
FPrint Current SheetG to print the selected sheet or FSaveG to produce B7P<WP> file with
defined resolution.
&&
$. Con%erting to PCB
@otice that you can open %ipTrace schematic files )T.dch, from the PCB 0ayout program
But to save your time after creating the schematic simply select F*ile < Convert to PCBG
or press FCtrlHBG in the Schematic Capture module and the PCB 0ayout with your
pro;ect will be opened automatically.
Bowever for $in +3<7- users it is strongly recommended to save your schematic file,
close the program, then run PCB 0ayout and open T.dch file from there. ncorrect
memory sharing in +=<7- may cause program crash while running several package
programs at once. $in @T<&'''<?P users may run several %ipTrace modules at once
without such problems.
6lso notice that in case of incorrect e=it from the program or if you forgot to save the
pro;ect, it is possible to recover the latest ;ob by selecting F*ile < 5ecover SchematicG in
Schematic or F*ile < 5ecover BoardG in PCB 0ayout module.
f you plan to use another PCB 0ayout software to design a PCB or give it to someone
else, you can use netlist e=port feature of Schematic program. Select *ile<-=port<@etlist
from main menu, then netlist format. %ipTrace supports popular netlist formats, such as
Tango, P6%S, P-C6%, etc. 6lso this feature is useful to check net structure.
$e will use %ipTrace PCB 0ayout module to design a PCB for our Schematic.
Place components according to your preferences and design rules. 7oving component
around is accomplished by placing a cursor over the component and dragging it to a
proper location. Press Space Bar or F5G-key to rotate the selected components by +'
degrees. f you need to rotate components by different angle, select them, then make right
click on one of the components and choose F%efine 6ngleG or F5otate 7odeG. 5otate
mode allows you rotate ob;ects freely using mouse.
&2
t is a good practice to keep power supply components in one area and functional blocks
grouped together. f circuit is high fre!uency, apply appropriate layout rules.
Cou can also use auto-placement or placement by list to place components after
converting to Schematic, however this is not necessary for such simple pro;ect. $e will
try these features in Part of this tutorial with more comple= circuits.
@otice that you can renew the PCB from updated Schematic file and keep component
placement and routed traces. Select F*ile < 5enew %esign from SchematicG then find and
open the updated schematic file.
&. Designing the PCB
&.1 Preparing to route
n PCB layout, make reference designators visible" Select F9iew < Pattern 7arking <
5ef%esG. This command allows a global 5ef%es visibility and shows all reference
designators on the screen )e=cept for the components with individual settings,. f the
marking ;ustification doesnMt look acceptable, select F9iew < Pattern 7arking < 7ain <
WustifyG in the submenu select F6utoG or another mode you want. *or PCB 0ayout 9ector
font type is strongly recommended, however you can also use TrueType fonts for non-
-nglish characters )9iew<Pattern 7arking<*ont Type,.
To define the individual parameters for the selected components" right-click on one of the
componentsProperties7arking. 6lso remember that you can use F*('G or F9iew <
Pattern 7arking < 7ove ToolG to move designators.
Probably the configuration of connections after placement is not convenient if you plan to
route the design manually, so select F9iew < Connections < :ptimi.eG from main menu to
optimi.e the connections.
&/
0et us show you how to change the net structure of our design and how to add<remove
connections. This step is not needed for this board, but ;ust to let you know that itMs
possible" move the mouse arrow over any pad )for e=ample 5/ - B,, right-click, then
select F%elete from @etG and the pad will be deleted from the net.
f you would like to add some pad to the net without creating connection )for e=ample
you donDt want to search the design for other pads of that net, move the mouse over that
pad, right-click and select F6dd to @et < Select from 0istG.
@ow move the mouse arrow over this pad, left-click, then move mouse to any other pad
and left-click on it. Cou have built the pad-to-pad connection )should be a blue line,. f
you canMt create such connection, probably you are not in default mode, so right-click to
disable the mode you are in. To delete e=isting connection simply try to create it
repeatedly and select F%elete ConnectionG from the submenu shown.
6lso you can edit the structure of nets from the connection manager. To open it, select
F5oute < Connection 7anagerG from the main menu and you can create new nets and
add<delete pads to<from nets.
f you have changed the structure of nets please press FAndoG until the design structure is
restored. By the way, if you lose the design or schematic because of incorrect e=it from
the program, use F*ile < 5ecover BoardG in PCB 0ayout and F*ile < 5ecover SchematicG
in the Schematic Capture to recover the latest pro;ect.
To protect net structure from accidental change it is possible to use F5oute<0ock @et
StructureG option.
@otice that we havenMt determined the board outline yet. $hen using the autorouter, the
routed area )board polygon, for simple boards a rectangle, is created automatically
depending on the tolerances specified in autorouter setup. But in many cases we re!uire a
fi=ed board si.e and must define it before the component placement and routing. To do
so, select F5oute < Place BoardG or the corresponding button on the routing panel in the
&4
upper side of the screen, then place the board outline polygon by clicking in the key
points, right-click in the final point and select F-nterG.
@otice that you can build arcs in board outline by selecting F6rc 7odeG after right-click.
To insert the point after completing board outline move the mouse over point-to-point
segment then drag-and-drop. $hen you right-click on the point of board outline the
submenu shows where you can make an arc with current middle point or delete the point
from board outline. 6lso notice that point coordinates are shown as hint when the cursor
is placed over the one of board outline point.
6lso, you can define the board key points and<or si.e from the Board Points dialog bo=.
To open it, select F5oute < Board PointsG from the main menu.

&8
n this dialog bo= you can 6dd, nsert and %elete the key points. The coordinates can be
shown and edited in the absolute and incremental modes )the second mode usually is
more convenient,. f you check F6rcG bo= for some point, that point will be the middle of
arc and neighboring points I start and end of it. *or rectangular boards, check FCreate
5ectangular BoardG bo= and simply define the first point )base,, width and height of the
board. Then click F:KG to apply changes or FCancelG to close the dialog bo=. @otice that
you can use F5oute < %elete BoardG from main menu if you want to delete the board.
@otice that origin of our design is not defined yet. By default the program places the
origin in the center of screen and doesnDt display it. To display the origin select
F9iew<:riginG from main menu or press *(. @ow the origin )two blue lines, is displayed,
however its position is not correct for our board, so select the origin tool in the top of
screen near 6rrow button )it shows F%efine :riginG hint, and left-click in the bottom left
corner of the board outline.
6ll coordinates in the program will be displayed and edited regarding this origin. 6lso
you can change its position in any time.
@otice that all patterns have their own origin you can define in Pattern -ditor I we will
do it below while designing the library and pattern coordinates are the position of pattern
origin. t will be displayed while placing the pattern or opening schematic if different
from the pattern center point. To show or hide the origin of selected patterns, right-click
on one of them and select FPattern :riginG from the submenu.

&." 'utorouting
@ow it is time to route your board. %ipTrace has a high !uality router, superior to many
routers included in other PCB layout packages available on the market today. 7ost of the
time, a simple PCB like the one shown, can be routed on a single layer )bottom side,,
which obviously presents many benefits for prototyping, like efficiency and speed of
&1
having a finished prototype. The traces might be a bit longer on a single sided PCB vs
two-sided but that most probably will be without effect on most designs.
Cou will first setup the router" go to F5oute < 6utorouter SetupG.
n the >rid 5outer setup dialog bo= uncheck FAse 6ll 0ayersG bo= and change the
number of layers to F(G - routing of traces will be done on the bottom side. @otice that
you can change the autorouting !uality by defining the F6uto SetupG parameter, but
higher !uality autorouting takes more time, makes several routing attempts and chooses
the best layout. 6lso it is possible to autoroute single layer PCBs with ;umper wires
)F6llow Wumper $iresG bo=,. n our case, the board is simple and we can route without
;umper wires, but also it is better to select in 6utoSetup bo= F@ormalG routing mode at
least. Quick mode can be used for non-comple= double-layer PCBs or when you try
preliminary autorouting for large multilayer PCB )where the final routing takes much
time,. Press :K to apply changes.
Then select F5oute < 5oute SetupG, change tolerances to '.'&'G and press :K.
)'.'&' traces are chosen with small prototype builder in mind, who possibly uses a laser
printer to make his bottom side laminations. 6n engineer<technician with preference and
access to A9 light may use '.'(2 traces and less, all depending on a collimating ability of
his e=posure e!uipment,.
Pad Clearance in any case can not be smaller than Trace Clearance, so if you define Pad
Clearance to (2mil and Trace to &'mil, all the pad-to-trace and pad-to-pad clearances will
be not less than &'mil, but you can define for e=ample (2 mil for trace clearance and &'
mil for a pad.
&3
6lso you can define the trace width for each net individually. 7ove the mouse arrow
over some pad of the net you want to change the settings, right-click, then select F@et
PropertiesG. n the net properties dialog bo= you can define the width of traces and trace
to trace spacing for the selected net only. Click F:KG or FCancelG to close the dialog bo=.
@otice that you can use templates to save your time when changing width and clearance
in different dialog bo=es and menus )such as manual routing,. f you want to configure
trace templates select F5oute < Trace TemplatesG from the main menu.
@otice for hobbyists" please be aware of the fact that a laser paper introduces some
degree of dimensional distortion due to heat e=pansion of paper. t all depends on your
laser printer and !uality of paper. *or many people it may be of no significance but for
some it may be important. :ne way to cope with it is to preheat the paper in the laser
printer by running it through a laser printer without printing on it )you may print ;ust a
dot,. *or ink-;ets that is not the case since ink-;et technology does not heat up the paper.
t is not to say that laser printer always distorts the image visibly but rather to make you
aware of possible source of dimensional discrepancies. Scaling an image is one method
or using 6dobe Postscript is another )some prefer >hostScript because it is free,. To
summari.e, there are two methods of prototyping a PCB at home" using a TT )Toner
Transfer, or A9 e=posure. TT is definitely a method for a laser printer and A9 e=posure
is better served by an ink-;et printer.
Time to route your board" F5oute < 5un 6utorouterG The board will be routed. f one or
more wires were not routed try to reroute" select FAndoG or F5oute < Anroute 6llG, then
run the autorouter again. By the way if you define the FBestG !uality in the 6utorouter
Setup dialog bo= probably the autorouter has found the optimal result - so if there are
non-routed traces it means that the tolerances and<or placement of the component have to
&+
be changed - a component has to have more clearance around or the traces are too thick.
Bowever tying to route it again or making better mode may be a solution too.
The %5C )%esign 5ule Check, are running after autorouting and are showing possible
errors if e=ist )red and blue circles,. Please correct the errors and rerun %5C by selecting
F5oute < Check %esignG from main menu or the corresponding button in upper side of the
screen. To change the design rules select F5oute < %esign 5ulesG from main menu. To
hide red circles select F5oute < Bide -rrorsG. 6lso you can disable the %5C after
autorouting, simply uncheck corresponding bo= in the route setup dialog bo= )F5oute <
5oute SetupG from main menu,.
@otice that if you want to finish your pro;ect faster, you can skip all topics until
FPrintingG )4.(&, because your PCB is ready to output. But if you want to learn some
features of PCB 0ayout )that can be learned with this design and probably are useful for
your further pro;ects, in depth we recommend to learn the topics 4.2 I 4.((.
&.# (orking )ith la*ers
The traces that you can see are gray because they are placed on the bottom layer and
your active layer is Top. 6lso the program has FContrastG mode to display layers by
default. Change the active layer" move mouse arrow to the list bo= in the upper right with
FTopG te=t and select FBottomG. By the way, there are two such lists" the first is used to
choose the placement side )located on the ob;ects panel near component placement tool,
and the second one to change active signal<plane layer )located in the right corner of route
panel,R you can move the mouse arrow over these bo=es and identify them by hint.
2'
Cou might not like the contrast mode and black color of Signal<Plane layers so let us
change these settings now. Select F0ayer < %isplay 7odeG from the main menu. *rom the
appeared submenu you can choose the mode to show layers you like. $e select F6ll
layersG to show all layers of the design with the same contrast. f you want to see current
layer only, then select FCurrentG.
2(
To change the color and other layer settings, select F0ayer < 0ayers SetupG from the main
menu. n the F0ayers SetupG dialog bo=, select the layer and press FNG button to change
its color. $e have changed the colors" Top I 5ed and Bottom I Blue. @otice that you
can also rename the layers, add and delete layers from this dialog bo= )Top and Bottom
canMt be deleted,. Cou can also add the plane layer )notice that it canMt contain traces,,
define the net for plane )usually it is >round or Power, and the method to build metal
.one of the plated holes for your plane layer. $e recommend to create signal<plane layers
and to set the plane layer parameters before autorouting.
Cou can mirror the design to see the bottom side by selecting F9iew < 7irrorG from the
main menu.
0ayers visibility and colors can be also changed from 0ayers tab of the %esign
7anager<0ayers<Properties panel )9iew<Toolbars<%esign 7anager,.
&.$ +easuring trace length
Current pro;ect doesnDt re!uire such measuring because it is simple and low-speed,
however if you make high-speed circuits, video devices, etc. trace length is important.
*irst of all notice that hint of each trace includes its length by default I this can be helpful
however is not enough to check trace length in real-time with ease.
@ow please select several traces )you can use usual bo= selection or Ctrl key to select
e=actly what you want,. 5ight click on one of selected traces and choose FShow Trace
0engthG from net submenu.
2&
Cou will see small bo=es with trace length near all pads of selected nets, they are also
highlighted while you move mouse over the trace. 9alues are shown in current units
)inches in our case, and are changed in real-time while you edit the trace.
22
@ow please hide trace length using net submenu )select the same item, or Ando function.
&.& +anual ,outing
*or our simple pro;ect we have received the final version of routed board using the
autorouter but for more comple= pro;ects for best result you will probably have to do a
manual correction after autorouting.
*irst try to edit an e=isting trace )you may have to switch to the trace layer you want to
edit by pressing the layer button in the upper top right corner," move a mouse arrow over
the trace, then drag-and-drop the trace to a new position. n this mode, the trace segment
is edited depending on the angles and can be either +' or /4 degrees but you can also cut
the +'H degrees angles by adding new segments.
%ipTrace allows you to edit traces freely by selecting F5oute < Tools < *ree -dit TracesG
from the main menu or the corresponding button on the 5oute panel in the upper side of
the screen. @ow you are able to move trace nodes and segments without any limitations.
@otice that you can change the grid si.e from the list bo= on the Standard Panel on the
left side of Scale bo=. f you want to edit traces and design ob;ects without grid, simply
press F*((G to disable the grid or select F9iew < >ridG from main menu.
7ove the mouse over trace segment and right-click on it. Cou can see the net submenu
and here you can define the name of your net, add new node to the trace segment, change
the width and layer, delete lines and segments. Please note that %ipTrace creates the vias
automatically between two segments placed in different layers. Select FSwitch 0ine
2/
0ayer < TopG I you will see that the trace segment you clicked on, has been moved to the
Top layer and there are two vias between this segment and ad;acent one.
Change current layer to Top, right-click on that segment and move it back to Bottom.
@ow we will try manual routing, so right-click on one of your nets, then select FAnroute
@etG from the submenu. @otice that FAnroute @etG command from net submenu is
applied to all selected netsR in our case there are no selected nets and only the net you
clicked on will be unrouted. Then select F5oute < Tools < 5oute 7anualG from the main
menu or corresponding button on the 5oute Panel )now you are in 7anual routing mode,.
7ove mouse arrow over one pad of the non-routed net )until it highlights in red,, then
left-click and define the key points of your trace step-by-step using left-click. Try to
right-click when placing trace I the F5oute 7anualG submenu is shown. @ow you can
finish placing your trace, cancel it, move step backward, change the route mode )+'E/4,
free or arc mode,, change the layer )a via will be placed and you will be able to route the
ne=t layer,, width of the ne=t trace segments or place ;umper wire.
@otice that submenu commands are duplicated by hot keys to make manual routing
process easier" F7G-switch between routing modes, F$G-switching between layers,
FTG-switch to Top, FBD-switch to bottom, FWG-switch to ;umper wire or back )if you are in
Bottom layer, the ;umper wire will be placed to Top side, if in Top - then it will be placed
to Bottom side,, F(G - F'G in the top of keyboard I switching between layers )up to (',.
Switch layer to FTopG.
24
Cou can see that from the last specified key point, the trace will be in new layer, then
move mouse a little to bottom left, right-click and select from the submenu F-nterG or
press F-nterG key. @ow you are in Top layer and the trace is placed, but not connected.
28
@ow move mouse arrow over the trace end, which is not connected yet, and build the line
to the second pad of your net )notice that you should be in F5oute 7anualG mode,. The
trace is connected to the second pad"
&.- (orking )ith .ias
%ipTrace has two via types" usual vias that are parts of traces and appear automatically
when you move trace segment to another layer and static vias that works in the same way
as pads. Static via has more properties and can be used to connect trace to planes, etc.
:ther useful feature of static via is hiding or removing it in some layers that allows you to
make blind<buried via. Asual via can be blind<buried too, but it is shown in the layers
between trace segments only and you can not show or hide it in other signal<plane layers.
6lso if you got accustomed with other PCB 0ayout software, it is probably more
comfortable for you to use static vias only. $e will work with usual via first, then place
static via and investigate some of its properties.
Currently our pro;ect has only one via between top and bottom layers, so to try working
with vias we will create more ones. So select the bottom layer from the FSignal<Plane
0ayerG bo= on the 5oute panel, move mouse cursor on some trace, right-click and select
FSwitch 0ine 0ayer < TopG from net submenu.
21
@ow we have 2 vias. Select F0ayer < 9ia PropertiesG from main menu.
n the dialog bo= shown you can change default via settings for the program. Change
outer diameter and hole diameter to another value )we will increase them a little,. %raw
your attention to F6pply ToG group I F%efault :nlyG should be selected by default, this
means only the vias of previous default si.e<type will be changed. 6lso you can change
default settings without applying them to e=isting vias or apply them to all vias of entire
design. Select F6pply To" 6llG and press F:KG to make changes and close the dialog
bo=.
23
@ow please move the mouse cursor to one of the vias, make right-click and select F9ia
PropertiesG. n the dialog bo= shown you can change via settings for the point, trace or
net. Change the settings and press F:KG to apply them.
2+
@otice that if you are trying to change the settings for current point only and nothing
happens, most probably you clicked on another trace segment. So try to click a bit closer
to the point or change current signal layer )in our case this can happen with upper-right
via and changing layer to Top or moving mouse arrow closer to the vertical segment
solves the problem,.
@ow please press Ando several times to return the board to the state it was after
autorouting, then select F0ayer < 9ia PropertiesG from main menu and change the
parameters to the ones you normally use.
Static via is the same ob;ect as pad and has similar properties. $e will review one of
them. Please select F:b;ects<Place Static 9iaG from main menu or appropriate button on
the elements panel )upper-right corner, and place several vias. They are displayed in the
same color as current layer, i.e. 5ed because we have red top layer.
Cou can easily connect them to nets, build traces, etc. in the same way as you do that
with pads. Select 0ayer<%isplay 7ode<Contrast from main menu to display layers in
contrast mode. @ow please make right click on one of those vias to display its submenu
and select 9ia 0ayers.
/'
n the dialog bo= shown you can remove via shape and hole in some layers to make it
blind or buried one. @ow please click on the Top layer to deselect it and press :K.
Cou will see that selected via is removed from top layer, however still e=ists in Bottom.
/(
@otice that you can do the same operation with pads. 6lso all selected pads<vias can be
changed at once if you choose F6pply to" Selected ComponentsG in 9ia<Pad layers dialog
bo=. To define custom settings for Paste and Solder 7ask layers you can use F7ask <
Paste SettingsG from pad<via submenu.
&./ Selecting ob0ects b* t*pe1la*er.
Sometime it is necessary to select all ob;ects of one layer or only component, only nets,
etc. $ith out PCB this is very easy using mouse and Ctrl key, however for comple=
layout this can be hard task. @ow please select F-dit<-dit SelectionG from main menu.
*irst we will select all components of our layout, check components bo= and click :K.
This is simple e=ample, however usually we need more comple= selections. @ow our task
is selecting only unconnected vias in defined area. %eselect components by right click in
empty place. Place several vias and connect some of them to nets" in default mode right
click on the via when its highlight is red, then on the pad that belongs to net,. %efine area
using bo= selection )move mouse cursor to Apper-0eft corner, hold down left button,
move to Bottom-right and release button,. This bo= represents area where we plan to
select vias, so we will not include all vias of layout to it. @otice that we are in bottom
layer which is blue, so if you have any troubles with connecting vias, please switch to
bottom and see what Fred highlightG means.
/&
6ll ob;ects in our area are selected, however we need only non-connected vias. :pen
-dit<-dit Selection and choose F7ode" Keep SelectedG, check only F9iasG bo= )other
bo=es should be unchecked,.
/2
Click :K and only non-connected vias are checked. @e=t step, for e=ample, is connecting
them to some net at once. Asually this is necessary for connecting ground net to
planes<copper pours. 5ight click on one of selected vias when it is highlighted in red and
choose F6dd to @et < Selected 9iasG.

Choose any net from the list and click :K. @otice that even if you have some vias
connected to other nets, only non-connected vias will be connected by this feature.
5emove all static vias from your design to return to previous state.
&.2 Placing Te3t and 4raphics
Cou probably want to add some te=t or graphics to your board )with %ipTrace you can
even add a logo in Bmp or Wpeg format and e=port it to >erber or %?*,. @ow we will add
the te=t to the PCB board. *irst you should select a layer to place shapes, te=ts and logos.
7ove mouse to the list bo= with FTop 6ssyG te=t in the upper side and select FTop SilkG
from the list. @ow all the graphical ob;ects will be placed in the Top Silk layer . @otice
that PCB 0ayout program has different lists to select current signal<plane layer and the
layer to place graphics, also if you choose Signal<Plane as a layer to place graphics, all
shapes, te=ts and logos will be placed on the current Signal or Plane layer. This may seem
more comple= than simply create only one list, but try this feature and you will see how it
saves you time.
//
Cou should make a board a little bigger to place additional ob;ect, so move the mouse
arrow to the upper left verte= of the board outline, then drag-and-drop it in the top
direction. %o the same with upper right verte=. @otice that you can add vertices to the
board outline I try to drag-and-drop the segment )not verte=, of board outline.
/4
f you want to move the board outline, then select it )press Ctrl key and left-click on the
board outline segment,, move mouse over the board outline and drag-and-drop it.
5emember that if you canMt highlight some ob;ects and edit them, probably you are not in
a default mode, so simply right-click to cancel the mode. 6lso the ob;ects located in
inactive signal<plane layer canMt be edited.
Select FTe=tG tool on the %rawing panel )the button with F6bcG,, then left-click where
you would like to place your te=t, enter the te=t and press enter or click the mouse button.
Ase the mouse to move your te=t around the design until find correct position for it.
@otice that if you want to change the font settings by default select F:b;ects < %rawing
Properties < *ontG from the main menu. *ont type can be changed from :b;ects < %rawing
Properties < *ont Type. t is strongly recommended to use vector font as it is e=ported to
gerber directly. True Type font can be used for any non--nglish characters, however it
will be e=ported to gerber as small lines )made by recognition algorithm,. Some
manufacturers also donDt accept such te=t ob;ects in copper layers.
/8
@otice that you can change a layer of the graphics and te=t ob;ects at any time. Simply
select your ob;ects, right-click on one of them, then FPropertiesG from the submenu. n
FShape PropertiesG dialog bo= change FTypeG and F0ayerG fields to move the selected
ob;ects to another layer or define different properties )such as F5oute :bstacleG that is
used for autorouting,.
@otice that you can also add shapes to 7ask, Paste, route obstacle and board cutout
layers. These properties can be defined on the drawing panel or via shape properties in
the same way as silk or signal<plane layers.
&.5 Copper Pour
Bow about adding Copper Pour in the bottom layerP t is probably not needed )like the
te=t and some other things, for such simple PCB but let me show you how to add it and
then weMll delete it. Select the Bottom layer, then F:b;ects < Place Copper PourG from
main menu or the FCopper PourG tool on the ob;ects panel )in the upper left side,. Then
place the copper outline polygon by defining key points and right-click<-nter when
finished. Cou will see the following dialog bo="
/1
%ipTrace has Shape-based copper pour system. The copper area is formed from lines
with fi=ed width. The F0ine SpacingG parameter is used only if you choose non-solid fill
for the copper pour. @otice that you can connect your copper area to the net and choose
the type of connections )Connectivity tab,, but we will not do this for such board.
F%epending on BoardG and FSnap to boardG tools can be used to save your time and to
build the copper outline automatically, if you want to use this feature, simply define two
random points and right-click when placing the copper pour, then check F%epending on
BoardG and enter board outline to copper outline spacing )this feature saves much time
when you PCB has comple= board outline or arcs in it,.
Click F:KG to place the Copper Pour.
/3
Copper Pour ob;ect has two modes of fill" Poured and non-Poured. The second mode is
better if you want to edit ob;ects on the layer where the copper pour is located. To change
copper pour state, properties and update it, right-click on the copper outline and select the
item you want from submenu.
@otice that if your active layer is FTopG, you are able to see and edit the ob;ects placed in
the Top, Top Silk or Top 6ssy layer first. @ow switch current signal layer to Top"

/+
&.16 Locking ob0ects
Sometime when you edit schematic or PCB you need to lock some ob;ects to prevent
further editing of their positions and properties. n %ipTrace you can lock selected ob;ects
and components by side. @ow please select several design ob;ects, make right click on
one of them and choose F0ock SelectedG from submenu.
4'
@otice that locked ob;ects have low contrast of selection rectangles )in our case they have
the same color as bottom copper pour, so we have to unpour it to see selection
rectangles,. 6lso hint of the locked ob;ect includes F0ockedG te=t.
Cou are unable to move, resi.e or edit locked ob;ect. @ow please unlock all ob;ects"
select all by pressing CtrlH6 and unlock all )-dit<Anlock Selected or CtrlH6ltH0,.
6lso you can lock components after placing them on the top or bottom side. Select
F-dit<0ock Components<TopG to lock top components. Asing this mode you can route the
board and donDt worry that some components can be moved by accident. To unlock
components in the top layer select F-dit<0ock Components<TopG from main menu again.
&.11 Design .erification
%ipTrace has number of features to verify your design, that are united in 9erification
item of main menu. *or complete verification of your board we recommend to use %5C,
net connectivity check and comparing PCB to Schematic.
%5C feature is one of the most important features, that allows you to check the distance
between design ob;ects and allowable si.es. 7ost probably current PCB doesnDt have
errors because it is simple. Press %5C button on the route panel or select F9erification <
Check %esignG from main menu to check entire design - the error list or F@o -rrorsG
message will be shown. @ow select F9erification < %esign 5ulesG to setup %5C feature.
4(
n the design rules dialog bo= you can define clearances for different ob;ect types. Select
FCheck Copper PoursG bo= and press F:KG to apply changes and close the window.
@ow switch to the bottom layer )select FBottomG on the route panel,, turn off the grid
)*((,, pour copper pour and move some trace segment a little to let it cross the copper
pour, then run %5C by pressing appropriate button on the route panel.
Cou can see the list of errors )currently it are only two there,. Probably you use
(&3'=('&/ or even higher resolution, so the window of error list will be smaller if
4&
compared to design area )the screen e=amples were made on 3''=8'' to allow you to see
all controls better,.
%ouble-click on the error item I the error location will be moved to the center of screen
and error circle targeted to let you recogni.e it easier. @ow correct the error without
closing %5C window, then rerun %5C to renew the list.
@et connectivity check allows you to verify if all nets are properly corrected. *or such
design this is not important, however if you have large design with many layers, pins,
copper pours or maybe even shapes in signal layers )where thermals or other things can
not be created, to connect nets, then net integrity check will be helpful for you. t checks
if all nets are properly connected and displays list of broken or merged ones. $e will
review this feature in the tutorial in details below.
@ow please select F9erification<Check @et ConnectivityG and click :K. 7ost probably
your design will not have connectivity errors and you will see appropriate message.
Comparing to Schematic allows you to check if your PCB pro;ect corresponds to source
Schematic file. t shows net structure errors and unknown components. Select
F9erification<Compare to SchematicG from main menu, then choose 6stable *lip *lop
Schematic file. f your net structure was not changed and has no errors, you will see
appropriate message.
@et connectivity check and Comparing to Schematic works in the same way as %5C and
you can select errors from a list to highlight them.
&.1" Design Information
Bow about counting number of pins or board area on our designP Currently it is not a
hard task, however if you have hundreds of pins and comple= board outline with arcs it
may be impossible. So select F*ile < %esign nformationG from the main menu.
42
n the design information dialog bo= you can preview number of different ob;ects, layers,
board si.e and hole si.es. To open FBoles by Si.eG window press F...G button in the
bottom right.
@ow delete copper pour from your design.
&.1# Paneli!ing
f you need several copies of the same PCB and want to save time and money you can
use paneli.ing feature to make several copies on single panel. Select -dit<Paneli.ing from
main menu"

$e will make / copies of the PCB, i.e. & columns and & rows. Spacings between boards
will be .ero. 5ail -dges means distance between boards and panel border. Asually it is
not necessary, however may help to determine appro= panel si.e. :ur rail edges for all
sides will be '.( in. 6lso some manufacturers need panel border in the board outline
layer, so we will also check FShow Panel BorderG bo=. Click F:KG and you will get the
following picture"
4/
n the design area we can see only bo=es with FCopy XG te=t, however in print preview,
while printing or e=porting gerber<d=f<drill complete copies of the board will be inserted
there.
@otice that paneli.ing works only if PCB has board outline.
@ow open Paneli.ing dialog bo= and change @umber of columns and rows to F(G )this
will remove panels,.
&.1$ Printing
$e recommend that you use print preview dialog bo= to print your PCB. To open it,
select F*ile < PreviewG from main menu or the corresponding button on Standard panel in
upper left side of the screen. @otice that we didnMt describe creating Titles in F%esigning
PCBG section. f you want to display titles like on the screenshot below, then select F*ile
< Titles and SheetG from main menu and select F6@S 6G in the FSheet TemplateG bo=,
check F%isplay TitlesG and close the dialog bo=, before opening Print Preview window.
44
n the FPrint PreviewG dialog bo= you can customi.e the view of your PCB by
checking<unchecking the bo=es in F:b;ectsG group. f you would like to change your
design printing scale, then select it from FPrint ScaleG bo= or press FJoom nG, FJoom
:utG buttons in the right side of screen. To move your PCB around the sheet select
F7ove BoardG button in the right side )selected on the picture below, and move your
PCB. n the Print Preview dialog bo= you can also select current FSignal<PlaneG layer and
the mode to show layers. f you want to get mirrored PCB and<or te=t, check F7irrorG
and<or F*lip Te=tG bo=es. To print, click on the FPrintG button. To save image in Bmp or
Wpeg file, select FSaveG. Small button with colors to the left from FJoom :utG tool allows
to define printing colors separately. By default F$hite BackgroundG scheme is used for
printing. 6lso notice that layer colors depends on color scheme only if they have default
color, otherwise they will be drawn using color defined in 0ayer<0ayer Setup. *or
printing all in black without changing layer colors check FPrint in Black :nlyG bo=.
48
Close the FPrint PreviewG dialog bo= and use Ando to recover copper pour )also notice
that you can simply unpour copper pour if you donDt want to print it,.
-. +anufacturing 7utput
-.1 D89 7utput
Cou can use %?* output feature to e=port your design to many C6%, C67 programs
that allow you to import %?* files. f you used 6utoCad for PCB design before
switching to %ipTrace, you might want to edit some pieces of your design with 6utoCad.
6lso the %?* e=port function allows to create the edge for milling automatically, the
edge can be converted from %?* to >-code using free 6C- Converter )you can
download it from our web-site,.
Select F*ile < -=port < %?*G from the main menu. Press FSelect 6llG in the F-=port
%?*G dialog bo= I all layers of your design will be selected. @otice that F-dgeSTopG and
F-dgeSBottomG are not the layers of your design. t is possible to select them by holding
down FCtrlG key and click, but now we donMt use these layers. f you want, you can
check<uncheck different bo=es in the right side of dialog bo= to show<hide ob;ects or
mirror your design or flip te=t. @ow press F-=portG and save your file.
41
@ow you can open it with 6utoCad or another program that supports 6utoCad %?*.
43
$hat do you think about producing your PCB using millingP This method is convenient
and cheap for non-comple= PCBMs. 0et me show you how to do this with %ipTrace.
Select F*ile < -=port < %?*G to open %?* -=port dialog bo=. Then select
F-dgeSBottomG, all traces of our PCB are in Bottom layer, right. Check F7irrorG bo= to
mirror the design )this will be how we see the board from Bottom side,. Then define
F-dge $idthG I the center line of milling will be in Ledge widthM<& spacing from design
ob;ects and the depth of milling depends on edge width and instrument angle. Press
F-=portG button and save %?* file.
@ow please open your file with 6utoCad or another program to view the result"
4+
The edge e=ported from %ipTrace is set of polylines with defined width. Before the
e=porting %ipTrace checks your design and if the ob;ect to ob;ect spacing somewhere is
less than edge width, then it shows the warning and errors to enable you to correct them.
@otice that C6% programs usually show the polylines with sharp angles and sometime
picture in C6% program have some issues )sharp angles,, but when you mill the PCB or
simulate the milling with C67 program there will be no issues because of the radius of
instrument.
@ow convert your edge from %?* to >-code using 6C- converter.
-." 4erber 7utput
Select F*ile < -=port < >erberG from the main menu. n the F-=port >erberG dialog bo=
select the layers )use FCtrlG and FShiftG for multiple select if necessary, and ob;ects to
e=port, then press FPreviewG button. @otice that you should e=port layers separately, i.e.
one layer per file. 6lso you can setup all layers )select them one-by-one, define
settings<ob;ects and preview,, then click F-=port 6llG to make all files at once.
$e will do >erber output in that way"
(. Select Top 6ssy I this is assemble layer and usually it is not necessary for board
production, it includes all shapes<te=ts placed in Top 6ssy and ob;ects defined in
F9iew<6ssembly 0ayersG sub-menu of main menu. *or our PCB this layer doesnDt
include anything when you preview it )if 9iew<6ssembly 0ayers has default settings,.
&. Select Top Silk I this layer includes pattern shapes<te=ts and shapes<te=ts placed in
Top Silk layer. %o not change settings and click Preview. @otice that if you can not see
8'
te=ts or they are displayed incompletely )depends on font and its si.e,, you should simply
make F5ecogni.e 6ccuracyG value a bit smaller )do not make it minimum possible,.
2. Top 7ask I this is solder mask layer. t is generated automatically based on pads, their
settings and common FSolder 7ask SwellG defined in gerber dialog bo= H includes
shapes placed in solder mask layer. suppose we should only uncheck F9iasG bo=, as
they are usually covered with the solder mask. To change custom solder mask settings for
pads right click on the pad and select F7ask<Paste SettingsG from its submenu.
/. Top Paste I this layer is usually used for S7T pads only, so we can check FPaste 7ask
for S7T Pads onlyG.
4. Signal layers )Top, Bottom, etc., - these are our copper layers, now please check
F9iasG bo= for all of them and preview if all layers are displayed correctly. @otice that if
you plan to drill holes manually you can also check FPad<9ia BolesG bo= to make you
work easier, however this option is not recommended if you send files to manufacturer.
6lso notice that in case that FPad<9ia BolesG bo= is checked, & layers will be created for
each signal layer if there are through pads or vias" drawing and clearing. The second layer
is used to remove artefacts over the drill holes.
8. Bottom Paste I Bottom 6ssy, by default all te=t ob;ects in Bottom layers are flipped -
F9iew<*lip Te=t 6utomaticallyG option in main menu, however if that option is off, you
can flip te=t manually for the layers you want )F*lip Te=tG bo=,.
1. Board outline includes board outline only with defined width. Board layer includes
board as filled polygon.

8(
@ow please select FBottomG layer and click FPreviewG to see it"
The :ffset in %?*, >erber, @<C drill and FPick and PlaceG e=port functions is the
distance between .eros and your board in the Bottom 0eft. 6lso you can use design
origin by checking appropriate bo= in e=port windows.
%ipTrace allows you to e=port any te=ts and fonts )even Chinese hieroglyphs, or raster
black and white images )for e=ample logo, to >erber, but you should define F5ecogni.e
6ccuracyG for such ob;ects )for e=ample, 2 mil is set by default,. Cou can use up to '.4
mil accuracy.
@ow please close the Preview and click F-=port 6llG )if the apertures are not predefined
the program will ask you to set them automatically,, then save your >erber files one-by-
one. -=tension can be defined in gerber dialog bo= or you can type it manually when
saving the file.
$ith %ipTrace you can also e=port %rill Symbols for different types of holes. :pen the
>erber -=port dialog bo= )FPad<9ia BolesG and F7tBolesG should be checked,, then
check F%rill SymbolsG bo= and press FSet SymbolsG button. n the F%rill SymbolsG
dialog bo= define the drill symbols, their si.e and line width, then close it and open
>erber Preview to view the result. @otice that if F%rill SymbolsG bo= is checked and you
try to e=port silk, assy, signal layers, etc., you can get blank file<preview.
8&
82
-.# Create :C Drill file for C:C machine drilling
To e=port current design to @<C %rill format, select Y*ile < -=port < @<C %rillY from main
menu. Then press F6utoG button to define tools and press F-=portG. @otice that you donMt
need to select the layers for through holes, but if your hole is blind )for e=ample internal
via,, then you should select the layer)s, where hole is located . 6lso use FPreviewG to
view the result.
CongratulationsZ Cou have finished designing a simple pro;ect with %ipTrace.
Please save your Schematic and PCB files I we will use them in your future practices
with this tutorial. t took longer to read it then to actually finish the pro;ect.
P.S. %o not forget to check FAse 6ll 0ayersG bo= in the 6utorouter Setup dialog bo= if
you plan to route &H layers PCBs. :r you can simply define the number of layers before
autorouting your further pro;ects.
8/
II. Creating libraries
This part of tutorial will teach you how to create component and pattern libraries using
Component and Pattern -ditors. 0ibraries are crown ;ewels of the design house and as
such needs to be treated and B6CK-% AP. 6gain" please remember to save your own
libraries in several places, ;ust to be safer than sorry.
1. Designing a pattern librar*
:pen %ipTrace Patter -ditor, i.e. go to Start 6ll Programs %ipTrace Pattern
-ditor.
1.1 Customi!ing Pattern ditor
6fter opening the Pattern -ditor you might want to show origin and ?,C a=is, so select
F9iew < %isplay :riginG from the main menu or press *(. @otice that you can change
origin any time while designing the pattern,. The origin will be .ero point of the pattern
when you place, rotate it or change position by coordinates in PCB 0ayout.

The panel in upper side of design area is FPattern PropertiesG panel, you can use it to
define pattern attributes and design the pattern from templates or types. Cou might want
to hide or to minimi.e it when designing the patterns. To minimi.e the panel, click arrow
button in its upper left corner. To close the panel click F?G button in the upper right, to
show it again, select F9iew < Pattern PropertiesG from main menu.
84
Ase FCtrlHG and FCtrl-G to Joom n and Joom :ut in component and pattern editors or
simply enter )select, necessary scale in appropriate bo=.
1." Designing a resistor
@ow you will design the first pattern of your library" resistor with /'' mils lead spacing.
*irst define the name and descriptor of your resistor. Type F5-S /''G in the @ame field
and F5G in the 5ef%es field of Pattern Properties panel. n Pattern -ditor and Component
-ditor you define base 5ef%es, i.e. in our case when you place the resistors to design the
5ef%es will be 5(, 5&, 52, etc. f 5ef%es is not specified, then program automatically
adds FAG to placed components or patterns.
@ote" for the first pattern we will use F*reeG type, but in future it is faster to use F0inesG,
will show how to do this with other patterns below.
@ow minimi.e FPattern PropertiesG panel. Select FPlace PadG tool on the F:b;ectsG
panel, move mouse arrow to the position where your first pad should be located, then left-
click to place itR move mouse to the position of second pad and left-click to place another
one. Then right-click to cancel placement mode.
88
The placement by sight is a convenient method, but not accurate, so we should check and
maybe correct the pad coordinates )you can see on the picture above that we place pads
with 2'' spacing, but you need /'',. There are several methods to change the ob;ect
coordinates and also simple drag-and-drop. n this case we will use F0ayer :b;ectsG
dialog bo=. n the right side of screen you can see the layers. @otice that those are only
logical layers for editing )not signal or silk layers,. @ow select the layers" move mouse
arrow over the F0ayer 'G, hold down the left mouse button, move cursor to F0ayer (G,
then release mouse button. Select F0ayer < 7erge 0ayersG or the corresponding button in
the upper side of layers panel. @ow you have a single layer with two pads on itR double
click on it to open F0ayer :b;ectsG dialog bo=.
Select the pad with incorrect coordinates and change them, then click FCloseG button to
close the dialog bo=.
81
Cou might want to change the pad settings, i.e. shape, si.e, hole diameter, S7% or
Through hole type, etc. @otice that pattern has pad settings by default, that can be applied
to all its pads and also each pad can haw its own settings. To change the settings by
default for the pattern select FPattern < Pad PropertiesG from main menu. n the FPad
PropertiesG dialog bo= you can change the shape of your pad" -llipse, :val, 5ectangle or
Polygon )click Points to define the number of vertices or point coordinates for polygonal
pad,. 6 hole diameter is applied to FThroughG pads only. 6lso you can use pad template
by selecting it from FTemplateG bo=. 6nd to create your own templates, click FNUUG
button to open templates manager. @otice that templates you can create here, can be used
for fast change of pad settings in different dialog bo=es of Pattern -ditor and PCB 0ayout
programs.
83

Please close FTemplatesG, change shape to F5ectangleG, width to F'.'3G, and :n Board to
FSurfaceG, then click F:KG to apply changes.
8+
@otice that for surface pads you can also change side, i.e. place them on the bottom side
)they will be on top when component is placed to the bottom side in PCB 0ayout,.to
change side select pad)s,, right click on one of them and select FChange SideG. Current
side for placing new pads and shapes can be also selected on the ob;ects panel )bo= with
FTopG te=t in the right side, by the way that bo= is not visible on 3''=8'' with default
panel placement,.
@ow you will change the settings of single pad. 7ove the mouse arrow over first pad,
right-click, select FPropertiesG )f the pad is not highlighted while moving mouse arrow
over it, right-click or use F%efault 7odeG button in the upper side of screen to switch to
default mode,.
n the Pad Properties dialog bo= uncheck F%efault for PatternG bo= to enable the padMs
own settings, change shape to FPolygonG, width and height to F'.'+G, then press FPointsG
to open FPolygon PointsG dialog bo=. Bere you can define the type of polygonal pad and
if non-5egular, polygon point coordinates. Close the FPolygon PointsG dialog bo=, then
change hole diameter to F','/G, :n Board to FThroughG and press F:KG to close the
dialog bo= and apply changes.
@otice that you can change pad coordinates and direction from the pad properties dialog
bo=. 6lso pad properties are applied to all selected pads )not a single one you clicked on,.
1'
@ow please define the following properties for the pads" The first I '.'+='.'+, 5ectangle,
Through, hole diameter I '.'/R the second I '.'+='.'+, -llipse, Through, hole diameter I
'.'/. Cou will place the silk for this resistor. Select F5ectangleG button on the :b;ects
panel in the upper part of the screen, then place rectangle by clicking on two of its key
points"
1(
%isable rectangle placement mode )right-click or F%efault 7odeG button,.
Cou might want to change the si.e of silk shape. Cou can do this in following ways"
using F0ayer :b;ectsG dialog bo= )double click on F0ayer (G graphic in the right side,,
right-click on the shape and selecting point from the submenu, or resi.e the shape using
drag-and-drop method )use it in this case,. Please close the pattern properties panel )F?G
button in upper right corner of it,, Joom n the resistor by placing FCtrlHG, change grid
si.e to F'.'&4inG )the grid bo= is located to the left from scale bo=,. Then move mouse
arrow over rectangle key points and resi.e )mouse cursor shows possible directions,.
The resistor is ready.
Try to rotate and mirror the first pattern of your library, select F-dit < 5otate PatternG to
rotate and F-dit < 9ertical *lipG, F-dit < Bori.ontal *lipG to mirror.
@otice that if you try to select and rotate the ob;ects of your pattern, the silk shapes are
si.ed in relation to pattern width and height )sometimes it looks fancy,. The silk resi.ing
is used when you change the width and height of pattern by defining different parameters
when using FTypeG of pattern )see designing F%PG below,.
1.# Sa%ing librar*
t is time to specify library name, comments and filename. Cou will add several other
patterns to this library in a minute, but we can define these parameters and save it now,
then add new patterns and simply click on FSaveG button.
Select F0ibrary < 0ibrary @ame and BintG from main menu. n the dialog bo= type the
name of your library )it should be short, and hint, then click F:KG. The name of your
1&
library will be shown on the 0ibrary Panel in PCB 0ayout program, the hint will be
shown when you move the mouse arrow over the button with library name.
Select F0ibrary < SaveG from main menu or the corresponding button on the standard
panel in upper left side of screen. *ind the folder to save, type filename, then click
FSaveG. recommend you to use different folders for Standard libraries
)FO%riveU"<Program *iles<%ipTrace<0ibG by default, and your own libraries )in this case
we have created F7y 0ibsG subfolder in %ipTrace folder,.
1.$ Designing a capacitor
Capacitor has very similar pattern if compared to resistor, but we will use another set of
Pattern -ditor function to create.
Cou might want to define the pad settings by default before adding new pattern and
placing the pads, so select F:b;ects < Placement SetupG from the main menu. %efine the
following settings in FCurrent PadsG group" ellipse, '.'4+='.'4+, hole diameter I '.'24,
:n Board - Through. Then click F:KG.
12
FPad to Pad SpacingG group of this dialog bo= is used to define the spacing when placing
the line, rectangle or circle of pads )you can find this tools in F:b;ects < Place PadsG
submenu or on the ob;ects panel in upper right side of the screen,.
F7t Bole %iameterG group is used to define the mounting hole diameters. 7ounting hole
in %ipTrace has two diameters" outer I the area where routing is restricted, and a hole
itself.
@otice that FPlacement SetupG dialog bo= does not change the pad settings of current
pattern, but changes program settings which are used when adding a new pattern.
6dd new pattern to the library" select FPattern < 6dd @ew To 0ibraryG then select your
new pattern on Patterns Table in the left side of the screen )this table shows all patterns of
library you design<edit,. Show the properties panel by selecting F9iew < PropertiesG from
main menu )if it was closed, or by clicking arrow button on its left side )if it was
minimi.ed, and type the name and 5ef%es of the capacitor.
1/
Select F0inesG from FTypeG bo=, then define F(G to F@umber (G )number of lines for
such type,, F&G to F@umber &G )number of pads, and F'./G to FSpacing (G )pad to pad
spacing,. FSpacingG is line to line spacing for F0inesG type I we will not use it because
our pattern includes single line. Check Fvariable parameterG in the right side of FSpacing
(G field, this will allow you to change lead spacing without pattern editor.
14
@otice that you can use different types )F0inesG, etc., to design the patterns with fi=ed
lead spacing, number of pads, etc. ) suppose +4-(''[ of your patterns will be not
variable,. Simply do not check Fvariable parameterG bo=es.
7inimi.e pattern properties panel, then change the shape of first pad to F5ectangleG"
right-click on the pad, Properties, select F5ectangleG in the shape bo= and press F:KG.
Select rectangle tool on the ob;ects panel in upper side of the screen and place rectangle
)this is first shape of the pattern silk screen,, then select line tool and place two lines to
create FHG symbol.
The capacitor is ready. %o not forget to save your library sometime by clicking on FSaveG
button in the upper left side of the screen.
1.& Designing DIP1$ pattern
Cou will design %P(/ pattern using pad line tool.
6dd new pattern to the library )FPattern < 6dd @ew To 0ibraryG from main menu,, then
select this pattern on pattern table in the left side and specify the name and 5ef%es.
@otice that we can simply select F0inesG type and change number of pads to F(/G as you
can see on the picture below )this is the fastest way to create such pattern,, but now our
goal is to use pad line tool, so please select F*reeG pattern type and minimi.e the pattern
properties panel.
18
Select F:b;ects < Placement SetupG from main menu and ensure the pad to pad spacing is
'.( in. Close the placement setup dialog bo= and select F:b;ects < Place Pads < 0ineG or
corresponding button on the ob;ects panel in upper right side of the screen. Then move
mouse to design area and place two vertical pad lines" left-click, move mouse arrow to
the bottom direction until line contains 1 pads )( to 1,, left-click to place first pad lineR
then place second line from bottom to top )3 to (/,. f you want to move one of the lines
select it on the layer panel, then drag-and-drop. @otice that lines were placed to different
graphical layers )on the right, and you can easily select the layer and move it to new
position. To control the line-to-line spacing use measure tool" select F7easureG button on
the ob;ects panel in upper side of the screen, then move mouse arrow over the first point
of spacing, hold down the left button and move the mouse arrow to the second point of
spacing"
11
Change the shape of first pad to F5ectangleG" right-click on the pad, select FPropertiesG
from submenu, then F5ectangleG in shape bo= and F:KG. Change grid si.e to F'.'&4 inG
using grid bo= in the upper side, then create silk for F%P (/G using line and arc tools"
13
Select the origin tool and click on the first pad of %P-(/ to move pattern origin there.
Cou can also rotate the pattern using F-dit < 5otate PatternG from main menu or
FCtrlH6ltH5G.
@otice that origin of %P-(/ is different from pattern center, however you can return it
there at any time by centering the pattern )-dit < Center Pattern,. $e also recommend to
use that feature for all newly created pattern to center the origin after creation if you donDt
plan to make a a different thing.
1.- Designing DIP pattern )ith %ariable number of pads.
Cou will design %P pattern with variable number of pads. 6dd new pattern to the library
)FPattern < 6dd @ew To 0ibraryG from main menu,, define name and 5ef%es for new
pattern, then select F0inesG, set F@umber &G to &' and check Fvariable parameterG in the
right side of F@umber &G field"
1+
Joom :n your pattern using FCtrlHG. Then draw pattern silk screen and change shape of
the first pad to F5ectangleG"
3'
Show pattern properties panel using arrow button in the left side of it and try to change
F@umber (G for e=ample to F(8G. Cou can see that silk graphics as scaled with pattern, so
you can receive any %P pattern with F'.2 inG line spacing by changing single parameter.
@otice that you can change this parameter in PCB 0ayout from Pattern Properties dialog,
Component -ditor and Schematic while attach the pattern.
n case you keep F(G while changing F@umber &G, the type of first pad can be reset to
default )in PCB 0ayout and other programs you will be able to edit number of pads using
up and down buttons on the right side of property field,.
:ur Pattern library is ready. Click on the save button, then close Pattern -ditor module.
1./. Placing the patterns
:pen %ipTrace PCB 0ayout module, i.e., go to
Start 6ll Programs %ipTrace PCB 0ayout. To add the created patterns to the
design using the pattern list in left side of the screen, you need to activate the library first.
Select F0ibrary < 0ibrary SetupG from main menu, then uncheck F>et 0ibraries from
*olderG bo= to activate the list. Click on FNG button in the right side of list, find your
library, then F:penG. F7y 0ibraryG is added to active libraries. @otice that you can easily
move it to another position in the list if necessary. Close the library setup dialog bo=.
3(
Scroll the library panel to the right )using arrow buttons on its right side, until you find
F7y 0ibraryG, then select your library. Place the patterns and change marking settings to
show 5ef%es and Type )9iew < Pattern 7arking for common settings and right-click on
the pattern < Properties < 7arking for individual ones,. @otice that individual settings are
changed for all selected patterns.
3&
$e have forgotten to change the shape of first pad to 5ectangle for the %P(/ pattern.
Cou will change it in PCB 0ayout" move the mouse arrow over the first pad of %P (/,
right-click, select FPad PropertiesG. n the dialog bo= uncheck F%efault for PatternG,
change shape to F5ectangleG and click F:KG. @otice that you can change default settings
for pattern pads" right-click on the pattern and select FPad PropertiesG from the submenu.
The %P (/ pattern is normal. @otice that if specified origin is different from pattern
centroid position, it will be shown while you place that pattern )or convert schematic to
PCB,. 6lso you can easily show or hide pattern origin for all selected patterns" right-click
on one of them and select FPattern :riginG from submenu.
Try to rotate different patterns and you will see that pattern origin is its rotation center.
6lso when you move mouse cursor over the pattern, the coordinates shown are
coordinates of pattern origin.
@ow you might need %P (', %P &' or %P &/, but we didnDt design them directly. So
move mouse over %PS965 pattern, right-click, select FPropertiesG from the submenu
and F9ariablesG tab in the properties dialog bo=. Try to change available parameter
F@umber &G )you had checked it in Pattern -ditor as variable, to F('G, G&'G or F&/G )you
can preview the result,, then click F:KG and you get new pattern. By the way, you can
rename it from F%PS965G to F%P &/G in the pattern properties dialog bo= )F7ainG
tab,.
32
The same operation you can make with capacitorMs lead spacing. Please be attentive when
creating, placing and changing dimensions of the patterns with variable parameters. $e
would recommend to use patterns with fi=ed parameters where possible.
". Designing a component librar*
:pen %ipTrace Component -ditor, i.e. go to Start 6ll Programs %ipTrace
Component -ditor. Cou will design several components )including multipart
components, and will attach related patterns to them using your pattern library.
".1 Customi!ing Component ditor
Customi.ing the Component -ditor is the same as customi.ing Pattern -ditor. 6fter
opening the program, select F9iew < %isplay :riginG from main menu to show .ero point
and ?, C a=is. Component Properties panel in the upper right side of design area can be
minimi.ed or closed using the buttons on panelMs upper side. Asing this panel you can
define component type" there are 2 types of components here" *ree )without any specific
properties,, 5ectangle and Shape5ect. The only difference for the second and third types
is silk rectangle for the last one. 6lso few words about FPart TypeG and FPartG
parameters" The first one can be F@ormalG, FPower and >ndG and F@et PortG. The
component can contain only single FPower and >ndG part )if you prefer to hide all power
net for your schematic, then place all power pins to this part,. @et Port is mostly designed
as a single-part component and is used to connect wires together without visual
connections, it can be used for >round or Power symbols, also for the schematics with
fle=ible structure )we will try to design such component and to use it - see below,.
3/
Cou might want to define pin settings before creating the components. So select F:b;ects
< Pin Placement SetupG from main menu. $e will not change these properties now, but
notice that length and ?,C Spacing should be divisible by grid step to create all part key
points on the grid points.
34
"." Designing a resistor
Cou will design the resistor using F*reeG type and placement by sight. Please define the
component name and 5ef%es first, use the corresponding fields on component properties
panel. 6fter specifying these attributes please minimi.e the component properties panel
using the arrow in its upper left corner.
38
Select FPlace PinG tool in the upper right side of the screen, then move mouse arrow to
design area and place two pins using left-click. 5otate one pin by (3' degrees" select it
and press FCtrlH5G twice. Select the rectangle tool and place silk rectangle for the
resistor.
31
@otice that you can move the pin)s, using drag-and-drop method. f you want to move or
rotate several pins, please select them first.
The symbol of our resistor is ready, but we need the attached pattern to be able to create
PCB from the Schematic with this resistor. So select FComponent < 6ttached PatternG
from main menu. n the attached pattern dialog bo= click on the F6ddG button, then find
your pattern library and open it. Select F5-S /''G from the pattern list in the bottom right
corner of dialog bo=. Cou can see the resistor pattern appeared in the right side of dialog
bo= and blue connections between symbol and pattern )this is pin to pad connections,. To
create or redefine such connection move mouse arrow over the part pin, left-click, then
move to pad and left-click to connect. To delete the connection simply right-click on the
pin or pad. $hen you move cursor over one of connected pins, they both are highlighted.
Click F:KG to apply changes and close the dialog bo=.
33
@otice that you can specify pin to pad connections using the connection list and this way
is preferred for medium or large components. 6lso pin numbers )related parts, can be
defined from pin manager )select FComponent<Pin 7anagerG from main menu to open it,
or from pin properties dialog bo=es.
The resistor is ready and contains both schematic part and PCB pattern.
%efine the name and hint for your library" select F0ibrary < 0ibrary @ame and BintG, then
type F7y 0ibraryG in name field and FThis is my first component libraryG in hint field
)you can use another name or hint, but remember the name should be short I it
corresponds to the button caption on library panel in Schematic program,.
Click FSaveG button in the upper left side of the screen, define library path and filename
and then click FSaveG to save the library.
3+

".# Designing a capacitor
Select FComponent < 6dd @ew To 0ibraryG from main menu to add new component to
the library and then select new component from component table in the left side of the
screen.
Cou will design the capacitor using F5ectangleG type, so define component name and
5ef%es and then select F5ectangleG in Type bo= of the component properties panel.
Change component width to F'.(G, number left and right pins to F(G. Pin spacing is not
needed in our case because it can be used when number of left<right pins is more than F(G

+'
@ow please minimi.e component properties panel, change grid si.e to F'.'(&4 inG and
place capacitor silk using three lines and one arc. Ase FCtrlHG to Joom :n the symbol.
+(
Show pin names for your symbol" select the pins )or select all using FCtrlH6G,, right-
click on one of pins and select FPin PropertiesG from submenu. n the pin properties
dialog bo= check FShow @ameG and press F:KG to apply changes and close the dialog
bo=.
6lso notice that all newly created pins have FAndefinedG electric type, so you can change
the electric type using pin properties dialog bo= or pin manager )see below,. -lectric type
is currently used for -5C feature only. FTypeG property is used mainly for pin graphics,
you can try different types to see what it draws )or see Belp,.
@ames are shown, but they are in strange positions )as for capacitor, and you need to
move them, so select F9iew < 7ove ToolG from the main menu or simply press *(', then
move mouse arrow over pin names and drag-and-drop them to new positions, then right-
click to return to default mode.
@otice that you can use such method to move pin names, numbers and part attributes in
the schematic capture.
+&

By the way we have shown the names )not pin numbers, and they will not be changed
when changing the pin numbers, i.e. related pads. 6lso you can show inversion line in the
pin name" move mouse arrow over the pin, right-click and select the first )top, item from
submenu, then enter Fnormal \invertG te=t and press F:KG, then move pin name using
move tool )*(',. F\G symbol in the pin name is start or end of inversion, so using it you
can define the inversion for separate parts )signals, of the pin name.
+2
Probably you donMt need to display pin names for the components like capacitor and you
might want to display pin numbers. @otice that you can define general settings for pin
numbers in the schematic capture and all components have general settings by default,
but also you can specify separate settings to display pin numbers for each part in the
component editor.
Select FComponent < Pin 7anagerG from main menu to open pin manager dialog bo=,
select pin F&G in the table and change the name to F&G, then hide pin name for both pins"
select them )move mouse arrow to first row, hold down left mouse button, then move
cursor to the second one, and uncheck FShow @ameG bo=. Close pin manager.
@otice that you can change pin numbers )i.e. related pads,, coordinates, length, type and
electric type of pins from FPin 7anagerG dialog bo=.
+/

n the component editor you can define the individual component settings to show pin
numbers from FComponent < Pin @umbersG menu and general program settings )the same
as in Schematic Capture, using F9iew < Pin @umbersG.
@ow please select FShowG from one of these submenus to show capacitor pin numbers.
@otice that you will not be able to change individual component settings in Schematic
Capture. f you like to move pin numbers concerning to pins use move tool )*(',.
+4
The ne=t step is attaching a pattern to the capacitor. Select FComponent < 6ttached
PatternG from main menu, then in dialog bo= your pattern library from library list and
FCapacitorG from the component list.

+8
@otice that you can change lead spacing for the pattern because you specified it as
variable in pattern editor. But after converting Schematic to PCB all variable parameters
are blocked and the placed pattern have fi=ed number of pins and pin-to-pin spacing.
Cou can use the patterns with variable parameters when design simple pro;ects and need
to be fast while attaching different patterns in Component -ditor or Schematic Capture.
But we donMt recommend you to use them for the comple= designs, because there is a
probability of mistake when defining or changing the variable parameters.
".$ Designing a multi;part component
Cou will design simple multipart component with four F6nd-@otG symbols and power
symbol. The attached pattern will be %P(/.
6dd new component to the library, i.e. select FComponent < 6dd @ew To 0ibraryG from
main menu, then select it in the component table. %efine the name and 5ef%es.
The ne=t step is creating component parts. %ipTrace allows you to create separate parts
and part groups )similar parts, in the component. 6ll parts in the part group have the
same pins, silk, etc. e=cept pin numbers )i.e. related pads,. 6lso parts can be @ormal,
Power and @et Ports. Power parts and power nets can be hidden in the schematic captureR
the component can contain only one power part.
+1
Cou will design the component with / similar 6nd@ot parts and ( power part. Select
FComponent < Create Similar PartsG from main menu, type F/G in the dialog bo= and
press F:KG to apply. @otice that similar parts are created basing on currently selected
part.
@ow you can see the following parts" Part ( )(,, Part ( )&,, Part ( )2, and Part ( )/, in the
bottom left side of the screen. 6ll the similar parts have the same part name and are
united by part name. Cou can change the part name for e=ample to F6@G.
The ne=t part will be power part. Select FComponent < 6dd @ew PartG from main menu,
select new part tab in the bottom right side and rename it to FP$5G. @otice that new part
is separate part and do not belong to F6@G group.
@ow design your power part" select FShape5ectG type from the type bo= of the
component properties panel and specify the following parameters" width I F'.2 inG, in
spacing I keep '.(, left pins I F&G, right pins I F'G. Then select FPower and >ndG from
the FPart Type Bo=G.
+3
Select FComponent < Pin 7anagerG from main menu, then change pin names to F9CCG
and F>@%G, pin numbers to F(/G and F1G, electric type to FPowerG, check FShow @ameG
bo= for both pins. @otice that FTypeG, FShow @ameG and F0engthG parameters you can
change for multiple pins.
++
Close pin manager dialog bo=, minimi.e component properties panel and see the first part
of your component. Ase FCtrlHG to Joom :n.

(''
Cou will design other parts of your component" select one of the 6@ parts, then define
the following parameters on the component properties panel" type I Shape5ect, width I
'.& in, left pins I &, right pins I (. Then minimi.e component properties panel.
Select te=t tool in the upper right side of the screen, move mouse into your symbol, left-
click and type FEG, then press F-nterG or click to place the te=t.
@otice that we planed to design F6nd - @otG parts )not F6ndG,, so the right pin has to
have inversion or F%otG type. right-click on the pin, select FPin PropertiesG from the
submenu, select F%otG in the type field, then click G:KG to apply changes and close the
dialog bo=.
@otice that you donMt need to design another F6@G parts. Try to select 6@ )2, or 6@ )/,
and you see that they are the same as ;ust designed part. 6ll parts in the group have the
design, but pin numbers should be different )not now, you will define them in a a few
seconds,.
('(
Select FComponents < Pin 7anagerG from main menu. n the pin manager dialog bo=
select the part, define its pin numbers, the select the ne=t part and so on until you define
pin numbers for all 6@ parts. @otice that you donDt have to select ne=t pin using mouse
every time, to switch to the ne=t pin simply press F%ownG key. Then close pin manager.
('&
6lso notice that you can define FnputG and F:utputG electric type to corresponding pins.
These parameters will be used for -lectrical 5ule Check feature in Schematic.
The ne=t step is attaching the related pattern to multipart component. Select FComponent
< 6ttached PatternG from main menu. n the attached pattern dialog bo= select your library
and pattern" you may use %P(/ with fi=ed parameters or %PS965 and define F(/G for
F@umber &G. $e will use the second way, because as you remember all the pads of F%P
(/G have round shape and the first pad of F%PS965G is rectangular. @otice that you
donMt need to specify pin-to-pad connections because the pin numbers )i.e. pin-to-pad
connections, are already specified from pin manager. Select different parts in upper left
side of dialog bo= and see the connections to ensure they are right. Press F:KG to attach
the pattern and to close the dialog bo=.

The multipart component is ready to enter into your designs.
".& Designing .CC and 4:D s*mbols
Cou will design 9CC and >@% symbols using net port type.
Select FComponent < 6dd @ew To 0ibraryG to add a new component, then select it in the
component table. %efine the name F9CCG on the component properties panel and select
F@et PortG in the part type bo=. @otice that all net ports have F@et PortG marking in the
upper right corner of their graphic on the component table.
('2
7inimi.e component properties panel, then select FPinG tool in the upper right side of
screen and place single pin, rotate it three times )select and FCtrlH5G,. Select line tool and
place silk line of the symbol.
('/
Bide pin number by selecting FComponent < Pin @umbers < BideG from main menu. 9CC
symbol is ready. @ow please add component and create >@% symbol in the same way.
Select F-dit<Center SymbolG for >@% because in our case its origin is not in the center,
so you have to center it to make the part origin hidden by default in Schematic.
@otice that you donMt need to attach patterns to net ports, because these symbols are used
only to connect wires together without visual connection..
".-. Using additional fields
%efault component fields in %ipTrace include 5ef%es, 9alue and Type. Bowever,
sometimes you need to add manufacturerDs name, link to data-sheet, description or other
field to the component. n this case you can use additional fields which you can specify
yourself.
@ow select FComponent < %efault 6dditional *ieldsG from main menu. This dialog bo=
allows you specify default fields and their values that will be added to all new
components. *or e=ample if your design the library of 0T components, you can add
manufacturer field and specify F0inear TechnologyG as its default value.
Please add 7anufacturer and %atasheet fields" type F7anufacturerG in the name bo=,
select Type"Te=t and click 6dd button, then type F%atasheetG in the name bo= select
Type"0ink, enter some link into F%efault 9alueG bo= and click 6dd. @otice that you can
also enter values directly into additional fields table.

('4

*rom now all your new components will have such additional fields. Close the dialog
bo=. Select FComponent < 6dd @ew To 0ibraryG or press FCtrlHnsG to add a new
component, then select it, ma=imi.e Component Properties panel using arrow in its left
side and click 6dditional fields to see the list of additional fields for new component.
@ow you can edit, add or delete additional fields to the component, however we will not
('8
Select your capacitor. @otice that it has no additional fields, because weDve created it
before changing F%efault 6dditional *ieldsG. So we will add several new fields to it.
Click 6dd button, enter F7anufacturerG into the name field, select FType"Te=tG and enter
your company name into the value field, then click :K. @otice that you can simply press
-nter key to accept and -sc key to cancel in all dialog bo=es.
('1
6dd F$eb-siteG field in the same way, but select FType"0inkG and enter some real web-
site address into the value field.
"./ Spice settings
$ith %ipTrace you can e=port your Schematics into 0T Spice to simulate and see how it
works. $e will review this step-by-step in the Part of this tutorial. Currently we will
only specify that our C6P part is capacitor with some value and it can be added to Spice
net-list. Please select C6P if it is not selected in the components table, then
FComponent<Spice SettingsG from main menu. Select F7odel Type" CapacitorG, then
double click in Parameters " 9alue )cell with F(u*G te=t, and edit value, press enter or
;ust move focus to another field. n the Template field above you can see how this part
will look in spice net-list. n our case pin-to-signal map is correct, however if you need to
edit it for other components simply enter signal names into the table in left side of spice
Settings window. 0ist of available signals )as information, is located below that table.
('3
Capacitor is very simple part, so we donDt need specific model in te=t file or program to
show how it works );ust model type and capacity,. Bowever for transistors you can load
models from e=ternal files )usually Spice models are available from manufacturer web-
sites, or enter model te=t manually if you know how to do that )see Spice 0anguage
documentation,. 6lso there is SubSkt type where you can enter<load model of almost any
part as the program.
F>et Spice 7odel from 0ibraryG button allows you load e=isting spice settings from
another %ipTrace component.
@otice that such dialog bo= is also available in Schematic program and you can define
spice settings after completing )or during, schematic drawing.
$eDve finished designing our library, click :K to apply and close spice settings, then
button with diskette icon in the upper left side to save your library and close Component
-ditor program.
('+
".2 Placing the components
:pen the Schematic Capture program, i.e. go to Start 6ll Programs %ipTrace
Schematic. Cou should add your library to library panel first, so select F0ibrary < 0ibrary
SetupG, uncheck F>et 0ibraries from *olderG bo=, press FNG button at the right side of
active libraries list and open your library. Close the library setup dialog bo= to apply
changes.
f the origin is shown press *( to hide it. Asually you donDt need origin to design
schematics. Bowever this feature works in the same way as in other package programs,
so you can use it if necessary.
@ow please scroll library panel to the right using arrow buttons on its right side, then
select F7y 0ibraryG. Select resistor in the component table and place it using left-click in
the design area, the same with capacitor.
@otice that you can also place the components using F:b;ects < Place PartG or the
corresponding button on the ob;ects panel. n this case you donMt need to configure
libraries via 0ibrary Setup dialog bo=.
$e will see how to use additional fields of our capacitor. Please make right click on it
and select F0inksG from submenu. @ow you can easily open web-site you entered.
(('

Cou can also display additional fields as Part 7arking from F9iew<Part
7arkings<7ain)6dditional,<6dditionalG or change via component properties window
)right click on the component and select FPropertiesG,.
(((
Select the multipart component from the component table. Cou have created the
component with similar parts and power part. 6ll similar parts can be placed using one
item from part list )in our case F6@ )/,G, or in the same way as separate parts. To change
the placement mode for similar parts, select F9iew < >roup PartsG from main menu.
Power part can be placed automatically )if F6uto 9CC<>@%G is checked, or manually by
selecting from part list and placing to the design area.

@otice that active part and number of parts are shown in the component table.
Select F6@ )/,G and try to place several symbols to the design area. The program
automatically select the part from part group and place power symbol for the component.
((&
will show you how to use @etPorts. Place more 6@ parts to receive two 6nd@ot
components )C( and C&, and two power symbols. Then select on the component table
9CC symbol and place two parts, the same with >@%. Connect the pins. @otice that for
net ports program shows Type )or F@ameG from Component -ditor,. Cou can unite two
net ports by defining the same type and two wires connected to the same pins of net ports
with similar type are connected. 7ove mouse arrow over the wire connected to 9CC or
>@% and you will see that all the wires connected to the same symbols belong to single
net.
((2
To rename the net which connects 9CC pins right-click on the wire and select the first
item or right-click on the pin and F@et @ameG.
@otice that you can form multipart components from the separate symbols and attach
patterns to them without using Component -ditor. Simply check F6llow PartsG bo= in the
component properties dialog bo= )right-click on the part, then FPropertiesG, and define
the same 5ef%es to symbols, then F6ttached PatternG button to define related pattern and
pad to pin connections.
6lso you can connect the pins to nets without wires )right-click on the pin, select F6dd to
@etG, then select net, check FConnect without wireG and F:KG,, unite nets by name
)check bo= in the net properties dialog bo=, and connect pins to the net with similar name
automatically )check bo= in the net properties dialog bo=,. The last method is the fastest
way to connect 9CC, >@% )if you plan to hide power nets and parts,, C0K, etc.
These features are described in details below.
((/
III. Using different package features
This part of tutorial includes the description of important features that werenDt reviewed
above. Bowever notice that tutorial doesnDt include detailed description of all %ipTrace
features yet, we are e=panding it step-by-step.
1. Connecting
1.1 (orking )ith buses and page connectors
This section will show you how to use buses and page connectors in the schematic
capture program.
Select F:b;ects < Circuit < Place BusG from main menu or the corresponding button on the
ob;ects panel, then place bus in the design area by defining its key points. 5ight-click
twice to finish placement and switch to the default mode. 7ove mouse over part pin, left-
click, then move to bus and left-click to connect. n the dialog bo= appeared you can
define the name of new net in the bus or connect the wire to e=isting net )which are
already connected to that bus,.
@otice that you can change wire to bus connection at any time" move mouse to the wire
segment connected to bus, right-click and FBus ConnectionG from the submenu.
There are / nets connected to our bus, we will change F@et /G connection to F@et &G.
@ow FC("(G and FC&.& " 4G are connected to the same net via bus.
The markings of wire-to-bus connections can be net names or numbers in the bus. Select
FConnection to BusG from main menu to change them.
((4
@ow please add a sheet to the schematic. Select F-dit < 6dd SheetG from main menu or
press FCtrlH0G. Cou can see the list of sheets on the Tab in bottom left corner of
schematic main window. Select FSheet &G there.
((8
Cou can rename or delete the schematic sheet or insert blank one between two e=isting
sheets using right-click on the tab in bottom left and selecting appropriate item from the
submenu.
Select Page Connector tool on the ob;ects panel in the top and place it to your empty
sheet )it should have FPort 'G name,, then change the sheet to Sheet ( using tab below
and place page connector there )it should be FPort (G,. Then connect e=isting bus to page
connector" select bus tool, then left-click on the bus, move mouse arrow to page
connection point )blue circle, and left-click to connect.
7ove mouse over FPort (G, right-click and select the first item from submenu and rename
page connector to FPort 'G. Cou can see that connection point color was changed to
green. This means that current page connector is connected to another one.
@otice that you can also connect more than & page connectors by defining the same name
to them.
((1
Select FSheet &G and create the bus connected to FPort 'G there.
@otice that the name of your bus is the same as the bus on Sheet ( has, i.e. this is the
same bus. @ow you can place parts on the second sheet and connect their pins to F@et &G
or F@et 2G using bus or create new nets common for both sheets.
((3
1." (orking )ith :et Ports
$e already tried to use net ports above to make 9CC and >@% connections. n the most
cases they are used in that way, however you can also make multiple connections using
net ports with several pins.
Place more parts on the second sheet, but do not connect their pins to the bus. Then select
FPortSSchG on the library panel )notice that you can scroll libraries if necessary,, find
FPort 3G there and place it to the design area.
7ake connections from the parts to Port 3, then place Port 3 to the first sheet and connect
the parts located on the first sheets to Port 3 too. @otice that net names connected to the
same pins of Port 3 on FSheet (G and FSheet &G are the same, i.e. all wires connected to
pin ( of FPort 3G parts are connected, the same with other pins. Cou can connect or
disconnect ports )i.e. easily change schematic structure, by changing FTypeG string in net
port properties )right-click, then select Properties,.
1.#. Connecting )ithout )ires
The pins can be also connected completely without wires. n this case they donDt depend
on the sheet or part location. 7ove mouse arrow over the pin that is not connected yet,
right-click on it and select FConnect to @etG, in the dialog bo= shown select the net and
check FConnect without $ireG bo=, then press :K. :n the picture below you can see the
pins connected to F@et 'G and F@et /G without wires.
((+
@ow please scroll the design to blank area - we will try to connect pins to the net by
name. Place single >@% symbol, move mouse over its pin, left-click to start creating
wire, then move mouse a bit up and press F-nterG key.
(&'
5ight-click on the wire segment connected to >@% and select Properties. n the net
properties dialog bo= rename net to >@% and check FConnect Pins by @ameG bo=. Press
F:KG to apply changes and close the window.
@ow select 6nalog %evices library )6%, and try to place the first component a few times.
@otice that all >@% pins of placed component are automatically connected to >@% net
without wire. 6lso when you change that property for the net, the program checks all
e=isting parts for free pin which name is the same as net name.
This feature is the easiest way to connect pins which have the same name for all
schematic. These can be power, C0K pins or even data buses.

1.$ Connection +anager in Schematic and PCB La*out
:ne of the easiest ways to make connections in Schematic and PCB 0ayout is connection
manager. To open it select F:b;ects < Connection 7anagerG from main menu in
Schematic or F5oute < Connection 7anagerG in PCB 0ayout.
:pen connection manager in the Schematic where you are in. Select some net in the bo=
above the window, you will see all its pins. @ow you can easily add<delete pins to<from
the net. To add the pin select part and its pin below, then press F6ddG. @otice that only
free pins are shown there, so if you canDt find the pin you need, it is already connected
)maybe to another net,. 6lso you can create new net by pressing FHG button.
F...G and F?G buttons rename and delete current net respectively.

(&(
Press F:KG to apply all changes you made and close connection manager or FCancelG to
close it and recover old net structure.

". ,eference Designators
*rom now on on we will work with schematic e=amples located in FC"<Program files <
%ipTrace < -=amplesG folder or another place where you installed %ipTrace.
:pen SchematicS&.dch file from -=amples folder.
(&&
:n this Schematic you can see different types of pin connections made by our electronic
engineer, however our goal is to make some e=periments with reference designators to
show you how it works.
Current Schematic contains &2 capacitors from C( to C&/ )C(+ is missing,, but when
trying to edit you probably need to insert for e=ample C4 somewhere. So please try to
place a capacitor from the library you recently create )7y 0ibrary,. t will be our C4, but
currently it has C(+ designator. 5ight-click on that capacitor and select the first item from
submenu, enter FC4G and press F:KG. Program will show the warning message, but also
suggest to rename the component with shift of 5ef%es numeration. Select FCesG.
The capacitor was renamed to C4 and old C4 became C8, etc. till C(3 - C(+. @ow you
can see in connection manager that C(+ designator is not missing, however you inserted
C4. n the same way you can place any component and rename its designator with shift of
other ones.
@ow please rename your C4 to C2', then check capacitor designators in connection
manager I C4 and C&4-C&+ are missing. To correct this issue simply right-click on the
capacitor )C&+, and select F:ptimi.e 5ef%es < 5ef%es CG - C2' become C&/, whyP
$hile optimi.ing the 5ef%es program removes all empty places in the designators array,
so C8-C&/ become C4-C&2 and C2' becomess C&/.
(&2

@ow please close your Schematic without saving and run PCB 0ayout module, then open
PCBS& file from -=amples folder. 5ename C3 and C(' in the upper side of the board to
C&3 and C2' )right-click on the component and select first item,. Select F*ile<Save 6sG
and save changed PCB file somewhere.
(&/
Close PCB 0ayout and open Schematic Capture again )notice that you can open it
directly from PCB 0ayout by selecting FPrograms<SchematicG from main menu, however
we donDt recommend to do this for $in +3<7- users,.
:pen SchematicS&.dch file and find C3 and C(' ...oops, sometimes it is really hard to
find the component with specified 5ef%es on big schematic or PCB, so press CtrlH* )or
select -dit < *ind :b;ect from main menu,. Type Fc3G and press F-nterG to find it, C3
will be placed in the center of design area and highlighted.

@otice that you can minimi.e F*ind :b;ectG window by clicking the arrow in its upper-
left and use it while editing your design without showing all parameters.
Joom n the schematic to see C3 and C(' better.
@otice that PCBS& is the design related to SchematicS& and weDve renamed these
capacitors there. $e can rename them here too, but what do you think if while designing
comple= pro;ect you renamed a few hundreds of components )according to their positions
on PCB, and donDt remember their old designators.
n this case we can use Back 6nnotate feature, so please select F*ile<Back 6nnotateG
from main menu and the PCB file you saved in open dialog bo=.
@ow you can see that all designators in Schematic )in our case C&3 and C2', are changed
according to PCB.
(&4
#. <o) to find components in libraries.
%ipTrace includes the impressive number of components in Standard libraries )appro=
4',''', and we enlarge these libraries step-by-step. The libraries are formed by
manufacturers and components are sorted there. Bowever sometimes we donDt know the
manufacturer of some component or it may be produced by number of manufacturers or
we donDt know its full name, but only digits in the end of its name, etc. To make
searching components easier all %ipTrace modules have special searching feature.
f you are in Schematic, select F0ibrary < Search ComponentsG from main menu. *or
e=ample we need some component that contains F&2&G in its name, but we donDt
remember other characters, letters or so, because a friend recommended it about a month
ago. So type F&2&G in the F@ameG field and press F*ind @owG.
n several seconds the program shows ((& components in the results list which contain
&2& in their names. Cou can also preview the component, its pattern and library where it
is located.
6lso you can place the selected part of the component directly from search window by
pressing FPlaceG button.
@otice that we have searched 6ctive libraries, however you can select the libraries you
want or search all known libraries )select appropriate item in FSearch nG group,.
The library list is active only if FSearch n" SelectedG is activated.
(&8
@otice that you can search component libraries in Schematic and Component -ditor
)Component < Search in 0ibraries, and pattern )footprint, libraries in PCB 0ayout and
Pattern -ditor )Pattern < Search in 0ibraries,.
6lso search function is included into all placing<inserting etc. dialog bo=es where you
may need to search libraries for components or patterns, however those dialog bo=es
allow you to search through their library lists only.
$. lectrical ,ule Check
-lectrical 5ule Check )-5C, feature helps you reduce the probability of error while
designing schematic. 5un the schematic module if you are not there and open
SchematicS&.dch from -=amples folder. *irst of all we have to define electrical rules, so
select F9erification<-lectrical 5ule SetupG from main menu.
n the dialog bo= shown you can define incompatible pin-to-pin connections that may
cause error or warning while running -5C by clicking in the grid cells with green, yellow
and red s!uares. FPin TypeG item in F5ules to CheckG bo= means checking pin-to-pin
connections defined in the gridR F@ot ConnectedG - looking for free pins that are not
connectedR F:nly :ne Pin in @etG - looking for nets with only one pin, i.e. the nets that
make no sense may be potential errors in net structureR FShort CircuitG - looking for
Power to >@% connections, you can define the mask for power and ground pins in
FPower Pins for SCG group.
(&1
Keep the default settings and press F:KG or FCancelG to close the dialog bo=.
@ow select F9erification < -lectrical 5ule Check )-5C,G from main menu. f you make
the check for SchematicS&, it should show one warning for FBidirectional to :utputG
connection. To locali.e the error on schematic double click on it I in case your resolution
is more than mine while writing the tutorial, you will see the net and pins highlighted in
the design area. Cou can correct the errors and rerun -5C without closing -5C results
window.

@otice that if you want to check not connected pins you can specify pins that are really
not connected )i.e. -5C must not report them,. 5ight click on one of the pins and select
F@ot ConnectedG from the submenu to block the pin for connecting any net and -5C.
(&3
&. Bill of +aterials =B7+>
%ipTrace Schematic module has B:7 feature that allows you to customi.e columns and
rows, add tables or pages to e=isting pro;ect, e=port files to -=cel CS9 format or save as
te=t file with appropriate table formatting.
Select F:b;ects < Bill of 7aterialsG from main menu. Specify FTable 5ows" Component
TypeG, add the columns with settings you can see on the picture below, select FCreate
:n" @ew SheetG and FS: 6/G in the sheet template bo=. Check F6d;ust by $idthG to
stretch the table accordingly to page width. Press FPlace TableG button to add new 6/
sheet with S: title and B:7 table to your pro;ect.
The B:7 dialog bo= will be closed and new sheet added to your design. Select FSheet &G
display titles and sheet using F9iewG menu and edit the row height and number of lines
for cells where the length of strings e=ceed column width )left-click in the appropriate
cell, then change te=t and row height,.
(&+
@ow we have B:7 table on the additional sheet, which we can print with the pro;ect.
(2'
6lso notice that you can place the table to the same sheet with Schematic" select FCreate
:n" Current SheetG, press FPlace TableG and choose table location after closing the dialog
bo= )left-click in design area,.
f you have multi-sheet schematic with many components, then it is possible to create
separate table for each schematic page directly on it.
Cou can e=port the file directly from B:7 dialog bo= or from the placed table after
editing it )for e=ample you need some columns that can not be inserted via B:7 dialog
bo=,. Tables in Schematic and PCB 0ayout can be easily saved to CS9 or te=t with
formatting" right-click on the e=isting table and select FSave to *ileG from table
submenu.
-. Importing13porting netlists
%ipTrace allows to create netlists of different formats to transfer them to other software
packages, and import netlists from other programs. 6lso e=ported netlist can be used to
review net structure of schematic file via notepad or other te=t editor.
To e=port netlist in Schematic select *ile<-=port<@etlist from main menu and set netlist
type. 6 netlist will be created from the drawing opened in the current Schematic window.
0et us see how to import a netlist in Tango format created by other program. To do that,
open a new document in PCB 0ayout and select *ile<mport<@etlist<Tango, then select
tangoS(.net file from FC" < Program files < %ipTrace < -=amplesG folder or another place
where you installed %ipTrace and open it. Program is trying to find components and
patterns included in the netlist. Then a window with listed components, their 5ef%es and
pattern names appears.
(2(
So in the first column we can see 5ef%es of components, in the second column their
patterns, and in the third column types of components. f the program couldnDt find the
pattern for the selected component, then in Pattern field below the table DnoneD will
appear. *or e=ample, component C/( that comes first in the list has C6P &&4 pattern that
isnDt included in %ipTrace libraries. n this case you need to choose a library containing
that pattern )probably you will need to create that pattern by yourself, or select an
alternative pattern, if possible. To attach pattern to a component, click 6dd.
n the appeared window you need to choose a library and a pattern in it, and press :K
afterwards. The selected pattern will be attached to component ]/(. ts name and the
name of the containing library are shown in Pattern field and 0ibrary.
6lso notice that you can attach patterns to components by type or to all components that
have the same pattern property at once. @ow please add patterns to all components in the
list using this feature. @otice that components with attached patterns have FstarG symbol
at the end of pattern name. f a component doesnDt have a pattern attached, it simply wonDt
be imported. ThatDs why you need to make sure that all components have attached
patterns.
Cou should also remember that pin numbers and their !uantity for a component in a
netlist and pad numbers of the attached pattern should match.
6fter that click mport to complete import. f your netlist has components without
attached patterns, appropriate message will be shown. Select F@oG to cancel importing
and attach all patterns or FCesG to import without some patterns.
(2&
/. Spice simulation
%ipTrace doesnDt have its own simulator, however allows you to define spice settings and
e=port net-list to any simulation software. $e will try to simulate astable flip-flop
schematic from part of this tutorial using 0T Spice. $e would recommend to use 0T
Spice for simulation as it is free and comparable )or even better, to e=pensive
professional simulators. Bowever if you have another program, you can use it too.
@ow please run Schematic program and open FC" <Program files<%ipTrace<-=amples<
Spice<6stableS*lipS*lopSSpice.dch G. $e have already defined all spice settings for this
schematic, however we will review a couple of parts to learn how to that. 5ight click on
C& capacitor and select FSpice SettingsG from its sub-menu. %efining capacitor is very
simple" you should select F7odel Type " CapacitorG, enter value into parameters table )in
our case &&u*, and specify positive and negative pins. To specify pin you should enter
value into pin-to-signal table in the left side, list of available signals is located below.
@otice that you can enter parameters directly into table cells. Template field shows how
the component looks in spice net-list. Cou can also scroll that field to the right.
(22
@ow try to select any different model type )for e=ample Current Source,. f you selected
current source, you can also specify its function )select P$0,"
-nter number of points for P$0 function and click :K. @ow you can see that you can
enter points in parameters table one-by-one. %ifferent functions re!uire different
parameters )amplitude, phase, etc.,. See detailed description in Spice language
documentation. :k, now return back to capacitor, define its value and click :K.
(2/
Capacitor and function donDt re!uire additional model description, so we simply define
parameters for them. @ow please right click on Q( and select spice settings, you can see
that F7odelG tab appeared near FParametersG, select it. Bere you can enter model te=t or
load it from e=ternal file, some component manufacturers publish spice models for their
components, so you can use them.

6lso notice that you can get all spice settings from another %ipTrace library )F>et Spice
7odel from 0ibraryG button,. Click :K or Cancel to close the dialog bo=.
The file we loaded doesnDt have valid spice model for power source and we should define
it, so right click on B( and select Spice Settings. Cou can see that we have voltage
source, but no valid function. Please select F*unction " PulseG, then define Pulse 9&^4,
Pulse P$^&'s, Pulse P-5^2's. Click :K, now we have voltage source that produces 49
during first &'s, then ('s interval, etc. 6ll things are ready.
Select F*ile<-=port<Spice @etlistG from main menu. n the small dialog bo= shown select
>@% net )this is our .ero point, and specify F.T56@ 's 2's '.(sG in FCommandsG - this
means simulate from 's to 2's with '.(s step. @otice that you can also define<change
commands directly in 0T Spice. Click :K and save .cir file somewhere.

(24
@ow please run 0T Spice. f you donDt have it yet, you can download it from
http"<<www.linear.com<designtools<software<switchercad.;sp
Select *ile<:pen in 0TSpice and open .cir netlist you ;ust saved )notice that you should
select correct F*iles of TypeG,. Cou can see net-list in te=t format. Select FSimulate<5unG
and close error log window. Select Plot Settings<9isible Traces and choose led(. @ow
you can see something like this"
This is current on 0-%(. 6s we can see it works during first &' seconds, then has (' sec
interval. @ow you can also add other signals to see how they work, etc.
2. Checking net connecti%it*
:ne of the most important features to verify your design before prototyping is net
connectivity check. t allows you to check if all nets are connected and reports all isolated
areas )not depending on connection type" traces, thermals or shapes,.
@ow please run PCB 0ayout module and open FPCBS&.dip fileG from FC" < Program files
< %ipTrace < -=amplesG or another place where you installed the program. Select
F9erification < Check @et ConnectivityG. n the dialog bo= you see you can define
ob;ects that will be used as connectors while checking connectivity, typically it is
recommended to keep all bo=es checked. Press :K.
Cou will see the progress bar, then F@o -rrors foundG message, so the design is correct
and we will make a few errors to see how the feature works.
Select F-dit TracesG tool on the route panel, then move mouse to the trace that connects
C(8"& to via to >@% copper pour in Bottom layer, right-click and select FAnroute TraceG
)connection will be hidden in this case because of copper pour,.
(28
The second error will be isolated copper pour area. Switch to Bottom layer and scroll to
bottom right corner of the design. @ow place two shapes )arcs or lines, to signal layer
)appropriate bo= on drawing panel, to isolate one of the vias and update copper pour
)right-click on its side and FApdateG,.
(21
This is a simple situation you can find by yourself, but if you have comple= design with
number of layers and thousands of pins, isolated copper pour areas and non-connected
pins can be unnoticed.
@ow select F9erification <Check @et ConnectivityG and click :K. Cou can see
connectivity check result which reports @et 1 as broken one with 2 areas" first area is
copper pour and all pins connected to it, second is C(8"& )our first error with S7% pad,
and third one is isolated copper pour area.
To make further correction process more comfortable you can save result to the te=t file.
5. Placement features

Starting from version (./' %ipTrace has advanced placement features and integrated
auto-placer to make placement after converting to Schematic and placement optimi.ation
easier. $e will see how these features works using one of our e=amples. @ow please run
PCB 0ayout module, select *ile<:pen and open FC"<Program files<%ipTrace<-=amples<
SchematicS/.dchG. @ow you can see something like on the image below and it is
necessary to spend some time to place all that components to their places inside board
outline manually.
(23
@ow we will import some board outline from %?*. Select *ile<mport<%?* and open
C"<Program files<%ipTrace<-=amples<outline.d=f file. n the dialog bo= shown you can
see %?* file we plan to import. Select FBoard :utlineG layer and Convert to" Board
:utline. 5esolution for screen e=amples is low so we should scroll the window to see
FConvert toG bo=, however you can do that without scrolling.
(2+
By the way you can fill closed areas and cut holes in them using embedded closed areas if
necessary )usually %?* designs are made from outlines without fill,. F*ill<embeddedG
features work for copper and mask<paste layers only.
Select Fmport mode " 6ddG to add board outline to e=isting layout and press FmportG
button in the Apper-0eft of the %?* window - now you can see board outline, but the
components are still messed. *irst we will arrange components a bit, select
Placement<Placement Setup from main menu"
Check FPlace Patterns :utside the Board :utlineG bo= to arrange components near board
outline. :ther things you can keep as is or simply make the same settings as on picture
above )notice that values are in mm, however would recommend not to change values
yet,. Click :K to apply changes and press F6rrange ComponentsG button on the
placement tool bar or select FPlacement<6rrange ComponentsG from main menu"
(/'
6ll components are now located in one place near board outline. Select
FPlacement<Placement by 0istG from main menu, then try to select some component from
the list )left click, and move mouse to the board outline )without holding left button,,
click inside the board outline to place the component you selected.
(/(
@otice that component disappears from the list )the list shows only the components that
are outside the board outline,. @ow please place A(, A&, A2, W(, W3, W(&, 5@( and 5@&
in such way. $e suppose that those components have fi=ed positions, that can not be
changed. @ow please select and lock them )CtrlH0,, e=cept A2. 6lso right click on A2
and select Properties, then Placement tab, Spacing U Ase"Custom and 9alue"&'mm )this
means that we use custom clearance for A2 and other components should be located
U&'mm far from it,. Click :K, then lock A2 too.
@ow we will auto-place all other components with 4mm spacing. Select
FPlacement<Placement SetupG, change ? Spacing and C Spacing to 4mm, also notice that
6llow Pattern 5otation is checked )sometime it is useful to turn it off though, for
e=ample for single-sided boards with ;umper wires where ;umpers have some direction
and changing component rotation you can define manually is not great idea,. Ancheck
FPlace Patterns :utside the Board :utlineG, FAse Pattern SpacingsG should be checked to
use &' mm clearance for A2. $e do not recommend to select Fncrease Placement
QualityG yet )you can play with it later if you want to do that,. @ow please click :K to
apply changes and click F5un 6uto-placementG button on the placement tool panel or
FPlacement<5un 6uto-placementG from main menu. Cou get something like this"
(/&
@otice that connections )blue lines, between different resistors, diodes, etc. are optimi.ed
by their length )i.e. minimum further trace length,. :f course some connections are not
ok, because we have placed large components manually before. f you auto-place 600
components, you can get better result, however usually this is not acceptable in real
conditions.
6lso A2 is separated from other components, because we defined &' mm spacing for it.
16. 9anout
Typically fanout feature can be used for two purposes" automatically adding vias to
components )such as B>6, S:C, QA6%, and automatically placing vias to connect
S7% pads to power<ground plane. $e will try both things.
:pen PCB 0ayout module or if it is already opened and have something select *ile<@ew
from main menu or @ew button on the standard panel.
@ow select S7T library and place one 00C&' package, then B>6 library and place two
B>6-(''<(4=(4 packages. 6dd two inner layers to your design )0ayer<6dd 0ayer,.
7ove mouse to 00C package to get green highlight, right click and select *anout. n the
fanout dialog bo= select Pads"0eft )this means that we place vias only for the left pad line
of the 00C package, and uncheck FAse Connected Pads :nlyG bo= )this means that we
connect all pads, not only connected to some net,. -nter '.'/ and '.'& in into outer
diameter and hole diameter fields for the via. Click :K.
(/2

@ow you can see that vias are placed outside for the left pads of our package.
5ight click on the pattern and select *anout again. @ow we will place .ig-.ag vias for the
top pads of our package. Select FPlacement"Jig-.agG and FPads"TopG, other settings keep
the same, click :K.

(//
$e have two B>6 packages. @ow we will make through vias for one of them and blind
vias for another. 5ight click on the first B>6 package and select *anout, select FPattern
Type" B>6 I Through viasG, set via si.e to '.'2 in and hole to '.'(4 in, click :K. *or
the second pattern do the same, but select FPattern type" B>6 I Blind viasG.
$e can see that for the first pattern all pads are connected to vias, for the second one two
rows are without vias )i.e. they should be connected on the top layer,, and for the ne=t
rows vias are placed by layers )to connect two rows on each layer,.
@ow place several additional S7% packages, few through-hole packages and make net to
connect several pins of these packages )we suppose this is our >@% net that we should
connect to plane layer,. 5ight click on one of the net pins and select F*anoutG. Keep all
settings without changes and click :K.
(/4
@ow all S7% pads of the net have vias that can connect pads to any plane layer.
11. <ierarchical Schematic

$e will design very simple hierarchical schematic to show you how this feature works.
:pen Schematic program. n %ipTrace hierarchy blocks are associated with sheets, so
first of all we will add two additional sheets to our blank schematic, select -dit<6dd
Sheet twice. Then we should specify that our additional sheets are hierarchical blocks.
Select the second sheet in the bottom-left corner and F-dit<Sheet Type<Bierarchy BlockG
from main menu, the same for the third sheet.
@ow select main )first, sheet and place several components to it. This will be our main
Schematic, without hierarchy blocks yet.
Select second sheet. @ow choose F:b;ect<Bierarchy<Place ConnectorG from main menu
or the button with connector and FBCG te=t on the ob;ects panel. Place several hierarchy
connectors to the second sheet )notice that you can not place hierarchy connectors to
common, not hierarchical, sheets,. These connectors are inputs<outputs of hierarchy
block, also position and rotating of the connectors shows where the pins of the block will
be located. $e will place 3 connectors, / on the left side and / on the right side. 6lso
place two diodes from %iode library and connect them to connectors.
(/8
Select Sheet 2 and make second hierarchy block" place several connectors, components
and connect them. @otice that you can also rename connectors by right click and
selecting the first item. Connector name correspond to pin name on the hierarchy block.
(/1
%ipTrace supports multi-level hierarchy, i.e. $e can insert hierarchy blocks into another
)top-level, blocks. @ow please select Sheet &, then :b;ects<Bierarchy<Place Block or
button with BB te=t on the ob;ects panel. n the list of available blocks select FSheet 2G
and place two blocks to the second sheet. @otice that you can also place Sheet & into
Sheet & or make a loop from blocks, i.e. make hierarchy error. To avoid such situations
use F9erification<Check BierarchyG option from main menu. PCB 0ayout program also
checks hierarchy for loops when open schematic and display warning message. $e will
not make loop right now, ;ust place two Sheet 2 blocks to Sheet & and connect them to
Sheet & connectors.
Select main sheet and place few blocks )this may be Sheet & or Sheet 2, to the main
schematic. Connect hierarchy blocks with other components.
@ow we can convert our simple )non-real, hierarchical schematic to PCB. Press CtrlHB.
n PCB 0ayout program components that were in hierarchy blocks are overlayed, so we
will use arrangement )first button on the placement panel, to arrange all components.
5ight click on one of the components that were in hierarchy block and select
FPropertiesG. See that each hierarchy component has additional field with block)s,
5ef%es and component 5ef%es. @otice that this additional field is used for updating PCB
from hierarchical schematic, because hidden % )updating by component, and designator
can be different when you change hierarchical schematic.
(/3

@ow you can auto-route this PCB or change schematic and try to update PCB, etc.

SSSSSSSSSSSSSSSSSSSSSSSSSSSS
ThatDs all for now.
Thank Cou for your interest in our software product and learning this tutorialZ
$e will enlarge the tutorial in future by adding description of e=isting features that are
not here yet and by upgrading %ipTrace package with appropriate changes in tutorial.
DipTrace Links
f you have any !uestions or suggestions, please contact our customer support at
support#diptrace.com and our staff will gladly answer all your !uestions.
To communicate with other %ipTrace customers, suggest new features for %ipTrace and
discuss them, ;oin %ipTrace Community at CahooZ" http"<<groups.yahoo.com<group<diptr
%ownload the latest version of %ipTrace at http"<<www.diptrace.com<download.php
Check your version and build )FBelp < 6boutG, and compare it to the one on our web-site.
:rder %ipTrace on-line at http"<<www.diptrace.com<order.php
(/+