ENGI 3861 Digital Logic

III. DIGITAL CIRCUITS

(a) CMOS Logic

- recall that in Complementary Metal Oxide Semiconductor
(CMOS) logic, voltage level represents binary value with
typical levels being:
0 01.5 V, 1 3.55.0 V

How do we implement gates? using electronic switches


Inverter (NOT)
















- switches can be implemented using transistors based on
semiconductor material such as n-doped silicon (NMOS) or
p-doped silicon (PMOS)

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ENGI 3861 Digital Logic
NMOS transistor




V
gate
=0 V transistor is off
and does not conduct (I =0)
switch open

V
gate
=5 V transistor is on
and conducts (I >0)
switch closed




PMOS transistor




V
gate
=0 V transistor is on
and conducts (I>0)
switch closed

V
gate
=5 V transistor is off
and does not conduct (I =0)
switch open




- PMOS operation is complementary to NMOS

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ENGI 3861 Digital Logic
- simple representation of transistors

NMOS PMOS









CMOS Inverter

- uses NMOS and PMOS in a complementary way to reduce
power/energy consumption
Complementary Metal Oxide Semiconductor (CMOS)

- aside: reflect on why reducing power/energy consumption is
important!











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ENGI 3861 Digital Logic
CMOS NAND




















Function Table for NAND

A B Q1 Q2 Q3 Q4 Z





Note: in CMOS circuits, PMOS transistors must be connected to
power supply (V
DD
) and NMOS transistors must be
connected to ground (0 V) CMOS AND cannot be
constructed using 4 transistors, but can be constructed with 6
transistors since AND NAND +NOT
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ENGI 3861 Digital Logic
CMOS NOR

















Function Table for NOR (complete at home)

A B Q1 Q2 Q3 Q4 Z






Note: CMOS OR gate must be constructed using 6 transistors
based on OR NOR +NOT
Digital Circuits - 5
ENGI 3861 Digital Logic
(b) Electrical Characteristics of CMOS

Static Behaviour
- input and output signals of gates are not changing
static power consumption, noise immunity, tolerances
between input and output levels

Dynamic Behaviour
- input and output signals of gates are changing
dynamic power consumption, timing from input change to
output change

Logic Levels and Noise Margin

I/O Characteristic of CMOS Inverter










- inputs allowed over wider range than precise outputs

e.g., V
in
<1.5 V produces V
out
very close to 5 V
V
in
>3.5 V produces V
out
very close to 0 V
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ENGI 3861 Digital Logic
- DC noise margin (NM) is amount of noise to corrupt an output so
that the input of the subsequent gate will not be properly
recognized















- consider data sheet in Table 3.3:

V
OHmin
=4.4 V (with I
OH
=20 A)
V
IHmin
=3.15 V

NM
H
=4.4 3.15 =1.25 V

V
ILmax
=1.35 V
V
OLmax
=0.1 V (with I
OL
=20 A)


NM
L
=1.35 0.1 =1.25 V

- this presumes the expected operating condition will have current
sourced/sunk by output to be ~20 A
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ENGI 3861 Digital Logic
Fanout

- fanout is number of gates that can be connected to an output

- consider











- ideally inverters have input impedance (resistance) I =0

in practice, small amount of leakage current, I
leak
, flows through
gate and if n too large, I ~ nI
leak
too large and V
out
<<V
DD

causing improper high input to 2nd level of gates

Leakage Current

- leakage current I
leak
will occur whenever power is applied to
circuit (i.e., V
DD
has voltage applied)

when a device is in standby mode, V
DD
is applied, and
even though logic gates are not changing, power
consumption occurs due to leakage current

device batteries are draining!
Digital Circuits - 8
ENGI 3861 Digital Logic
Electrostatic Discharge

- in CMOS devices, static electricity may discharge across
insulation between gate and drain/source of transistor thereby
destroying device

sometimes necessary to be careful when handling CMOS
devices, e.g., wear wrist strap that connects to ground to
avoid static charge build up

CMOS devices used in lab should be robust enough to avoid
electrostatic damage without any special precautions

Transition Time

- when a gates output changes, it needs to charge/discharge stray
capacitances caused by transistors and wires













- obviously t
r
and t
f
affect speed of switching, i.e., rate of gate
changes

Digital Circuits - 9
ENGI 3861 Digital Logic
Propagation Delay

- propagation delay is time required for input signal to cause a
change in output signal of a gate due to change of state
required on internal transistors prior to state change at output

idealized inverter timing




realistic inverter timing





Fan-in

- in theory could design CMOS NAND and NOR gates with any
number of inputs n

Consider output of NAND gate











as n |, #transistors in series goes up (since =n)
Digital Circuits - 10
ENGI 3861 Digital Logic

- since drain-source resistance is not zero and current being drawn
from Z to ground, voltage across transistors increases as n |

practically limits n because with transistors in series all
on, Z should be small (~ 0 V) and must meet V
OLmax


- typically NAND gates are kept to 6 or fewer inputs, fan-in s 6

- similar arguments limit the fan-in of NOR gates


Logic Families

TTL Transistor-Transistor Logic (Bipolar Logic)
- uses bipolar junction transistor
will learn about in ENGI 4854 Electronic Devices
- popular in 1970s, but now supplanted by CMOS

CMOS Complementary Metal Oxide Semiconductor
- takes much less power that TTL
- many sub-families
high speed, lower power, and/or TTL compatibility
- to operate CMOS at high speed, use supply voltage V
DD
~ 5 V
- to operate CMOS at lower power, use lower supply voltage
of, say, V
DD
~ 3.3 V

- 7400 series ICs are SSI and MSI packages for building digital
systems out of discrete component when size, power, speed,
large scale manufacturing costs are not important

- in practice, many digital systems are now integrated into one or at
most a few ICs LSI, VLSI, ULSI
Digital Circuits - 11
ENGI 3861 Digital Logic
(d) Timing Hazards

Static Hazards

Consider AND-OR circuit:







- recall each gate has a propagation delay, which is typically
different for different types of gates and can even vary
somewhat from gate to gate of same type

for convenience, assume all gates in above circuit have same
propagation delay, t
prop


Timing Diagram











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ENGI 3861 Digital Logic
F should stay at 1, but drops to 0 momentarily
static-1 hazard
static because output should not change, but does
experience a momentary glitch
hazard possibility that glitch can occur

- static-0 hazards would exist with OR-AND circuits (circuits built
from POS form)

- note: a circuit with a static hazard may experience a glitch, but
may not depends on propagation delay of gates

- also, hazard may not matter to functionality of circuit
e.g., not critical in synchronous sequential logic but
critical in asynchronous sequential logic design

- can use K-maps to identify and remove:


YZ
01 11 10

0

1
00
1 1 0
0 1 0
1
0
X


no AND term covers XYZ =110 and 111
moving between these inputs could cause a glitch

to resolve, add extra gate to cover these 2 minterms resulting in

- no glitch possible
no static hazard
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ENGI 3861 Digital Logic
Digital Circuits - 14
Dynamic Hazards

Consider










output should be




but becomes




- hence, circuit has dynamic hazard possibility of output
changing more than once due to a single input change

- methods to eliminate in multilevel circuits
not in scope of course