SWITCHED CAPACITOR NETWORKS 165

SWITCHED CAPACITOR NETWORKS

The requirement for fully integrated analog circuits prompted
circuit designers two decades ago to explore alternatives to
conventional discrete component circuits. A sound alternative
was developed, a switched-capacitor (SC). The basic idea was
replacing a resistor by a switched-capacitor C
R
simulating a
resistor. Thus, this equivalent resistor could be implemented
with a capacitor and two switches operating with a two-phase
clock. This equivalent resistor is equal to 1/f
C
C
R
, where f
C
is
the sampling (clock) frequency. SC circuits consist of
switches, capacitors, and operational ampliers (op amps).
They are described by difference equations in contrast to dif-
ferential equations for continuous-time circuits. Concurrently
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright #1999 John Wiley & Sons, Inc.
166 SWITCHED CAPACITOR NETWORKS
the mathematical operator to handle sample-data systems, approach. Furthermore, many practical analog/digital
(A/D) converters use SC implementations. such as switched-capacitor circuits is the z-transform, and the
Laplace transform for continuous-time circuits. A host of
practical properties of SC circuits have made them very popu-
FUNDAMENTAL BUILDING BLOCKS
lar in industry:
The fundamental building blocks in SC circuits are voltage-
1. The time constants (RC products) from active-RC cir-
gain ampliers, sample/holds integrators, and multipliers. A
cuits become capacitor ratios multiplied by the clock pe-
combination of these blocks is interconnected to yield a num-
riod T
C
, that is,
ber of useful circuits.
Gain Ampliers
=
1
f
C
C
C
R
= T
C
_
C
C
R
_
(1a)
The gain amplier is a fundamental building block in
where T T
c
1/f
C
is the sampling frequency. The
switched-capacitor circuits. A voltage amplier is imple-
accuracy of is expressed as
mented as shown in Fig. 1(a). The switched-capacitor resistor
gives a dc path for leakage current but reduces further the
low-frequency gain. A detailed analysis of this topology shows
d

=
dT
C
T
C
+
dC
C

dC
R
C
R
(1b)
that the dc output voltage is equal to I
leak
T/C
P
, with C
P
the
parasitic capacitor associated with the feedback path. The
Assuming that T
C
is perfectly accurate gives
leakage current I
leak
in switched-capacitor circuits is a result
of the diodes associated with the bottom plate of the capaci-
tors and the switches (drain and source junctions). This leak-
d

=
dC
C

dC
R
C
R
(1c)
age current is about 1 nA/cm
2
. Using typical analytical meth-
ods for switched-capacitor networks, it can be shown that the
Because the two capacitors C and C
R
are built close to-
z-domain transfer function of this topology becomes
gether, d/ compatible with conventional CMOS tech-
nologies is in the neighborhood of 0.1%.
2. Ordinarily the load of an SC circuit is mainly capaci-
tive. Therefore the required low-impedance output-
stage op amp is no longer required. This allows the use
of a single-stage operational transconductance amplier
H(z) =
V
0
(z)
V
i
(z)

=
C
S
C
I
1 z
1
1
_
1
C
P
C
I
_
z
1
=
C
S
C
I
z 1
z (1 C
P
/C
I
)
(2)
(OTA) which is especially useful in high-speed applica-
tions. Op amp and OTA are not differentiated in the
with z e
j2fT
. For low frequencies, z 1, the transfer function
rest of this article.
is very small, and only for higher frequencies does the circuit
3. Reduced silicon area, because the equivalent of large re-
behave as a voltage amplier.
sistors is simulated by small capacitors. Moreover, posi-
A practical version is shown in Fig. 1(b). During
2
, the op
tive and/or negative equivalent resistors are easily im-
amp output voltage is equal to the previous voltage plus the
plemented with SC techniques.
op amp offset voltage plus V
0
/A
V
, where A
V
is the open-loop dc
4. Switched-capacitor circuits are implemented in a digital
gain of the op amp. In this clock phase, both capacitors, C
I
circuit process technology. Thus, useful mixed-mode sig-
and C
S
, are charged to the voltage at the inverting terminal
nal circuits are economically realized in standard MOS
of the op amp. This voltage is approximately equal to the op
technology with available double-poly.
amp offset voltage plus V
0
/A
V
. During the next clock phase,
the sampling capacitor is charged to C
S
(V
I
V

), but because 5. The SC design technique has matured. In the audio

range, SC design techniques are the dominant design it was precharged to C
S
V

, the injected charge to C

I
is equal
Figure 1. Voltage gain ampliers: (a)
with dc feedback; (b) available during both
clock phases.

1

2
C
p
C
l
V
o
C
s
V
i

2
V
o
V
i C
s
C
H
C
l
C
spike
(a) (b)
SWITCHED CAPACITOR NETWORKS 167
simplicity and potential speed. It is often convenient to add
an input buffer stage to the S/H circuit. The acquisition time
depends on the tracking speed and input impedance of the
input buffer, the on-resistance of the switch, and the value of
the holding capacitor. The hold settling time is governed by
the settling behavior of the buffer. A drawback of this archi-
tecture is the linearity requirements imposed on the buffers
as a consequence. This limits the speed. Moreover, the input-
dependent charge injected by the sampling switch onto the
hold capacitor yields an undesirable source of nonlinearity.
This type of S/H architecture achieves a linearity to nearly 8
bits. A full-period S/H signal is obtained by either a cascade
of two S/H circuits of Fig. 2, driven by opposite clock phases,
or by a parallel connection of two simple S/H circuits, output
sampling switches, and a third (output) buffer as illustrated
in Fig. 3. Structures with closed-loop connections are also
used. Figure 4(a) illustrates a popular architecture often en-
countered in pipelined A/D converters. In the acquisition
mode, switches associated with
1
and
1
are on whereas
2
is off, and the transconductance amplier acts as a unity-gain
amplier. Thus the voltage across C
H
is the input voltage and
the virtual ground. In the transition to the hold mode, the
switches associated with
1
and
1
turn off one after the
other. Then
2
turns on. One advantage of this architecture

1
C
H
V
in
(a)
(b)
Time (T)
(n1) (n1/2) n
is that because
1
turns off rst, the input-dependent charge
Figure 2. Open-loop S/H: (a) simple S/H buffer; (b) timing diagram.
injected by
1
onto C
H
does not appear in the held output volt-
age. Besides, because of the virtual ground, the channel
charge associated with
1
does not depend on the input signal.
to C
S
V
I
. As a result of this, the op amp output voltage is equal
Yet another advantage is that the offset voltage is not added
to (C
I
/C
S
)V
I
. Therefore, this topology has low sensitivity to
to the output. A disadvantage is that a high-slew-rate trans-
the op amp offset voltage and to the op amp nite DC gain. A
conductance amplier is required. Figure 4(b) shows a double-
minor drawback of this topology is that the op amp stays in
sampling S/H circuit. The S/H operation is valid for both
the open loop during the nonoverlapping phase transitions,
clock phases.
producing spikes during these time intervals. A solution for
this is to connect a small capacitor between the op amp out-
Multipliers
put and the left-hand plate of C
S
.
One difculty in an SC multiplication technique is that con-
Sample-and-Hold
tinuous programmability or multiplication of two signals is
not available. A digitally programmable coefcient is realized The function of a sample/hold (S/H) is to transform a continu-
with a capacitor bank, as shown in Fig. 5. The resolution of ous-time signal into a discrete-time version. A simple S/H cir-
this technique is limited because the capacitor size increases cuit is shown in Fig. 2(a). Its clock phases are shown in Fig.
2(b). This open-loop architecture is attractive because of its by 2
k
where k is the number of programming bits.
Figure 3. Double-sampling S/H archi-

2
C
H
V
in
V
0

+
C
1

+
C
2
tecture.
168 SWITCHED CAPACITOR NETWORKS

+

+

1
V
in

2
C
H

1'

1

1

2
V
in
V
0
C
H
G
m
V
0
(a) (b)
Figure 4. (a) SC S/H single-ended. (b) Double-sampling S/H.
When continuous programmability is required, a continu- These two approaches are depicted in Fig. 6. The topology of
ous multiplier is used. Despite many reported multiplier cir- Fig. 6(a) is based on two-quadrant multipliers. Fig. 6(b) is
cuits, only two cancellation methods for four-quadrant multi- based on square law devices. X and Y are arbitrary constant
plication are known. Because a single-ended conguration terms and are not shown in Fig. 6.
does not completely cancel nonlinearity and has poor PSRR, MOS transistors are used to implement these cancellation
a fully differential conguration is often necessary in a sound schemes. Let us consider a simple MOS transistor model
multiplier topology. The multiplier has two inputs. Therefore characterized in its linear and saturation regions, respec-
there are four combinations of two differential signals, that tively by the following equations:
is (x, y), (x, y), (x, y), and (x, y). The multiplication and
cancellation of an unwanted component are achieved by ei-
ther of the following two equalities:
I
d
= K
_
V
gs
V
T

V
ds
2
_
V
ds
for |V
gs
| > |V
T
|, |V
ds
| < |V
gs
V
T
| (4a)
4xy =[(X +x)(Y +y) + (X x)(Y y)]
[(X x)(Y +y) + (X +x)(Y y)] (3a)
I
d
=
K
2
(V
gs
V
T
)
2
for |V
gs
| > |V
T
|, |V
ds
| > |V
gs
V
T
| (4b)
or
where K
o
C
ox
W/L and V
T
are the conventional notations
for the transconductance parameter and the threshold voltage
of the MOS transistor, respectively. The terms V
gs
V
ds
in Eq.
(4a) or V
2
gs
in Eq. (4b) are used to implement Eqs. (3a) and
8xy ={[(X +x) +(Y +y)]
2
+[(X x) + (Y y)]
2
}
{[(X x) + (Y +y)]
2
+[(X +x) + (Y y)]
2
} (3b)
(3b), respectively. Next we discuss a sound combination of a
continuous-time multiplier and an SC integrator. In an SC
circuit, the multiplier precedes the integrator, thus forming a
weighted integrator. The output of the multiplier is a voltage
signal or a current signal. In the case of a voltage-mode multi-
plier, the conguration of the SC integrator is identical with
a conventional integrator, as shown in Fig. 7. The transcon-
ductance multiplier is connected directly to the op amp, as
shown in Fig. 8. A common drawback in a weighted integrator
is the multiplier offset because it is accumulated in the inte-
grator. This problem is more serious for the transconduc-
tance mode.
The topology in Fig. 8 with the multiplier implemented by
a FET transistor operating in the linear region is known as
MOSFET-C implementation. Instead of using a single tran-
sistor, a linearizing scheme uses four transistors as shown in
Fig. 9.
C
2
1
C
2
2
C
2
k
C
The four FETs in Fig. 9(a) are operating in the linear re-
gion, and depletion FETs are often used in many cases to Figure 5. Digitally programmable capacitor bank.
SWITCHED CAPACITOR NETWORKS 169
Figure 6. Four-quadrant multiplier topol-
ogies: (a) using single-quadrant multipli-
y
y
x
x
y

xy
xy
xy
4xy
xy
+

x + y
x + y
x y
x y

8xy
x
2
+ 2xy + y
2
x
2
+ 2xy + y
2
x
2
2xy + y
2
x
2
2xy + y
2
+

( )
2
( )
2
( )
2
( )
2
(a) (b)
ers; (b) Using square devices.
overcome the transistor threshold limit. The drain current of Several modications are possible from this prototype. In
the balanced differential op amp, the drain voltage v
d
is virtu- each FET is given by
ally grounded because the common-mode voltage is xed to
ground. In this case, only two FETs are required, as shown in
Fig. 9(b). The drain current of each FET is given by
i
d1
= K
_
v

y
v
x
V
T

v
x
2
_
(v
x
)
i
d2
= K
_
v
+
y
v
x
V
T

v
x
2
_
(v
x
)
(9)
and the differential current is given by
i
d1
= K
_
v
+
y
v
+
x
V
T

v
+
d
v
+
x
2
_
(v
+
d
v
+
x
)
i
d2
= K
_
v

y
v
+
x
V
T

v

d
v
+
x
2
_
(v

d
v
+
x
)
i
d3
= K
_
v

y
v

x
V
T

v
+
d
v

x
2
_
(v
+
d
v

x
)
and
i
d4
= K
_
v
+
y
v

x
V
T

v

d
v

x
2
_
(v

d
v

x
)
(5)
i
d
= (i
d1
i
d2
) = Kv
x
(v
+
y
v

y
) (10)
Because of the closed loop, the voltages v

d
and v

d
are virtually
If depletion-mode FETs are used, then the v
y
is referred to
equal and xed by the common-mode feedback circuit in the
the ground, as shown in Fig. 10. The differential current is
op amp. The differential current applied to the integrator is
given by
expressed by
i
d
= (i
d1
i
d2
) = Kv
x
v
y
(11)
i
d
= (i
d1
+i
d3
) (i
d2
+i
d4
) = K(v
+
x
v

x
)(v
+
y
v

y
) (6)
A switched, single-ended implementation using three op
The common-mode current injected into the integrator is can-
amps is achieved, as shown in Fig. 11. C
1
is reset at
1
, and
celed out by the common-mode feedback. The integrator out-
then the difference of the two integrators is sampled at
2
.
put is given by
The charge on C
2
is transferred at the next
1
. The output
voltages of the two integrators are given by
v
o
(t) = v
+
o
(t) v

o
(t) =
K
C
_
t
0
v
x
( )v
y
( ) d (7)
where v
x
v

x
v

x
, v
x
v

x
v

x
, and v
y
v

y
v

y
. If v
x
and
v
y
are sampled signals, then the circuit operates as a discrete-
time MOSFET-C circuit. The integrator output yields
v
o
(nT ) =
KT
C
n

k=0
v
x
(k)v
y
(k) (8)
v
1
=
1
C
1
_
T
K
_
v
y
v
x
V
T

v
x
2
_
(v
x
) dt
=
TK
C
1
_
v
x
v
y

_
v
x
+V
T

v
x
2
_
v
x
_
v
2
=
1
C
1
_
T
K
_
v
x
V
T

v
x
2
_
(v
x
) dt
=
TK
C
1
_

_
v
x
+V
T

v
x
2
_
v
x
_
(12)
where T is the time period of the sampled system.
V
y
V
x
i
m
V
out

+
V
y
V
x
V
m
V
out

+
Figure 7. Weighted integrator with voltage-mode multiplier. Figure 8. Weighted integrators with transconductance multiplier.
170 SWITCHED CAPACITOR NETWORKS
v
y
v
o
v
x

+

+
C
3
C
1
2
C
1
C
2
v
2
v
1

Figure 11. An SC weighted integrator.

reset at
1
. Its output is sampled at
2
. Then, the voltage sam-
pled in C
2
yields the expression
v
C
2
(
A
) =
1
C
1
_
T
K
_
v
y
v
x
V
T

v
x
2
_
(v
x
) dt
=
TK
C
1
_
v
x
v
y

_
v
x
+V
T

v
x
2
_
v
x
_
(15)
v
o
+
v
y
+
v
y
+
v
x
+
v
x

v
y
+
v
y

v
x
v
y

v
o

+
+
v
o
+
v
o

+
+
(a)
(b)
During the second phase
B
, T the gate input is connected to
v
y
. Integrator A is reset at
1
. At
2
, v
1
becomes Figure 9. (a) Multiplier implemented by MOSFET-C techniques.
(b) A MOSFET-C multiplier with balanced differential op amp.
v
C
2
(
B
) =
TK
C
1
_

_
v
x
+V
t

v
x
2
_
v
x
_
(16)
where T is the period dened as the time difference between
the end of
1
and the end of
2
. The voltage across C
2
is given
One node of C
2
is connected to integrator A and the other
by
node is connected to integrator B. The total charge into inte-
grator B is given by
v
C
2
=
TK
C
1
v
x
v
y
(13)
Q
2
=C
2
[v
1
(
B
) v
1
(
B
)] =
TKC
2
C
1
v
x
v
y
(17)
At
1
, the charge in C
2
is transferred to C
3
. The output of the
integrator becomes
A single FET SC weighted integrator does not have an off-
set due to an FET mismatch. However, all transconductance-
weighted integrators depend on the clock period T. Unfor-
v
o
=
TKC
2
C
1
C
3
z
1/2
1 z
1
v
x
( z)v
y
( z) (14)
tunately, a jitter-free clock is impossible to implement. This
jitter causes offset and incomplete cancellation, even in the
A weighted integrator is also implemented with two op
circuit shown in Fig. 12. Next an SC weighted integrator with
amps and one FET. It requires several additional clocks. Basi-
voltage-mode offset cancellation is described.
cally, it multiplexes the FET and the op amp by substituting
The multiplier offset caused by device mismatch in the
two FETs and two integrators, as shown in Fig. 12.
multiplier is the most critical limitation in continuous-time
The operation involves two additional clock phases. During
weighted SC integrators. A simple and effective offset cancel-
phase
A
, the gate input is connected to v
y.
Integrator A is
v
y
v
x
v
o

+

+
C
3
C
1
C
2
v
1
1

2

A

2

A

Integrator A Integrator B
Figure 12. Single FET SC weighted integrator.
v
y
v
x
v
o
+
v
o

+
+
Figure 10. Ground-referenced MOSFET-C multiplier.
SWITCHED CAPACITOR NETWORKS 171
of (x, y), (x, y), (x, y), (x, y) at each clock phase 1, 2, 3,
4, respectively.
At the end of phase 4, C
I
contains
v
out
( phase 4) = 4K
C
H
C
1
xy (21)
x and y should be kept constant during the four phases. If the
four phases are considered unit time period than the
weighted integrator is characterized as follows:
v
out
( z) = 4K
C
H
C
1
1
1 z
1
x( z)y( z) (22)
Note that multiplier offset cancellation is obtained in the in-
C
H
C
I
C
I
V
out
+
V
out
C
H
2

x
+
x

y
+
y

Reset
Reset
B

2

B

+
+
A
v
m
+
v
m

tegrator.
Figure 13. A switched-capacitor weighted integrator with offset can-
cellation.
Integrators
Standard stray-insensitive integrators are shown in Fig. 15.
lation scheme using SC techniques is discussed next. The
In sampled data systems, input and output signals are sam-
multiplier offset is modeled by
pled at different times. This yields different transfer func-
tions. We assume two-phase nonoverlapping clocks, an odd
z = K( x +x
o
)( y +y
o
) +z
o
(18)
clock phase
1
and an even clock phase
2
. Thus, for a nonin-
verting integrator, the following transfer functions are often where K is a multiplication constant, x
o
and y
o
are offset-
related device mismatches at the input stage of the x and y used:
signals, respectively, and z
o
is the offset caused by device mis-
match at the output stage. This offset is canceled by four com-
binations of input signal polarity as follows:
H
oo
( z) =
V
o
o
( z)
V
o
in
( z)
=
a
p
z
1
1 z
1
=
a
p
z 1
(23a)
H
oe
( z) =
V
e
o
( z)
V
o
in
( z)
=
a
p
z
1/2
1 z
1
=
a
p
z
1/2
z
1/2
(24a)
For an inverting integrator,
z
x,y
= K( x +x
o
)( y +y
o
) +z
o
z
x,y
= K(x +x
o
)( y +y
o
) +z
o
z
x,y
= K(x +x
o
)(y +y
o
) +z
o
z
x,y
= K( x +x
o
)(y +y
o
) +z
o
(19)
Then the offset is canceled out similarly to a nonlinearity can-
cellation in a multiplier, that is,
H
oo
( z) =
V
o
o
( z)
V
o
in
( z)
=
a
n
1 z
1
=
a
n
z
z 1
(23b)
( z
x,y
z
x,y
) + (z
x,y
z
x,y
) = 4Kxy (20)
This scheme is implemented with a switched-capacitor cir-
cuit, as shown in Fig. 13.
1
and
2
are nonoverlapping clock
phases. At
1
, the multiplier output is sampled and is held in
C
H
. At
2
, one node of C
H
is connected to the multiplier output
whereas the other node is connected to the integrator input.
Then, the charge is injected into the integrating capacitor C
I
.
The voltage across C
I
, after the clock
2
, becomes [v
m
(
2
)
v
m
(
1
)] where v
m
is the multiplier output voltage at the given
clock phase. The switches (
1

2
and
A

B
), at the multi-
plier input nodes, change input signal polarities. Using clocks
shown in Fig. 14, the multiplier input is given as a sequence
V
in
a
p
a
n
V
o
o
V
o
e
C
C

2
V
in
V
o
o
V
o
e
C
C

2
(a)
(b)

B
Phase 1 2 3 4
Figure 15. Conventional stray-insensitive SC integrators: (a) nonin-
verting; (b) inverting. Figure 14. Clock phase diagram.
172 SWITCHED CAPACITOR NETWORKS
V
in
o
V
o
o
C
1
C
h
C
B
C
M

2
( )

1
( )

2
Figure 17. Offset and gain-compensated integrator.
V
in
o
V
o
e
C
1
C
4
C
3
C
2

2
Figure 16. An inverting SC integrator with reduced capacitance
spread.
age. The voltage across C
h
compensates for the offset voltage
and the dc gain error of the op amp. Note that the SC inte-
grator of Fig. 17 can operate as a noninverting integrator if
and
the clocking in parenthesis is employed. C
M
provides a time-
continuous feedback around the op amp. The transfer func-
tion, for innite op amp gain, is given by
H
oe
( z) =
V
e
o
( z)
V
o
in
( z)
=
a
n
z
1/2
1 z
1
=
a
n
z
1/2
z
1/2
(24b)
where z
1
represents a unit delay. A crude demonstration,
showing the integrative nature of these SC integrators in the
H
oo
( z) =
V
o
o
( z)
V
o
in
( z)
=
C
1
C
B
(1 z
1
)
(28)
s-domain, is to consider a high sampling rate, that is, a clock
Furthermore, if the dc offset is tolerated in certain applica-
frequency ( f
c
1/T) much higher than the operating signal
tions, an autozeroing method is used to compensate for the dc
frequencies. Thus, let us consider Eq. (23a) and, assuming a
offset. Next we discuss a general form of a rst-order building
high sampling rate, we can write a mapping from the z- to
block (see Fig. 18). The output voltage is expressed as
the s-domain:
z 1 +sT (25)
V
e
0
=
C
1
C
F
V
e
i
1

C
2
C
F
1
1 z
1
V
e
i
2
+
C
3
C
F
z
1
1 z
1
V
e
i
3
(29)
Then
Observe that the capacitor C
3
, and switches are the imple-
mentation of a negative resistor. Also note that if V
e
i
2
is equal
H(s) =
a
p
z 1

=1+sT

=
1
(T/a
p
)s
(26)
to V
e
0
, this connection makes the integrator a lossy one. In
that case Eq. (29) is written
This last expression corresponds to a continuous-time, nonin-
verting integrator with a time constant of T/a
p
1/f
c
a
p
, that
is, a capacitance ratio times the clock period.
In many applications the capacitor ratios associated with
integrators are very large, thus the total capacitance becomes
excessive. This is particularly critical for biquadratic lters
V
e
0
_
1 +
C
2
C
F
_
z 1
z 1
=
C
1
C
F
V
e
i
1
+
C
3
C
F
1
z 1
V
e
i
3
forV
e
i
2
=V
e
0
(30)
with high Q, where the ratio between the largest and smallest
capacitance is proportional to the quality factor Q. A suitable
inverting SC integrator for high Q applications is shown in
Fig. 16. The corresponding transfer function is given by
H
oe
( z) =
V
e
o
( z)
V
o
in
( z)
=
C
1
C
3
C
2
C

4
1
1 z
1
Z
1/2
(27)
where C
4
C
4
C
3
. This integrator is comparable in perfor-
mance to the conventional circuit of Fig. 15, in terms of stray
sensitivity and nite-gain error. Note from Eq. (27) that the
transfer function is dened only during
2
. During
1
, the cir-
cuit behaves as a voltage amplier. Thus high slew-rate op
amps could be required. A serious drawback in the integrator
of Fig. 16 is the increased offset compared with standard SC
integrators. In typical two-integrator loop lters, however, the
other integrator is chosen to be offset and low dc gain-com-
V
i
3
V
i
2
V
o
C
3
C
F

+
1

2
C
2
C
1
V
i
1

1

1

2

2
pensated, as shown in Fig. 17. The SC integrator integrates
by C
1
and C
B
, and the hold capacitor C
h
stores the offset volt- Figure 18. General form of a rst-order building block.
SWITCHED CAPACITOR NETWORKS 173
V
o
e
C
2
C
B

+
2

1
C
1

+
1

2
C
4
C
3
C
A
V
i
C
5
C
6
Figure 19. An SC biquadratic section.
The building block of Fig. 18 is the basis of higher order l- In particular cases, this capacitance spread is prohibited. For
ters. An illustrative example follows. such cases the SC integrators shown in Figs. 16 and 17 re-
place the conventional building blocks. This combination
yields the practical SC biquadratic section shown in Fig. 20. SC Biquadratic Sections
This structure offers reduced total capacitance and also re-
The circuit shown in Fig. 19 implements any pair of poles and
duces the effect of the offset voltage of the op amps. Note that
zeros in the z-domain. For C
A
C
B
1,
the capacitor C
h
does not play an important role in the design,
and can be chosen with a small value. For the poles, compar-
ing z
2
(2 r cos )z r
2
and the analysis of Fig. 20, H
ee
( z) =
V
e
0
( z)
V
e
in
( z)
=
(C
5
+C
6
)z
2
+ (C
1
C
2
C
5
2C
6
)z +C
6
z
2
+ (C
2
C
3
+C
2
C
4
2)z + (1 C
2
C
4
)
(31)
Simple design equations follow:
C
2
C
3
C
A
+C
B
= 1 +r
2
2r cos (34a)
C

A
C
2
C
4
C
A
1
C
A
C
B
= 1 r
2
(34b)
Low-pass C
5
=C
6
= 0
High-pass C
1
=C
5
= 0
Band-pass C
1
=C
6
= 0
where C
A
1
C
A
C
A
. Simple design equations are obtained
by assuming a high sampling rate, a large Q, and C
2
C
3

Comparing the coefcients of the denominator of Eq. (31) with
C
4
C
A
C
h
1. Then
the general expression z
2
2 r cos r
2
, we obtain the fol-
lowing expressions:
C
A
+C
B

=
1

od
T
(35a)
C
2
C
4
= 1 r
2
(32a)
C
2
C
3
= 1 2r cos +r
2
(32b)
and
For equal voltages at the two integrator outputs and assum-
C

A

= Q
od
T 1 (35b)
ing that Q is greater than 3 and a high sampling rate (

o
d
T 1),
Another common use of SC lters is high-frequency appli-
cations. In such cases a structure with a minimum gain-band-
C
2
=C
3
=
_
1 +r
2
2r cos

=
0
d
T (32c)
width product (GB
u
) is desirable. This structure is shown
in Fig. 21 and is often called a decoupled structure. It is worth
mentioning that two SC architectures can have ideally the
C
4
=
1 r
2
C
2

=
1
Q
(32d)
same transfer function, but with real op amps, their fre-
quency (and time) response can differ signicantly. A rule of
The capacitance spread for a high sampling rate, C
A
1, and
thumb for reducing GB effects in SC lters is to avoid a direct
a high Q is expressed as
connection between the output of one op amp to the input of
another op amp. It is desirable to transfer the output of an op
amp to a grounded capacitor and, in the next clock phase,
transfer the capacitor charge into the op amp input. More dis-
C
max
C
min
= max
_
C
1
C
2
,
C
1
C
4
_
= max
_
1

0
d
T
, Q
_
(33)
174 SWITCHED CAPACITOR NETWORKS
Figure 20. An improved capacitance
area SC biquadratic section.
V
o
o
C
2
C
H
C
B

+
1

2
C
1

+
1

2
C
4
C
3
C
A
V
i
C
A
'
C
A
"

2

2

2
C
5
C
6
Figure 21. A decoupled SC biquadratic
section.
V
0

+
1

+
2

2
C
0
V
in

1
a
'
5
C
0'
a
5
C
'
0
a
2
C
'
0
a
9
C
'
0
a
7
C
0
a
8
C
0
'
C
'
0
a
1
C
0

2
+

SWITCHED CAPACITOR NETWORKS 175

cussion on
u
effects is in the next section. Analysis of Fig. 21 The actual center frequency suffers small deviations:
yields the following expressions:

o
A
=
A
0
1 +A
0

o
(41)
We can conclude that the
o
deviations are negligible. How-
ever, the Q deviations are signicant depending on the Q and
r
2
=
1 +a
9
1 +a
8
(36a)
2r cos =
2 +a
8
+a
9
a
2
a
7
1 +a
8
(36b)
A
0
values.
If the input is sampled during
2
and held during
1
, the ideal
Finite OP AMP Gain-Bandwidth Product. The op amp band-
transfer function is given by
width is very critical for high-frequency applications. The
analysis is carried out when the op amp voltage gain is mod-
eled with one dominant pole that is,
A
V
(s) =
A
0
1 +s/
3
=
A
0

3
s +
3
=

u
s +
3

=

u
s
(42)
where A
0
is the dc gain,
u
is approximately the unity-gain
H
e
(z) =
V
e
0
(z)
V
e
i
(z)
=
_
a

5
1 +a
8
_
_
_
_
_
z
2
z(a

5
+a
5
a
1
a
2
)/a

5
+a
5
/a

5
z
2
z
2 +a
8
+a
9
a
2
a
7
1 +a
8
+
1 +a
9
1 +a
8
_
_
_
_
(37)
bandwidth, and
3
is the op amp bandwidth. Also, it is as-
sumed that the op amp output impedance is equal to zero.
The capacitor a
9
C
0
can be used as a design parameter to opti-
The analysis taking into account A
V
(s) is rather cumbersome
mize the biquad performance. A simple set of design equa-
because the op amp input-output characterization is a con-
tions follows:
tinuous-time system modeled by a rst-order differential
equation and the rest of the SC circuit is characterized by
discrete-time systems modeled by difference equations. The
step response of a single op amp SC circuit to a step input
applied at t t
1
is given by
a
8
=
(1 +a
9
) r
2
r
2
(38a)
a
2
= a
7
=
_
1 +r
2
2r cos
r
2
(1 +a
9
) (38b)
V
o
(t) =V
o
(t
1
)e
(tt
1
)
u
+V
od
{1 e
(tt
1
)
u
} (43)
Under a high sampling rate and high Q, the following expres-
sions are obtained:
where V
od
is the desired output which is a function of the ini-
tial conditions, inputs, and lter architecture and is a topol-
ogy-dependent voltage divider, 0 1.
0

= f
c
_
a
2
a
7
1 +a
8
(39a)
and
=

C
f

i
C
i
(44)
where the C
f
sum consists of all feedback capacitors connected
Q

=
_
a
2
a
7
(1 +a
8
)
a
8
a
9
(39b)
directly between the op amp output and the negative input
terminal and the C
i
sum is over all capacitors connected to
A tradeoff between Q-sensitivity and total capacitance is
the negative op amp terminal. Note that the
u
product de-
given by a
8
and a
9
.
termines the rise time of the response, therefore both and

u
should be maximized. For the multiple op amp case, the
basic concept prevails. For the common case where t t
1

EFFECTS OF THE OP AMP FINITE PARAMETERS
T/2 at the end of any clock phase, the gure of merit to be
maximized becomes T
u
/2. This means that a rule of thumb
Finite Op Amp dc Gain Effects
for reduced gain-bandwidth effects requires that
The effect of nite op amp dc voltage gain A
0
in a lossless SC
integrator is to transform a lossless integrator into a lossy T
u
/2 5 (45)
one. This degrades the transfer function in amplitude and
This rule is based on the fact that ve times constants are phase. Typically the magnitude of deviation due to the inte-
required to obtain a steady-state response with a magnitude grator amplitude variation is not critical. By contrast, the
of error of less than 1%. phase deviation from the ideal integrator has a very impor-
tant inuence on overall performance. When real SC inte-
grators are used to build a two-integrator biquadratic lter, Noise and Clock Feedthrough
the actual quality factor becomes
The lower range of signals processed by electronic devices is
limited by several unwanted signals at the circuit output. The
rms values of these electrical signals determine the noise
level of the system, and it represents the lowest limit for the
incoming signals to be processed. Input signals smaller than
Q
A
=
1
1
Q
+
2
A
0

=
_
1
2Q
A
0
_
Q (40)
176 SWITCHED CAPACITOR NETWORKS
the noise level, in most of the cases, cannot be driven by the
circuit. The most critical noise sources are those due to (1) the
elements used (transistors, diodes, resistors, etc.); (2) the
noise induced by the clocks; (3) the harmonic distortion com-
ponents generated by the intrinsic nonlinear characteristics
of the devices; and (4) the noise induced by the surrounding
circuitry. In this section, types (1), (2) and (3) are considered.
The noise generated by the surrounding circuitry and coupled
to the output of the switched-capacitor circuit is further re-
duced by using fully differential structures.
Noise Due to the MOSFET. In an MOS transistor, noise is
generated by different mechanisms but there are two domi-
nant noise sources, channel thermal noise and 1/f or icker
noise. A discussion of the nature of these noise sources
V
0
V
R1
V
R2
V
R1
V
i1
V
C1
V
i 2
V
R2
V
C2
V
DD
M
3
M
2
M
2
M
1
M
1
M
4
M
5
M
3
M
4
M
5
M
6
V
SS
follows.
Thermal Noise. The ow of the carriers caused by drain-
Figure 22. A folded-cascade operational transconductance amplier.
source voltage takes place on the source-drain channel, most
like in a typical resistor. Therefore, thermal noise is gener-
ated because of the random ow of the carriers. For an MOS
(folded cascade OTA) is shown in Fig. 22. To compute the
transistor biased in the linear region, the spectral density of
noise level, the contribution of each transistor must be evalu-
the input referred thermal noise is approximated by
ated. This can be done by obtaining the OTA output current
generated by the gate referred noise of all the transistors. For
V
2
eqth
= 4kTR
on
(46)
instance, the spectral density of the output referred noise cur-
rent due to M
1
is straightforwardly determined because the
where R
on
, k, and T are the drain-source resistance of the
gate referred noise is at the input of the OTA, leading to
transistor, the Boltzmann constant, and the temperature (in
degrees Kelvin), respectively. In saturation, the spectral noise
i
2
o1
= G
2
m
V
2
eq1
(49)
density is calculated by the same expression but with R
on
equal to 2/3g
m
, where g
m
is the small signal transconductance
where G
m
(equal to g
m1
at low frequencies) is the OTA trans-
of the transistor.
conductance and v
eq1
is the input referred noise density of
M
1
. Similarly, the contributions of M
2
and M
5
to the spectral
1/f Noise
density of the output referred noise current are given by
This type of noise is mainly caused by the imperfections in
the silicon-silicon oxide interface. The surface states and the
traps in this interface randomly interfere with the charges
owing through the channel. Hence the noise generated is
i
2
o2
= g
2
m2
v
2
eq2
i
2
o5
= g
2
m5
v
2
eq5
(50)
strongly dependent on the technology. The 1/f noise (icker
noise) is also inversely proportional to the gate area because The noise contributions of transistors M
3
and M
4
are very
with larger areas, more traps and surface states are present small compared with the other components because their
and some averaging occurs. The spectral density of the input noise drain current, due to the source degeneration implicit
referred 1/f noise is commonly characterized by in these transistors, is determined by the equivalent conduc-
tance associated with their sources instead of by their trans-
conductance. Because the equivalent conductance in a satu-
rated MOS transistor is much smaller than the transistor
V
2
eq1/f
=
k
F
WLf
(47)
transconductance, this noise drain current contribution can
be neglected. The noise contribution of M
6
is mainly common-
where the product of WL, f , and k
F
are the gate area of the
mode noise. Therefore it is almost canceled at the OTA input
transistor, the frequency in hertz, and the icker constant,
because of current substraction. The spectral density of the
respectively. The spectral noise density of an MOS transistor
total output referred noise current is approximated by
is composed of both components. Therefore the input referred
spectral noise density of a transistor operating in its satura-
tion region becomes i
2
0
= 2[G
2
m
v
2
eq1
+g
2
m2
v
2
eq2
+g
2
m5
v
2
eq5
] (51)
The factor 2 is the result of the pairs of transistors M
1
, M
2
,
and M
5
. From this equation, the OTA input referred noise
V
2
eq
=
8
3
kT
g
m
+
k
F
WLf
(48)
density becomes
Op Amp Noise Contributions. In an op amp, the output re-
ferred noise density is composed of the noise contribution of
all transistors. Hence the noise level is a function of the op
amp architecture. A typical unbuffered folded-cascade op amp
V
2
OTAin
= 2v
2
eq1
_
1 +
g
2
m
2v
2
eq2
+g
2
m5
v
2
eq5
G
2
m
v
2
eq1
_
(52)
SWITCHED CAPACITOR NETWORKS 177
According to this result, if G
m
is larger than g
m2
and g
m5
, the
OTA input referred noise density is mainly determined by the
OTA input stage. In that case and using Eq. (48), Eq. (52)
yields
V
2
OTAin

= 2V
2
eq1
=V
2
equ1/f
+4kTR
eqth
(53)
where the factor 2 has been included in V
eq1/f
and R
eqth
. In Eq.
(47), v
eq1/f
is the equivalent 1/f noise density and R
eqth
is the
V
i
V
o
C
s
V
x
V
y
C
I

+
2

2
'

1
'

1
equivalent resistance for noise, equal to 4/3g
m
.
Figure 23. Typical switched-capacitor, lossless integrator.
Noise in a Switched-Capacitor Integrator
In a switched-capacitor lossless integrator, the output re-

1
goes down before
1
. This is shown in Fig. 24. Although
ferred noise density component due to the OTA is frequency
C
P1
is connected between two low-impedance nodes, C
P2
is con-
limited by the gain-bandwidth product of the OTA. To avoid
nected between
1
, a low impedance node, and the capacitor
misunderstandings, in this section f
u
(the unity gain fre-
C
S
. For
1
v
i
V
T
, the transistor M
1
is on, and the current
quency of the OTA in Hertz) is used instead of
u
(in radians
injected by C
P2
is absorbed by the drain-source resistance.
per second). Because f
u
must be higher than the clock fre-
Then v
x
remains at a voltage equal to v
i
.When M
1
is turned
quency f
c
and because of the sampled nature of the SC inte-
off,
1
v
i
V
T
, and charge conservation at node v
x
leads to
grator, the OTA high-frequency noise is folded back into the
integrator baseband. In the case of the SC integrator and as-
suming that the icker noise is not folded back, the output
v
x
= v
i
+
C
P2
C
S
+C
P2
(V
SS
v
i
V
T
) (55)
referred spectral noise density becomes
where V
SS
is the low level of
1
and
2
. During the next clock
phase, and both capacitors C
P2
and C
S
are charged to v
x
, and
v
2
oeq1
=
_
v
2
eq1/f
+4kTR
eqth
_
1 +
2f
u
f
c
__
|1 +H(z)|
2
(54)
this charge is injected to C
I
. Thus, an integrator time constant
error proportional to C
P
2/(C
S
C
P2
) is induced by C
P2
. In addi-
where the folding factor is equal to f
u
/f
c
) and H(z) is the z-
tion, an offset voltage proportional to V
SS
V
T
is also gener-
domain transfer function of the integrator. The factor 2f
u
/f
c
is
ated. Because the threshold voltage V
T
is a nonlinear function
the result of both positive and negative foldings. Typically,
of v
i
, an additional error in the transfer function and har-
the frequency range of the signal to be processed is around
monic distortion components appears at the output of the in-
and below the unity-gain frequency of the integrator. There-
tegrator. The same effect occurs when clock phases
2
and
2
fore H(z) 1 and Eq. (54) are approximated by
have a similar sequence.
Let us consider the case when
1
is opened before
1
, as
shown in Fig. 24(b). Before M
1
turns off, V
x
v
i
, and v
Y

v
2
oeq1
=
_
v
2
eq1/ f
+4kTR
eqth
_
1 +
2f
u
f
c
__
|H(z)|
2
(54b)
0. When M
1
is off, V
SS

1
v
i
V
T
, the charge is recombined
among C
S
, C
P1
, C
P2
, and C
P3
. After the charge redistribution,
Noise from Switches. In switched-capacitor networks,
the charge conservation at node v
Y
leads to
switches are implemented by single or complementary MOS
transistors. These transistors are biased in the cutoff and
C
S
[v
x
(t) v
Y
(t)] C
P3
v
Y
(t) =C
S
v
i
(t
0
) (56)
ohmic region for open and closed operations, respectively. In
the cutoff region, the drain-source resistance of the MOS
where v
i
(t
0
) is the input voltage just at the end of the previous
transistor is very high. Then the noise contribution of the
clock phase. Observe from Eq. (56) that the addition of the
switch is conned to very low frequencies and it can be con-
charges stored on C
S
and C
P3
is conserved. During the next
sidered a dc offset. This noise contribution is one of the most
clock phase, v
x
(t) 0, and both capacitors C
S
and C
P3
transfer
fundamental limits for the signal-to-noise ratio of switched-
the ideal charge C
S
v
i
(t
0
) to C
1
, making the clock-feedthrough-
capacitor networks.
induced error negligible. The conclusion is that if the clock
Clock Feedthrough
Another factor that limits the accuracy of switched-capacitor
networks is the charge induced by the switch clocking. These
charges are induced by the gate-source capacitance, the gate-
drain capacitance, and the charge stored in the channel when
the switch is in the on state. Furthermore, some of these
charges depend on the input signal and introduce distortion
in the circuit. Although these errors cannot be canceled, there
are some techniques to reduce these effects.
Analysis of clock feedthrough is very difcult because it
C
1
C
2
C
s
V
x
V
i

1
C
1
C
2
C
s
C
p
V
x
V
i

1
'

1
depends on the order of the clock phases, the relative delay of
the clock phases, and also on the speed of the clock transis- Figure 24. MOS Switches: Charge induced due to the clocks: (a) if

1
goes down before
1
and (b) if
1
goes down before
1
. tions. For instance, in Fig. 23 let us consider the case when
178 SWITCHED CAPACITOR NETWORKS
phase
1
is a bit delayed, then
1
the clock-induced error is According to this result, the dynamic range of the switched-
capacitor integrator is reduced when power supplies are negligible. This is also true for clock phases
2
and
2
.
In Fig. 23, the right hand switches also introduce clock scaled down and a minimum number of capacitors are em-
ployed. Clearly, there is a compromise between power con- feedthrough but unlike the clock feedthrough previously ana-
lyzed, which is input-signal-independent. When clock phase sumption, silicon area, and dynamic range. As an example,
for the case of C
I
1.0 pF, supply voltages of 1.5 V, and
2
decreases, the gate-source overlap capacitor extracts the
following charge from the summing node: neglecting V
DSATP
, the dynamic range of a single integrator is
around 78 dB. For low-frequency applications, however, the
dynamic range is lower because of the low-frequency icker Q =C
GS0
(V
SS
V
T
) (57)
noise component.
In this case, V
T
does not introduce distortion because v
y
is
almost at zero voltage for both clock phases. The main effect
DESIGN CONSIDERATIONS FOR LOW-VOLTAGE,
of C
GS0
is to introduce an offset voltage. The same analysis
SWITCHED-CAPACITOR CIRCUITS
reveals that the bottom right-hand switch introduces a simi-
lar offset voltage.
For the typical digital supply voltages of 05V, switched-
From the previous analysis it can be seen that the clock
capacitor networks achieve dynamic ranges of the order of 80
feedthrough is reduced by using transistors of minimum di-
to 100 dB. As long as power supplies are reduced, the swing
mension. This implies minimum parasitic capacitors and min-
of the signal decreases and the resistance of the switches in-
imum induced charge from the channel. If possible, the clock
creases further. Both effects reduce the dynamic range of
phases should be arranged for minimum clock feedthrough.
switched-capacitor networks. For very low supply voltages,
The effect of the charge stored in the channel has not been
however, the main limitation on the dynamic range of the
considered.
switched-capacitor circuit is from analog switches. A discus-
sion of these topics follows.
Dynamic Range
Low-Voltage Operational Ampliers
Dynamic range is dened as the ratio of the maximum signal
that the circuit drives without signicantly distorting the
The implementation of op amps for low voltage applications
noise level. The maximum distortion tolerated by the circuit
is not a fundamental limitation as long as the transistor
depends on the application, but 60 dB is commonly used.
threshold voltage is smaller than (V
DD
V
SS
)/2. This limita-
Because the linearity of the capacitors is good enough and if
tion becomes clear in the design example presented in this
the harmonic distortion components introduced by the OTA
section. The design of the operational amplier is strongly de-
input stage are small, the major limitation for distortion is
pendent on the application. For high-frequency circuits, the
determined by the output stage of the OTA. For the folded
folded-cascade is suitable but the swing of the signals at the
cascade OTA of Fig. 22 this limit is given by
output stage is limited by the cascade transistors. If a large
output voltage swing is needed, a complementary output
v
o max

=V
R2
+V
TP3
(58)
stage is desirable. To illustrate the design tradeoffs involved
in a design of a low-voltage OTA, let us consider the folded
If the reference voltage V
R2
is maximized, Eq. (45) yields
cascade OTA of Fig. 22. For low-voltage applications and
small signals, the transistors must be biased with very low
V
GS
V
T
. For 0.75 V applications and V
T
0.5 V, V
GS1

v
o max

=V
DD
2V
DSATP
(59)
V
T1
V
DSAT6
must be lower than 0.25 V, otherwise the transis-
where V
DSATP
is the source-drain saturation voltage for the P tor M
6
goes to the triode region. For large signals, however,
transistors M
2
(M
3
) and M
3
. A similar expression is obtained the variations of the input signal produce variations at the
for the lowest limit. Assuming a symmetrical output stage, source voltage of M
1
. These variations are of the order of
from Eq. (59), the maximum rms value of the OTA output 1.44(V
GS1
V
T1
). Hence, for a proper operation of the OTA
voltage is given by input stage it is desirable to satisfy the following equation:
0.25 > 2.44(V
GS1
V
T1
) +V
DSAT6
(63)
v
ORMS

= (V
DD
2V
DSATP
)/

2 (60)
The increases in threshold voltage of M
1
because of body
If the in-band noise, integrated up to 1/R
int
C
I
is consid-
effects have to be taken into account. In critical applications,
ered and if the most important term of Eq. (60) is retained,
the dynamic range of the single-ended, switched-capacitor in-
tegrator becomes
DR

=
(V
DD
2V
DSATP
)
2

2kT/C
I
(61)
At room temperature operation, this equation reduces to the
following expression
DR

= 5.5 10
9

C
I
(V
DD
2V
DSATP
) (62)
Table 1. Dimension and Bias Current for the Transistors
Transistor W, m/L, m I
BIAS
, mA
M
1
48/2.4 2.5
M
2
120/2.4 5.0
M
3
60/2.4 2.5
M
4
60/4.2 2.5
M
5
60/4.2 2.5
M
6
60/4.2 5.0
SWITCHED CAPACITOR NETWORKS 179
For a single NMOS transistor, the switch resistance is ap-
proximated by
R
DS
=
1
m
n
C
OX
W
L
(V
GS
V
T
)
(64)
where m
n
and C
OX
are technological parameters. According to
Eq. (44), the switch resistance increases further when V
GS
ap-
proaches V
T
. This effect is shown in Fig. 25 for the case
V
DD
V
SS
0.75 V and V
T
0.5 V. From this gure, the
0.00 0.05 0.10 0.15 0.20
S
w
i
t
c
h

r
e
s
i
s
t
a
n
c
e

(

1
0
3
)
200
300
400
0
100
V
in
(V)
switch resistance is higher than 300 k for input signals of
Figure 25. Typical switch resistance for an NMOS transistor.
0.2 V. However, for a drain-source voltage higher than V
GS

V
T
, the transistor saturates and no longer behaves as a
switch. This limitation clearly further reduces the dynamic
PMOS transistors fabricated in a different well with their
range of switched-capacitor circuits.
source tied to their own well are used. The dimensioning of
A possible solution to this drawback is to generate the
the transistors and the bias conditions are directly related to
clocks from higher voltage supplies. A simplied diagram of
the application. For instance, if the switched-capacitor inte-
a voltage doubler is depicted in Fig. 26a. During the clock
grator must slew 1 volt in 4 ns and the sampling capacitor is
phase
1
, the capacitor C
1
is charged to V
DD
, and, during the
of the order of 20 pF, the OTA output current must be equal
next clock phase, its negative plate is connected to V
DD
.
to or higher than 2.5 mA. Typically, for the folded cascade
Hence, at the beginning of
2
, the voltage at the top plate of
OTA, the DC current of the output and the input stages are
C
1
is equal to 2(V
DD
) (V
SS
). Hence, C
1
is connected to C
LOAD
the same. Therefore, the bias current for M
1
, M
3
, M
4
, and M
5
and, after several clock cycles, if C
LOAD
is not further dis-
equals 2.5 mA. The bias current for M
2
and M
6
is 5 mA. If
charged, the charge is recombined leading to an output volt-
V
GS1
V
T1
equals 0.06 V the dimensions of M
1
can be com-
age equal to 2(V
DD
V
SS
). An implementation for an N-well
puted. Similarly, the dimensions of the transistors can be cal-
process is shown in Fig. 26(b). In this circuit, the transistors
culated, most of them designed to maximize the output range
M
1
, M
2
, M
3
, and M
4
behave as the switches S
1
, S
2
, S
3
, and S
4
of the OTA. The dimensions and the bias condition for the
of Fig. 26(a). Whereas normal clocks are used for M
1
and M
2
,
OTA are given in Table 1.
special clock phases are generated for M
3
and M
4
because they
A very important issue in the design of low-voltage ampli-
drive higher voltages. The circuit operates as follows.
ers is the reference voltage. In the folded-cascade of Fig. 22,
During
1
, M
8
is opened because
2
is high. The voltage at
the values of the reference voltages V
R1
and V
R2
must be opti-
node v
y
is higher than V
DD
because the capacitors C
3
and C
P
mized for maximum swing of the output signal.
were charged to V
DD
during the previous clock phase
2
. At
the beginning of
1
, when the voltage goes up, charge is in-
Analog Switches
jected to the node through the capacitor C
3
. Because the bot-
tom plate of C
2
is connected to ground by M
6
, C
2
is charged to For low-voltage applications, the highest voltage processed is
limited by the analog switches rather than by the op amps. V
DD
V
SS
through M
7
. Also, C
1
is charged to V
DD
V
SS
. Dur-
Figure 26. Voltage doubler: (a) simplied
V
DD
V
DD
V
SS
V
SS
S
4
M
8
V
y
V
x
C
1
C
p
C
2
M
7
M
6
M
5
M
4
M
2
M
1
M
3
S
1
V
0
C
1
C
Load
V
0
C
Load

2

2

2
'

2
'

2
'
S
2

2
(b) (a)
diagram and (b) transistor level diagram.
180 SWITCHED CAPACITOR NETWORKS
ing
2
, the refresh clock phase, the bottom plate of C
1
is con-
nected to V
DD
by the PMOS transistor M
2
. Note that if an
NMOS transistor is employed, the voltage at the bottom plate
of C
1
is equal to V
DD
V
T
resulting in lower output voltage.
If C
1
is not discharged, the voltage at its top plate is 2V
DD

V
SS
The voltage at node v
x
approaches 3V
DD
2V
SS
volts turn-
ing M
3
on and enabling the charge recombination of C
1
and
C
LOAD
. As a result, after several clock periods, the output volt-
age v
0
is equal to 2V
DD
V
SS
. It has to be noted that v
Y
is
precharged to V
DD
during this clock phase and that M
7
is off,
keeping the voltage v
x
high. To avoid discharges, the gate of
M
4
is also connected to the bottom plate of C
2
. Thus, M
4
is
turned off during the refresh phase.
Some results are shown in Fig. 27. For this gure, the volt-
3000 2500 2000 1500 1000 500
B
a
n
d
-
p
a
s
s

g
a
i
n

(
d
B
)
20
15
10
5
20
0
5
10
Frequency (Hz)
age at the nodes v
X
, v
Y
, and v
0
are depicted. The supply volt-
ages used are V
DD
0.75 V and V
SS
0.75 V. The voltage
Figure 28. Frequency response of the second-order, band-pass lter.
at node v
x
is nearly equal to 3V
DD
2V
SS
, for this example,
equal to 3.75 V. The output voltage nearly equals 2.25 V.
Equating the terms of Eq. (65) with the terms of Eq. (37), the
following equations are obtained:
Design Example
Biquadratic lter. In this section, a second-order band-pass
lter is designed. Following are the specications for this
biquad:
Center frequency: 1.63 kHz
a
8
=
1
0.9229
1
a

5
=
0.1953
0.9229
a
2
a
7
= 2 +a
8

0.5455
0.9229
(66)
Quality factor: 16
Solving these equations, the following values are obtained: Peak gain: 10 dB
Clock frequency: 8 kHz
A transfer function that realizes this lter is given by the
a
8
= 0.0835
a

5
= 0.2116
a
2
a
7
= 1.4924
following expression:
A typical design procedure employs a
2
1. For this case, the
total capacitance is of the order of 32 unity capacitances. The
frequency response of the lter is shown in Fig. 28.
H(z) =
0.1953(z 1)z
z
2
0.5455z +0.9229
(65)
This transfer function is implemented by using the biquad
Reading List
presented before. For the biquad of Fig. 21 and employing
a
1
a
5
a
9
0, the circuit behaves as a band-pass lter.
P. E. Allen and E. Sa nchezSinencio, Switched-Capacitor Circuits,
New York: Van Nostrand, 1984.
R. W. Brodersen, P. R. Gray, and D. A. Hodges, MOS switched-capaci-
tor lters, Proc. IEEE, 67: 6175.
R. Castello and P. R. Gray, A high-performance micropower switched-
capacitor lter, IEEE J. Solid-State Circuits, SC-20: 11221132,
1985.
R. Castello and P. R. Gray, Performance limitations in switched-ca-
pacitor lters, IEEE Trans. Circuits Syst., CAS-32: 865876, 1985.
J. Crols and M. Steyaert, Switched-op amp: An approach to realize
full CMOS switched-capacitor circuits at very low power supply
voltages, IEEE J. Solid-State Circuits, 29: 936942, 1994.
A. I. A. Cunha, O. C. Gouvevia Filho, M. C. Schneider, and C. Galup-
Montoro, A current-based model of the MOS transistor, IEEE IS-
CAS, 1997, pp. 16081611.
R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques
for Analog and Digital Circuits, New York: McGrawHill, 1990.
R. Gregorian and G. Temes, Analog MOS Integrated Circuits, New
York: Wiley, 1986.
M
a
g
n
i
t
u
d
e

(
V
)
4
3
2
1
0
140 120 100 80 60 40 20 0
Time (s 10
6
)
A. Mekkaou and P. Jespers, Four quadrant multiplier for neural net-
works, Electron. Lett., 27: 320322, 1991. Figure 27. Time response of the voltage doubler at start-up.
SWITCHED RELUCTANCE MOTOR DRIVES 181
H. Qiuting, A novel technique for the reduction of capacitance spread
in high-Q SC circuits, IEEE Trans. Circuits Syst., 36: 121126,
1989.
B. Razavi, Principles of Data Conversion System Design, New York:
IEEE Press, 1995.
J. J. F. Rijns and H. Wallinga, Stray-insensitive sample-delay-hold
buffers for high-frequency switched-capacitor lters, Proc. IEEE/
ISCAS, June 1991, 3, 16651668.
E. Sa nchezSinencio, J. SilvaMart nez, and R. L. Geiger, Biquad-
ratic SC lters with small GB effects, IEEE Trans. Circuits Syst.,
876884, 1984.
R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Contin-
uous-Time Integrated Circuits and Systems, Berlin, Heidelberg:
Springer-Verlag, 1989.
E. Vittoz, Very low power circuit design: Fundamentals and limits,
IEEE/ISCAS 93 Proc., Chicago, Illinois, May 1993, 14511453.
G. Wegmann, E. A. Vittoz, and F. Rahali, Charge injection in analog
MOS switches, IEEE J. Solid-State Circuits, 22: 10911097, 1987.
EDGAR SA

NCHEZSINENCIO
Texas A&M University
SWITCHED-CURRENT TECHNIQUE. See ANALOG IN-
TEGRATED CIRCUITS.
SWITCHED FILTERS. See DISCRETE TIME FILTERS.
SWITCHED NETWORKS. See DISCRETE TIME FILTERS;
TELEPHONE NETWORKS.