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Microprocessor and Microcontroller

The 8051 microcontroller provides 5 vectored interrupts including two external interrupts, two timer interrupts, and a serial port interrupt. The interrupts can be configured to be edge-triggered or level-triggered and have either high or low priority. When an interrupt occurs, the program counter is pushed to the stack and the interrupt service routine is executed before returning to the original program.

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Abhisek Sarkar
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49 views

Microprocessor and Microcontroller

The 8051 microcontroller provides 5 vectored interrupts including two external interrupts, two timer interrupts, and a serial port interrupt. The interrupts can be configured to be edge-triggered or level-triggered and have either high or low priority. When an interrupt occurs, the program counter is pushed to the stack and the interrupt service routine is executed before returning to the original program.

Uploaded by

Abhisek Sarkar
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Interrupts in 8051

8051 provides 5 vectored interrupts. They are


1.
2. TF0
3.
4. TF1
5. RI/TI
Out o these! and are e"terna# interrupts $hereas Ti%er and &eria# port interrupts are 'enerated
interna##y. The e"terna# interrupts cou#d (e ne'ative ed'e tri''ered or #o$ #eve# tri''ered. )## these interrupt! $hen
activated! set the correspondin' interrupt #a's. *"cept or seria# interrupt! the interrupt #a's are c#eared $hen the
processor (ranches to the Interrupt &ervice Routine +I&R,. The e"terna# interrupt #a's are c#eared on (ranchin' to
Interrupt &ervice Routine +I&R,! provided the interrupt is ne'ative ed'e tri''ered. For #o$ #eve# tri''ered e"terna#
interrupt as $e## as or seria# interrupt! the correspondin' #a's have to (e c#eared (y sot$are (y the pro'ra%%er.
The sche%atic representation o the interrupts is as o##o$s -
Interrupt .ector
/ocation
Fig 8051 Interrupt Details
*ach o these interrupts can (e individua##y ena(#ed or disa(#ed (y 0settin'1 or 0c#earin'1 the correspondin' (it in the
I* +Interrupt *na(#e Re'ister, &FR. I* contains a '#o(a# ena(#e (it *) $hich ena(#es/disa(#es a## interrupts at once.
Interrupt Enable register (IE): )ddress2 )83
*40 interrupt +*"terna#, ena(#e (it
*T0 Ti%er-0 interrupt ena(#e (it
*41 interrupt +*"terna#, ena(#e (it
*T1 Ti%er-1 interrupt ena(#e (it
*& &eria# port interrupt ena(#e (it
*T2 Ti%er-2 interrupt ena(#e (it
*) *na(#e/5isa(#e a##
&ettin' 011 *na(#e the correspondin' interrupt
&ettin' 001 5isa(#e the correspondin' interrupt
Priority level structure:
*ach interrupt source can (e pro'ra%%ed to have one o the t$o priority #eve#s (y settin' +hi'h priority, or c#earin'
+#o$ priority, a (it in the I6 +Interrupt 6riority, Re'ister . ) #o$ priority interrupt can itse# (e interrupted (y a hi'h
priority interrupt! (ut not (y another #o$ priority interrupt. I t$o interrupts o dierent priority #eve#s are received
si%u#taneous#y! the re7uest o hi'her priority #eve# is served. I the re7uests o the sa%e priority #eve# are received
si%u#taneous#y! an interna# po##in' se7uence deter%ines $hich re7uest is to (e serviced. Thus! $ithin each priority
#eve#! there is a second priority #eve# deter%ined (y the po##in' se7uence! as o##o$s.
Interrupt Priority register (IP)
001 #o$ priority
011 hi'h priority
Interrupt handling:
The interrupt #a's are sa%p#ed at 62 o &5 o every instruction cyc#e +8ote that every instruction cyc#e has si"
states each consistin' o 61 and 62 pu#ses,. The sa%p#es are po##ed durin' the ne"t %achine cyc#e +or instruction
cyc#e,. I one o the #a's $as set at &562 o the precedin' instruction cyc#e! the po##in' detects it and the interrupt
process 'enerates a #on' ca## +/9)//, to the appropriate vector #ocation o the interrupt. The /9)// is 'enerated
provided this hard$are 'enerated /9)// is not (#oc:ed (y any one o the o##o$in' conditions.
1. )n interrupt o e7ua# or hi'her priority #eve# is a#ready in pro'ress.
2. The current po##in' cyc#e is not the ina# cyc#e in the e"ecution o the instruction in pro'ress.
3. The instruction in pro'ress is R*TI or any $rite to I* or I6 re'isters.
;hen an interrupt co%es and the pro'ra% is directed to the interrupt vector address! the 6ro'ra% 9ounter +69,
va#ue o the interrupted pro'ra% is stored +pushed, on the stac:. The re7uired Interrupt &ervice Routine +I&R, is
e"ecuted. )t the end o the I&R! the instruction R*TI returns the va#ue o the 69 ro% the stac: and the ori'ina##y
interrupted pro'ra% is resu%ed.
eset is a non-%as:a(#e interrupt. ) reset is acco%p#ished (y ho#din' the R&T pin hi'h or at #east t$o %achine
cyc#es. On resettin' the pro'ra% starts ro% 00003 and so%e #a's are %odiied as o##o$s -

egister
!alue("e#) on eset
69
00003
56TR 00003
)
003
< 003
&6
0=3
6&; 003
6orts 60-3 /atches
FF3
I6 444 00000 (
I*
0 44 00000 (
T9O8 003
T>O5
003
T30 003
T/0
003
T31 003
T/1
003
&9O8 003
&<?F
44 3
69O8 0 4444 444 (
The sche%atic dia'ra% o the detection and processin' o interrupts is 'iven as o##o$s.
Instruction 9yc#es
Fig: Interrupt "andling in 8051
It shou#d (e noted that the interrupt $hich is (#oc:ed due to the three conditions %entioned (eore is not
re%e%(ered un#ess the #a' that 'enerated interrupt is not sti## active $hen the a(ove (#oc:in' conditions are
re%oved! i.e. !every po##in' cyc#e is ne$.

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