Scribd
Upload
135 views2 pages

Sample Paper For DSD

1. The document is a midterm exam for a digital system design course assessing students' knowledge of concepts like addition, subtraction using 2's complement, custom adder design, fixed point conversion, convolution, data flow graph buffer sizing, and adding in Q format with sign extension. 2. The first question asks students to design a custom adder that performs addition, subtraction, negative addition, and negative subtraction using one adder and write RTL code for it. 3. The last question asks students to add three numbers in Q format using sign extension logic and compute the resulting Q format.

Uploaded by

mtkhusro92
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
135 views2 pages

Sample Paper For DSD

1. The document is a midterm exam for a digital system design course assessing students' knowledge of concepts like addition, subtraction using 2's complement, custom adder design, fixed point conversion, convolution, data flow graph buffer sizing, and adding in Q format with sign extension. 2. The first question asks students to design a custom adder that performs addition, subtraction, negative addition, and negative subtraction using one adder and write RTL code for it. 3. The last question asks students to add three numbers in Q format using sign extension logic and compute the resulting Q format.

Uploaded by

mtkhusro92
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Center for Advanced Studies in Engineering

Mid Exam
CE-3201 DIGITAL SYSTEM DESIGN
Time: 90 mins Instructor: Syed Ali Jabir
Marks: 50 Date: 20
th
July, 2012

Q1.
In hardware, subtraction is also done using an adder by adding 2s complement of the number
to be subtracted i.e.
= + (

+)
1. Design a custom adder that performs all the given operations (using only one adder)
A + B
A B
-A + B
-A B
2. Write RTL Code for your design.
3. TAKE HOME: Write the code on a separate sheet and submit the softcopy of the running code
with stimulus. You can ONLY make minor changes to correct the syntax.
Marks (8, 7, 5)
Q2.
float x[5] = {0.22,-0.135,0.877,-0.516,-0.99};
float h[3] = {-2.375,1.24,0.531};

Convolution is to be done on the numbers declared in C/C++ code. Define an appropriate 16-bit
fixed point format for the given arrays and convert them into fixed point. What will be the Q
format of y[n]?
[] = [][ ]

=

Marks (10)





Q3.

Consider the above hypothetical DFG
1. Compute buffer sizes to implement the DFG by a greedy approach.
2. Compute Buffer sizes to implement the DFG so that no single node has to wait.
3. Map the DFG on hardware using sequential approach.
Marks (3, 4, 3)

Q4.
Add the following Q format numbers with using sign extension logic (compute CV).
1111010 Q3.4
100101 Q5.1
01110100 Q1.7
Marks (10)

You might also like