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Tute Sample

This document contains solutions to questions about instruction set architectures, processor performance, number representation, and addressing modes. For processor performance, the solutions calculate cycles per instruction (CPI) for different processor configurations to determine which design change would improve performance more. For number representation, it shows the conversion of decimal values to single-precision floating point binary formats and performs addition and subtraction in that format. For addressing modes, it calculates an effective address given a PC-relative instruction and classifies different addressing modes and their memory references.

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Prateek Khare
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114 views4 pages

Tute Sample

This document contains solutions to questions about instruction set architectures, processor performance, number representation, and addressing modes. For processor performance, the solutions calculate cycles per instruction (CPI) for different processor configurations to determine which design change would improve performance more. For number representation, it shows the conversion of decimal values to single-precision floating point binary formats and performs addition and subtraction in that format. For addressing modes, it calculates an effective address given a PC-relative instruction and classifies different addressing modes and their memory references.

Uploaded by

Prateek Khare
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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T.A.

Shashank Sheshar Singh


[email protected]
1. Instruction Set Architecture (ISA)
Q.1. Consider an example processor which supports two-address, one-address and zero address
instruction set. 24 bit instruction is placed in the 1024 word memory. If there exist 3 two-address
instruction, 100 one-address instructions then how many zero address instruction formulated.
SOL. 24 -bits
Step 1:
4 bit 10 bit 10 bit
Step 2: total #operation possible: 2
4
= 16.
Step 3: total #free combination possible after allocate higher instruction: 16-3=13.
Step 4: total # one address instruction possible: 13*2
10
.
Step 5: total #free combination possible after allocate one address instruction: 13312
(13*1024=13312). Zero address instruction = (13312-100)*2
10
=13212*2
10
.

2. Processor performance equation
Q.1. Assume a processor with instruction frequencies and costs
Integer ALU: 50%, 1 cycle
Load: 20%, 5cycle
Store: 10%, 1 cycle
Branch: 20%, 2cycle
Which change would improve performance more?
A. Branch prediction to reduce branch cost to 1 cycle?
B. Faster data memory to reduce load cost to 3 cycles?
SOL. Compute CPI
Base = 0.5*1 + 0.2*5 + 0.1*1 + 0.2*2 = 2 CPI
A = 0.5*1 + 0.2*5 + 0.1*1+ 0.2*1 = 1.8 CPI (1.11x or 11% faster)
B = 0.5*1 + 0.2*3 + 0.1*1 + 0.2*2 = 1.6 CPI (1.25x or 25% faster)
B is the winner

Q.2. Suppose we have made the following measurements
Frequency of FP operations = 25%
Average CPI of FP operations = 4.0
Op code Address 1 Address 2
Average CPI of other instructions = 1.33
Frequency of FPSQR= 2%
CPI of FPSQR = 20
Assume that the two design alternatives are to decrease the CPI of FPSQR to 2 or to decrease the
average CPI of all FP operations to 2.5. Compare these two design alternatives using the
processor performance equation.
SOL. CPI
original
= CPI

=1
k
*Frequncy
= (4*25% ) + (1.33*75% ) = 2.0
CPI
Iwith new

FPSQR
= CPI
original
- 2%*(

CPI
with olds

FPSQR
-

CPI
with new

FPSQR only
)
= 2.0 2% *( 20 2) = 1.64
We can compute the CPI for the enhancement of all FP instructions the same way or by
summing the FP and non-FP CPIs. Using the latter gives us

CPI
new

FP
= (75% *1.33) +( 25%*2.5) = 1.625
The speedup for the overall FP enhancement is
Speedup
new

FP
= ( CPI
original
/ CPI
new

FP
) = (2/1.625) = 1.23
2. Number Representation
Q.1. Do the following calculations below in single precision floating point representation. Show
the floating point binary values for the operands, show the result of the add or subtract, then
show the final normalized binary representation.
(A) 0.5 + 0.3125,
(B) 12 3.875.
SOL. Each of the numbers can be represented in the following single precision floating point
format.
Sign (1 bit) Exponent (8 bits) (1),Fraction (23 bits)
(A) 0.5:
0 01111110 (1),00000000000000000000000
0.3125:
0 01111101 (1)01000000000000000000000

0.3125 After aligning the exponent:
0 01111110 (0)10100000000000000000000
0.3125+0.5:
0 01111110 (1)10100000000000000000000
Normalize the result:
0 01111110 10100000000000000000000
(B). 12:
0 10000010 (1)10000000000000000000000
3.875
0 10000000 (1).11110000000000000000000
3.875 After aligning the exponent:
0 10000010 (0).01111100000000000000000
12-3.875: use the 2s complement to represent the fractions, and do addition for two operands:
0 1.100000 (all zeros)
+ 1 1.100001 (all zeros)
0 1.000001 (all zeros)
Therefore the result is:
0 10000010 00000100000000000000000

3. Addressing Modes
Q.1. A three byte long PC-relative instruction is stored in the memory with starting address of
304052 (decimal) onwards. If a (-31) signed displacement is present in the address field of the
instruction what is the next instruction address (effective address).
SOL. EA= PC+IR [address field value]
EA=304055 +(-31) =304024
Q.2. Find out the name of addressing modes presented and number of memory references of
following instructions-
1. ADD A [R
0
], @B
2. MOV R
0
, [2000][R
1
]
3. MOV Ax, [Bx][SI]
4. ADD @R
0
, @5000
SOL.1. Indexed and indirect addressing mode, 4[1(D)+1(S1)+2(S2)] memory references
2. Indirect Indexed addressing modes, 2[1-base address cal,1-read-write data] memory ref.
3. Base indexed addressing mode, 1[for read-write data] memory ref.
4. Memory indirect addressing mode, 4[1+1+2] memory ref.

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