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    Triple 3-Input NOR Gate: High-Voltage Silicon-Gate CMOS

    Uploaded by

    Eric Fisher
    This document provides specifications for the SL4025B triple 3-input NOR gate made by System Logic. Key details include: - It operates from 3-18V and has low input current even at high voltages. - Noise margins ensure reliable operation over temperature. - Maximum ratings, recommended operating conditions, and electrical characteristics are specified. - It has low propagation delay and transition times even at high voltages and temperatures.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Triple 3-Input NOR Gate: High-Voltage Silicon-Gate CMOS

    Uploaded by

    Eric Fisher
    26 views4 pages
    This document provides specifications for the SL4025B triple 3-input NOR gate made by System Logic. Key details include: - It operates from 3-18V and has low input current even at high voltages. - Noise margins ensure reliable operation over temperature. - Maximum ratings, recommended operating conditions, and electrical characteristics are specified. - It has low propagation delay and transition times even at high voltages and temperatures.

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    Data Sheet

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    This document provides specifications for the SL4025B triple 3-input NOR gate made by System Logic. Key details include: - It operates from 3-18V and has low input current even at high voltages. - Noise margins ensure reliable operation over temperature. - Maximum ratings, recommended operating conditions, and electrical characteristics are specified. - It has low propagation delay and transition times even at high voltages and temperatures.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    26 views4 pages

    Triple 3-Input NOR Gate: High-Voltage Silicon-Gate CMOS

    Uploaded by

    Eric Fisher
    This document provides specifications for the SL4025B triple 3-input NOR gate made by System Logic. Key details include: - It operates from 3-18V and has low input current even at high voltages. - Noise margins ensure reliable operation over temperature. - Maximum ratings, recommended operating conditions, and electrical characteristics are specified. - It has low propagation delay and transition times even at high voltages and temperatures.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    SL4025B

    Syst em Logi c
    Semi c onduc t or
    SLS
    Triple 3-Input NOR Gate

    High-Voltage Silicon-Gate CMOS

    The SL4025B NOR gates provide the system designer with direct
    emplementation of the NOR function.
    Operating Voltage Range: 3.0 to 18 V
    Maximum input current of 1 A at 18 V over full package-
    temperature range; 100 nA at 18 V and 25C
    Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply



    ORDERING INFORMATION
    SL4025BN Plastic
    SL4025BD SOIC
    T
    A
    = -55 to 125 C for all packages

    LOGIC DIAGRAM



    PIN 14 =V
    CC

    PIN 7 = GND

    PIN ASSIGNMENT

    FUNCTION TABLE
    Inputs Output
    A B C Y
    L L L H
    H X X L
    X H X L
    X X H L
    X = don t care
    SL4025B


    Syst em Logi c
    Semi c onduc t or
    SLS

    MAXIMUM RATINGS
    *

    Symbol Parameter Value Unit
    V
    CC
    DC Supply Voltage (Referenced to GND) -0.5 to +20 V
    V
    IN
    DC Input Voltage (Referenced to GND) -0.5 to V
    CC
    +0.5 V
    V
    OUT
    DC Output Voltage (Referenced to GND) -0.5 to V
    CC
    +0.5 V
    I
    IN
    DC Input Current, per Pin 10 mA
    P
    D
    Power Dissipation in Still Air, Plastic DIP+
    SOIC Package+
    750
    500
    mW
    P
    D
    Power Dissipation per Output Transistor 100 mW
    Tstg Storage Temperature -65 to +150 C
    T
    L
    Lead Temperature, 1 mm from Case for 10 Seconds
    (Plastic DIP or SOIC Package)
    260 C
    *
    Maximum Ratings are those values beyond which damage to the device may occur.
    Functional operation should be restricted to the Recommended Operating Conditions.
    +Derating - Plastic DIP: - 10 mW/C from 65 to 125C
    SOIC Package: : - 7 mW/C from 65 to 125C

    RECOMMENDED OPERATING CONDITIONS
    Symbol Parameter Min Max Unit
    V
    CC
    DC Supply Voltage (Referenced to GND) 3.0 18 V
    V
    IN
    , V
    OUT
    DC Input Voltage, Output Voltage (Referenced to GND) 0 V
    CC
    V
    T
    A
    Operating Temperature, All Package Types -55 +125 C



    This device contains protection circuitry to guard against damage due to high static voltages or electric
    fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
    voltages to this high-impedance circuit. For proper operation, V
    IN
    and V
    OUT
    should be constrained to the range
    GND(V
    IN
    or V
    OUT
    )V
    CC
    .
    Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
    CC
    ).
    Unused outputs must be left open.

    SL4025B


    Syst em Logi c
    Semi c onduc t or
    SLS

    DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
    V
    CC
    Guaranteed Limit
    Symbol Parameter Test Conditions V -55C 25C 125
    C
    Unit
    V
    IH
    Minimum High-Level
    Input Voltage
    V
    OUT
    =0.5V
    V
    OUT
    =1.0 V
    V
    OUT
    =1.5V
    5.0
    10
    15
    3.5
    7
    11
    3.5
    7
    11
    3.5
    7
    11
    V
    V
    IL
    Maximum Low -Level
    Input Voltage
    V
    OUT
    =0.5 V or V
    CC
    - 0.5 V
    V
    OUT
    =1.0 V or V
    CC
    - 1.0 V
    V
    OUT
    =1.5 V or V
    CC
    - 1.5 V
    5.0
    10
    15
    1.5
    3
    4
    1.5
    3
    4
    1.5
    3
    4
    V
    V
    OH
    Minimum High-Level
    Output Voltage
    V
    IN
    =GND 5.0
    10
    15
    4.95
    9.95
    14.95
    4.95
    9.95
    14.95
    4.95
    9.95
    14.95
    V
    V
    OL
    Maximum Low-Level
    Output Voltage
    V
    IN
    =GND or V
    CC
    5.0
    10
    15
    0.05
    0.05
    0.05
    0.05
    0.05
    0.05
    0.05
    0.05
    0.05
    V
    I
    IN
    Maximum Input
    Leakage Current
    V
    IN
    = GND or V
    CC
    18 0.1 0.1 1.0 A
    I
    CC
    Maximum Quiescent
    Supply Current
    (per Package)
    V
    IN
    = GND or V
    CC
    5.0
    10
    15
    20
    0.25
    0.5
    1.0
    5.0
    0.25
    0.5
    1.0
    5.0
    7.5
    15
    30
    150
    A
    I
    OL
    Minimum Output Low
    (Sink) Current
    V
    IN
    = GND or V
    CC

    U
    OL
    =0.4 V
    U
    OL
    =0.5 V
    U
    OL
    =1.5 V

    5.0
    10
    15

    0.64
    1.6
    4.2

    0.51
    1.3
    3.4

    0.36
    0.9
    2.4
    mA
    I
    OH
    Minimum Output High
    (Source) Current
    V
    IN
    = GND or V
    CC

    U
    OH
    =2.5 V
    U
    OH
    =4.6 V
    U
    OH
    =9.5 V
    U
    OH
    =13.5 V

    5.0
    5.0
    10
    15

    -2.0
    -0.64
    -1.6
    -4.2

    -1.6
    -0.51
    -1.3
    -3.4

    -1.15
    -0.36
    -0.9
    -2.4
    mA

    SL4025B


    Syst em Logi c
    Semi c onduc t or
    SLS

    AC ELECTRICAL CHARACTERISTICS(C
    L
    =50pF, R
    L
    =200k, Input t
    r
    =t
    f
    =20 ns)
    V
    CC
    Guaranteed Limit
    Symbol Parameter V -55C 25C 125C Unit
    t
    PLH
    , t
    PHL
    Maximum Propagation Delay, Input A, B or C to
    Output Y (Figure 1)
    5.0
    10
    15
    250
    120
    90
    250
    120
    90
    500
    240
    180
    ns
    t
    TLH
    , t
    THL
    Maximum Output Transition Time, Any Output
    (Figure 1)
    5.0
    10
    15
    200
    100
    80
    200
    100
    80
    400
    200
    160
    ns
    C
    IN
    Maximum Input Capacitance - 7.5 pF





    Figure 1. Switching Waveforms




    EXPANDED LOGIC DIAGRAM
    (1/3 of the Device)

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