MC14099B

8-Bit Addressable Latches

The MC14099B is an 8bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.

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MARKING
DIAGRAMS

Features

PDIP16
P SUFFIX
CASE 648

Serial Data Input

Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One
LowPower Schottky TTL Load over the Rated Temperature
Range
MC14099B pin for pin compatible with CD4099B
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable

SOIC16 WD
DW SUFFIX
CASE 751G

14099BG
AWLYYWW
1

A
WL
YY
WW
G

= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Indicator

Value

Unit

0.5 to +18.0

ORDERING INFORMATION

0.5 to VDD + 0.5

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Input or Output Current

(DC or Transient) per Pin

10

mA

PD

Power Dissipation, per Package

(Note 1)

500

mW

TA

Ambient Temperature Range

55 to +125

Tstg

Storage Temperature Range

65 to +150

TL

Lead Temperature
(8Second Soldering)

260

VDD
Vin, Vout
Iin, Iout

Parameter

MC14099BCP
AWLYYWWG

16

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

16

DC Supply Voltage Range

Input or Output Voltage Range
(DC or Transient)

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2013

June, 2013 Rev. 8

Publication Order Number:

MC14099B/D

MC14099B
PIN ASSIGNMENT
Q7

16

VDD

RESET

15

Q6

DATA
WRITE
DISABLE
A0

14

Q5

WRITE DISABLE
DATA

13

Q4

12

Q3

A0
A1
A2

A1

11

Q2

RESET

A2

10

Q1

VSS

Q0

MC14099B
4
3
5
6
DECODER
7

9
10
11
12
8
13
LATCHES 14
15
1

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

VDD = 16
VSS = 8

ORDERING INFORMATION
Package

Shipping

MC14099BCPG

PDIP16
(PbFree)

500 Units / Rail

MC14099BDWG

SOIC16 WB
(PbFree)

47 Units / Rail

MC14099BDWR2G

SOIC16 WB
(PbFree)

1000 Units / Tape & Reel

Device

NLV14099BDWR2G*

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable.

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2

MC14099B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Output Voltage
Vin = VDD or 0

Symbol

55_C

25_C

125_C

VDD
Vdc

Min

Max

Min

Typ
(Note 2)

Max

Min

Max

Unit

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL

5.0
10
15

1.5
3.0
4.0

2.25
4.50
6.75

1.5
3.0
4.0

1.5
3.0
4.0

1 Level

VIH

5.0
10
15

3.5
7.0
11

3.5
7.0
11

2.75
5.50
8.25

3.5
7.0
11

5.0
5.0
10
15

3.0
0.64
1.6
4.2

2.4
0.51
1.3
3.4

4.2
0.88
2.25
8.8

1.7
0.36
0.9
2.4

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

mAdc

Input Capacitance (Vin = 0)

Cin

5.0

7.5

pF

Input Capacitance
MC14599B Data (pin 3)
(Vin = 0)

Cin

15

22.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

5.0
10
20

0.005
0.010
0.015

5.0
10
20

150
300
600

mAdc

IT

5.0
10
15

Vin = 0 or VDD

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

Output Drive Current

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

Source

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Sink

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

IOH

Vdc

Vdc

mAdc

IT = (1.5 mA/kHz) f + IDD

IT = (3.0 mA/kHz) f + IDD
IT = (4.5 mA/kHz) f + IDD

2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004.

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3

mAdc

MC14099B

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

VDD
Vdc

Min

Typ
(Note 6)

Max

5.0
10
15

100
50
40

200
100
80

5.0
10
15

200
75
50

400
150
100

Write Disable to Output Q

5.0
10
15

200
80
60

400
160
120

ns

Reset to Output Q

5.0
10
15

175
80
65

350
160
130

ns

CE to Output Q (MC14599B only)

5.0
10
15

225
100
75

450
200
150

ns

5.0
10
15

200
80
65

400
160
130

5.0
10
15

200
90
75

400
180
150

5.0
10
15

150
75
50

75
40
25

5.0
10
15

320
160
120

160
80
60

5.0
10
15

100
50
35

50
25
20

5.0
10
15

150
75
50

75
40
25

Characteristic

Symbol

Output Rise and Fall Time

tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns

tTLH,
tTHL

Propagation Delay Time

Data to Output Q

tPHL,
tPLH

Propagation Delay Time, MC14599B only

Chip Enable, Write/Read to Data

ns

ns

tPHL,
tPLH

ns

Address to Data

Pulse Widths
Reset

Unit

tw(H)
tw(L)

ns

ns

Write Disable

ns

Set Up Time
Data to Write Disable

tsu

ns

Hold Time
Write Disable to Data

th

Set Up Time
Address to Write Disable

tsu

5.0
10
15

100
80
40

45
30
10

ns

Removal Time
Write Disable to Address

trem

5.0
10
15

0
0
0

80
40
40

ns

ns

5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

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4

MC14099B
FUNCTION DIAGRAM

RESET 2
9Q0
DATA 3

WRITE
4
DISABLE

EACH LATCH
TO
OTHER
LATCHES

ZERO
SELECT
10Q1

A0 5

11Q2
12Q3
ADDRESS
DECODER

A1 6

OTHER LATCHES

13Q4
14Q5
15Q6

A2 7
(M.S.B.)

1Q7

TRUTH TABLE
Write
Disable

Reset

Addressed
Latch

Unaddressed
Latches

Data

Qn*

Data

Reset {

Qn*

Qn*

1
1
Reset
*Qn is previous state of latch.
Reset to zero state.

CAUTION: To avoid unintentional data changes in the latches, Write

Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.

Reset

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5

MC14099B
SWITCHING WAVEFORMS

VDD
DATA OR
WRITE DISABLE

50%
VSS
tPHL

tPLH

OUTPUT Q

90%
50%
10%

VDD
ADDRESS

50%
VSS

tTHL

tTLH

tw(L)

tsu

trem
VDD

WRITE
DISABLE

50%
VSS

tw(H)

tsu

VDD
RESET

50%

VDD
DATA

VSS
tPHL

OUTPUT Q

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6

th

50%
VSS

MC14099B
PACKAGE DIMENSIONS
PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
16

S
T
H

SEATING
PLANE

K
G

16 PL

0.25 (0.010)

T A

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7

DIM
A
B
C
D
F
G
H
J
K
L
M
S

INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040

MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01

MC14099B
PACKAGE DIMENSIONS
SOIC16 WB
CASE 751G03
ISSUE D
A

D
9

h X 45 _

0.25

8X

16

NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.

16X
M

B
T A

0.25

MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_

14X

A1

SEATING
PLANE

SOLDERING FOOTPRINT
0.58

16X

11.00
1

16X

1.27
PITCH

1.62

DIMENSIONS: MILLIMETERS

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limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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MC14099B/D