Combinational Circuit Design

Part I: Design Procedure and

Examples Examples
Part II : Arithmetic Circuits
Part III : Multiplexer, Decoder,
Encoder, Hamming Code
1
Combinational Circuits
Combinational
Circuits
n inputs
m outputs
A combinational circuit has:
n Boolean inputs (1 or more),
m Boolean outputs (1 or more)
logic gates mapping the inputs
to the outputs
2
Design Procedure
1. Specification
Write a complete specification for the circuit
Specify/Label input and output
2. Formulation
Derive a truth table or initial Boolean equations
that define the required relationships between that define the required relationships between
the inputs and outputs, if not in the specification
Apply hierarchical design if appropriate
3. Optimization
Apply 2-level and multiple-level optimization
(Boolean Algebra, K-Map, software)
Draw a logic diagram for the resulting circuit
using necessary logic gates.
3
Design Procedure (Cont.)
4. Technology Mapping
Map the logic diagram to the implementation
technology selected (e.g. map into NANDs)
5. Verification
Verify the correctness of the final design Verify the correctness of the final design
manually or using a simulation tool
Practical Considerations:
Cost of gates (Number)
Maximum allowed delay
Fan-in/Fan-out (# of Input ports/Output
ports provided by devices)
4
Example 1
Question: Design a circuit that has a 3-
bit binary input and a single output (f)
specified as follows:
F = 0, when the input is less than (5)
10
F = 1, otherwise
Solution: Solution:
Step 1 (Specification):
Label the inputs (3 bits) as X, Y, Z
X is the most significant bit, Z is the least
significant bit
The output (1 bit) is F:
F = 1 (101)
2
, (110)
2
, (111)
2
F = 0 other inputs
5
Step 2
(Formulation)
Obtain Truth table
X Y Z F
0 0 0 0
0 0 1 0
Step 3
(Optimization)
F = XYZ+XYZ+XYZ
= XYZ+XYZ+XYZ+XZ+XY
= XZ + XY
Example 1 (cont.)
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
(Use consensus theorem)
X
Z
X
Y
F
Circuit Diagram
Boolean Expression:
F = XYZ+XYZ+XYZ
6
Example 2
Question (BCD to Excess-3 Code
Converter)
Code converters convert from one code
to another (BCD to Excess-3 in this
example) example)
The inputs are defined by the code that is
to be converted (BCD in this example)
The outputs are defined by the converted
code (Excess-3 in this example)
Excess-3 code is a decimal digit plus
three converted into binary, i.e., 0 is
0011, 1 is 0100, etc.
7
BCD Input Excess 3 Output
Decimal A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
Example 2 (cont.)
Step 1 (Specification)
4-bit BCD input (A,B,C,D)
4-bit E-3 output (W,X,Y,Z)
Step 2 (Formulation)
Obtain Truth table
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10-15 All other inputs X X X X
8
Example 2 (cont.)
Step 3 (Optimization)
source: Manos book
9
Example 3
Question (BCD-to-Seven-Segment
Decoder)
src: Manos book
A seven-segment display is digital readout found in
electronic devices like clocks, TVs, etc.
Made of seven light-emitting diodes (LED) segments;
each segment is controlled separately.
A BCD-to-Seven-Segment decoder is a
combinational circuit
Accepts a decimal digit in BCD (input)
Generates appropriate outputs for the segments to
display the input decimal digit (output)
10
Example 3 (cont.)
Step 1 (Specification):
4 inputs (A, B, C, D)
7 outputs (a, b, c, d, e, f, g)
BCD-to-Seven-
Segment
Decoder
a b c d e f g
Step 2 (Formulation)
BCD Input 7 Segment Decoder
Decimal A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
A B C D
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
10-15 All Other Inputs 0 0 0 0 0 0 0
Invalid
BCD
codes
=
No Light
11
Example 3 (cont.)
Step 3 (Optimization)
a b c d
e f g
12
a = AC + ABD + ABC + BCD
b = AB + ACD + ACD + BC
c = AB + BC + AC + AD
d = ACD + ABC +
Example 3 (cont.)
Step 3 (Optimization) (cont.)
d = ACD + ABC +
BCD+ABC+ABCD
e = ACD + BCD
f = ABC + ACD + ABD + ABC
g = ACD + ABC + ABC + ABC
Exercise: Draw the circuit
13
Part II Arithmetic Circuits
Adder
Subtractor
Carry Look Ahead Adder
BCD Adder BCD Adder
Multiplier
14
Half Adder
Design a half-Adder for 1-bit numbers
1. Specification: 3. Logic Diagram
Optimization/Circuit
2 inputs (X,Y)
2 outputs (C,S)
2. Formulation: 2. Formulation:
x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Graphical Symbol
15
Full Adder
A combinational circuit that adds 3 input bits (x
i
,
y
i
, c
in
) to generate a Sum bit and a Carry-out bit
From Browns Fundamentals of digital logic
16
Full Adder Logic Diagram
From Browns Fundamentals of digital logic
17
Full Adder = 2 Half Adders
Block diagram
Circuit
From Browns Fundamentals of digital logic
Exercise : Verify this full-adder implementation.
18
Bigger Adders
How to build an adder for n-bit
numbers?
Example: 4-Bit Adder
Inputs ? 9 inputs
Outputs ? 5 outputs Outputs ? 5 outputs
What is the size of the truth table?
512 rows!
How many functions to optimize? 5
functions
19
Ripple Carry Adder
Note:
Carry signal ripples through the full-adder stages.
Delay can be an issue.
20
Subtraction (2s Complement)
How to build a subtractor using 2s
complement?
1
S = A + ( -B)
Src: Manos Book
21
Adder/Subtractor
0 : Add
1: subtract
Src: Manos Book
Using full adders and XOR we can build an Adder/Subtractor!
22
Full-Adder (Review)
i i i i i i i i i i i
c y c x y x c c y x s + + = =
+

1
;
23
Carry-Lookahead Adder (CLA)
Define
Then
g
i
is called generate function and
p is called propagate function.
i i i i i i
y x p y x g + = = ;
i i i i
c p g c + =
+1
p
i
is called propagate function.
Rewriting c
i+1
in terms of i-1 terms
yields
1 1 1
1 1 1 1
) (

+
+ + =
+ + =
i i i i i i
i i i i i i
c p p g p g
c p g p g c
24
CLA (cont.)
Repeating until 0 term yields
0 0 1 2 1
0 1 2 1 2 1 1 1
c p p p p p
g p p p p g p p g p g c
i i
i i i i i i i i i
L
L L

+
+
+ + + + =
c
i+1
can be implemented in 2-level
AND-OR circuits.
A Carry-Lookahead Adder is based
on this expression.
0 0 1 2 1
c p p p p p
i i
L

+
25
Ripple-carry Adder Delay
LSB:
Only First 2
stages shown
LSB:
(x
0
, y
0
) = (0,1)
Delay: 5 gates
For n stages:
Delay: 2n+1 gates
From Browns Fundamentals of digital logic
26
CLA Delay
LSB:
(x
0
, y
0
) = (0,1)
Only First 2
stages shown
0 0 0 1
c p g c + =
Delay: 3 gates
For n stages:
Delay: 3 gates
0 0 0 1
c p g c + =
0 0 1
0 1 1 2
c p p
g p g c
+
+ =
27
CLA Implementation
Total delay : 4 gates (1 for all g
i
,p
i
, 2 for
all carry, 1 for the final XOR to compute
all s
i
)
Becomes very complex when n large.
Hierarchical CLA with ripple-carry Hierarchical CLA with ripple-carry
28
CLA : A better implementation
Consider c
8
out of block 0:
Recall that
If define
0 0 1 2 6 7
0 1 2 6 7 5 6 7 6 7 7 8
c p p p p p
g p p p p g p p g p g c
L
L L
+
+ + + + =
0 0 0 1
c p g c + =
c p p p p p p p p P =
If define
Then can write
Likewise
0 1 2 6 7 5 6 7 6 7 7 0
g p p p p g p p g p g G L L+ + + + =
0 0 1 2 3 4 5 6 7 0
c p p p p p p p p P =
0 0 0 8
c P G c + =
0 0 1 0 1 1 16
c P P G P G c + + =
0 0 1 2 0 1 2 1 2 2 16
c P P P G P P G P G c + + + =
0 0 1 2 3 0 1 2 3 1 2 3 2 3 3 32
c P P P P G P P P G P P G P G c + + + + =
29
CLA : A better implementation
30
BCD Addition
31
BCD Adder
Adjust=0 -> S = Z + 0
Adjust=1 -> S = Z + 6
32
4-bit Comparator
0
0
1
0
1
1
1
1
0 1 0 1
1 0 0 0
1
1
0
0
0
1
0
1
1 1 0 0
0 1 1 1
3-(-5)=-8 -5-4=7
33
4-bit Comparator
X < Y
Same sign: No overflow (V=0) and N=1
Different sign: V=0 && N=1, OR V=1
(overflow) && N=0 (positive)
Thus, condition is N V=1. Thus, condition is N V=1.
X = Y -> Z = 1
X > Y
Same sign: No overflow (V=0) and N=0
Different sign: V=0 && N=0, OR V=1
(overflow) && N=1 (negative)
Thus, condition is N V=0, i.e., the
complement of N V, (N V).
34
2-to-1 Multiplexer (MUX)
Multiplexer has multiple
inputs and one output; it
passes the signal on one
input to the output.
Symbol Truth Table Symbol Truth Table
SOP circuit
Circuit with transmission gates
35
4-to-1 Multiplexer
3 0 1 2 0 1 1 0 1 0 0 1
' ' ' ' w s s w s s w s s w s s f + + + =
36
4-to-1 Multiplexer
4-to-1 mux using
2-to-1 mux
16-to-1 mux using
4-to-1 mux
37
2 2 crossbar switch
2 inputs, 2 outputs
s = 0 -> connect x
1
->y
1
, x
2
->y
2
s = 1 -> connect x
1
->y
2
, x
2
->y
1
38
Synthesis of Logic Functions
2 1
w w f =
39
3-input XOR
Using
2-to-1 MUX 2-to-1 MUX
Using
4-to-1 MUX
40
3-input Majority Function
Get 3 inputs and output 1 if # of 1s
greater than # of 0s.
41
Shannons Expansion
Shannons Expansion Theorem
1 1
1 ' 1
2 1 2 1 2 1
'
) , , , 1 ( ) , , , 0 ( ' ) , , , (
w w
n n n
f w f w
w w f w w w f w w w w f
+ =
+ = K K K
cofactors : ,
1 1
' w w
f f
Example : 3-input majority function
Can be rewritten as
3 1 3 2 2 1 3 2 1 3 2 1 3 2 1 3 2 1
' ' ' w w w w w w w w w w w w w w w w w w f + + = + + + =
) ( ) ( '
3 2 1 3 2 1 3 1 3 2 2 1
w w w w w w w w w w w w f + + = + + =
42
Shannons Expansion
Using
2-to-1 MUX
3-input XOR
)' ( ) ( '
3 2 1 3 2 1 3 2 1
w w w w w w w w w f + = =
43
Shannons Expansion
In general : expand by w
i
2-variable expansion:
i i
w i w i
n i n i n
f w f w
w w w f w w w w f w w w w f
+ =
+ =
'
2 1 2 1 2 1
'
) , , 1 , , , ( ) , , 0 , , , ( ' ) , , , ( K K K K K
2-variable expansion:
which can be implemented by a 4-to-1
MUX.
) , , , 1 , 1 ( ) , , , 0 , 1 ( '
) , , , 1 , 0 ( ' ) , , , 0 , 0 ( ' ' ) , , , (
3 2 1 3 2 1
3 2 1 3 2 1 2 1
n n
n n n
w w f w w w w f w w
w w f w w w w f w w w w w f
K K
K K K
+ +
+ =
44
Example 1
) 1 ( ' ' ' ' ' '
) ( ' '
' '
2 1 3 2 1 3 2 1 3 2 1
3 2 1 3 1
3 1 2 1 3 1
w w w w w w w w w w w
w w w w w
w w w w w w f
+ + + =
+ + =
+ + =
Using
2-to-1 MUX
Using
4-to-1 MUX
45
3-input majority function
Let g = w
2
w
3
, h = w
2
+w
3
, then
) ( ) ( '
3 2 1 3 2 1 3 1 3 2 2 1
w w w w w w w w w w w w f + + = + + =
) 1 ( ' ; ) 0 ( '
2 3 2 3 2 2
w w w h w w w g + = + =
46
Decoder
Main function: decode encoded data.
n-to-2
n
decoder
2-to-4 decoder
47
Decoder
3-to-8 decoder using
2-to-4 decoder
4-to-1 MUX using
2-to-4 decoder
48
4-to-16 Decoder
49
Demultiplexer (DEMUX)
A 2
m
m ROM Block
50
Encoder
2
n
-to-n encoder
4-to-2 binary encoder
51
Hamming Code
In linear block code family.
Can correct 1-bit error or detect
2-bit error.
Add parity bits to message bits. Add parity bits to message bits.
Typically use notation (n,k)
Hamming code, which means n
total bits, k message bits.
Clearly there are (n-k) parity bits.
52
(7,4) Hamming Code
System Structure
53
Codewords
3 1 0 2 3 2 1 1 2 1 0 0
; ; a a a r a a a r a a a r = = =
Codeword : a
3
a
2
a
1
a
0
r
2
r
1
r
0
with
54
Syndrome
Error pattern is given by syndrome, i.e., s
2
s
1
s
0
(=s) where
2 3 1 0 2 1 3 2 1 1 0 2 1 0 0
; ; q b b b s q b b b s q b b b s = = =
Example : Send 0110100
Receive 0110100 -> s = 000 -> No error
Receive 0111100 -> s = 101 -> Error at b
0
Receive 0010100 -> s = 011 -> Error at b
2
55
(7,4) Hamming Encoder
Exercise : Design the
(7,4) Hamming Decoder
56
Gate Arrays (Programmable Logic Device)
Basic
Structure
(AND-OR GA)
57
Example
f = ab + abc
g = abc + ab + bc
h = ab + c
58
Simplified Diagram
59
Using ROM

=
=
=
) 15 , 11 , 7 , 5 , 1 ( ) , , , (
) 15 , 14 , 10 , 7 , 5 , 4 , 3 ( ) , , , (
) 15 , 11 , 9 , 8 , 7 , 3 ( ) , , , (
m D C B A Y
m D C B A X
m D C B A W
60
Using PLA

=
= =
) 15 , 11 , 7 , 5 , 1 ( ) , , , (
) 15 , 14 , 10 , 7 , 5 , 4 , 3 ( ) , , , ( ; ) 15 , 11 , 9 , 8 , 7 , 3 ( ) , , , (
m D C B A Y
m D C B A X m D C B A W
} ' or { ' '
} or { ' ' ' '
' ' ' ' '
BD A BCD ACD D C A Y
ABC BCD CD A ACD BC A X
ACD CD A C AB CD C AB W
+ + =
+ + + =
+ + = + =
61
Using PLA (2)
62
Using Programmable Array Logic
63