Low-Power Design of Reed-Solomon Encoders

Wei Zhang, Jing Wang

School of Electronic Information Engineering
Tianjin University
Tianjin, China
{tjuzhangwei, wangjing2011}@tju.edu.cn
Xinmiao Zhang
Department of Electrical Engineering and Computer Science
Case Western Reserve University
Cleveland, OH
[email protected]
AbstractReed-Solomon (RS) codes are one of the most widely
used block error-correcting codes in modern communication and
computer systems. Multiplication is the key computation in RS
encoding. Adopting the generator polynomial with symmetric
coefcients, the number of multipliers in RS encoders can
be reduced by half, and their power consumption may also
reduce. However, in some cases, the encoder based on the
generator polynomial with asymmetric coefcients have better
power performance. Additionally, since more than one primitive
polynomial can generate a nite eld with certain order, different
choices of primitive polynomial also change the complexity of
multipliers. In this paper, we exploited the relationship between
the power consumption of RS encoders and their different
encoding parameters. A simple way to nd the encoder with the
lowest power consumption is also presented. Simulation results
prove its effectiveness.
I. INTRODUCTION
Reed-Solomon (RS) codes are among the most popular
error-correcting codes applied in many elds such as digital
communication and storage systems. They could detect and
correct multiple random symbol errors, particularly well-suited
to the situation where errors occur in bursts.
RS encoders usually use a linear feedback shift register
(LFSR) architecture [1] [2]. Many factors have inuence on
its encoding power consumption, such as multipliers, corre-
sponding primitive polynomials and generator polynomials.
For a certain RS code which can correct t error symbols,
its encoder consists of 2t multiplication so that multipliers
can partly determine the power consumption of encoders.
Noting that feedback terms are known, the implementation
circuit just needs 2t one-input constant multipliers (CM),
which have lower circuit complexity, smaller area and shorter
critical path than standard two-input multipliers. The primitive
polynomial is another crucial factor, whose weight has an
immediate relationship with the tuple presentation of each
element as well as circuit complexity of its corresponding CM.
Hence to reduce the encoder power consumption, selecting an
appropriate one is effective.
Whats more, the coefcients of generator polynomial can
be symmetric or asymmetric, corresponding to the symmetric
and asymmetric encoders respectively. For one RS code, the
symmetric encoder only requires half CMs less than the asym-
metric one. Thus, the symmetric encoder is usually considered
This work was supported in part by the Tianjin Nature Science Fund, China,
under grants No. 11ZCKFGX00700 and by the National Science Foundation
under Grants 0846331 and 0835782.
to be the most energy-efcient. However, when t is relatively
lower this general cognition will be opposite.
In this paper we intend to design a low-power RS encoder
by exploiting the efforts of different parameters, including
primitive polynomials, generator polynomials and code lengths
and rates. Analyses are carried out on the power consump-
tion of the multipliers and the encoders with these different
parameters. Simulations are based on Smic 0.18m CMOS
technology and the system clock is 100MHz. Our results can
serve as guidelines for the low power design of RS encoders.
The results prove that the asymmetric encoder can be more
energy-efcient than the symmetric ones when t < 3.
The structure of this paper is organized as follows. Sec-
tion II introduces a brief background information on RS
encoding. Then in Section III, a discussion about factors
affecting encoding power is provided, such as parameters and
circuit structures. Section IV presents the proposed low-power
encoder design in details. Section IV gives the simulation
results. Conclusions are drawn in SectionV.
II. REED-SOLOMON ENCODING
A. Reed-Solomon Encoding Algorithm
This paper focuses on an (n, k) RS code whose codeword is
a block of n symbols, including k symbols of information and
2t = n-k symbols of redundancy check. It is generated from
the k information symbols and t is the maximum number of
error corrections. Each symbol is an element of GF(2
m
) and
can be described in m-tuple representation [3]. Considering a
k-symbol message (f
0
, f
1
, . . . , f
i
, . . . , f
k1
) (f
i
GF(2
m
), 0
i <k) as the coefcients of a degree k-1 message polynomial
f (x) = f
0
+ f
1
x + . . . + f
k1
x
k1
, the corresponding codeword
polynomial with a degree of n-1 can be expressed as c(x) =
f(x)g(x) = c
0
+ c
1
x + . . . + c
n1
x
n1
, where the n-symbol
codeword (c
0
, c
1
, . . . , c
i
, . . . , c
n1
) belongs to GF(2
m
) and
0 i < n. RS encoding consists of multiplication of a
feedback term with several known items. Given as the
primitive element over GF(2
m
), the generator polynomial of
a primitive t-error corrective RS code with length of 2
m
1
is
g(x) = (x +
d
)(x +
d+1
) . . . (x +
d+2t1
)
= g
0
+ g
1
x + . . . + g
2t1
x
2t1
+ x
2t
(1)
g(x) has
d
,
d+1
, . . . ,
d+(2t1)
as all its roots and its
coefcients (g
0
, g
1
, . . . , g
2t1
) also belong to GF(2
m
). The
978-1-4673-5762-3/13/$31.00 2013 IEEE 1560
a
b
D D D D

0
g 2 1 t
g

1
g 2 2 t
g

( ) f x
( ) c x
0
a
b
Fig. 1. Asymmetric encoder
a
b
D D D D
1
g
t
g
( ) f x
( ) c x
0
a
b

Fig. 2. Symmetric RS encoder

choice of d will not affect the dimension or the minimum
distance of the codes.
B. Reed-Solomon Encoder Architecture
The systematic encoding [4] is often accomplished with
an LFSR-based circuit. An asymmetric encoder is shown in
Fig. 1. Clearly, changing d can obtain different encoding
implementation. To reduce the complexity of the encoder,
multiplication is implemented by CMs. Especially, when d =
2
m1
t, the coefcients of the generator polynomial are
symmetric and g(x) = 1+g
1
x+. . .+g
t
x
t
+. . .+g
1
x
2t1
+x
2t
.
The corresponding architecture of the symmetric encoder is
shown in Fig. 2.
The entire encoding process takes n clock cycles. During
the rst k clock cycles, all the two multiplexors in Fig. 1 select
a ports and k symbols are input to the LFSR-based encoder
serially with the most signicant symbol rst. Meanwhile, the
message is also sent to the output to form the systematic part of
the codeword. After k clock cycles, the registers contain nk
symbols of redundancy check. At this time, the multiplexors
select b ports and the remainders are shifted out from the
registers to form the rest of the codeword. The critical path
of the architecture above consists of one XOR gate and one
CM. A same process also presents in Fig. 2.
III. ENCODER POWER ANALYSIS
A. Finite Field Multipliers
The key operation in RS encoding is multiplication [5]. In
this paper, we research CMs based on the Mastrovito multi-
plier [6], whose computation processes are clearly described
in [7]. The number of gates each CM requires depends on
the primitive polynomial used to generate the eld and the
constant multiplicand.
Each element over the eld GF(2
m
) will be represented
by a polynomial of degree m-1. The word-level multiplica-
tion operation receives two m-bit input polynomials a(x) =
a
m1
x
m1
+a
m2
x
m2
+. . . +a
0
and b(x) = b
m1
x
m1
+
b
m2
x
m2
+. . . +b
0
, where a
i
, b
i
GF(2) and 0 i < m.
0 10 20 30 40 50 60 70
0
5
10
15
20
25
30
35
40
45
constant b(x)
p
o
w
e
r

c
o
n
s
u
m
p
t
io
n

o
f

e
a
c
h

c
o
n
s
t
a
n
t

m
u
lt
ip
lie
r
s

(
u
W
)
GF(2
5
)
GF(2
6
)
Fig. 3. Power consumption of each CM over GF(2
m
)
The output result is (x) = a(x)b(x) mod p(x), where p(x)
is the primitive polynomial. In the CM case, we consider b(x)
the constant multiplicand.
The hardware implementation of a two-input multiplier
needs m
2
AND and (m1)
2
XOR gates. As for the CM-based
RS encoding, m AND and m XOR gates will be removed
for each 0 in the m-tuple representation of the constant
element b(x), while each 1 results in a reduction of m AND
gates. Therefore the circuit complexity of each CM should be
determined by both the primitive polynomial and the known
item b(x).
Three kinds of constant b(x) contribute to the low power of
multipliers. (a) b(x) =
0
. If the b(x) is equal to
0
, the multi-
plier is just the connecting wires and power-consumption free;
(b) b(x) {
1
,
2
, . . . ,
m1
}. In this situation, the weights
of b(x) (the number of 1 in the m-tuple representations) is
only one. Such data structures facilitate to reduce the circuit
complexity; (c) b(x) =
2
m
2
. The last element is equal to

1
and we can get it by transforming
0
directly. The way
of elements generating is

0
= 1,
j
= (
j1
<< 1) mod p(x) (j Z) (2)
where Z is the integer set. The inversion of (2) is
(p(x)q +
j
) >> 1 =
j1
(j Z) (3)
where q is the quotient. We get

2
m
2
=
1
= (p(x) 1 +
0
) >> 1 (4)
in (4), q is always equal to 1. Consequently, the last element is
equal to the most signicant m bits of p(x). It can be proved
that if a 5-tuple representation of the element is similar to
p(x), there would be more redundant items in the product and
low power CMs can be obtained. We denote the multipliers
described in (b) and (c) by the set R.
As an example, for b(x) =
30
= x
4
+x, p(x) = x
5
+x
2
+1,
since the word-level addition is the bit-wise XOR operation
over the nite eld, by eliminating redundant items and
1561
TABLE I
XOR GATES COMPLEXITY IN DIFFERENT PRIMITIVE POLYNOMIALS
GF(2
5
) GF(2
8
) GF(2
10
)
prime 37 47 351 451 1153 2041
(m + 1)-Tuple 100101 101111 101011111 111000011 10010011111 11111111001
Weight 3 5 7 5 7 9
Area of CM
1
1 3.5 5.5 3 1 7.5
Area of CM
(2
m
2)
1 3.5 5.5 3 1 7.5
Mean area of all CM 6.8 6.1 17.4 17.8 27.9 27.3
Variance(normalization) 4.4 1 1 2.03 2.23 1
TABLE II
RESULTS IN ALGORITHM A STEP 2
d g
0
g
1
g
2
g
3
g
4
l
7
3

16

30

0
2
8
7

19

0
1
12
23

10

0
1
14
0

14

0
0
intermediate variables, we have the following simple results:

4
=
0
;

3
=
4
;

2
=
3
;

1
=
2

0
;

0
=
1
; (5)
Power of CMs over GF(2
5
) and GF(2
6
) are shown in Fig.
3, with their primes to be 37 and 67 respectively (In brief,
p(x) = x
5
+ x
2
+ 1 also can be considered as a prime 37).
The corresponding power of CMs for a symmetric encoder
with t = 2 are marked in Fig. 3. Even the number of CMs in
symmetric encoder is t, much less than that of an asymmetric
counterpart, the former do not have the lowest power in
the 2
m
1 CMs. Hence there can be other possibilities in
asymmetric encoders that lead to more low-power.
B. Primitive Polynomial
Table I shows the effect of primitive polynomials on the
CMs over GF(2
5
), GF(2
8
) and GF(2
10
). Each AND gate
requires 3/4 the area of an XOR. The area consumptions to be
equivalent XOR gate complexities are listed [8]. Obviously, the
hardware requirements in
1
,
2
m
2
R are much less than
the mean area of all the multipliers. What should be noticed
is that the CMs with high-weighted p(x) have less means
and variances over the whole elds while the low-weighted
lead the CMs in R to reduce circuit complexity and power
consumption more effectively. That is because higher weights
of primitive polynomials tend to increase the complexity
of the expression between input and output. Nevertheless,
more intermediate computation items have opportunities to be
reused so that the circuit complexity and power consumption
decline. The expressions about CMs in R are just simple
without much intermediates, so the low-weighted primitive
polynomials are better.
C. Generator Polynomial
At the last of Section III-A, we present that the symmetric
encoder is usually considered to be the most energy-efcient
but there will be other possibilities in asymmetric encoders that
478
591
981
596
762
1325
811
1083
2030
462
602
1000
559
789
1378
801
1145
2199
0
500
1000
1500
2000
2500
t=2 t=3 t=6 t=2 t=3 t=6 t=2 t=3 t=6
GF(2^5) pri me=37 GF(2^6) pri me=67 GF(2^8) pri me=451
power of symmetric coefficients encoder the lowest power of rest asymmetric encoders
/ W P
Fig. 4. The power consumption of RS encoders over different GF(2
m
)
lead to even lower power. The basic idea for the low power
design of RS encoders is that the encoder includes multipliers
in R

{
0
} as many as possible. A way to nd the proper d
is shown in algorithm A.
Algorithm A: Search for generator polynomials
Input: g(x) = (x +
d
)(x +
d+1
) . . . (x +
d+2t1
),
d {0, 1, 2, . . . 2
m
2}, l = 0, v = 0, S =
Step 1: for i = 0 to 2t 1
begin
for j = 0 to 2
m
2
if (g
i
(d
j
) mod
2
m
1
=
0
and d
j
/ S)
v = v + 1, d
v
= d
j
;
end
S = {d
1
, d
2
, . . . , d
v
};
Step 2: for = 1 to v
begin
g(x) = (x+
d
)(x+
d+1
) . . . (x+
d+2t1
);
for = 0 to 2t 1
if g

R l = l + 1;
d

= argmax
l
(d);
end
Output: d

In order to describe clearly, we take an example here. When

p(x) = x
5
+x
2
+1, t = 2 , for Step 1, (1) can be modied as
g(x) = (x +
d
)(x +
d+1
)(x +
d+2
)(x +
d+3
)
= g
0
+ g
1
x
1
+ g
2
x
2
+ g
3
x
3
+ x
4
(6)
Making g
i
=
0
in turn and solving the equations to obtain d,
g
0
=
4d+6
mod
2
m
1
=
0
g
1
=
3d+3
(1 + )
3
mod
2
m
1
=
3d+3
(
18
)
3
=
0
g
2
=
2d+1
(1 + )
2
(1 + +
2
) mod
2
m
1
=
2d+1
(
18
)
2
(
11
) =
0
g
3
=
d
(1 + )
3
mod
2
m
1
=
d
(
18
)
3
=
0
(7)
According to (7), we achieve the solution set S = {7, 8, 12,
14}. Table II shows the results in Step 2. Consequently we
can get the nal result d = 7.
1562
/ W P
462 476
981 999 993
811
2031 2030
0
500
1000
1500
2000
2500
prime = 37 prime = 47 prime = 37 prime = 47 prime = 351prime = 451prime = 351prime = 451
t=2 t=6 t=2 t=6
GF(2^5) GF(2^8)
Fig. 5. The power consumption of RS encoders with different p(x)
IV. SIMULATION RESULTS
To further exploit low power design of RS encoders, the
encoders on GF(2
5
), GF(2
6
) and GF(2
8
) are implemented.
All the encoders are modeled by Verilog HDL and synthesized
based on Smic 0.18m CMOS process with Synopsys Design
Compiler. The power consumption is estimated with Synopsys
Prime Time PX.
Fig. 4 shows the simulation results of the power consump-
tion in the cases of symmetric encoders and the minimum
ones in asymmetric encoders. The RS codes considered are
GF(2
5
), GF(2
6
) and GF(2
8
), with t = 2, 3, 6 over each
nite led. When d = 2
m1
t and t = 2, the symmetric RS
encoder as shown in Fig. 2 has the lowest power consumption.
But when t = 2, there exists at least one asymmetric encoder
which has lower power consumption than the symmetric.
Therefore, for most of the cases, we can set d = 2
m1
t, in
another word, the symmetric encoder to achieve a better power
performance directly. When t is quiet small, a proper generator
polynomial can be found with algorithm A to achieve an
encoder with the lowest power consumption. Table. III shows
the coefcients of g(x) of RS encoders with the lowest power
consumption when t = 2. d
min
denotes as the parameter
picked by proposed algorithm to lead the encoder power
consumption lowest. It is showed by these three d
min
rows
that most of coefcients of g(x) belong to R.
When t is large, the number of CMs of an RS encoder is
also large. Along with the code rate increasing, which means
t gets small, the impact of each CM on the encoder becomes
more signicant. This might be the reason that only when t is
small, there may exist asymmetric encoders whose power is
lower. For example, when p(x) = x
5
+x
2
+1, approximately
ten out of the 31 CMs have low power consumption. The
corresponding multipliers has been marked on curves in Fig. 3
with symmetric coefcients of g(x) and they do not belong to
R. When t = 2, it is possible that the power consumption of
the asymmetric encoder with low power multipliers is lower
than that of the symmetric one.
Simulation results in Fig. 5 show primitive polynomials
impact on the encoding power. Low-weighted primitive poly-
nomial should facilitate low circuits complexity of CMs in
R and more energy-effective. Along with t increasing, this
inuence declines.
Table III lists the comparison results of hardware require-
ments with different generator polynomials for RS codes.
TABLE III
COMPARISON OF HARDWARE REQUIREMENTS FOR DIFFERENT CODES
g(x) number of total CMs gates
(31, 27) dsym=14
6

14
7+13=20 XOR
prime = 37 d
min
=7
3

16
,
30
3+8+1=12 XOR
dgen=1
10

29

19

24
10+2+8+12=32 XOR
(63, 59) dsym=30
48

36
13+17=30 XOR
prime = 67 d
min
=14
62

32
1+4+9=14 XOR
dgen=1
10

24

41

19
7+10+17+16=50 XOR
(255, 251) dsym=126
87

208
24+28=52 XOR
prime = 451 d
min
=97
139

150

58
24+16+12=52 XOR
dgen=1
10

222

213

217
33+26+26+23=108 XOR
Considering that the only difference among these circuits
constitution is the CM, the comparison of CM can be enough
to represent the point. Moreover the important performances
of encoder circuits, such as the throughput, latency etc. are
not deteriorated. Without loss of generality, the roots of a
generator polynomial are expressed with
1
,
2
, . . . ,
nk
,
and we denote d
gen
= 1. Additionally, d
sym
= 2
m1
t is
regarded as the parameters that can make g(x) symmetrical.
We have already known the exact number of XOR gates of
each CM over different nite elds. Therefore, by comparing
the number of XOR gates of total CMs involved in each
encoder, the hardware requirement with beginning root d
min
is no more than that of its counterpart d
sym
, even though
the latter has more CMs than the former. Furthermore, the
common parameter d
gen
= 1 may lead to more extra hardware
requirements. These prove that the proposed algorithm is an
effective way to nd the parameters of encoder with the lowest
power consumption.
V. CONCLUSION
In this paper, we analyze the low power design of RS
encoders. All factors such as multipliers, primitive polynomial
and generator polynomial are discussed in details. Simulation
results show that in the case of t = 2, there exists g(x)
with asymmetric coefcients which makes the encoder power
consumption lower than the symmetric encoders. And low-
weighted primitive polynomials are better. While t > 2,
the symmetric encoders have better power performance. In
addition, a method to nd the proper generator and primitive
polynomial quickly is also proposed.
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