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Design Rules

This document discusses design rules for CMOS fabrication. It explains that design rules provide guidelines for translating circuit concepts into silicon geometries and constructing fabrication masks. The document compares scalable lambda rules and micron rules for specifying design rules. It outlines design rule entities like layers, and intra-layer and inter-layer constraints. Examples of CMOS process layers and a single transistor layout using typical design rules are shown.

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127 views

Design Rules

This document discusses design rules for CMOS fabrication. It explains that design rules provide guidelines for translating circuit concepts into silicon geometries and constructing fabrication masks. The document compares scalable lambda rules and micron rules for specifying design rules. It outlines design rule entities like layers, and intra-layer and inter-layer constraints. Examples of CMOS process layers and a single transistor layout using typical design rules are shown.

Uploaded by

sivapothi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Inel

Inel
-
-
6080
6080
VLSI Systems Design
VLSI Systems Design
Design Rules for CMOS
Design Rules for CMOS
Lecture 7
Electrical and Computer Engineering Department
University of Puerto Rico at Mayagez
Fall 2008
Design Rules
Allow for a ready translation of a circuit concept
into an actual geometry in silicon
Provide a set of guidelines for constructing the
fabrication masks
Minimum line width
Minimum spacing between objects
Multiple design rule specification methods exist
Scalable Design Rules (Lambda rules)
Micron Rules
DESIGN RULES AND LAYOUT
Specifying Design Rules
Lambda Rules:
Expressed in terms of a scaling parameter: Lambda ()
Minimum line width: 2
Main disadvantages:
Limited linear scaling
Too conservative
Micron Rules
Express designs in absolute dimensions
Pro: Allow taking full advantage of technology
Con: Scaling and Porting becomes more complicated
DESIGN RULES AND LAYOUT
Design Rule Entities
1. Layer Representations
Substrates and/or Wells
Diffusion Regions (Active areas)
Select regions: For contacts to substrate or well
Polysilicon Layers
Metal Interconnects
Contact: Metal to active
Via: Metal to metal
2. Intralayer Constraints
3. Interlayer Constraints
DESIGN RULES AND LAYOUT
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+)
Green
DESIGN RULES AND LAYOUT
Layers in 0.25m CMOS Process
DESIGN RULES AND LAYOUT
Intra-Layer Design Rules
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
DESIGN RULES AND LAYOUT
Single Transistor Layout
1
2
5
3
T
r
a
n
s
i
s
t
o
r
DESIGN RULES AND LAYOUT
Vias and Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
DESIGN RULES AND LAYOUT
Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5
DESIGN RULES AND LAYOUT
CMOS Inverter Layout
A A
n
p-substrate Field
Oxide
p
+
n
+
In
Out
GND V
DD
(a) Layout
(b) Cross-Section along A-A
A
A
V
DD
V
in
M1
M2
V
out
DESIGN RULES AND LAYOUT
Layout Editor
DESIGN RULES AND LAYOUT
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um
DESIGN RULES AND LAYOUT
Stick Diagrams
Dimensionless layout
entities
Only topology is
important
Final layout generated
by compaction
program (if available)
1
3
In
Out
V
DD
GND
Stick diagram of an inverter

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