SEMICON Solutions

IP Design Manual
Created: Duong Dang
Date: 10/03/09
Content
Design Procedure
Verification Plan Procedure
Implementation Process
Content
Design Procedure
Verification Plan Procedure
Implementation Process
Design Procedure
Basic Policies
Create the development plan
Design function specification
Design module detail
Basic Policies
The design procedure is recommened when
IP is designed
Design according to this procedure
However, this procedure deviates according
to the planning of development and
requirement for design module.
In this case, new procedure must be clear
and output items and the quality equal with
the procedure showed here
Create development plan
Do this when IP is developed and designed
Development policy
(synchonous design, new or reuse RTL, design rule)
Input
Create development plan
Do this when IP is developed and designed
Development policy
(synchonous design, new or reuse RTL, design rule)
Creating the development plan document
(Enumerate the deliverables)
Input
Action
Create development plan
Do this when IP is developed and designed
Development policy
(synchonous design, new or reuse RTL, design rule)
Creating the development plan document
(Enumerate the deliverables)
Development Plan Document
(It contains the schedule and assiged tool version, etc)
Input
Action
Output
Create development plan
Do this when IP is developed and designed
Development policy
(synchonous design, new or reuse RTL, design rule)
Creating the development plan document
(Enumerate the deliverables)
Development Plan Document
(It contains the schedule and assiged tool version, etc)
Development Plan Design Review
Input
Action
Output
Create development plan
Do this when IP is developed and designed
Development policy
(synchonous design, new or reuse RTL, design rule)
Creating the development plan document
(Enumerate the deliverables)
Development Plan Document
(It contains the schedule and assiged tool version, etc)
Development Plan Design Review
Input
Action
Output
Design the function spec
Function specification design defines
functions and operations of desiged module
clearly
Function spec must be neither lack or
contradiction
Description should be easy to understand
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Input
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Extract to functions
Extract to modes
Input Action
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Extract to functions
Extract to modes
Functions and mode
Information
- Enumerated operations
- The modes
Input Action
Output
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Extract to functions
Extract to modes
Define Plan I/O
Functions and mode
Information
- Enumerated operations
- The modes
Input Action
Output
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Extract to functions
Extract to modes
Define Plan I/O
Functions and mode
Information
- Enumerated operations
- The modes
Table of I/O
Input Action
Output
Design the function spec
Requirement Spec
- Function items
- Development type
+ All New
+ Reuse RTL
Extract to functions
Extract to modes
Define Plan I/O
Functions and mode
Information
- Enumerated operations
- The modes
Table of I/O
Input Action
Output
Output to step 2
Only the I/O written in the function spec
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Register table
(address map, bit allocation)
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Register table
(address map, bit allocation)
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Register table
(address map, bit allocation)
Functional block diagram
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Register table
(address map, bit allocation)
Functional block diagram
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Decide I/O of module
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Decide I/O of module
Interface Specification
(decision of module entity)
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Decide I/O of module
Interface Specification
(decision of module entity)
Design the function spec
Function
and modes
information
(containing
enumerated
operation
and modes)
Bus I/F Spec
I/O Table
Define the functions
of interface register
Create a functional
block diagram
(detailed block diagram)
Create a functional
timing chart
(all functions and items)
Create an abnormal
operation timing chart
Create a Function Spec
Register table
(address map, bit allocation)
Functional block diagram
Functional timing chart
Function Specification
Decide I/O of module
Interface Specification
(decision of module entity)
DR
here
Create Design Details
The module is designed detail in this process
A detailed design is a process of deciding how to
realize the function and the operation that became
clearly in the process of the function specification
design
Show how to realize the function by using the block
diagram and the timing chart
Clarifying that there are neither contradiction nor
considered shortage of logic
Descryption should be easy to understand
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Input
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Input Action
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
- Function and modes information
- Table of registers
- Block diagram
- Timing chart
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
- Function and modes information
- Table of registers
- Block diagram
- Timing chart
Divide module block in the role
- Second level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
- Function and modes information
- Table of registers
- Block diagram
- Timing chart
Divide module block in the role
- Second level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (2
nd
level)
(Decide the block name
and role of each block)
Create Design Details
- Function and modes Information
(contain enumerated operation
and the modes)
- Table of registers
Divide module block in the role
- First level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (1
st
level)
(Decide the block name
and role of each block)
Block Diagram
(1
st
level)
Decide I/O of each block
Block diagram
(Connection between blocks
or connection table)
Create interface timing chart
between each block
Timing chart
(Detailed timing chart
between each block)
Input Action Output
- Function and modes information
- Table of registers
- Block diagram
- Timing chart
Divide module block in the role
- Second level of hierarchy
- Decide the role of each block
- Decide the mode of each block
Block diagram (2
nd
level)
(Decide the block name
and role of each block)
Next step
Create Design Details
Block Diagram
(2
nd
level)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Create the hierarchy structure
diagram
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Create the hierarchy structure
diagram
Hierarchy structure
diagram
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Create the hierarchy structure
diagram
Hierarchy structure
diagram
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
-All documents (block diagram,
Timing chart, hierarchy structure)
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Create the hierarchy structure
diagram
Hierarchy structure
diagram
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
-All documents (block diagram,
Timing chart, hierarchy structure)
Create Design Details document
Create Design Details
Block Diagram
(2
nd
level)
Decide I/O of each block
(3
rd
level)
Block diagram (2
nd
level)
(Connection between blocks
or connection table)
Create interface timing chart
between each block (3
rd
level)
Timing chart
(Detailed timing chart
between each block)
- Block diagram of all hierarchies
Create the hierarchy structure
diagram
Hierarchy structure
diagram
Repeat to submodules
- Divide block to functional block such as counter
- Unit of hierarchichal divisions is not so details, easy to understand in the outsider
- The hierarchy structure is not sometimes the same as RTL structure
Ex: the counter is written by always sentence
-All documents (block diagram,
Timing chart, hierarchy structure)
Create Design Details document Design Detail Document
DR
Content
Design Procedure
Verification Plan Procedure
Implementation Process
Create Verification Plan
Function Spec
Interface Spec
Design Details
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
All verification items
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Conflict Matrix
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Conflict Matrix
Conflict Matrix
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Conflict Matrix
Conflict Matrix
Create the verification item
From conflict matrix
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Conflict Matrix
Conflict Matrix
Create the verification item
From conflict matrix
Verification Checklist
From Conflict matrix
(UT: Unit Test)
Create Verification Plan
Function Spec
Interface Spec
Design Details
Enumerate all the
verification matrix
All verification items
Create conflict matrix
All verification items
Classify the verification
items
- Create Deskchecklist
- Create Verification checklist
(There is an items written in
both checklists)
Desk Checklist
(DT: Desk Test)
Verification Checklist
(UT: Unit Test)
Conflict Matrix
Conflict Matrix
Create the verification item
From conflict matrix
Verification Checklist
From Conflict matrix
(UT: Unit Test)
Comparation step
Create Verification Plan
Whole image of verification plan is understood by
planning the function verification plan
Verification methodology and verification schedule
can be estimated
Enumerate all verification items to understand whole
image of the function verification accurately
Classify the verification items based on the
structure, the function of mode, etc.
Finally, Judge covering verification item by yourself
However, should be easy to explain the criteria to
the outsider
Create Verification Plan
Function Spec
Interface Spec
Design Details
Create Verification Plan
Desk Checklist
Function Spec
Interface Spec
Design Details
Verification Checklist
Verification Checklist
From Conflict Matrix
Create Verification Plan
Desk Checklist
Function Spec
Interface Spec
Design Details
Verification Checklist
Verification Checklist
From Conflict Matrix
Compare specifications
between Items of checklist
(Paint the item and the spec
that coresponds with a maker
pen)
Create Verification Plan
Desk Checklist
Function Spec
Interface Spec
Design Details
Verification Checklist
Verification Checklist
From Conflict Matrix
Compare specifications
between Items of checklist
(Paint the item and the spec
that coresponds with a maker
pen)
Verification Plan Design Review (DR)
View of enumerating
verification items
Normal function
Extract the verification item from the function specification
Extract the verification item from CPU interface register
Extract the verification item from the modes
Combination of normal function
Extract the verification item that combines the above mentioned
normal function
Continous operation
Continuous operation (R -> W -> R) or (R -> R -> R)
White box verification item
Verification item seen from operation boundary condition
Verification item seen from conflict condition
Verifcation item seen from abnormal operation
View of Creating Conflict
Matrix
E xtract the states (ST)
Combination of values set to control FF = State (Dynamic state)
Operatinal mode (Static state)
Extract the event (EV)
Input signal and combination of input signals
Assert event and negate event
Transaction event such as writing by CPU
Create the ST & EV matrix
Create the EV & EV matrix
Combination before and behind time of event A and event B
Event A and event B occur same time
* There are important meanings in looking each cell and the
explanation enough of a completed matrix
View of Classifying
Verification Item
Items descibed to Desk Checklist
Descibe all function specification
Confirm whether all items described in the function specification
are written in RTL code
Combination of all the thinking fuctions must be confirmed by desk
check (Some items are selected and verified by simulation)
Difficult items must be confirmed by simulation
Items descibed to Verification Checklist
Items selected from all verification items (Narrow it to a specific
condition because it becomes huge in all verification item)
Selection method: The item(including explanation) written in the
function spec is not enumerated without fail
(When verification items become huge, the role of desk check
should be reviewed)
Describe forgetting neither the test mode nor the concealment
function (It is item that is sure to be described in Design Details)
Content
Design Procedure
Verification Plan Procedure
Implementation Process
Process
RTL Coding
Process
RTL Coding
TMs Creating
Process
RTL Coding
TMs Creating
Verification by simulation
Process
RTL Coding
TMs Creating
Verification by simulation
RTL Coverage
Process
RTL Coding
TMs Creating
Verification by simulation
RTL Coverage
Synthesis and
formal verification
Process
RTL Coding
TMs Creating
Verification by simulation
RTL Coverage
Synthesis and
formal verification
Checking of Netlist
Process
RTL Coding
TMs Creating
Verification by simulation
RTL Coverage
Synthesis and
formal verification
Checking of Netlist
DFT
Work Purpose
Understand Why do you do? clearly
Do not misunderstand each work as the
purpose
Clarify the output of each work for the
understanding of correct purpose
Clarify the quality demanded by the output
Outputs
The output of each work should be a demanded
quality
Consult the project leader when the output is not
demanded quality by some reasons
Report the work result bt the report documents,
described result explicity when the output is a
demanded quality
Report on reason anf the background when it is not
a demand for quality
The format of the report is according to it when there
is united format
Q & A