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Ec 1201digital Electronics: 91-9444067484 (Cellphone)

Unit32

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Subathra Devi Mourougane
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35 views30 pages

Ec 1201digital Electronics: 91-9444067484 (Cellphone)

Unit32

Uploaded by

Subathra Devi Mourougane
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EC 1201DIGITAL ELECTRONICS

A. Jawahar,
Assistant Professor, ECE Dept.
SSN College of Engineering
Phone: 044 320!"" 2#" $E%tn : 3"&
'(4440)#4!4 $*ellphone&
E+ail: ,awahara-ssn.e./.in

01er1ie
w
2
3at*hes respon. to trigger le1els on *ontrol inp/ts

E%a+ple: 4f 5 6 ', inp/t refle*te. at o/tp/t


2
Diffi*/lt to pre*isel7 ti+e when to store .ata with lat*hes
2
8lip flips store .ata on a rising or falling trigger e.ge.

E%a+ple: *ontrol inp/t transitions fro+ 0 (9 ', .ata inp/t appears at


o/tp/t

Data re+ains sta:le in the flip flop /ntil /ntil ne%t rising e.ge.
2
Different t7pes of flip flops ser1e .ifferent f/n*tions
2
8lip flops *an :e .efine. with *hara*teristi* f/n*tions.

D 3at*h
;
;<
C
D
S
R
S
R
S R C Q Q
0 0 1 Q
0
Q
0


Store
0 1 1 0 1 Reset
1 0 1 1 0 Set
1 1 1 1 1 Disallowed
X X 0 Q
0
Q
0


Store
0 1 0 1
1 1 1 0
X 0 Q
0
Q
0


D C Q Q
2 =hen C is high, D passes fro+ inp/t to o/tp/t $;&

Clo*>ing E1ent
Lo-Hi Lo-Hi edge Hi-Lo Hi-Lo edge
2
=hat if the o/tp/t onl7 *hange. on a C transition?
C
D ;
;<
0 0 1
1 1 0
X 0 Q
0
Q
0


D C Q Q
Positive edge triggered

?aster(Sla1e D 8lip 8lop
2
Consi.er two lat*hes *o+:ine. together
2
0nl7 one C 1al/e a*ti1e at a ti+e
2
0/tp/t *hanges on falling e.ge of the *lo*>

D 8lip(8lop
D gets latched to Q on the rising edge of the clock.
2
Stores a 1al/e on the positi1e e.ge of C
2
4np/t *hanges at other ti+es ha1e no effe*t on o/tp/t
C
D ;
;<
0 0 1
1 1 0
X 0 Q
0
Q
0


D C Q Q
Positive edge triggered

Clo*>e. D 8lip(8lop
2
Stores a 1al/e on the positi1e e.ge of C
2
4np/t *hanges at other ti+es ha1e no effe*t on o/tp/t

Positi1e an. Negati1e E.ge D 8lip(8lop
2
D flops *an :e triggere. on positi1e or negati1e e.ge
2
@/::le :efore Clock (C) inp/t in.i*ates negati1e e.ge trigger
Lo-Hi Lo-Hi edge
Hi-Lo Hi-Lo edge

Positive Edge-Triggered J-K Flip-Flop
0 0

Q
0
Q
0

0 1

0 1
1 0

1 0
1 1


A0553E

; J ;<
C3B
B C
Created from D flop
C
J et
C
! reet
C
J"!"1 -# i$%ert o&tp&t

Clo*>e. J(B 8lip 8lop
2
Awo .ata inp/ts, J an. B
2
J (9 set, B (9 reset, if J6B6' then toggle o/tp/t
C'ara(teriti( Ta)le

Positive Edge-Triggered T Flip-Flop
0

Q
0
Q
0

1


A0553E

; ;<
C
A
C
Created from D flop
C
T"0 -# *eep (&rre$t
C
! reet
C
T"1 -# i$%ert (&rre$t

As7n*hrono/s
4np/ts
J, K are synchronous inputs
o Effects on the output are synchronized with the !K input.

Asynchronous inputs operate independently of the synchronous


inputs and clock
o "et the ## to $%& states at any ti'e.

As7n*hrono/s 4np/ts

As7n*hrono/s 4np/ts
(ote reset signal )*+ for
D flip flop
,f * - &, the output Q is
cleared
.his event can occur at
any ti'e, regardless of the
value of the !K

Parallel Data Aransfer
2
8lip flops store o/tp/ts fro+ *o+:inational logi*
2
?/ltiple flops *an store a *olle*tion of .ata

S/++ar
7
2
8lip flops are powerf/l storage ele+ents

Ahe7 *an :e *onstr/*te. fro+ gates an. lat*hesD


2
D flip flop is si+plest an. +ost wi.el7 /se.
2
As7n*hrono/s inp/ts allow for *learing an. presetting the flip flop
o/tp/t
2
?/ltiple flops allow for .ata storage

Ahe :asis of *o+p/ter +e+or7D


2
Co+:ine storage an. logi* to +a>e a *o+p/tation *ir*/it
2
Ne%t ti+e: Anal7Eing seF/ential *ir*/its.

SeF/ential Cir*/its
Combinational
circuit
Flip
Flops
Outputs
Inputs
Next
state
resent
state
!imin" si"nal
#cloc$%
Clo(*
Clo(*
a periodi( e+ter$al e%e$t ,i$p&t-
s7n*hroniEes when */rrent state *hanges happen
>eeps s7ste+ well(:eha1e.
+a>es it easier to .esign an. :/il. large s7ste+s

Cross(*o/ple. 4n1erters
0
'
'
0
State &
State '
2
A sta:le 1al/e *an :e store. at in1erter
o/tp/ts

S(G 3at*h with
N0Gs
1 1
1 0
0 1
0 0
S R Q Q
0 1
1 0 Set
1 0
Stable
0 1 Reset
0 0 Undefined
R ,reet-
.
.
S ,et-
2
S(G lat*h +a.e fro+ *ross(*o/ple. N0Gs
2
4f ; 6 ', set state
2
4f ; 6 0, reset state
2
Hs/all7 S60 an. G60
2
S6' an. G6' generates /npre.i*ta:le res/lts

S(G 3at*h with
NANDs
S
G
;
;<
0 0
0 1
1 0
1 1
S R Q Q
0 1
1 0 Set
1 0
Store
0 1 Reset
1 1 Disallowed
2
3at*h +a.e fro+ *ross(*o/ple. NANDs
2
So+eti+es *alle. S<(G< lat*h
2
Hs/all7 S6' an. G6'
2
S60 an. G60 generates /npre.i*ta:le
res/lts

"/* !atches

S(G 3at*h with *ontrol
inp/t
2
0**asionall7, .esira:le to a1oi. lat*h *hanges
2
C 6 0 .isa:les all lat*h state *hanges
2
Control signal ena:les .ata *hange when C 6 '
2
Gight si.e of *ir*/it sa+e as or.inar7 S(G lat*h.

Lat(' operatio$ Lat(' operatio$
e$a)led )/ e$a)led )/
C C

I$p&t ampli$g
e$a)led )/ gate
N0G S(G 3at*h with Control 4np/t
R0
S0
.0
.
C0
O&tp&t ('a$ge 1'e$ C i O&tp&t ('a$ge 1'e$ C i
lo12 lo12
RESET a$d SET RESET a$d SET
Ot'er1ie2 HOLD Ot'er1ie2 HOLD
Lat(' i Lat(' i le%el-e$iti%e le%el-e$iti%e3 i$ regard to C 3 i$ regard to C
O$l/ tore data if C0 " 0

D 3at*h
;
;<
C
D
S
R
(
)
( ) C Q Q
0 0 1 Q
0
Q
0


Store
0 1 1 0 1 Reset
1 0 1 1 0 Set
1 1 1 1 1 Disallowed
X X 0 Q
0
Q
0


Store
0 1 0 1
1 1 1 0
X 0 Q
0
Q
0


D C Q Q
2 ;
0
in.i*ates the pre1io/s state $the pre1io/sl7 store.
1al/e&

D 3at*h
;
;<
C
D
S
R
(
)
0 1 0 1
1 1 1 0
X 0 Q
0
Q
0


D C Q Q
2 4np/t 1al/e D is passe. to o/tp/t ; when C is high
2
4np/t 1al/e D is ignore. when C is low

D 3at*h
E
x
*atc+es on ,ollowin"
ed"e o, cloc$
E
D
;
C
x
-
-
2
I onl7 *hanges when E is high
2
4f E is high, I will follow J

D 3at*h
E
x
*atc+es on ,ollowin"
ed"e o, cloc$
E
D
;
C
x
-
-
2
Ahe D lat*h stores .ata in.efinitel7, regar.less of inp/t D 1al/es, if
C 6 0
2
8or+s :asi* storage ele+ent in *o+p/ters

S7+:ols for
3at*hes
2
SG lat*h is :ase. on N0G gates
2
S<G< lat*h :ase. on NAND gates
2
D lat*h *an :e :ase. on either.
2
D lat*h so+eti+es *alle. transparent lat*h

S/++ar7
2
3at*hes are :ase. on *o+:inational gates $e.g. NAND, N0G&
2
3at*hes store .ata e1en after .ata inp/t has :een re+o1e.
2
S(G lat*hes operate li>e *ross(*o/ple. in1erters with *ontrol inp/ts $S 6
set, G 6 reset&
2
=ith a..itional gates, an S(G lat*h *an :e *on1erte. to a D lat*h $D
stan.s for .ata&
2
D lat*h is si+ple to /n.erstan. *on*ept/all7

=hen C 6 ', .ata inp/t D store. in lat*h an. o/tp/t as ;

=hen C 6 0, .ata inp/t D ignore. an. pre1io/s lat*h 1al/e o/tp/t


at ;
2
Ne%t ti+e: +ore storage ele+entsD

Any Queries ?
Please Contact jawahara
@ssn.edu.in
Thank You

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