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Department of Computer Science & Engineering Question Bank Subject: DLD Faculty: P.Siva Ram Prasad Branch: II CSE I Sem Unit - I

This document contains a question bank for a digital systems course covering topics in binary, Boolean algebra, combinational logic, sequential circuits, and programmable logic devices. It includes over 100 questions on topics such as binary addition and subtraction, Boolean simplification, logic gate implementation of functions, flip-flop based design of registers, counters, and sequential circuits. It also covers programmable devices like PLDs and FPGAs, memory systems, and hazards in digital design.

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Harold Wilson
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0% found this document useful (0 votes)
31 views3 pages

Department of Computer Science & Engineering Question Bank Subject: DLD Faculty: P.Siva Ram Prasad Branch: II CSE I Sem Unit - I

This document contains a question bank for a digital systems course covering topics in binary, Boolean algebra, combinational logic, sequential circuits, and programmable logic devices. It includes over 100 questions on topics such as binary addition and subtraction, Boolean simplification, logic gate implementation of functions, flip-flop based design of registers, counters, and sequential circuits. It also covers programmable devices like PLDs and FPGAs, memory systems, and hazards in digital design.

Uploaded by

Harold Wilson
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Computer Science & Engineering

QUESTION BANK
Subject: DD !acu"t#: $%Si&a 'am $ra(a)
Branc*: II CSE I Sem
UNIT + I
1. Convert the following number with indicated bases to decimal [42=8]
i) 1 ! 1 1 1 1)2 = ii. " # $)1% = iii. 2 # &)8 = iv. 4 #)' =
2. (btain the 1)s and 2)s com*lements of the following binar+ numbers [42=8]
i. 1 1 1 ! 1 ! 1 ! = ii. ! 1 1 1 1 1 1 ! = iii. 1 ! ! ! ! ! ! ! = iv. ! ! ! ! ! ! ! ! =
#. Convert the following numbers. [4=8] i. '#)1! = )2 ii. 2#1)4 = )1! iii. 1 1 ! 1 1 ! 1)2 = )8
iv. 4,.'%)1% = )2
4. "dd and subtract in binar+ [4=8] i. 1 1 1 1 and 1 ! 1 ! ii. 1 1 ! 1 1 ! and 1 1 1 ! 1 iii. 1 ! ! 1 ! ! and 1 !
1 1 ! iv. 1 1 ! 1 ! ! 1 and 1 1 ! 1 1
'. -erform the following binar+ multi*lication o*erations i. 1!!!1! !!1!1! = ii. !!11!! !11!!1 = iii.
!!!1!! !1!1!1 =
%. .rite the one)s and two)s com*lements of the following e/am*le. i. !!11!!1 ii. 111!!11 iii. 111111
&. 0ind the decimal e1uivalent of the following two)s com*lement numbers. i. 11111 ii. 1!!!1
iii. !1!1! iv. 1!!11 v. 1!1!1
8. 2/*lain about error ,etecting code with e/am*le.
UNIT + II
1. 3im*lif+ each of the following e/*ressions i. "$C, 4 "$C, 4 C, ii. " 4 $) " 4 $ 4 ,) $ 4 C 4 ,)
2. 2/*lain about *ositive and 5egative logic in binar+ signals.
#. 3tate and e/*lain the ,ualit+ *rinci*le with e/am*le.
4. 6iven the $oolean function 0 = /+7 4 /+7 4 w/+ 4 w/+ 4 w/+ i. (btain the truth table of the function ii.
,raw the logic diagram using the original $oolean e/*ression iii. 3im*lif+ the function to a minimum number
of literals using $ooleanalgebra.
'. 8m*lement the following $oolean function using "5,9 (: and inverter gates. 0 = /+ 4 / + 4 + 7.
%. ;sing the rules of boolean algebra9 sim*lif+ the e/*ressions that follow to the fewest total number of literals i. f
= "$ 4 "$C 4 "C, ii. f = $ 4 ",4$C 4 [$4"C4,)]1
&. 3im*lif+ the following $oolean e/*ression to a minimum number of literals.
i. 0 = $ C 4 " ,) " $ 4 C ,) ii. 0 = .<= 4 >< 4 > = 4 <=
8. 2/*ress the following function in sum of minterms and *roduct of ma/terms.0"9 $9 C9 ,) = $ , 4 " , 4 $,
UNIT + III
1. 8m*lement the following $oolean function with 5"5, gates 0 /9+97) = ? 1929#949'9&).
2. 3im*lif+ the following $oolean function using four@variable ma*. 0 w9 /9 +9 7) = ? 19 #9 &9 119 1') 4 d!9 29 ').
#. 0ind all the *rime im*licatiants for the following $oolean functions and determine which are essential.
0"9$9C9,) = ?!9 29 #9 '9 &9 89 1!9 119 149 1')
4. a) 3um of *roduct and b) -roduct of sum e/*ressions for the function given below 0 "9 $ 9C 9 ,) = ?!9 19 29
'9 89 A9 1!)
UNIT + I,
1. 8m*lement a $oolean function 0 /9 +9 7)= ? 29 49 %) with a Bulti*le/er.
2. 2/*lain about Cri @ 3tate gates in digital s+stems.
#. .hat is meant b+ encoderD
4. ,esign a 4 @ in*ut *riorit+ encoder.
'. 2/*lain carr+ *ro*agation in *arallel adder with a neat diagram.
%. .hat is a decoderD Construct a 41% decoder with two #8 decoders.
&. ,esign a code converter that converts $C, to e/cess @ # code.
UNIT - ,
1. ,esign a ,@t+*e *ositive edge triggered fli* flo*."lso show the o*eration of the se1uential circuit when C- = 1.
2. .hat is a fli* flo*.,esign basic fli* flo* circuit with 5"5, gates.
#. ,esign a 4@bit register with *arallel load using , fli* flo*s
4. " se1uential circuit has four fli* flo*s "9 $9 C9 , and an in*ut /. 3tate e1uations are as follows "t41) = C,1 4
C1,)/ 4 C, 4 C1,1)/1
$t41) = "
Ct41) = $
,t41) = C
'. (btain the se1uence of states when /=19 starting from state "$C,=!!!1and when /=!9 starting from state
"$C,=!!!1."lso draw the state diagram.
%. ,esign a clocEed FG fli* flo*.
&. ,efine a latch and a fli* flo*. Bention the similarities and differences between them
8. ,efine the following terms related to fil*@flo*s. set@u* time hold time *ro*agation dela+ *reset and clear.
A. ,istinguish between combinational logic and se1uential logic.
1!. ,raw the circuit diagram of clocEed ,@ fli*@flo* with 5"5, gates and e/*lain its o*eration using truth table.
6ive its timing diagram.
11. " 3e1uential circuit with two , fli*@flo*s " and $9 two in*uts / and + and one out*ut 7 is s*ecified b+ the
following ne/t@state and out*ut e1uation. "t 4 1) = /+ 4 /" 7 = $ $t 4 1) = /$ 4 /"
i),raw the logic diagram of the circuit. ii)Hist the state table for the se1uential circuit. iii),raw the
corres*onding state diagram.
UNIT - ,I
1. .hat is a shift register. ,raw the blocE diagram and timing diagram of a shift register that shows the serial
transfer of information from register " to register $.
2. ,efine a ri**le counter. ,esign a $C, ri**le counter
#. ,esign a counter with the following re*eated binar+ se1uenceI !9 19 29 #9 49' using ,@ fli* flo*s.
4. ,istinguish between s+nchronous and as+nchronous counters.
'. .rite the J,H structural descri*tion of the 4@ bit binar+ counter with *arallel load.
%. ,esign a 4@bit ring counter using ,@ fli* flo*s and draw the circuit diagram and timing diagrams.
&. ,raw and e/*lain 4@bit universal shift register.
8. 2/*lain different t+*es of shift registers.
A. ,esign a 4@bit ring counter using C@ fli* flo*s and draw the circuit diagram and timing diagrams.
1!. ,raw the blocE diagram and e/*lain the o*eration of serial transfer between two shift registers and draw its
timing diagram.
11. ,esign a 4@bit Fohnson counter using C@ fli* flo*s and draw the circuit diagram and timing diagrams
12. ,esign a modulo @# u*Kdown s+nchronous counter using C@ fli* flo*s and draw the circuit diagram.
1#. .rite about the J,H behavioral descri*tion of a 4@bit shift register
UNIT - ,II
1. " combinational circuit is defined b+ the functions
2. 01"9$9C) = L#9 '9 %9 &) 902"9$9C) = L!9 29 49 &) 2/*lain in detail se1uential *rogrammable devices
8m*lement the circuit with a -H" having # in*uts 9 four *roduct terms and two out*uts
#. 2/*lain in detail ha7ards in combinational networEs.
4. 2/*lainI a) 3e1uential *rogrammable devices b) :"B and :(B
'. 6ive the J,H code for a memor+ read9 write o*erations if the memor+ si7e is %4 words of 4 bits each. "lso
e/*lain the code.
%. Cabulate the -H" *rogramming table for the four $oolean functionsI "/9+97) = ? 192949%)
$/9+97) = ? !919%9&)
C/9+97) = ? 29%)
,/9+97) = ? 1929#9'9&)
&. Binimi7e the number of *roduct terms and also show the internal logic in the -H" structure.
8. ,raw and e/*lain the blocE diagram of -"H.
A. 8m*lement the following $oolean functions using -"H. w"9$9C9,) = ? m !929%9&989A91291#) / "9$9C9,)
=?m !929%9&989A91291#914) + "9$9C9,) = ? m 29#989A91!91291#) 7 "9$9C9,) = ? m19#949%9A912914).
1!. 2/*lain the construction of a basic memor+ cell and also e/*lain with diagram the construction of a 4 M 4 :"B
11. 6iven a #2M8 :(B chi* with an enable in*ut9 show the e/ternal connections
12. 2/*lain the blocE diagram of a memor+ unit. 2/*lain the read and write o*eration a :"B can *erform
1#. Hist the -"H *rogramming table and draw the -"H structure for the $C,@toe/cess@#@code converter.
14. 2/*lain about error detection and correction with e/am*le.
UNIT - ,III
1. 2/*lainI a)Ja7ards in combinational networEs.
i. b) J,H for registers and counters
2. 2/*lainI a) race@free state assignment ha7ards. i. b) -H"
#. :educe the number of states in the state table listed below. ;se an im*lication table -resent state 5e/t state
(ut*ut
/=! /=1 /=! /=1
a f b ! !
b d c ! !
c f e ! !
d g a ! !
e d c ! !
f f b 1 1
g g h ! 1
h g a 1 !
4. 6ive the im*lementation *rocedure for a 3: Hatch using 5(: gates.
'. 8m*lement the circuit defined above with a 5(: 3: latch. :e*eat with a 5"5, 3: latch.
%. ,escribe the o*eration of the 3: Hatch using 5"5, gate with the hel* of truth table9 transition table and the
circuit.
&. 2/*lain the o*eration and use of ,e bounce circuit.
8. 2/*lain the difference between as+nchronous and s+nchronous se1uential circuits.
a. ,efine fundamental@mode o*eration.
b. 2/*lain the difference between stable and unstable states.
c. .hat is the difference between an internal state and a total state.
A. 2/*lain critical and non critical races with the hel* of e/am*le
1!. .rite about Ja7ards in se1uential circuits.

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