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So, Ware: Instruc (On Set

The document discusses various trade-offs in designing an instruction set architecture (ISA). It covers the advantages and disadvantages of complex versus simple instructions, as well as placing the ISA closer to hardware or closer to high-level languages. Other trade-offs discussed include instruction length, uniformity of decoding, and classification of ISAs based on the number of memory operands allowed. Common ISA examples like x86, Alpha, and MIPS are also referenced.

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Rohan Jain
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© © All Rights Reserved
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36 views

So, Ware: Instruc (On Set

The document discusses various trade-offs in designing an instruction set architecture (ISA). It covers the advantages and disadvantages of complex versus simple instructions, as well as placing the ISA closer to hardware or closer to high-level languages. Other trade-offs discussed include instruction length, uniformity of decoding, and classification of ISAs based on the number of memory operands allowed. Common ISA examples like x86, Alpha, and MIPS are also referenced.

Uploaded by

Rohan Jain
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CADSL

Instruction Set Architecture


(ISA)
lnsLrucuon seL
soware
hardware
26 Aug 2014 EE-309@IITB 1
CADSL
Complex vs. Slmple lnsLrucuons
- Complex lnsLrucuon: An lnsLrucuon does a loL of work, e.g. many
operauons
- lnserL ln a doubly llnked llsL
- CompuLe ll1
- SLrlng copy
- Slmple lnsLrucuon: An lnsLrucuon does small amounL of work, lL
ls a prlmluve uslng whlch complex operauons can be bullL
- Add
- xC8
- Muluply
2 26 Aug 2014 EE-309@IITB
CADSL
Complex vs. Slmple lnsLrucuons
- AdvanLages of Complex lnsLrucuons
+ uenser encodlng ! smaller code slze ! beuer memory
uullzauon, saves o-chlp bandwldLh,
(beuer packlng of lnsLrucuons)
+ Slmpler compller: no need Lo opumlze small lnsLrucuons as
much

- ulsadvanLages of Complex lnsLrucuons
- Larger chunks of work ! compller has less opporLunlLy Lo
opumlze (llmlLed ln ne-gralned opumlzauons lL can do)
- More complex hardware ! Lranslauon from a hlgh level Lo
conLrol slgnals and opumlzauon needs Lo be done by hardware

3 26 Aug 2014 EE-309@IITB
CADSL
lSA-level 1radeos: Semanuc Cap
- Where Lo place Lhe lSA? Semanuc gap
- Closer Lo hlgh-level language (PLL) ! Small semanuc gap,
complex lnsLrucuons
- Closer Lo hardware conLrol slgnals? ! Large semanuc gap,
slmple lnsLrucuons
- 8lSC vs. ClSC machlnes
- 8lSC: 8educed lnsLrucuon seL compuLer
- ClSC: Complex lnsLrucuon seL compuLer
- ll1, CulCkSC81, CL?, l lnsLrucuons
- vAx lnuLx lnsLrucuon (array access wlLh bounds checklng)
4 26 Aug 2014 EE-309@IITB
CADSL
lSA-level 1radeos: Semanuc Cap
- Slmple compller, complex hardware vs.
complex compller, slmple hardware
- 1ranslauon (lndlrecuon) can change Lhe Lradeo!
- 8urden of backward compaublllLy
- erformance?
- Cpumlzauon opporLunlLy:
- lnsLrucuon slze, code slze
5 26 Aug 2014 EE-309@IITB
CADSL
Memory Address
- lnLerpreung memory address
- 8lg Lndlan
- Llule Lndlan
- lnsLrucuon mlsallgnmenL
- Addresslng mode
26 Aug 2014 EE-309@IITB 6
CADSL
26 Aug 2014 EE-309@IITB 7
Kinds of Addressing Modes
- 8eglsLer dlrecL [8l]
- lmmedlaLe (llLeral) v
- ulrecL (absoluLe) M[v]
- 8eglsLer lndlrecL M[[8l]]
- 8ase+ulsplacemenL M[[8l] + v]
- 8ase+lndex M[[8l] + [8[]]
- Scaled lndex M[[8l] + [8[]*d + v], e.g. d=8
- AuLolncremenL M[[8l]+1]
- AuLodecremenL M[[8l] - 1]
- Memory lndlrecL M[ M[8l] ]
M
R
memory
reg. file
OP Ri Rj v
Addressing Mode value in [ ] is the operand
CADSL
26 Aug 2014 EE-309@IITB 8
varlable formaL, 2- and 3-address lnsLrucuons
VAX-11
OpCode
A/M A/M A/M
Byte 0
1
n m
32-blL word slze, 16 C8 (4 reserved)
- 8lch seL of addresslng modes (apply Lo any operand)
- 8lch seL of operauons
- blL eld, sLack, call, case, loop, sLrlng, poly, sysLem
- 8lch seL of daLa Lypes
- Condluon codes
CADSL
lSA-level 1radeos: lnsLrucuon LengLh
- llxed lengLh: LengLh of all lnsLrucuons Lhe same
+ Lasler Lo decode slngle lnsLrucuon ln hardware
+ Lasler Lo decode muluple lnsLrucuons concurrenLly
-- WasLed blLs ln lnsLrucuons
-- Parder-Lo-exLend lSA (how Lo add new lnsLrucuons?)
- varlable lengLh: LengLh of lnsLrucuons dlerenL (deLermlned by
opcode and sub-opcode)
+ CompacL encodlng
lnLel 432: Puman encodlng (sorL of). 6 Lo 321 blL lnsLrucuons.
-- More loglc Lo decode a slngle lnsLrucuon
-- Parder Lo decode muluple lnsLrucuons concurrenLly
- 1radeos
" Code slze (memory space, bandwldLh, laLency) vs. hardware complexlLy
" lSA exLenslblllLy and expresslveness
" erformance? Smaller code vs. complex decode
9 26 Aug 2014 EE-309@IITB
CADSL
lSA-level 1radeos: unlform uecode
- unlform decode: Same blLs ln each lnsLrucuon correspond Lo Lhe same
meanlng
" Cpcode ls always ln Lhe same locauon
" uluo operand speclers, lmmedlaLe values, .
" Many 8lSC lSAs: Alpha, MlS, SA8C
+ Lasler decode, slmpler hardware
+ Lnables parallellsm: generaLe LargeL address before knowlng Lhe
lnsLrucuon ls a branch
-- 8esLrlcLs lnsLrucuon formaL (fewer lnsLrucuons?) or wasLes space
- non-unlform decode
" e.g., opcode can be Lhe 1sL-7Lh byLe ln x86
+ More compacL and powerful lnsLrucuon formaL
-- More complex decode loglc
10 26 Aug 2014 EE-309@IITB
CADSL
x86 vs. Alpha Instruction Formats
x86:
Alpha:
11 26 Aug 2014 EE-309@IITB
CADSL
MlS lnsLrucuon lormaL
- 8-Lype, 3 reglsLer operands
- l-Lype, 2 reglsLer operands and 16-blL lmmedlaLe operand
- !-Lype, 26-blL lmmedlaLe operand

- Slmple uecodlng
- 4 byLes per lnsLrucuon, regardless of formaL
- musL be 4-byLe allgned (2 lsb of C musL be 2b'00)
- formaL and elds easy Lo exLracL ln hardware
12
8-Lype
0
6-blL
rs
3-blL
rL
3-blL
rd
3-blL
shamL
3-blL
funcL
6-blL
opcode
6-blL
rs
3-blL
rL
3-blL
lmmedlaLe
16-blL
l-Lype
opcode
6-blL
lmmedlaLe
26-blL
!-Lype
26 Aug 2014 EE-309@IITB
CADSL
A noLe on LengLh and unlformlLy
- unlform decode usually goes wlLh xed lengLh
- ln a varlable lengLh lSA, unlform decode can be
a properLy of lnsLrucuons of Lhe same lengLh
- lL ls hard Lo Lhlnk of lL as a properLy of lnsLrucuons
of dlerenL lengLhs
13 26 Aug 2014 EE-309@IITB
CADSL
ISA Classification
26 Aug 2014 EE-309@IITB
# Memory
Address
Max. no. of
operands
allowed
1ype of
archlLecLure
Lxamples
0 3 Load-SLore Alpha, A8M,
MlS,
owerC
1 2 8eg-Mem l8M360, lnLel
x86, 68000
2 2 Mem-Mem vAx
3 3 Mem-Mem vAx
14
CADSL
ISA Classification
1ype Adv ulsadv
8eg-8eg Slmple, xed lengLh encodlng,
slmple code generauon, all
lnsLr. 1ake same no. of cycles
Plgher lnsLrucuon counL,
lower lnsLrucuon denslLy
8eg-
Mem
uaLa can be accessed wlLhouL
separaLe load lnsLrucuon rsL,
lnsLrucuon formaL Lend Lo be
easy Lo encode and yleld good
denslLy
Lncodlng reglsLer no and
memory address ln each
lnsLrucuon may resLrlcL Lhe
no. of reglsLers.
Mem-
Mem
MosL compacL, doesn'L wasLe
reglsLers for Lemporarles
Large varlauon ln
lnsLrucuon slze, large
varlauon ln ln amounL of
work (nC1 uSLu 1CuA?)
26 Aug 2014 EE-309@IITB 15
CADSL
Thank You
EE-309@IITB 26 Aug 2014 16

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