ELEC343 Basic VHDL Design Practical 2

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ELEC343 Digital Systems Design

Basic VHDL Design Practical 2

Getting Started with VHDL and Modelsim
Directly click Next instead of New Source within the Create a New Source
dialog box.

Click Add Source in the Adding Existing Sources dialog box.

Locate the file sequential.vhd on your local drive, double click it, and click
Next. This will automatically copy this file into your project folder.

Click Finish in the Project Summary window.

Click OK in the Adding Source Files dialog box.

Copy the file sequential.vhd on the iLearn to your local drive.

Part I. Creating a New VHDL Project

Creating a schematic project is introduced in the lab notes ISE_Quick_Start_Tutorial.pdf
on the server. This time we need to create a VHDL design project, which is quite similar
in the first few steps. Please follow that lab notes in creating a new project on schematic
design.

Your are recommended to create this new project in H:\Labs\VHDL. Put sequential in
the Project Name field and select HDL from the To-Level Module Type fileld.
This will allow us to use VHDL module in the design.

The VHDL file on your local drive needs to be added rather than a schematic to be created.
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Part II. Implementing a VHDL Design
Synthesis and Implementation need to be done after VHDL description of a circuit is
finished.

Double click the file sequential.vhd in the Sources window. The source
code is opened and it has already been finished at this stage. You need to
design this kind of code in Part II and III.

Usually what youd like to do after writing a code is to check the syntax first.
Expand Synthesize XST within the Processes window. Double click check
syntax. You will see a green tick ahead of check syntax if no error is found,
otherwise a red cross will appear there.

After fixing syntax errors (if any), double click Synthesize XST to
synthesize the circuit. Note this will take you an awfully long time if an
enough complicated circuit is being processed, but it just takes 3 seconds for
our circuit.

You might want to check the resulting looking of the circuit by double
clicking View RTL Schematic and View Technology Schematic under
Synthesize XST. The RTL Schematic just results from a simple analysis of
your syntax while the Technology Schematic is the actual synthesized
outcome and much closer to the finally produced physical circuit.

We usually want to implement the design by doing translating, mapping and
placing & routing after synthesis. Double click Implement Design in the
Processes window.

The next step is to configure an FPGA board using an implementation
constraint file. These are all explained in detail in your lab notes on page 31
to 33. You will need to do this in Part II and III. In this Part, we need to do a
more important step simulation.


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Part III. Modelsim Simulation

3.1 Create Test Bench Waveforms

To perform a test, a test bench needs to be created. A test bench can be composed by
writing a VHDL code or visually drawing waveforms. For simple tests, the latter way
is easier to get started with. Below are the steps to create test bench waveforms using
Xilinx.

Go to Project => New Source.

Select Test Bench WaveForm, type sequential_test, and click Next =>
Next => Finish.

In the Initialize Timing window, choose Combinatorial (or internal clock)
for Clock Information, and click finish.

Set input A to high or low simply by clicking on the A waveform. Try
clicking waveform A at 200 ns to pull it up and at 400 ns to pull it down.
Press Ctrl-S to save the test file.

Select Behavioral Simulation from the Sources for drop down menu in the
Sources window.

Highlight the Sequential_Test file. Click the Processes tab in the Processes
window. Expand Modelsim Simulator and double click Simulate Behavioral
Model. The Modelsim XE will start and it should look similar to Figure 1.


3.2 Simulation Results

Among all the sub-windows embedded in the Modelsim window what we are usually
interested in is the waveform window.

Click the zoom full button on the menu bar in the Modelsim window. Click
anywhere within the waveform window to add a yellow marker to the waves.

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Figure 1. A Modelsim Simulation Window

You will find the useful signals are listed on the left column in the waveform
window. The values of these signals at the instant specified by the marker are
listed on the next column.

Highlight any signal in the waveform window by clicking its name. You can
use to find the exact time of its transition.

Use to add or delete other markers. Two markers can be used to measure
the delay between two transitions of any two signals.

You probably have already found that there are only entity input and output
signals existing in the waveform window, i.e. a, b and c. It does not have the
signals defined within the architecture, i.e. temp. Try to look it up and add it
into your waveform window.

Redo the simulation by clicking the Restart button , keep all the options
ticked and click Restart. You may need to specify the simulation time in the
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Run Length field , say 800ns, because 100ps is obviously too short
to see anything substantial. Click the Run button on the menu bar.
Think about why c changes later than temp does.

Undock your waveform window and go to File => Save => Image Save it
in the name of signal_temp.bmp. Close the main Modelsim window.

Go back to Xilinx, change the signal temp to the type of variable in
sequential.vhd VHDL code. Select Synthesis/Implementation from the
Sources for drop down menu in the Sources window. Double click check
syntax in the Processes window. You may find syntactic errors as the change
may not be as simple as you expect. Think about the syntactic requirements
for variables, fix up the errors and save the file.

Double click Simulate Behavioral Model in the Processes window. Again
look up and add temp to the Modelsim waveform window, and then redo the
simulation.

Save your waveforms to a bitmap named variable_temp.bmp.

Think about the difference between signal_temp.bmp and
variable_temp.bmp. Show them to your tutor.


3.3 Simulation using Modelsim only

So far we have been starting Modelsim from Xilinx. In fact, Modelsim is quite self-
contained and can do most types of simulations itself. Below we will do the
simulation of the sequential design again, basically all in Modelsim.

Create a new folder called Modelsim under H:\Labs\VHDL. Go back to
H:\Labs\VHDL\sequential, locate sequential.vhd and sequential_test.vhw,
and copy them to the new folder H:\Labs\VHDL\Modelsim. Make sure
sequential.vhd is on the version with a variable temp.
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Double click sequential_test.vhw and choose Select the program from a
list. Tick off Always use the selected program to open this kind of file.
Choose WordPad in the Programs list and click OK.
You should now see the sequential_test.vhw is actually a VHDL code. The
statement wait for will remind you that this actually is a test bench instead of
a design because wait for is not synthesisable in design. This is what a VHDL
test bench looks like. The two wait for statements specify the two transition
times of A on 200ns and 400ns.
Now you should understand that this test bench was actually automatically
created by Xilinx from the sequential_test.tbw waveform you set up.
Actually you can also directly open this sequential_test.vhw file within
Xilinx. Back to Xilinx, go to Open => sequential_test.vhw and the code
shows up.
Start Modelsim by going to Start Menu => Programs => Modelsim XE =>
Modelsim.
Select File => Change Directory. Choose H:\Labs\VHDL\Modelsim to be
your directory path.
Before you simulate any design, you have to compile the code. Before you
compile any code, you need a library to hold the compilation results. Go to
File => New => Library to create a new design library. The create a New
Library dialog box turns up as shown in Figure 2. Leave every option as in
Figure 2 and click OK.









Figure 2. Create a New Library in Modelsim
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Note this creates a subdirectory named work (your design library) within the
current directory. Modelsim saves a special file named _info in the
subdirectory. This file will not be created if a Library directory is created
using Windows commands. Hence, always use the Library menu to do this.
3.3.1 Simulation without a test bench

Locate the Compile button on the menu bar and click it. Choose
sequential.vhd and click Compile. You will see some new messages in the
Transcript window. Click Done.
Time to do simulation now. Click on the Simulate button to start the
Start Simulation window in Figure 3. The list under the Design tab contains
all the libraries you may use for your simulation. All of them are pre-defined
except our current work library, which is the only one interesting us at this
stage. Expand work and you can see the only entity in it is our sequential
design. Click on sequential to add it into the field of Design Unit(s) because
this is the design to be simulated. Click OK. The simulation is ready to go.
















Figure 3. Start Simulation in Modelsim

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Go to View => Wave to activate the wave window. Try to add signals (a, b
and c) and variables (temp) on to the wave window.
Again specify the simulation time 800ns in the Run Length field
and click the Run button . You should now see four 800ns long red lines
in the waveform window. The Us in the second column indicate they are at
the Uninitialized status. This was because no value was assigned to input a.
Click the Restart button to reset the simulation. You need to add some
stimuli to your input a now.
Write the following instruction after the VSIM prompt in the transcript
window:
force a 0 0, 1 200ns, 0 400ns
Press Enter.
The simulator interprets this force command as follows:
o force a to the value 0 at 0ns after the current time
o then to 1 at 200ns after the current time
o then to 0 at 400ns after the current time
Click Run button and you should see green lines this time. Click the zoom
full button to see your result.


3.3.2 Simulation using a test bench

Rename the suffix of sequential_test.vhw to sequential_test.vhd in the
folder H:\Labs\VHDL\Modelsim.
Click the Compile button and you should see sequential_test.vhd in the
window. Compile it and click Done.
Click the Simulation button and add sequential_test to Design Unit(s) and
click OK.
Add signal a, b, c and temp to the wave window, change the Run Length to
be 800ns and click Run.
You should see green lines show up directly. This means no input value has to
be specified for this simulation because the test bench has already got the
stimuli in its code.


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3.4 Debugging a Design

Double click sequential_test in the Workspace window. This will open the
sequential_test.vhd source file for you.
Now you can set a breakpoint in the code. Scroll the window vertically until
line 61 is visible. Click on or near line number 61 to set a breakpoint. You
should see a red dot next to the line number where the breakpoint is set. This
breakpoint can be toggled on and off by clicking it. Note breakpoints can be
set only on executable lines denoted by red line numbers.
Go back to your wave window and click the Run button. The simulation
will hit the breakpoint, as shown by an arrow in the source file
sequential_test.vhd.
Click the proc_a under uut in the Workspace window. You should see the
variable temp in the Locals window. The Objects and the Locals window are
the two you need to keep an eye on during the simulation. You may see all of
a, b, c and temp are have the value 1 at the current time, which should be the
same as those in the wave window.
Now click the Step button to single-step through the simulation. After
clicking it once, the arrow in your source file should move to line 63 while
nothing in the Objects or Locals window has changed.
A second click on the Step button should open the source sequential.vhd as
the simulation is running into it at the current time. The arrow should point to
the proc_a line. Also note that the value of a has just been changed to 0.
A third click on the Step button will push the arrow into the process. Slowly
step through the process will make some findings:
o When was temp changed?
o When were b and c changed?
Answer the two questions to your tutor. Now you should know exactly how
VHDL treats the transitions of signals and variables.