DWC DDR MultiPHY Smic40ll25 DB

July 29, 2011
PHY Version: 1.00a

DesignWare Cores DDR multiPHY
Databook for SMIC40LL25
DDR multiPHY SMIC40LL25
Copyright Notice and Proprietary Information
Copyright 2011 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information
that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Registered Trademarks ()
Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, Confirma, CODEV,
Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst,
HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler,
PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, the
Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, UMRBus, VCS, Vera, and
YIELDirector are registered trademarks of Synopsys, Inc.
Trademarks ()
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE,
CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision,
DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler,
Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync,
iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan,
Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-
PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System
Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks of
Synopsys, Inc.
Service Marks (
SM
)
MAP-in, SVP Caf, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under license.
ARM and AMBA are registered trademarks of ARM Limited.
Saber is a registered trademark of SabreMark Limited Partnership and is used under license.
PCI Express is a trademark of PCI-SIG.
All other product or company names may be trademarks of their respective owners.
Synopsys, Inc.
700 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
2 Synopsys, Inc. July 29, 2011
DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
July 29, 2011 Synopsys, Inc. 3
DDR multiPHY for SMIC40LL25 Databook Contents
SolvNet
DesignWare.com
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Databook Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.1.1 System-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.1.2 Component Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.1.3 Component Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Chapter 2
Lane-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Byte Lane PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2 Command Lane PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 PHY Utility Block Lite (PUBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.4 PHY Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 3
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.1 Memory Controller RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.1 DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.2 ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.3 SSTL I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3 Solution Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Chapter 4
Timing and Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1 Clocking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.2 Command/Data To ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.3 Command/Data To SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contents DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
4.3.1 Single Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.3.2 Double Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.4 Read Data From SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.5 Communication with ASIC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Chapter 5
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chapter 6
Interface and Control Solution Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Chapter 7
External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Chapter 8
DLL Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1 DLL Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.1.3 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.1.5 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.2 Master DLL for DDRn (MSD_MDLL_DDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.2.1 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8.2.2 Master Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
8.2.3 Master DLL Control for Trim and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
8.2.4 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.2.5 MDLL Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.2.6 MDLL Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.3 Master-Slave DLL for DDRn MSD_MSDLL_DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.3.1 Master-Slave DLL Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
8.3.2 MSDLL Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.3.3 MSDLL Control for Trim and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
8.3.4 MSDLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.3.5 MSDLL Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
8.3.6 MSDLL Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
8.4 Mobile DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
8.5 DLL DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.5.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.5.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.5.3 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
8.5.4 Working with SDRAM Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Chapter 9
ITM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.1 ITM Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.1.3 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.1.5 ITM Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
DDR multiPHY for SMIC40LL25 Databook Contents
SolvNet
DesignWare.com
9.1.6 Byte Lane PHY Construction with ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9.1.7 Command Lane PHY Construction with ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.2 ITMs for Byte Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.2.1 ITM for Data (MSD_ITMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.2.2 ITM for Strobe (MSD_ITMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
9.2.3 ITM Byte Lane Clock Buffer (MSD_ITMBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
9.2.4 ITM Byte Lane Fill Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
9.3 ITMs for Command Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.3.1 ITM for Command (MSD_ITMC_D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.3.2 Command Lane Clock Buffer, Stage 0 (MSD_ITMCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.3.3 Command Lane Clock Buffer, Stage 1 (MSD_ITMCB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.3.4 ITM Command Lane Fill Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.4 DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.4.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.4.3 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9.5 Placement Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Chapter 10
SSTL I/O Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.1 SSTL I/O Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.1.3 I/O Metal Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
10.1.5 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.1.6 Cell Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
10.2 Bi-Directional Buffer (MSD_D3R_PDDRIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
10.2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
10.2.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
10.2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.3 Differential Bi-Directional Buffer (MSD_D3R_PDIFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.3.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.3.3 Differential Cell Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10.4 ZQ Calibration Cell (MSD_D3R_PZQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
10.4.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
10.4.3 ZPROG Settings for Zo and ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
10.5 Impedance Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.5.1 Direct Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.5.2 Override Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.5.3 Custom Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.6 Impedance Control Logic (MSD_D3R_zctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.6.1 Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.6.3 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.6.4 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10.7 Reference Voltage Cell (MSD_D3R_PVREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Contents DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
10.7.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
10.7.3 Requirements for Powering Up/Powering Down PVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
10.8 Retention Latch Enable Input (MSD_D3R_PRETLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
10.8.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
10.8.3 Retention Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.9 Retention Latch Enable Input - External (MSD_D3R_PRETLEX) . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.9.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.10 Retention Latch Enable Input - Core (MSD_D3R_PRETLEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10.10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10.11 Analog Signal Cell (MSD_D3R_PAIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
10.11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
10.12 Power/Ground Supply Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
10.12.2 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
10.13 Corner and Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
10.13.2 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
10.14 Wire Bond Pad Cells with Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
10.15 SnapCap Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.16 SSTL I/O DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
10.16.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
10.16.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.16.3 DC Drive Mode Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
10.16.4 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
10.16.5 Decoupling Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
10.16.6 ESD and LU Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
10.17 Power-Up/Power-Down Sequence Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
SolvNet
DesignWare.com
Revision History
The following table provides revision history for this document.
PHY
Version
Databook
Version Date Description
1.00a 1.00 July 29, 2011 Initial release
Revision History DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
SolvNet
DesignWare.com
Preface
This document describes the DWC DDR multiPHY for communicating with DDRn SDRAMs. This PHY is
part of the DDRn SDRAM Interface solution, designed specifically for ease of use, ease of implementation,
and robust system timing while maximizing channel bandwidth.
The DDR2/3-Lite/mDDR features support for the following:
DDR2
DDR3
Mobile DDR (also referred to as mDDR and LPDDR)
LPDDR2
The PHY works with the following memory controllers:
DWC Universal Protocol Controller (uPCTL)
DWC Universal Memory Controller (uMCTL)
The PHY corresponds to DDR multiPHY for SMIC40LL25 in the SolvNet database.
Databook Organization
The chapters of this databook are organized as follows:
Product Overview provides an overview of the solution, key features, and system-level overview.
Lane-Based Architecturedescribes the architecture of the PHY.
Timing and Clocking discusses the critical timing relationships at the external interface.
Timing Diagrams provides timing diagram examples that show the timing between the
customers ASIC logic and the Memory Controller logic, the Controller and PHY, and the external
interface between the PHY I/O and the SDRAMs.
Test Methodologyprovides recommendations for testing the product.
Interface and Control Solution Connectivity provides examples of connectivity within the
command and byte lane PHY components and between the PHY and Memory Controller
components.
Note Note Note Note
The term DDRn refers to DDR2/ DDR3/ Mobile DDR/ LPDDR2
Note Note Note Note
In some instances, documentation-only updates occur. The DesignWare IP product information
(http://www.designware.com) has the latest documentation.
Preface DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
External Memory Configuration provides an example of how the Synopsys DDR2/DDR3
interface is connected to DDR2 SDRAMs.
DLL Library describes the DDR2/DDR3 SDRAM interfacing DLL (Delay Locked Loop) library, a
component of the PHY.
ITM Library describes the DDR2/DDR3 SDRAM Interface Timing Modules (ITMs), which are
timing translation components used in a DDR2/DDR3 PHY between memory controller logic and
DDR-specific SSTL I/Os.
SSTL I/O Library describes the Synopsys DDR2/DDR3 series SSTL (Stub Series Terminated
Logic) I/O library.
Web Resources
DesignWare IP product information: http://www.designware.com
Your custom DesignWare IP page: http://www.mydesignware.com
Documentation through SolvNet: http://solvnet.synopsys.com (Synopsys password required)
Synopsys Common Licensing (SCL): http://www.synopsys.com/keys
Recommended Reading
The following documentation provides essential information about Synopsys controllers that can be
attached to the DDR2/3-Lite/mDDR to create a complete DDR2/3-Lite/mDDR solution, as well as
information on implementing and packaging the PHY:
DesignWare Cores Universal DDR Memory Controller Databook, Synopsys, Inc.
DesignWare Cores Universal DDR Protocol Controller Databook, Synopsys, Inc.
DesignWare Cores DDR2/3-Lite Memory Controller Databook, Synopsys, Inc.
DesignWare Cores DDR2/3-Lite Protocol Controller Databook, Synopsys, Inc.
DesignWare Cores PHY Ultility Block Lite (PUBL) Databook, Synopsys, Inc.
DesignWare Cores DDR2/3-Lite/mDDR/multiPHY SDRAM PHY Implementation Guide, Synopsys, Inc.
Guidelines for Implementing Signaling Environments for DDRn Interfaces: Packages and PCBs, Synopsys,
Inc.
DesignWare Cores DDRn SDRAM PHY Implementation Checklist, Synopsys, Inc.
Application notes maybe added after the publication of this databook, so please check the DesignWare Cores
DDR2/3-Lite PHY Application Notes overview document.
DDR multiPHY for SMIC40LL25 Databook Preface
SolvNet
DesignWare.com
Customer Support
To obtain support for your product, choose one of the following:
Enter a call through SolvNet.
Go to http://solvnet.synopsys.com/EnterACall
and provide the requested information, including:
Product: DesignWare Cores
Sub Product: Memory DDRn SDRAM PHY
Tool Version: <release version>
Send an e-mail message to [email protected].
Include the Product name, Sub Product name, Process (such as, TSMC 65GP25), and Version
(product version number) in your e-mail so it can be routed correctly.
Telephone your local support center.
North America:
Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.
All other countries:
http://www.synopsys.com/Support/GlobalSupportCenters
Preface DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
SolvNet
DesignWare.com
1
Product Overview
Over 70% of SoCs designed today require an interface to off-chip memory. Due to their huge volumes
supplying the computer market, DDRn SDRAMs are the least expensive off-chip memory solution for SoC
designs. However, these memories come with a unique high-speed, parallel, source synchronous interface
and complex command protocol.
Synopsys DWC DDR multiPHYs are mixed-signal PHY IP cores that supply the complete physical interface
to JEDEC standard DDR2 and DDR3 SDRAM memories up to 1066 Mbps data rates and Mobile DDR (also
referred to as mDDR and LPDDR) SDRAM memories up to 400 Mbps data rates. This particular PHY
supports switching between DDR2 and DDR3 memories once a chip is in production. This Lite PHY does
not go up to the full 1600 Mpbs data rate targeted for DDR3. Instead, this is an area and feature optimized
DDR2/DDR3 PHY for customers that want to go to market with DDR2 interfaces up to 1066 Mbps and also
want an insurance policy against equivalent DDR3 devices becoming cheaper while their chip remains in
the market. As part of the optimization of this PHY, a small number of the new features for DDR3, such as
write leveling, are not supported as they are not supported by DDR2 SDRAMs.
A complete memory interface and control solution is achieved when utilizing the complete component
family of memory controller and PHY. The PHY consists of Interface Timing Modules, DLLs, and
DDR-specific SSTL I/Os.
This chapter includes the following sections:
System Overview on page 14
Key Features on page 20
Limitations on page 20
Applicable Standards on page 20
Product Overview DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
1.1 System Overview
This section provides a system-level overview of the DWC DDR multiPHY in an SoC, and an overview of
the components that comprise the solution.
1.1.1 System-Level Block Diagram
Figure 1-1 shows the DDR multiPHY, controller solution, and related components.
Figure 1-1 DDR multiPHY and Controller Solution
1.1.2 Component Packages
Providing a robust timing system at high data rates requires hardening of critical timing components. To
maximize system timing margins, timing-critical near-pad logic for DDR drive and capture has been
specially designed for optimal DDR performance and hardened into a library of ITM (Interface Timing
Module) components. The IP is provided as a combination of RTL for the general control logic and GDSII
for the ITM, Timing DLLs, and DDR-specific I/Os to complete the PHY portion of the solution. This unique
offering of soft and hard IP permits architectural design flexibility, effortless physical implementation,
correct-by-construction timing closure, and seamless implementation in customer-specific design flows.
M
S
D
L
L
M
D
L
L
M
S
D
L
L
C
o
n
t
r
o
l
l
e
r
S
o
l
u
t
i
o
n
I
T
M
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
I
T
M
S
e
g
m
e
n
t
I
T
M
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
Byte
Lane
PHY
DQ/DQS
To/From
SDRAM
Command
Lane PHY
ADDR/CMD/CK
To SDRAM
Byte
Lane PHY
DQ/DQS
To/From
SDRAM
To/From
ASIC Logic
DDR multiPHY for SMIC40LL25 Databook Product Overview
SolvNet
DesignWare.com
1.1.3 Component Overview
In order to facilitate robust system timing and ease of use, Synopsys interface and control architecture
utilizes a mixture of soft-IP and hard-IP design elements. The main control logic (Memory Controller) is
supplied as soft-IP. The PHY is comprised of hard-IP components that include double-data rate Interface
Timing Modules, input and output path DLLs, and application-specific SSTL I/Os.
1.1.3.1 Controller Solutions
The Synopsyss DDR SDRAM interface and controller solution can be implemented in either the
recommended implementation, a legacy implementation, or a non-Synopsys implementation.
Synopsys offers the following controller solutions:
Recommended Solutions (see Recommended Solution on page 16)
Universal DDR Memory Controller (uMCTL)
The uMCTL is an advanced multi-port memory controller which accepts memory access
requests from up to 32 application-side host ports. Application-side interfaces can be connected
to the uMCTL either through the standard AMBA 3 AXI/AHB bus interfaces or through
Synopsys custom-defined interface (ENIF). The controller connects to a DFI 2.1 interface
compatible PHY to create a complete memory interface and control solution. The controller
includes software configuration registers, which are accessed through an AMBA 2.0 APB
interface.
Universal DDR Protocol Controller (uPCTL)
The uPCTL delivers efficient bandwidth with minimum latency and provides the designers with
transparent access and complete control of the memory subsystem. The uPCTL serves the
memory control needs of applications with simple transactions that do not require an internal
scheduler, and can also be deployed with custom-designed memory management units. The
uPCTL SoC application bus interface supports a lowest-latency native application interface
(NIF).
The controller connects to a DFI 2.1 interface compatible PHY to create a complete memory
interface and control solution. The controller includes software configuration registers, which
are accessed through an AMBA 2.0 APB interface.
PHY Utility Block Lite (PUBL) (see PHY Utility Block Lite (PUBL) on page 27)
The PUBL is a soft-IP component to be used with the DWC DDR multiPHY. It provides control
features to ease the customer implementation of digitally controlled features of the PHY such as
initialization, DQS gate training, Zo and ODT impedance control, and programmable
configuration controls. The PUBL has built-in self test features to provide support for production
testing of the PHY. It also provides a DFI 2.1 compliant interface to the PHY.
Non-Synopsys Controller Solution (seeNon-Synopsys Controller Solution on page 17)
PHY Utility Block Lite (PUBL) (see PHY Utility Block Lite (PUBL) on page 27)
This implementation does not use a Synopsys controller, but does use the PUBL to interconnect
the PHY to the customer controller through the DFI 2.1 interface.
SolvNet
DesignWare.com
1.1.3.1.1 Recommended Solution
The recommended solution uses the PUBLs DFI 2.1 interface to connect between the PHY and the Synopsys
DWC Universal DDR Protocol Controller or DWC Universal DDR Memory Controller (see Figure 1-2 on
page 16). For more information on the PUBL, refer to PHY Utility Block Lite (PUBL) on page 27.
This implementation has the following requirements:
The zctrl RTL is not used in this implementation. This configuration uses the PUBL RTL, which
contains the zctrl logic.
Figure 1-2 Recommended Implementation of the DDR Interface and Control Solution
Soft-IP Hard-IP
MDLL
S
y
n
o
p
s
y
s
D
W
C
U
n
i
v
e
r
s
a
l
D
D
R
P
r
o
t
o
c
o
l
C
o
n
t
r
o
l
l
e
r
o
r
Control
Data
Data
Address
System Clock
SSTL I/O DLL Controller RTL
(
o
n
e
f
o
r
e
v
e
r
y
8
b
i
t
s
o
f
d
a
t
a
)
SDRAM Interface
C
o
m
m
a
n
d
L
a
n
e
P
H
Y
B
y
t
e
L
a
n
e
P
H
Y
(
o
n
e
p
e
r
m
e
m
o
r
y
i
n
t
e
r
f
a
c
e
)
ITM
MSDLL
DQS_b
DQS/
CK_b
CK /
RTL
PUBL
PUBL RTL
D
F
I
D
F
I
zctrl
U
n
i
v
e
r
s
a
l
D
D
R
M
e
m
o
r
y
C
o
n
t
r
o
l
l
e
r
R
T
L
PVREF
PZQ
C
F
G
C
F
G
J
T
A
G
J
T
A
G
A
P
B
A
P
B
Chip Logic
SolvNet
DesignWare.com
1.1.3.1.2 Non-Synopsys Controller Solution
A non-Synopsys controller solution uses the PUBL's DFI 2.1 interface to connect between the PHY and the
customer controller (see Figure 1-3 on page 17).
This implementation has the following requirements:
The zctrl cell is not used in this implementation.
Figure 1-3 Non-Synopsys Controller Implementation of DDR Interface and Control Solution
MDLL
Controller
RTL
Customer
Control
Data
Data
Address
System Clock
SSTL I/O DLL
Chip Logic
Controller RTL
(
o
n
e
f
o
r
e
v
e
r
y
8
b
i
t
s
o
f
d
a
t
a
)
SDRAM Interface
C
o
m
m
a
n
d
L
a
n
e
P
H
Y
B
y
t
e
L
a
n
e
P
H
Y
(
o
n
e
p
e
r
m
e
m
o
r
y
i
n
t
e
r
f
a
c
e
)
ITM
MSDLL
DQS_b
DQS/
CK_b
CK /
RTL
PUBL
PUBL RTL
D
F
I
D
F
I
zctrl
PVREF
PZQ
C
F
G
C
F
G
J
T
A
G
J
T
A
G
A
P
B
A
P
B
Soft-IP Hard-IP
SolvNet
DesignWare.com
1.1.3.2 Controller Configurable Parameters
To permit optimum flexibility, each controller option includes a wealth of configurable parameters and
register-programming options. Each controller has a user (chip-logic) interface, which is translated by the
controller logic into Mobile DDR/DDR2/DDR3 transactions. To facilitate 533 MHz DDR (1066 Mbps) at the
SDRAM interface, the data width throughout the controller is 2x the external data width. For example, for a
32-bit SDRAM interface, the data width throughout the controller is 64 bits. The ITMs handle both the 2x
SDR to 1x DDR conversion for data output to the SDRAM and 1x DDR back to 2x SDR conversion for input
from the SDRAM.
1.1.3.3 Timing
In order to maximize system timing margins on the command/write path, inputs to the SDRAM are
provided with the clock or data strobe centered in the associated data eye. The ITM components perform
timing translation for the various signal groups of the interface. The hardened ITM approach ensures
minimal pin to pin skew while allowing optimal circuit design for drive and capture circuitry. A DLL is
utilized to facilitate the clock centering. In the Command Lane, a master DLL (MDLL) is utilized. In the Byte
Lane, the master portion of a master/slave DLL macrocell (MSDLL) is utilized.
On the read path, read data from the SDRAM is arriving from the SDRAM edge aligned with the data
strobes. In order to maintain maximum system timing margins on the input path, the data strobes are
translated to the center of the data eye. The MSDLL macrocell associated with each Byte Lane contains a
master DLL and 2 slave DLLs (mirror delay lines). The slave DLL portion of the MSDLL is utilized to
facilitate the clock centering. DQS and DQS_b strobe inputs each utilize one of these slave DLL functions.
The captured double data rate inputs are then converted to single data rate and passed onto the DDR
Controller RTL logic. The ITM facilitates both data capture and DDR to SDR conversion.
1.1.3.4 SSTL I/O Buffers
The physical interface between the DDR controller and DDR SDRAMs uses DDR-specific SSTL I/O buffers
with programmable on-die termination (ODT). These I/Os operate at either 1.8V for Mobile DDR/DDR2
interfacing (SSTL_18), or 1.5V for DDR3.
The Synopsys memory interface and control architecture follows a common signal grouping philosophy. A
Byte Lane is a complete eight-bit data unit consisting of the associated DQ, DM, and DQS/DQS_b signals. A
16-bit system would consist of two Byte Lanes. A Command Lane is a complete command and address unit
including also clock signals. There would normally be only one Command Lane in a particular DDR
SDRAM interface. All clock and data signals relative to a Lane, either Byte or Command, are isolated to
within that Lane only. Timing critical clock and data signals do not traverse between Lanes. Implementation
of a memory interface involves placing the Command Lane components, placing the Byte Lane components,
and standard synthesis/place and route to complete the design.
SolvNet
DesignWare.com
1.1.3.5 ITM Library
Each SSTL cell communicating with the SDRAM has an associated ITM component. The ITM library
consists of individual components designed specifically for signal groups of address and command, data &
data mask, and data strobes. In order to ensure low pin to pin skews and facilitate ease of implementation,
the ITM components are tileable. DLL output clock distribution is embedded within the ITM components.
The ITM library contains filler cells to allow continuous clock and power connections across power/gnd cell
locations and to allow for variations in pad pitch. Break cells are also provided to isolate clock signals within
a Lane while allowing power connections to continue.
Figure 1-4 on page 19 provides a basic view of ITM cell library placement. Refer to the ITM GDSII /LEF for
the actual physical design of the ITM cells.
Figure 1-4 ITM Placement
This figure provides a relative example of
the ITM library functional and break cell
implementation. Various width fill cells
permit matching the ITM cell pitch with the
desired I/O pad pitch. Larger fill cells are
placed where ITM functional cells are not
required, such as power cell slots. Break cells
are used to discontinue the embedded clock
distribution between abutting Lanes.
TO / FROM
SSTL I/O
TO / FROM
SSTL I/O
TO / FROM
SSTL I/O
TO/FROM
CONTROLLER
TO/FROM
CONTROLLER
TO / FROM
SSTL I/O
TO/FROM
CONTROLLER
TO/FROM
CONTROLLER
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
L
A
N
E
A
L
A
N
E
B
Break Cell
ITM
ITM
ITM
ITM
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
ITM FILL
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
P
O
W
E
R
G
R
O
U
N
D
G
R
O
U
N
D
P
O
W
E
R
ITM FILL
C
L
K
0
C
L
K
9
0
C
L
K
1
8
0
C
L
K
2
7
0
SolvNet
DesignWare.com
1.2 Key Features
The DesignWare Cores DDR multiPHY includes the following features:
Compatible with JEDEC standard DDR2/ DDR3LPDDR (or Mobile DDR)/ LPDDR2 SDRAMs
Operating range of 100MHz (200Mb/s) to 533MHz (1066Mb/s) in DDR2/DDR3/LPDDR2 modes
Operating range of DC to 200MHz in Mobile DDR mode
PHY Utility Block (PUBL) component
DFI 2.1 compliant interface to controller
At-speed loopback testability
Configurable external data bus widths in 8-bit increments
Permits operating with SDRAMs using data widths narrower than the implemented data width
Programmable output and ODT impedance with dynamic PVT compensation
Embedded Dynamic Drift Detection in the PHY to facilitate Dynamic Drift Compensation with the
controller
Utilizes Master and Slave DLLs for precise timing management
Lane-based architecture (Byte Lane, Command Lane)
Test modes supporting IDDq and DLL characterization
Library-based hard-IP PHY to permit maximum flexibility while ensuring high data rates
Full documentation including physical implementation guide
Includes all required views for a typical ASIC design flow
1.3 Limitations
Does not support write leveling as required by DDR3 DIMM
Must supply both DQS and DQS_b in DDR2 mode
1.4 Applicable Standards
The following JEDEC standards are applicable in the DDR multiPHY design:
JESD8-15A JEDEC Stub Series Terminated Logic for 1.8V (SSTL_18)
JESD79-2E JEDEC DDR2 SDRAM Specification
JESD79-3C JEDEC DDR3 SDRAM Specification
JESD209A JEDEC LPDDR (Mobile DDR) Specification
JESD209-2B JEDEC LPDDR2 SDRAM Specification
SolvNet
DesignWare.com
2
Lane-Based Architecture
Byte Lane PHY on page 22
Command Lane PHY on page 25
PHY Utility Block Lite (PUBL) on page 27
PHY Type on page 28
Floorplanning on page 29
Lane-Based Architecture DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
2.1 Byte Lane PHY
Figure 2-1 provides an example Byte Lane configuration for discussion purposes. Actual Byte Lane
configurations are dependent on the anticipated memory configuration, performance goals, and packaging
technology. The designer should refer to the component datasheets for actual port lists.
Figure 2-1 Byte Lane Overview
ITMBFILLnn
DO
OE
DI
DOUT
OUT_EN
DIN
ITMD
DO
OE
DI
DOUT
OUT_EN
DIN
ITMD
ITMBFILLnn
ITMBFILLnn
DO
OE
DI
DOUT
OUT_EN
DIN
ITMD
ITMBFILLnn
DO
OE
DI
DOUT
OUT_EN
DIN
ITMD
ITMBFILLnn
DQ_x
DQ_y
SSTL I/O
SSTL I/O
SSTL I/O
SUPPLY
SUPPLY
SUPPLY
DQ[y]
DQS
DO
OE
DRIFT
OUT_EN
DIN
DRIFT
DQS
IDDq SSTL
DLL ITM SEGMENT PAD RING
DQ[x]
SUPPLY
DQ_m
DQ_n
SSTL I/O
SSTL I/O
SSTL I/O
SUPPLY
SUPPLY
SUPPLY
DQS_b
DQ[m]
DQ[n]
DO
OE
DRIFT
OUT_EN
DIN
DQS GATE
DQS GATE
GATE
ITMS
ITMS
CLK0
CLK90
CLK180
CLK270
DQS_90
ITMBB
MSDLL
IDDq DLL
DI
DI
OUTPUT ENABLE
DQSb_90
DQS_b
REFERENCE
CLOCK
DLL ADJUST
ODT SELECT
CONTROLLER CLOCK (ALL DQ ITMs)
ITM ADJUST (ALL ITMs)
ITMBFILLnn
P
U
B
L
DDR multiPHY for SMIC40LL25 Databook Lane-Based Architecture
SolvNet
DesignWare.com
The data bus interface to the external memory is organized into self-contained units referred to herein as
Byte Lanes. The external memory components are designed to support Byte Lanes for optimal system
timing. The partitioning of the data word into discrete Byte Lanes allows pin to pin skew to be managed
across a much smaller group of signals than would typically be required. This also helps ease the task of
signal track topology matching in the package and PCB environments.
All components of the Byte Lane PHY are designed to permit connectivity by abutment. The ITM connects
by abutment to the SSTL I/O, and the DLL connects by abutment to the ITM. It is highly recommended to
implement these components by abutment whenever possible. An example scenario where this might not
be possible is if filler cells are used to create a larger than minimum pad pitch, in which case the ITM would
continue to abut to the SSTL I/O but the DLL may not be able to abut to the ITM due to pin alignment
offsets. In such scenarios the components do also fully support standard routing for connectivity.
The SDRAM contains data strobes associated with each 8 bits of data and there is a timing skew allowance
between the main clock signal to the SDRAM and its data strobe inputs during a Write command (tDQSS). 8
bit memory components provide a single DQS. 16 bit memory components provide 2 DQS, one for each 8
bits. 4 bit memory components provide a single DQS where 2 components are used to realize an 8 bit word
and the DQS from each of the components are connected together to interface with the host. With this 4 bit
DQS connectivity, during a Write the host will drive the DQS to both components and during a Read both
components together will drive the DQS back to the host, which without careful design may result in false
triggering of the DQS back to the host. Due to the additional address and command signal loading and lack
of a matched DQS/DQ Lane from a single device, memory systems configured with 4 bit memory
components is not recommended.
A Byte Lane consists of the following I/O slots:
8 data bits (DQ)
data strobe bits (DQS / DQS_b)
1 data mask bit (DM)
I/O power and ground cells
Core power and ground cells
The number of required power cells is dependent on desired operating frequencies, packaging options, and
core power requirements of the customers chip logic. It is recommended the customer work with Synopsys
to determine the proper Byte Lane configuration for their design.
Each functional I/O slot has an associated ITM module, including DQ, DM, and DQS/DQS_b. ITM library
fill cells are inserted in the associated power cell slots to maintain a continuous ITM segment. Clock
distribution is embedded within the ITM components, relieving the designer of this critical task. Corner
cells are not provided in the ITM library, as Byte Lanes are not permitted to wrap around a corner of the IC.
All components of a Byte Lane must reside on the same side of the IC. Complete Byte Lane units may be
placed on different sides of the IC.
The ITMs provide a mechanism for monitoring read timing drift, which can be used to adjust timing to
maintain optimum system margins. Drift analysis and compensation is performed by the controller on a per
Byte Lane basis. Read DQS recognition and drift compensation is described further in the related Memory
Controller databooks. The ITM components contain the functions to monitor DQS drift and permit timing
adjustment, the controller provides the analysis and control for these functions. These functions operate
dynamically for each data bit of every user-issued Read command. There are no overhead penalties in
channel bandwidth or utilization incurred by the use of these functions.
The memory interface (PHY) architecture is based on the concept of independent, but related, signal groups
to provide the highest level of system timing performance. In order to maintain robust system timing, all
SolvNet
DesignWare.com
clock and data signals relevant to a Byte Lane remain within that Byte Lane. These signals are not shared
between other Byte Lanes or between a Byte Lane and a Command Lane. Alternate approaches require
clock distribution networks that span the full length of the interface including all address, command, and
data signals. These large clock distribution networks are difficult for the user to design and implement, and
add an additional component of pin to pin skew to the critical timing budget.
A DLL macrocell (MSDLL) consisting of a master DLL and 2 slave DLLs (mirror delay lines) is utilized at
each Byte Lane to facilitate optimal PHY timing for drive and capture of DDR data streams, and allows the
Lanes to be independent. The master DLL section provides outputs for DDR data stream creation to the
SDRAMs and acts as a reference for the slave delay line sections. The slave delay line sections translate the
incoming DQS/DQS_b into the center of the read data eye to maximize read system timing margins.
The user is permitted to fine tune the relationship of the DQS and DQ signals to maximize read system
timing margin. The DLL includes adjustability of the slave delay lines for the DQS and DQS_b signals,
which provide byte-wide timing adjustments. The ITMs include adjustability of the read DQS/DQS_b
strobe timing, which provides byte-wide timing adjustments. The ITMs include adjustability of the read DQ
signal timing, which provides per-bit timing adjustability. To permit Lane-independent timing adjustments,
DLL adjustment bits are provided by the controller per Byte Lane and ITM adjustment bits are provided per
bit.
Synopsyss interface and control solution allows memory systems with a word width narrower than the
design. For example, an IC may be designed with a 32 bit data width and this IC can then be utilized with
either 16 bit or 32 bit memory systems. The controller contains register settings to allow the desired
operational mode to be set in the final device.
A FIFO is used in the ITM to provide reliable read data capture. This FIFO permits clock-domain crossing
from the external SDRAM read DQS domain to the general control logic synthesized clock tree domain
(controller clock). Each ITM requires the controller clock to read data from the FIFO. Distribution of the
controller clock is not embedded in the ITMs. There are no special timing requirements for this controller
clock input to the ITMs. The ITMs should be treated as any other register in the design during clock tree
synthesis.
The DDR-specific SSTL I/Os include programmable ODT and output impedance selection. The ODT and
output impedances can be dynamically calibrated to compensate for variations in voltage and temperature.
The ODT feature can be disabled by the controller. When ODT is enabled by the controller, the SSTL I/O
automatically enables its internal ODT circuitry when in input mode and disable this circuitry when in
output mode, as determined by the output enable signal. The initial programming and subsequent
calibration of the of the ODT and output impedance is achieved through the use of an impedance control
loop that can be triggered to calibrate the ODT and output impedance values at the I/Os based on the
desired impedance value when compared to an precision external resistor. All the necessary pieces of the
impedance control loop are included in the SSTL I/O library.
The SSTL I/Os include embedded boundary scan support logic to permit the insertion of boundary scan by
the customer without interfering with the matched timing of the mission-mode paths. This can also be used
by the customer for test purposes other than boundary scan.
The number of Byte Lanes required for a design is determined by the desired maximum databus interface
width to the external memory. For example, a maximum 16 bit system would be comprised of 2 Byte Lanes
and a maximum 64 bit system would be comprised of 8 Byte Lanes.
SolvNet
DesignWare.com
2.2 Command Lane PHY
Figure 2-2 provides an example Command Lane configuration for discussion purposes. A reduced number
of address signals has been included in this figure. Actual Command Lane configurations are dependent on
the anticipated memory configuration, performance goals, and packaging technology. The designer should
refer to the component datasheets for actual port lists.
Figure 2-2 Command Lane Overview
ITMFILLnn
ITMC DOUT DO
ITMC DOUT DO
ITMC DOUT DO
ITMCFILLnn
ITMC DOUT DO
ITMC DOUT DO
ITMCFILLnn
ITMC DOUT DO
ITMCFILLnn
ITMC DOUT DO
ITMCFILLnn
ITMCFILLnn_BREAK
ITMCB0
ITMCB1
ITMCFILLnn_BREAK
ITMCB1
SSTL I/O
SSTL I/O
SUPPLY
CK
CMDx
CMD_x
CONTROLLER
CLOCK
CCLK0
SSTL I/O
SSTL I/O
SUPPLY
CK_b
CMDy
CMD_y
SUPPLY
SSTL I/O
SSTL I/O
SUPPLY
SUPPLY
A[m]
A[m]
A[n]
A[n]
SUPPLY
SSTL I/O
SSTL I/O
SUPPLY
SUPPLY
SUPPLY
A[x]
SYS CLK
IDDq SSTL
A_x
To Byte Lane DLLs
ITM SEGMENT PAD RING DLL
MDLL
CLK0
CLK90
CLK180
CLK270
IDDq DLL
DLL ADJUST
P
U
B
L
SolvNet
DesignWare.com
The control and address interface to the external memory is organized into a self-contained unit referred to
herein as a Command Lane. A memory interface would typically contain a single Command Lane and one
or more Byte Lanes.
All components of the Command Lane PHY are designed to permit connectivity by abutment. The ITM
connects by abutment to the SSTL I/O, and the DLL connects by abutment to the ITM. It is highly
recommended to implement these components by abutment whenever possible. An example scenario
where this might not be possible is if filler cells are used to create a larger than minimum pad pitch, in
which case the ITM would continue to abut to the SSTL I/O but the DLL may not be able to abut to the ITM
due to pin alignment offsets. In such scenarios the components do also fully support standard routing for
connectivity.
A typical Command Lane consists of the following I/O slots:
1 system clock input (optional)
Memory clocks (CK/CK_b)
Command signals (RAS_b, CAS_b, WE_b)
1 or more clock enable (CKE)
1 or more on-die termination (ODT)
0 or more chip select (CS_b)
2 or 3 bank address (BA)
Up to 16 row/column address (A)
I/O power and ground cells
Core power and ground cells
Note that for LPDDR2, the address/command address bus (CA) is 10-bit wide and there is no command
signals (RAS_b, CAS_b, WE_b.
The system clock input is used to provide the source clock for the memory interface. If the system clock is
being provided from an on-die source, this input is not required.
Each memory controller supports from 1 to 4 SDRAM ranks. There is one CKE, ODT, and CS_b signal
provided for each rank. The designer can set the maximum number of ranks to be supported at compile
time. Note that if a single-rank system is used, the CS_b output can be removed. In this case the CS_b input
of the DRAM(s) is tied low on the PCB.
The number of required power cells is dependent on desired operating frequencies, packaging options, and
core power requirements of the customers chip logic. It is recommended the customer work with Synopsys
to determine the proper Command Lane configuration for their design.
Each functional I/O slot has an associated ITM module, with exception of the system clock input. ITM
library fill cells are inserted in the associated power / system clock cell slots to maintain a continuous ITM
segment. Clock distribution is embedded within the ITM components, relieving the designer of this critical
task. Corner cells are not provided in the ITM library, as the Command Lane is not permitted to wrap
around a corner of the IC. All components of the Command Lane must reside on the same side of the IC.
A master DLL (MDLL) is utilized with the Command Lane to facilitate optimal PHY timing for drive of
DDR data streams, and allows the Lane to be independent. The DLL macrocells provide two 0 degree phase
outputs, one which can be used to drive the controller logic. The Command Lane MDLL is used for this
purpose. Standard clock tree synthesis tools can be applied from this DLL output. Clocking of the memory
interface and control solution is described later in this document.
SolvNet
DesignWare.com
To permit Lane-independent timing adjustments, DLL and ITM adjustment bits are provided by the
controller separately for Command and Byte Lanes.
2.3 PHY Utility Block Lite (PUBL)
The PUBL is a soft IP component to be used with the DWC DDR multiPHY. It provides control features to
ease the customer implementation of digitally controlled features of the PHY such as initialization, DQS
gate training, and programmable configuration controls. The PUBL has built-in self test features to provide
support for production testing of the DWC PHY. It also provides a DFI 2.1 compliant interface to the PHY.
The PUBL includes configuration registers that are accessible via a configuration port. The configuration
port can be either a generic configuration interface (CFG) or an APB interface. There is also an optional
JTAG interface that improves access for test functions. An example of a complete memory interface and
control solution (Figure 2-3 on page 27) is achieved when the PUBL is combined with Synopsys DWC DDR
multiPHY and with either Synopsys Universal Controllers (uPCTL or uMCTL) or a third party controller.
Figure 2-3 DDR Memory Interface and Control Solution
SolvNet
DesignWare.com
2.3.1 Key Features
The PUBL supports the following features:
DDR/DDR2/DDR3/DDR3L/mDDR (LPDDR)/LPDDR2 operation
Scalable performance from 0 MHz (LPDDR) through DDR3-1066
Maximum controller clock frequency of 533 MHz resulting in maximum SDRAM data rate of
1066Mbps
Data path width scales in 8-bit increments
Multiple (4) memory rank support
Complete PHY initialization, training and control
Automatic DQS gate training and drift compensation
At-speed built-in-self-test (BIST) loopback testing on both the address and data channels for DWC
DDR multiPHYs
PHY control and configuration registers
APB or generic interfaces to configuration registers
Optional, additional JTAG interface to configure registers
DFI 2.1 interface
A full description of the PUBL is contained in the standalone DesignWare Cores DDR1/2/3 SDRAM PHY
Utility Block (PUBL) Databook.
2.4 PHY Type
The Synopsys DesignWare DDR multiPHY PHYs include minor differences for the various PHYs to support
orientation sensitive processes. This has resulted in minor changes in SSTL and ITM cell selection. The
PUBL is a configurable soft IP and may be configured to support each PHY. To easily distinguish between
these PHYs they are denoted by TYPE A and TYPE B1 in the DesignWare Cores PHY Utility Block "Lite"
(PUBL) databook. The SMIC40LL25 PHY is of PHY TYPE A, and the PHY Utility Block "Lite" (PUBL) must
be configured for this type when using this PHY.
Note Note Note Note
You must make sure you are using the latest available version of the PUBL. Refer to the DesignWare
Cores PHY Utility Block "Lite" (PUBL) Release Notes and PHY Utility Block "Lite" (PUBL) Databook
for details.
SolvNet
DesignWare.com
2.5 Floorplanning
Figure 2-4 provides basic examples of proper memory interface floorplanning. There are a few simple
guidelines to keep in mind when floorplanning the PHYs.
Figure 2-4 PHY Floorplanning Examples
Follow these guidelines to ensure a robust design with ease of integration.
1. Insert ITM break cells at the end of a given byte lane when it will abut with another byte lane to
ensure clock signals do not cross Lanes. Command Lane ITMs do not physically abut to Byte Lane
ITMs, therefore, a space is required to prevent these two ITM types from interacting.
2. Place all components of a lane on the same side of the IC. Only wrap around corners at lane
boundaries.
3. Position the lane clocking signals (CK/CK_b, DQS/DQS_b) centered in the Lane.
4. Position the DLL for a Lane centered in the length of the Lane.
SolvNet
DesignWare.com
5. Position the Command Lane equivalently centered in the Byte Lanes when utilizing balanced tree
Command Lane routing on the PCB. If using a pseudo-fly-by routing style for the Command Lane
signals on the PCB, where the Byte Lane signals are effectively length matched to the Command
Lane signals for each SDRAM component, than it may improve efficiency to place the Command
Lane at one end of the group of Byte lanes.
6. Aside from placing the padframe cells for Command and Byte Lanes, a number of V
REF
supply cells
must be placed to ensure the V
REF
supply on the die is free of coupling noise. Refer to the Physical
Implementation Guide for V
REF
implementation guidelines.
Please refer the Physical Implementation Guide for further design and implementation details.
SolvNet
DesignWare.com
3
Test Methodology
This chapter outlines testing recommendations for the Memory Interface and Control Solution.
Memory Controller RTL on page 32
PHY on page 32
Solution Testing on page 34
Test Methodology DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
3.1 Memory Controller RTL
The general logic of the Controller is delivered as synthesizable RTL. It is suggested the customer add
internal scan and utilize ATPG for production testing. This will provide traditional Stuck-At and Stuck-
Open fault coverage. Scan techniques using low-speed ATE hardware to provide Delay-Fault testing are
now popular. In process geometries of 130nm and below, resistive faults begin to appear which are not hard
faults that can be detected by traditional low-speed stuck-at testing. Delay-faults are of high enough
resistance that the net drivers can overcome them at low speed, however they extend the amount of time
required for the driver to pull the net to a logic 0 or 1 level, thus at higher speeds they have the effect of
slowing down net transitions and possibly causing timing errors. When possible, it is recommended to
implement delay-fault testing to improve your overall test strategy.
3.2 PHY
This section describes the blocks of the PHY.
3.2.1 DLLs
For low-speed functional test purposes of circuitry outside of the DLL, the DLL contains a bypass mode to
buffer the input clock to the output clocks. Bypass is also used for IDDq test mode as all DC current paths
within the DLL are disabled when bypass is asserted.
The DLL jitter, lock range, and characterization across PVT can be measured using the CK/CK_b and
DQS/DQS_b output clocks. Phase relationships can be determined by viewing a DQS output and a DQ
output simultaneously. These tests are functional tests requiring a small test vector set and the ability to
operate the design at the maximum clock rate on the ATE. Direct pin measurements such as these provide
good system-level measurements, but due to the ITM in the path do not allow direct access to characterize
the DLLs. It is also not always possible to operate the ATE at full interface speed test rates.
For enhanced characterization purposes, the DLLs include special analog and digital test outputs for
viewing various internal signals and references. The use of these test outputs requires the addition of 1
analog signal pad (included in the SSTL I/O library) and 2 SSTL I/O pads on the die. It is recommended
that the customer add these extra signals to allow DLL characterization in the final design.
The DLLs include the ability to place their analog test output into tristate, thus the DLL analog test outputs
can be connected together and only one analog test output is required to observe all DLLs on the die. In this
method the analog test output from only 1 DLL is enabled at a time. The digital test outputs from the DLLs
can be routed to the 2 digital test outputs of the die and the customer implements muxing to select one DLL
at a time. The two digital test outputs are required to be able to perform phase measurements. The digital
test output path requires the ability to pass 533MHz clock signals through the output.
By implementing the above recommendation of 3 dedicated test pins which are shared for all DLLs of the
design, each DLL of the design can be directly characterized and it can be performed on a lower-speed ATE.
The load board and/or DUT card for the ATE could be designed such that after setting the device into test
mode, a PLL or other clock source can be substituted for the ATE clock input such that the DLLs can be
ramped-up to the desired operating frequency. Time measurement equipment can then be used to capture
data such as jitter and phase relationships. Scopes could also be used to monitor the waveforms.
DDR multiPHY for SMIC40LL25 Databook Test Methodology
SolvNet
DesignWare.com
3.2.2 ITMs
The ITM macrocells are not included in logic scan due to the critical timing nature of the drive and receive
logic and the issue of modeling the ITM functionality to ATPG tools. These modules are efficiently tested
with a simple functional test pattern. For complete testing, it is suggested that a functional test be run which
performs a series of Write commands followed by a series of Read commands in which a one-hot pattern
can be created at the external interface. For example, a device with a 16-bit data bus width might use two
Write commands and two Read commands, each burst of 8. A walking 1 pattern would be used for the
commands to get full test coverage of the databus. A second series of Write commands with a walking data
mask activation would permit full test coverage of the mask bits. A third series of commands can be output
with a walking bit pattern to verify the command and address signals.
Testing of the ITM drift detection and compensation requires the ability to operate the device on an ATE
capable of operating at a test rate supported by the solution with the DLLs enabled, i.e. 125MHz/250Mbps
or higher. For this test a normal Read operation functional test vector is established. In the same test case,
after a normal read operation the timing of the Read data back to the device is altered such that it should
cause a 90 degree adjustment in the DQS window. This is repeated 4 times such that the window is moved a
full 360 degrees in one direction. The same operation is repeated, this time moving the window in the
opposite direction. A successful Read operation under these changing conditions indicates the drift
detection and compensation is working properly.
Examples of these testcases is included in the verification environment delivered with the memory
controller RTL.
3.2.3 SSTL I/Os
The SSTL I/O buffer is designed to allow the input buffer to be placed into an LVCMOS mode, called
Mobile DDR mode. When performing IDDq testing, the user can place the I/Os into a low-power mode. In
this mode, the SSTL input buffer mode, which consumes static current, is disabled and the Mobile DDR
input buffer mode enabled. Note that this mode only disables the SSTL static current paths. The user must
also bypass the DLLs, which also disables all of their internal static current paths.
Much of the required testing of the SSTL I/O can be performed with the same testing used for the ITMs.
This includes VOH, VOL, VIH, VIL, leakage current, and drive current. The ITM vectors should, if required,
be supplemented with vectors which test different I/O voltages (1.8V versus 1.5V), SSTL ODT and SSTL
drive strength options. Testing is not required for modes which are not used in the end application.
As an alternative access method, the embedded boundary scan logic of the SSTL I/Os, if used, is an
excellent method of testing I/O parameters such as VOH/VOL/VIH/VIL. This test support logic could also
be used by the customer for other test purposes for their chip.
Regarding the impedance control logic of the SSTL I/O, be aware of the following guidelines:
You can override the impedance control logic and write whatever drive codes you wish into the
registers that control pull-up and pull-down ODT and Zout.
You can let the impedance control logic perform its PVT compensation and then freeze the code so it
no longer changes.
In order to run the PVT compensation closed-loop system, you must have the prescribed external
resistor connected to the ZQ pin.
Test Methodology DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
3.3 Solution Testing
The main method of testing connectivity of the entire solution is through the use of a relatively small
functional test vector set. This will be performed by the ITM and SSTL functional test vectors.
Low-speed testing with the DLLs bypassed will give a good measure of output time matching of the clock,
strobe, address/ command, and data signals taking into account the system reference clock distribution to
the DLLs, the ITM clock distribution, the ITM output circuitry, and the SSTL output circuitry. At-speed
functional testing will also allow output time matching checks to be performed, and will allow the phase
relationships of the clock and data signals to be verified.
Where possible, testing the solution at-speed with a select set of functional test vectors provides a good
degree of testing. When at-speed is not possible, defaulting to partial at-speed if the ATE platform is capable
of operating within the normal operating range of the system with the DLL enabled will still provide a
higher level of testing than low-speed functional test alone. Normally some level of low-speed functional
test vectors are required to supplement the at-speed or partial at-speed tests to achieve a high overall test
coverage.
For ATE platforms that cannot support at-speed testing due to the double data rate bandwidth (i.e. 250MHz
clock = 500Mbps data rate), 2-pass testing could be an option. The data stream can be created such that it
only switches once per clock cycle instead of twice per clock cycle. This is done by driving the same data
twice. For example, one set of test vectors would transition data in the first bit period and drive that same
data in the second bit period. The second set of test vectors would transition data in the second bit period
and drive that same data in the following first bit period. Most ATE platforms today support pin muxing
and/or pattern muxing which allow an effective doubling of the test rate, permitting at a minimum partial-
at speed testing with or without a 2-pass test methodology.
While performing at-speed or partial at-speed testing it is recommended to apply different forms of noise
patterns and observe the response. The greatest amount of noise in the interface solution is created by the
output drivers. Testing with data patterns of very low switching activity (i.e. 1 bit switching) and data
patterns of high switching activity (i.e. all outputs switching 0-1-0-1 simultaneously) is an excellent test for
noise impact.
At-speed testability is supported through the PUBL. Refer to the DesignWare Cores DDR1/2/3 SDRAM PHY
Utility Block (PUBL) Databook.
SolvNet
DesignWare.com
4
Timing and Clocking
Clocking Overview on page 36
Command/Data To ITMs on page 37
Command/Data To SDRAMs on page 37
Read Data From SDRAMs on page 38
Communication with ASIC Logic on page 38
Timing and Clocking DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
4.1 Clocking Overview
The interface and control solution is based on the use of DLLs in conjunction with ITMs to manage the
critical timing relationships at the external interface. The architecture naturally places timing priority on the
external interface. The PHY is designed such that interface timing is correct by construction. Once
placement of the Lane components (I/O, ITM, DLL) is complete, there are no timing closure issues or static
timing analysis required for the PHY portion of the interface. The general control logic RTL is designed such
that synthesis/place & route and timing closure will not pose a challenge even at a clock rate of 533MHz.
There are only two timing relationships of focus to complete the implementation passing data from the
general control logic to the ITMs, and communication between the customers ASIC logic and the Memory
Controller host port logic.
Figure 4-1 provides a block diagram of the clock architecture for the solution to be used for discussion
purposes, assuming the DWC memory controller is implemented. Please refer to the component databook
for actual port names.
Figure 4-1 Solution Clocking Overview
Q D
Q D
Q D
Q D
ITM
Q D
Q D
Q D
Q D
Q D
Q D
System Clock
Synthesized
Clock Tree
Controller
D
Q
/
D
M
A
D
D
R
/
C
M
D
/
C
K
/
C
K
_
b
ITM
ITM
DQSb_90
CLK
CCLK_0
CLK_0
CLK_90
CLK_180
CLK_270
DQS_90
MSDLL
Memory
D
Q
S
/
D
Q
S
_
b
DQS_b DQS
MDLL
CCLK_0
CLK_0
CLK_90
CLK_180
CLK_270
CLK
A
D
D
R
/
C
M
D
/
D
A
T
A
f
o
r
c
l
o
c
k
c
r
o
s
s
i
n
g
l
o
g
i
c
t
o
c
h
i
p
l
o
g
i
c
D
A
T
A
f
r
o
m
c
h
i
p
l
o
g
i
c
C
o
n
f
i
g
A
D
D
R
/
C
M
D
/
D
A
T
A
f
r
o
m
/
t
o
c
h
i
p
l
o
g
i
c
ITM
rclk
DDR multiPHY for SMIC40LL25 Databook Timing and Clocking
SolvNet
DesignWare.com
The system clock is the reference clock for the interface, which can operate at up to 533MHz. The system
clock may be provided externally or from an on-die source. Each Lane contains a dedicated DLL (MDLL,
MSDLL) which is used to create clock phases used for PHY timing management. The clock phases produced
are 0, 90, 180, and 270 degrees. The customer distributes the system clock to the DLL in each Lane. The
customer should ensure that this distribution has a relatively low skew (<100ps).
These four phase outputs from the DLL are connected to the ITM segment. The ITM library components
have embedded clock distribution. The DLL outputs are normally connected to the ITM clock distribution
by abutment. This completes the correct-by-construction assembly for the PHY output timing path. The ITM
components use these phases to automatically format all timing to the SDRAMs.
The DLL has a non-zero insertion delay. To permit a fully deterministic timing relationship for
communication from the controller to the ITM, the DLL provides two matched 0 degree outputs, referred to
here as clk_0 & cclk_0. The customers physical design team utilizes cclk_0 to generate the synthesized clock
tree for the controller logic, while clk_0 is connected to the ITM distribution. The MDLL within the
Command Lane is used for this purpose. Clock insertion is discussed further in the next section.
4.2 Command/Data To ITMs
The ITM captures data from the controller using clk_0. The controller drives data to the ITM directly from a
register with no intermediate logic. This allows a full clock cycle, ideally, to get from the control logic to the
ITM. The timing path from controller to ITM is analyzed in STA including the insertion delay of the two
clock trees (controller clock and clk_0). Due to the custom nature of the ITM clock distribution, the insertion
delay of clk_0 will be very small (as in, <500ps). The insertion delay of the controller clock will be larger due
to the increased area, increased number of registers, and clock tree synthesis. The designer must ensure the
insertion delay of the synthesized clock tree is not excessively large as to prevent proper controller to ITM
communication, which would be flagged as failing timing paths in STA. The following is a time budget
estimation to estimate an acceptable insertion delay for the controller clock. This same analysis should be
performed by the designer for the specific memory controller option, process node, design libraries, and
chosen clocking strategy.
4.3 Command/Data To SDRAMs
As mentioned previously the ITM, in conjunction with the DLL, formats all timing to the SDRAMs. The data
and data mask signals to the SDRAM operate at double data rate. The address and command signals to the
SDRAM operate at single data rate, or double data rate if LPDDR2 is enabled through the Timing Mode
Select Line (tmsel) signal.
4.3.1 Single Data Rate
The address and command lines are commonly more heavily loaded than data lines due to data width
expansion (multiple memory devices to create a wide word width). The PHY maximizes system timing
margins by centering the clock or strobe signal in the associated data eye. The DQS/DQS_b are offset 90
degrees from the DQ/DM. The CK/CK_b are offset 180 degrees from the address and command signals.
This results in the PHY providing to the SDRAM an ideal tSU/tHD time of 90 degrees for DQ/DM and 180
degrees for address and command. This ideal will be reduced in the actual application at the SDRAM input
pins due to various offsets and disturbances such as PCB trace matching and PCB crosstalk. Figure 4-2
shows the relative timing produced at the PHY outputs for driving the SDRAMs.
SolvNet
DesignWare.com
Figure 4-2 Output Signal Timing from PHY for SDRAM Interfacing
4.3.2 Double Data Rate
The address and command lines are commonly more heavily loaded than data lines due to data width
expansion (multiple memory devices to create a wide word width). LPDDR2 uses double data rate on the
address and command lines. LPDDR2 is enabled through the Timing Mode Select Line (tmsel) signal.
For more information, refer to ITMs for Command Lane on page 117.
4.4 Read Data From SDRAMs
During a Read command, the SDRAMs output the DQS/DQS_b and DQ edge aligned. The slave DLLs
(mirror delay lines) within the MSDLL at each byte lane are used to shift the incoming DQS/DQS_b strobes
by 90 degrees to place them into the center of the data eye for capture of the DQ. In order to permit
customers to fine-tune the relationship of the shifted DQS and the data eye at the capturing ITM, per-byte
timing adjustment is included in both the MSDLL and the ITMs. In addition, per-bit timing adjustability is
included in the ITMs.
After capturing the read data, it is entered into a FIFO within the ITM. A data valid flag is supplied by the
ITM to indicate to the controller when it can fetch the data. This permits an asynchronous crossing of the
DQS clock domain back to the controller clock domain, removing timing constraints on this path. The
synthesized controller clock tree will connect to the ITMs for reading of the FIFOs. Communication from the
ITM back to the controller is direct register to register. There are no special clocking requirements on this
Read path, standard synthesis, place & route, and STA methods are used.
Due to inherent system-level skews between data bits within a byte lane, it is possible that the controller
may see the valid flags asserted for some data bits at the end of one controller clock cycle and the remaining
data bit valid flags asserted at the beginning of the next clock cycle. This is permitted. The controller
performs a logical AND of all data bit valid flags within a byte lane, and when all are asserted it
immediately fetches the data. The ITM is designed to permit such timing behavior.
Due to inherent system-level skews between byte lanes, it is possible that the controller may see the valid
flag asserted from some byte lanes at the end of one controller clock cycle and the remaining byte lane valid
flags asserted at the beginning of the next clock cycle. This is permitted. The controller will independently
fetch data from each byte lane when all bits of the lane are available, and then aligns the captured data from
each byte lane before further processing the captured read data.
4.5 Communication with ASIC Logic
At the host ports, communication between the controller and the ASIC logic is synchronous to the controller
clock domain. In most instances the memory interface is designed to operate at a different clock rate than
DDR multiPHY for SMIC40LL25 Databook Timing and Clocking
SolvNet
DesignWare.com
the asic logic, at an adjustable clock rate versus the ASIC logic, or the various host ports are required to
operate at different clock rates. In these circumstances the designer is to add clock domain crossing logic
external to the controller host ports. A port is added to the controller interface to provide a convenient
connection point to the controller clock for the ASIC chip logic to be used for clock crossing logic.
Additional discussion of clock crossing at the controller/ASIC logic interface can be found in the memory
controller databook.
In instances where the chip logic interfacing with host ports is to operate at the same clock rate as the
memory controller and clock crossing logic is not desired, direct communication is accommodated. If there
is a relatively small amount of chip logic, it is possible to drive it directly from the clock output provided for
clock domain crossing logic, and this branch would be taken into account during normal clock tree
synthesis such that all points are within the user-defined clock skew parameters.
If there is a large amount of chip logic that may make the total insertion delay of the controller clock too
great to ensure proper timing to the ITMs, the clock output for clock crossing could be treated as the root for
a second pass of clock tree synthesis for the chip logic, paying attention to ensure the insertion delay to the
chip logic permits proper communication to and from the controller logic.
Figure 4-3 on page 39 provides a brief look at this scheme.
Figure 4-3 Direct Communication with ASIC Logic
In this scheme the controller logic clock is synthesized such that the CLKOUT path is constrained with a
lower insertion delay than the rest of the tree endpoints. This leaves timing margin for the subsequent chip
logic clock tree synthesis.
The following example in Table 4-1 on page 40 shows the collective insertion delay of the chip logic versus
the insertion delay to the controller logic registers results in a large setup time margin but a low hold time
margin. In this case the hold margin can easily be raised by allowing the optimization tool to add buffers in
the DOUT path.
SolvNet
DesignWare.com
A further option for direct communication between the chip logic and the controller host port logic involves
multi-pass clock tree insertion. In this scenario the asic logic and the memory interface and control solution
are treated as separate logical entities. A clock tree is synthesized for the chip logic. Separately the clock
system for the memory controller is developed, as a cclk_0-based timing system as previously described.
Once the insertion delay for the memory controller logic clock (including DLL) and the chip logic clock are
known, a top-level balancing using the clock tree synthesis tool is performed. The designer must take into
account the varying delay of the DLL based on clock frequencies and operating mode. Also the designer
must be aware that the two clock paths will have different logical structures, and timing must be well
margined to allow for PVT variances. The designer must apply great attention to detail in timing analysis to
ensure the system works properly and is adequately margined. This method of clock balancing is not
recommended for most scenarios.
Additional clocking examples for direct communication when there is a large ASIC clock insertion
requirement include use of DLLs and/or PLLs between the controller clock domain and the ASIC clock
domain to effectively zero-out the insertion delay of the ASIC clock domain. This method of clocking can be
applicable in many situations.
Customers are encouraged to discuss their clocking requirements with Synopsys in order to plan the most
appropriate clocking strategy for the application.
Table 4-1 Insertion Delay Example
Reviewing the DIN path
Delay
Insertion delay of Controller logic clock to CLKOUT 0.300 ns
Insertion delay of chip logic clock 0.200 ns
Chip logic register clock to data out 0.200 ns
Routing delay 0.150 ns
Controller register setup time requirement 0.150 ns
Total time required 1.000 ns
Clock cycle @ 533 MHz 1.875 ns
Setup Time Margin 0.875 ns
Reviewing the DOUT path
Data
Insertion delay of Controller logic clock to register 1.00 ns
Controller logic register clock to data out 0.20 ns
Routing delay 0.15 ns
Total Data Path 1.35 ns
Clock
Insertion delay of Controller logic clock to CLKOUT 0.30 ns
Insertion delay of chip logic clock 1.15 ns
Total Clock Path 1.45 ns
Hold Chip logic register hold time requirement -0.10 ns
Hold Time Margin 0.00 ns
SolvNet
DesignWare.com
5
Timing Diagrams
The following timing diagrams provide an example of timing between the customers ASIC logic and the
Memory Controller logic, the Memory Controller logic and the PHY (Controller to/from ITM), and the
external interface between the PHY I/O pins and the SDRAMs.
Figure 5-1 on page 42 shows Write timing assuming:
DWC Universal Memory Controller is implemented
DDR2 device type
Burst length 4
CAS latency 4
Additive CAS latency 0
Row being accessed is already open (page hit)
For clarity, the timing diagram assumes a data width of 1 bit. In actual use, the minimum data width is 8
bits.
Figure 5-2 on page 43 shows Read timing assuming:
DWC Universal Memory Controller is implemented
DDR2 device type
Burst length 4
CAS latency 4
Additive CAS latency 0
Row being accessed is already open (page hit)
Active windowing mode used for DQS gating
For clarity, the timing diagram assumes a data width of 1 bit. In actual use, the minimum data width is 8
bits.
Timing Diagrams DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
Figure 5-1 Write Timing, DDR2, Burst of 4, CL=4, AL=0
rqvld
rdy
cmd
a
d
cclk
D[1:0] D[3:2]
A
WRITE
sdr_a
sdr_cas_b
sdr_we_b
sdr_odt
sdr_ds_oe_0
sdr_ds_oe_1
sdr_do
sdr_d_oe
D[1:0] D[3:2]
A
CK
CK_b
CMD
ADDR
DQS
DQS_b
DQ
P
H
Y
/
S
D
R
A
M
I
n
t
e
r
f
a
c
e
C
o
n
t
r
o
l
l
e
r
/
P
H
Y
I
n
t
e
r
f
a
c
e
A
S
I
C
/
C
o
n
t
r
o
l
l
e
r
I
n
t
e
r
f
a
c
e
NOP NOP WRITE
D[0] D[1] D[2] D[3]
A
NOP
DDR multiPHY for SMIC40LL25 Databook Timing Diagrams
SolvNet
DesignWare.com
Figure 5-2 Read Timing, DDR2, Burst of 4, CL=4, AL=0
D[1:0] D[3:2]
D[1:0] D[3:2]
NOP
10
sdr_a
sdr_cas_b
sdr_dqs_en
sdr_dqs_dis
sdr_valid
sdr_di[1:0]
sdr_read
A
CK
CK_b
CMD
ADDR
DQS
DQS_b
DQ
P
H
Y
/
S
D
R
A
M
I
n
t
e
r
f
a
c
e
NOP NOP READ
A
NOP
rqvld
rdy
cmd
a
qvld
cclk
q
A
S
I
C
/
C
o
n
t
r
o
l
l
e
r
I
n
t
e
r
f
a
c
e
READ
A
D[2] D[3] D[0] D[1]
phase_sel[1:0]
C
o
n
t
r
o
l
l
e
r
/
P
H
Y
I
n
t
e
r
f
a
c
e
10 10
Timing Diagrams DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
SolvNet
DesignWare.com
6
Interface and Control Solution Connectivity
Figure 6-1 on page 46 shows an example of connectivity both within the Command Lane PHY components
and between the PHY components and the Memory Controller. To reduce the figure for clarity, one
example of each different connectivity type has been shown, which are CK output, CK_b output, an active-
high output (A[0]), and an active-low output (RAS_b). ITM buffer cells have not been shown in this figure.
Please refer to ITM Library for detailed descriptions of the ITM library components.
Figure 6-2 on page 48 shows an example of connectivity both within the Byte Lane PHY components and
between the PHY components and the Memory Controller. The example assumes a 32-bit data interface to
the external SDRAMs. The example shown is Byte Lane 0 consisting of DQ[7:0]. To reduce the figure for
clarity, one example of each different connectivity type has been shown, which are DQS bi-direct, DQS_b bi-
direct, a data bi-direct (DQ[0]), and the tri-state data mask output (DM). The ITM buffer cell has not been
shown in this figure. Please refer to ITM Library for detailed descriptions of the ITM library components.
The connectivity between each memory controller option and the customers ASIC logic is presented in
detail in the Memory Controller databook.
Note that the DLL test outputs have been shown connecting directly to dedicated test outputs, however as
described previously it is recommended to share a single set of dedicated test outputs for all DLLs of the
PHY through proper signal muxing / selection.
The SSTL I/Os include embedded boundary scan support logic to facilitate customer insertion of boundary
scan logic in the chip. Placeholders for these connections are shown in the following figures. It is the
customers responsibility to properly connect boundary scan, or to properly tie-off the boundary scan logic if
not used. More detailed information on the boundary scan support logic can be found in the SSTL I/O
Library.
Interface and Control Solution Connectivity DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
Figure 6-1 Command Lane PHY Connectivity Detail

1'b1
1'b1
1'b1
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b1
1'b1
abut clocks
abut clocks
io_oe
io_do
io_di
do_rst_b
do_set_b
di
dout[1]
dout[0]
oe
MSD_ITMC
abut clocks
abut clocks
io_oe
io_do
io_di
do_rst_b
do_set_b
di
dout[1]
dout[0]
oe
MSD_ITMC
abut clocks
abut clocks
io_oe
io_do
io_di
do_rst_b
do_set_b
di
dout[1]
dout[0]
oe
MSD_ITMC
OE
IDDQ
TE
DI
DOUT
PAD
DJ
OJ
SJ
DT
ET
P
D
D
R
I
O
OE
IDDQ
TE
DI
DOUT
PAD
DJ
OJ
SJ
DT
ET P
D
D
R
I
O
AE
AT
PAD
P
A
I
O
MSD_MDLL_DDR
t
e
s
t
_
o
u
t
_
d
[
0
]
t
e
s
t
_
o
u
t
_
a
clk_in
bypass
dll_ctrl[51:0]
srstb
rst_b
clk_0
clk_90
clk_180
clk_270
cclk_0
t
e
s
t
_
o
u
t
_
d
[
1
]
A[0]
CK
CK_b
RAS_b
t
o
M
S
D
_
I
T
M
C
B
0
dll_ato
dll_dto[0]
PUBL or
cmd_dll_ctrl[51:0]
cmd_dll_bypass
only bit[0] shown, bit[1] to be similar
clk
sdr_a[0]
sdr_ras_b
reference clock from customer
DLL soft reset from customer
system reset from customer
1. Reference clock distributed to all DLLs in PHY
2. Suggest DLL soft reset per DLL in PHY, registered or signal
3. The PDDRIO pins SJ/OJ/DJ/ET/DT support customer insertion of boundary scan
Notes:
OE
IDDQ
TE
DI
DOUT
PAD
DJ
OJ
SJ
DT
ET
P
D
D
R
I
O
OE
IDDQ
TE
DI
DOUT
PAD
DJ
OJ
SJ
DT
ET
P
D
D
R
I
O
OE
IDDQ
TE
DI
DOUT
PAD
DJ
OJ
SJ
DT
ET P
D
D
R
I
O
abut clocks
abut clocks
io_oe
io_do
io_di
do_rst_b
do_set_b
di
dout[1]
dout[0]
oe
MSD_ITMC
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
io_cmd_iddq
io_cmd_odt
1'b0
io_test_oe
MCTL or
PCTL
DDR multiPHY for SMIC40LL25 Databook Interface and Control Solution Connectivity
SolvNet
DesignWare.com
Interface and Control Solution Connectivity DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
Figure 6-2 Byte Lane PHY Connectivity Detail
1'b1
1'b1
1'b1
1'b1
1'b1
1'b0
1'b1
1'b0
1'b1
1'b0
1'b1
1'b1
1'b1
1'b1
t
o
M
S
D
_
I
T
M
B
B
1'b0
1'b1
io_oe
io_do
io_di_0
dqs_dis_polarity
dqs_drift[1:0]
ddr_mode
dqs_dis
dqs_config
phase_sel[1:0]
dqs_en
dqs
dout[0]
dout[1]
oe[0]
rst_b
srst_b
oe_set_b
oe_rst_b
do_set_b
do_rst_b
abut clocks
abut clocks
MSD_ITMS
oe[1]
dqs_trm[2:0]
OE
IDDQ
TE
DI
DOUT
PAD
PDIFF
DT
ET
DJ
OJ
SJ
OE
IDDQ
TE
DI
DOUT
PAD
PDDRIO
DT
ET
DJ
OJ
SJ
OE
IDDQ
TE
DI
DOUT
PAD
PDDRIO
DT
ET
DJ
OJ
SJ
t
e
s
t
_
o
u
t
_
d
[
0
]
t
e
s
t
_
o
u
t
_
a
clk_in
bypass
dll_ctrl[51:0]
srstb
rst_b
clk_0
clk_90
clk_180
clk_270
t
e
s
t
_
o
u
t
_
d
[
1
]
dqs_90
dqsb_90
dqsb
dqs
cclk_0
MSD_MSDLL_DDR
io_oe
io_do
io_di
di_trm[3:0]
valid
read
rclk
di[1]
dout[0]
dout[1]
oe[0]
rst_b
srst_b
oe_set_b
oe_rst_b
do_set_b
do_rst_b
abut clocks
abut clocks
MSD_ITMD
oe[1]
di[0]
AE
AT
PAD
PAIO
io_oe
io_do
io_di
di_trm[3:0]
valid
read
rclk
di[1]
dout[0]
dout[1]
oe[0]
rst_b
srst_b
oe_set_b
oe_rst_b
do_set_b
do_rst_b
abut clocks
abut clocks
MSD_ITMD
oe[1]
di[0]
io_oe
io_do
io_di_0
dqs_dis_polarity
dqs_drift[1:0]
ddr_mode
dqs_dis
dqs_config
phase_sel[1:0]
dqs_en
dqs
dout[0]
dout[1]
oe[0]
rst_b
srst_b
oe_set_b
oe_rst_b
do_set_b
do_rst_b
abut clocks
abut clocks
MSD_ITMS
oe[1]
dqs_trm[2:0]
OE
IDDQ
TE
DJ
DOUT
PAD
PDDRIO
DT
ET
DJ
OJ
SJ
0'b1
DQS
dll_dto[0]
dll_ato
DQS_b
DM
DQ[0]
PUBL or
byte_dll_bypass[0]
dll_ctrl[51:0]
io_byte_iddq[0]
clk
sdr_read[0]
sdr_d_oe[0]
sdr_do[32]
sdr_do[0]
sdr_di[32]
sdr_valid[0]
di_trm[3:0]
itm_srst_b
io_test_oe
sdr_dm[1]
sdr_dm[0]
system reset from customer
DLL soft reset from customer
reference clock from customer
sdr_ds_oe_1[0]
sdr_ds_oe_0[0]
sdr_dqs_en[0]
phase_sel[1:0]
dqs_config
dqs_drift[1:0]
only bit[0] shown, bit[1] to be similar
sdr_dqs_dis[0]
ddr_mode
dqs_b_trm[2:0]
dqs_b_drift[1:0]
dqs_trm[2:0]
Notes:
1. Reference clock distributed to all DLLs in PHY
2. Suggest DLL soft reset per DLL in PHY, registered or signal
3. The PDDRIO and PDIFF pins SJ/OJ/DJ/ET/DT support customer insertion of boundary scan
sdr_di[0]
io_odt[0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
ZIOH[63:0]
io_odt[1]
OE
IDDQ
DI
DOUT
PAD
PDIFF
DT
ET
DJ
OJ
SJ
TE
MCTL or
PCTL
SolvNet
DesignWare.com
7
External Memory Configuration
Figure 7-1 provides a basic example of how the DDR2/3-Lite/mDDR is connected to DDRn SDRAMs. Two
SDRAM ranks using SDRAMs with 16-bit I/O width are shown. This illustrates how the interface is used
when multiple smaller size SDRAMs are used for both width and depth expansion. Note that the address
and command signals connect to every device and are thus heavily loaded compared to other signals. The
PHY provides extra timing margin on these signals versus, for example, the DQ signals to permit high clock
rates under varying system configurations. This example shows the importance of the recommendation to
avoid memory configurations based on 4 bit memory devices. Refer to the memory vendors datasheets and
application notes for actual port names and additional system design recommendations.
Figure 7-1 DDRn System Configuration Brief Example
External Memory Configuration DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
SolvNet
DesignWare.com
8
DLL Library
DLL Library Overview on page 52
Master DLL for DDRn (MSD_MDLL_DDR) on page 54
Master-Slave DLL for DDRn MSD_MSDLL_DDR on page 61
Mobile DDR on page 70
DLL DC and AC Characteristics on page 71
Working with SDRAM Jitter Specifications on page 76
DLL Library DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
8.1 DLL Library Overview
The chapter describes the Synopsys DDRn SDRAM interfacing DLL (Delay Locked Loop) library. The
library is designed specifically to support the complex interfacing requirements of SDRAM devices as
described in the JEDEC specifications for Mobile DDR/ DDR2/DDR3/LPDDR2 SDRAMs. Operating range
of the library components is 100 MHz to 533 MHz, permitting a 533-MHz memory system operating in
double-data rate mode to provide a 1066-Mb/s per pin data rate.
Figure 8-1 shows the DDR2/3-Lite/mDDR, Memory Controller, and related components.
Figure 8-1 DesignWare Cores DDRn SDRAM PHY and Control Solution
8.1.1 Key Features
The Synopsys DDR2/3-Lite/mDDR DLL includes the following features:
Locked operating range of 100MHz to 533MHz permits interfacing to various speed grades of
Mobile DDR/ DDR2/DDR3/LPDDR2 SDRAMs
Bypass operating modes permit support of Mobile DDR SDRAMs from DC to 200MHz, as well as
low-speed functional and IDDQ tests
Multi-phase outputs: 0, 90, 180, 270
Master/Slave DLL approach for complex timing applications while reducing total power
consumption and area
Master DLL component for SDRAM command generation and general host timing
Master-Slave DLL component for SDRAM write data generation and read data capture
Generous offering of DLL adjustability to facilitate timing system fine-tuning
Analog and digital DLL test outputs provided for device characterization
D
L
L
D
L
L
D
L
L
C
o
n
t
r
o
l
L
o
g
i
c
I
T
M
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
I
T
M
S
e
g
m
e
n
t
I
T
M
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
S
S
T
L
S
e
g
m
e
n
t
Byte
Lane
PHY
DQ/DQS
To/From
SDRAM
Command
Lane PHY
ADDR/CMD/CK
To SDRAM
Byte
Lane PHY
DQ/DQS
To/From
SDRAM
To/From
ASIC Logic
DDR multiPHY for SMIC40LL25 Databook DLL Library
SolvNet
DesignWare.com
8.1.2 Process Information
The following table shows the process information of the DLL.
Notes:
1. Please contact your sales representative for availability in alternate process nodes/variants.
8.1.3 Metal Layer Usage
The DLL components use the first four metal layers of the process. The 4th metal layer is a shield layer,
allowing the customer to route above the DLL components in all remaining metal layers of the process. The
DLL is designed assuming the first four metal layers of the process are thin.
8.1.4 Deliverables
Deliverables, as shown in Table 8-2, include all views required to support a typical ASIC design flow.
8.1.5 Cell List
Table 8-3 shows the cell list of the DLL.
Table 8-1 DLL Process Information
Foundry Process Variant Core Voltage I/O Oxide Dielectric Metal Layers
SMIC 40nm LL 1.2V 2.5V low-K 5 or more
Table 8-2 DLL Deliverables
Behavioral Verilog
Timing Synopsys lib
Layout Abstract LEF
Detailed Layout GDSII
LVS Netlist SPICE
Documentation Databook, Implementation Guide
Table 8-3 DLL Cell List
Cell Name Description
MSD_MDLL_DDR Master DLL with 0, 90, 180, 270 clock phase outputs
MSD_MSDLL_DDR Master DLL with 0, 90, 180, 270 clock phase outputs, and two slave delays for 90
data strobe delay
SolvNet
DesignWare.com
8.2 Master DLL for DDRn (MSD_MDLL_DDR)
The Synopsys Master DLL for Mobile DDR/
DDR2/DDR3/LPDDR2 applications
(MSD_MDLL_DDR) is a Delay Locked Loop
that takes an input reference clock (clk_in) and
generates four clock outputs, each delayed in
quarter clock cycle (90) increments. These four
clock phases (clk_0, clk_90, clk_180, clk_270)
can be generated with very high accuracy and
low jitter across a wide range of frequencies.
Utilizing self-bias techniques, the
MSD_MDLL_DDR offers superior noise
immunity and precision. One clock period is
locked in the delay line, resulting in simpler
start control, easier phase tapping, less chances
of false lock, and a shorter delay line. The
shorter delay line permits lower operating
current, less jitter, and smaller area.
The MSD_MSDLL_DDR has internal power
decoupling and filtering for improved power supply noise rejection. Embedded power and ground
decoupling circuits help reduce supply noise caused by surrounding circuitry. This decoupling and filtering
allows the DLL to be integrated into a design without a need for a dedicated VDD_DLL or ground supply.
A number of test modes and configuration settings are included:
A bypass mode shuts down all analog circuitry, and directly buffers the input clock and strobes with
appropriate delays and inversions to the output clocks and strobes. This mode can be used for low
speed functional or IDDQ testing.
A digital test output (test_out_d) provides direct observability of several internal reference clock and
timing nodes.
An analog test output (test_out_a) provides direct observability of several internal reference
voltages.
The primary application for MSD_MDLL_DDR is a DDRn Command Lane PHY with Synopsys Interface
Timing Modules (ITMs). The design and layout has been optimized for very tight integration with the ITM
macrocells in a Command Lane architecture. Figure 8-2 illustrates the Master DLL.
Figure 8-2 Master DLL (MSD_MDLL_DDR)
SolvNet
DesignWare.com
8.2.1 Pin List
Table 8-4 provides the pin list of the Master DLL.
Table 8-4 MDLL Pin List
Pin Name Direction Description
General
Inputs
clk_in input Input reference clock
bypass input
DLL bypass. Active high.
When bypass is 1 (enabled), DLL locking and delay line circuitry is
bypassed and disabled, and output clocks are generated as buffered
versions of the input reference clock.
When bypass is 0 (disabled), DLL locking circuitry is enabled, and
output clocks are generated with proper phase relationships through the
normal delay paths.
rstb input
Asynchronous reset. Active low.
When rstb is 0, internal capacitors are charged to default values and
delay line circuitry is disabled.
srstb input
Asynchronous soft reset. Active low.
When srstb is 0, internal capacitors are charged to default values and
delay line circuitry is disabled.
dll_ctrl[51:0] input
DLL trim and test configuration controls. See Master DLL Control for
Trim and Test on page 56 for details.
Reference
Clock
Outputs
clk_0 output Output clock
clk_90 output Output clock, shifted 90from clk_0
cclk_0 output Buffered copy of clk_0
Test Outputs
test_out_d[1:0] output Digital test output
test_out_a output Analog test output
Supply
MVDD input Power
MVSS input Ground
SolvNet
DesignWare.com
8.2.2 Master Cell Size
8.2.3 Master DLL Control for Trim and Test
The performance and testing of the MDLL can be accessed through the dll_ctrl bus, as provided in Table 8-6.
The following sections provide an overview of the various trim and test features but the material is not
intended to be comprehensive. It is recommended that control buses be configurable for trim and test but
the default suggestions should be used. Should these features need to be investigated once a design has a
prototype, please contact Synopsys support resources for more information.
Table 8-5 Master Cell Size
Width 385um
Height 80.8um
Table 8-6 Trim and Test MDLL Control
Static Input Field Description See
dll_ctrl [1:0] Reserved
[4:2] ipump_trm[2:0] Charge pump current trim
Section 8.2.3.1
(page 57)
[5] test_ctrl_en Test control enable for analog and digital test outputs
Section 8.2.3.3
(page 58)
Section 8.2.3.2
(page 57)
[8:6] test_ctrl_d[2:0]
Digital test control. Selects the digital signal to be
viewed at the digital test output
[10:9] test_ctrl_a[1:0]
Analog test control. Selects the analog signal to be
viewed at the analog test output
[11] Reserved
[14:12] bias_trm[2:0] Bias generator frequency trim
Section 8.2.3.4
(page 58)
[19,15] fdtrm[1:0] Bypass mode fixed delay trim
Section 8.2.4
(page 59)
[18:16] bias_trm[6:4] Bias generator control voltage trim
Section 8.2.3.5
(page 58)
[22:20] Reserved
[23] bps200 Bypass frequency select
Section 8.2.4
(page 59)
[28:24] Reserved
[29] Reserved
[37:30] Reserved
[43:38] fb_trm[5:0] Feedback delay adjust
Section 8.2.3.5
(page 58)
SolvNet
DesignWare.com
8.2.3.1 Charge Pump Current Trim
The charge pump current trim capability can be used in the event that an adjustment is desired in the lock
time of the DLL. Characteristics of the DLL that may warrant an adjustment of this trim value include the
inability to lock or drifting in and out of lock, which can be determined by viewing the phase alignment of
the output clocks. These inputs can be set to any value between 000(binary) and 111(binary).
8.2.3.2 Digital Test Control
Table 8-7 shows the digital test control information for the DLL.
Notes:
1. Bits [2:0] select signal to be viewed at test_out_d[1]. test_out_d[0] will output clk_0 when enabled by test_ctrl_en.
[49:44] Reserved
[50] test_hizb_a Analog test output tri-stated control
Section 8.2.3.3
(page 58)
[51] Reserved
Field Setting Function Suggested Default
ipump_trm[2:0]
000 Maximum current
000
111 Minimum current
Table 8-7 DLL Digital Test Control
test_ctrl_en test_ctrl_d[2:0] Function Suggested Default
0 XXX digital test outputs disabled (drive '0')
0, 000
1 000 0output clock (clk_0)
1 100 360internal clock (clk_360_int)
1 101 Speed-up pulse (spdup)
1 110 Slow-down pulse (slwdn)
1 111 Asic output clock (cclk_0)
Table 8-6 Trim and Test MDLL Control (Continued)
Static Input Field Description See
SolvNet
DesignWare.com
8.2.3.3 Analog Test Control
Table 8-8 shows the analog test control information for the DLL.
8.2.3.4 Bias Generator Trim
The bias generator trim capability can be used to adjust the behavior of the bias voltages being supplied to
the delay line. Characteristics of the DLL that may warrant an adjustment of this trim value include the
inability to lock due to a slow clock (suggest decreasing Vc adjust), inability to lock due to fast clock
(suggest increasing Vc adjust) and increase noise margin on bias voltages (suggest decreasing Fmax
adjust).The bit fields described in the following table can be set to any value between 000(binary) and
111(binary).
8.2.3.5 Feedback Trim
The feedback trim capability can be used in the event that an adjustment is desired in the phase detector
feedback of the DLL. Characteristics of the DLL that may warrant an adjustment of this trim value include
non-optimal phase alignment. The lower 3 bits (2:0) are used for feed-back delay trimming and the upper 3
bits (5:3) are used for feed-forward delay trimming. The feed-back trimming is used to decrease total delay,
decreasing the amount of delay between phase outputs. The feed- forward trimming is used to increase
total delay, increasing the amount of delay between phase outputs. For each 3-bit field, the inputs can be set
to any value between 000(binary) and 111(binary), as shown in Table 8-10.
Table 8-8 DLL Analog Test Control
test_hizb_a test_ctrl_en test_ctrl_a[1:0] Function Suggested Default
0 X XX Tri-state 0, 0, 00
1 0 XX MVSS
1 1 00 Replica bias output for PMOS (Vbp)
1 1 01 Replica bias output for NMOS (Vbn)
1 1 10 Filter output (Vc)
1 1 11 MVDD
Table 8-9 Bias Generator Trim
bias_trm[2:0]
000 Fmax trim: minimum adjust
111
111 Fmax trim: maximum adjust
bias_trm[6:4]
000 Vc level trim: minimum adjust
011
111 Vc level trim: maximum adjust
Table 8-10 MDLL Feedback Trim
fb_trm[5:3]
(feed-forward path)
000 Minimum additional delay
000
111 Maximum additional delay
SolvNet
DesignWare.com
8.2.4 Bypass Mode
The DLL has a bypass mode which allows phased clocks to be generated with analog locking circuitry
disabled. This mode may be used for low-speed functional testing and for IDDq testing. Bypass mode can
also be used when operating with Mobile DDR SDRAMs (see Section 8.4 on page 70). When bypass mode is
enabled, all analog circuitry is disabled, and all static current paths are shut down. Phased outputs are
generated during bypass with inverters and standard delays.
The absolute delay of clk_0, cclk_0, clk_90, clk_180 and clk_270 relative to clk_in in bypass mode is specified
in DLL DC and AC Characteristics on page 71. Bypass mode operation is not affected by the state of
rstb/srstb.
Bypass mode has two settings for the clk_90 delay to optimize it for two different frequency ranges.
Table 8-11 shows how to select these two ranges.
It is also possible to trim the 90-degree delay using the fdtrm control bits as shown in Table 8-12:
fb_trm[2:0]
(feed-back path)
000 Minimum additional delay
000
111 Maximum additional delay
Table 8-11 Bypass Mode Frequency Range
bps200
0 0 to 100MHz
0
1 0 to 200MHz
Table 8-10 MDLL Feedback Trim
clk90
clk180
clk270
clk0
clkin
SolvNet
DesignWare.com
8.2.5 MDLL Reset Operation
When reset is asserted and bypass is not asserted, the Master DLL output clocks are active with minimum
fix delay between various outputs.
8.2.6 MDLL Reset Requirements
Reset issued to the MSD_MDLL_DDR must always meet the following requirements:
1. Reset must always be asserted for a minimum of 50ns to ensure proper reset of the DLL.
2. On power-up, reset must be held for a minimum of 50ns after MVDD has been raised to its full
value.
3. After reset has been asserted and then de-asserted, a number of clock cycles must pass for the DLL to
achieve lock.
4. The input clock to the DLL must be stable for a minimum of 50ns before DLL reset is de-asserted.
The following additional requirements apply when transitioning to/from bypass mode:
1. There must be at least 50ns between reset de-assertion and DLL bypass mode entry.
2. The DLL bypass pin must be asserted for at least 1000ns.
3. Reset must always be issued after the DLL mode has changed from bypass to normal mode.
4. A minimum of 100ns is required between bypass de-assertion and reset assertion.
5. Reset must be issued whenever DLL control/trim/option input bits are modified, with the
exception of:
a. Analog/digital test controls
b. Slave DLL phase trim (if applicable).
Figure 8-3 shows the DLL reset requirements.
Table 8-12 fdtrm Control Bits
fdtrm[1:0]
00 nominal delay
00
01 nominal delay 10%
10 nominal delay + 10%
Note Note Note Note
Because both edges of clk_in are used to generate active edges of the output clocks, the duty cycle of
clk_in impacts the tBYPxxx timing values. An input duty cycle of 48%/52% or better is recommended.
SolvNet
DesignWare.com
Figure 8-3 DLL Reset Requirements
8.3 Master-Slave DLL for DDRn MSD_MSDLL_DDR
The Synopsys Master-Slave DLL for Mobile
DDR/ DDR2/DDR3/LPDDR2 applications
(MSD_MSDLL_DDR) is an integrated Delay
Locked Loop and a pair of slave delays.
The Delay Locked Loop (DLL) takes an input
reference clock (clk_in), and generates four clock
outputs, each delayed in quarter clock cycle (90)
increments. These four clock phases (clk_0,
clk_90, clk_180, clk_270) can be generated with
very high accuracy and low jitter across a wide
range of frequencies.
The slave delay pair uses timing reference from
the delay line to provide a highly accurate 90
delay to dqs and dqsb inputs (generating dqs_90
and dqsb_90 respectively).
Based on popular self-bias techniques, the
MSD_MSDLL_DDR offers superior noise
immunity and precision. One clock period is
locked in the delay line, resulting in simpler start
control, easier phase tapping, less chances of
false lock, and a shorter delay line. The shorter
delay line permits lower operating current, less jitter, and smaller area.
The MSD_MSDLL_DDR has internal power decoupling and filtering for improved power supply noise
rejection. Embedded power and ground decoupling circuits help reduce supply noise caused by
surrounding circuitry. This decoupling and filtering allows the DLL to be integrated into a design without a
need for a dedicated VDD_DLL or ground supply.
A number of test modes and configuration settings are included:
A bypass mode shuts down all analog circuitry, and directly buffers the input clock and strobes with
appropriate delays and inversions to the output clocks and strobes. This mode can be used for low
speed functional or IDDQ testing.
A digital test output (test_out_d) provides direct observability of several internal reference clock and
timing nodes.
An analog test output (test_out_a) provides direct observability of several internal reference
voltages.
Figure 8-4 Master-Slave DLL
SolvNet
DesignWare.com
The primary application for MSD_MSDLL_DDR is a DDRn Byte Lane PHY with Synopsys Interface Timing
Modules (ITMs). The design and layout has been optimized for very tight integration with the ITM
components in a Byte Lane architecture.
8.3.1 Master-Slave DLL Pin List
Table 8-13 shows the pin list of the Master-Slave DLL.
Table 8-13 MSDLL Pin List
General Inputs
clk_in input Input reference clock
bypass input
DLL bypass. Active high.
When bypass is 1 (enabled), DLL locking and delay line circuitry is bypassed and disabled, and
output clocks are generated as buffered versions of the input reference clock.
When bypass is 0 (disabled), DLL locking circuitry is enabled, and output clocks are generated
with proper phase relationships through the normal delay paths.
rstb input
Asynchronous reset. Active low.
When rstb is 0, internal capacitors are charged to default values and delay line circuitry is
disabled.
srstb input
Asynchronous soft reset. Active low. When srstb is 0, internal capacitors are charged to default
values and delay line circuitry is disabled.
dll_ctrl[51:0] input
DLL trim and test configuration controls. See MSDLL Control for Trim and Test on page 64 for
details.
Reference Clock Output
clk_0 output Output clock
cclk_0 output Buffered copy of clk_0.
Slave Delay I/O
dqs input Input to slave delay line #1
dqsb input Input to slave delay line #2
dqs_90 output Output of slave delay line #1. Nominal shift of 90(25% of the clk_in clock period)
dqsb_90 output Output of slave delay line #2. Nominal shift of 90(25% of the clk_in clock period)
Test Outputs
test_out_d[1:0] output Digital test output
test_out_a output Analog test output
SolvNet
DesignWare.com
8.3.2 MSDLL Cell Size
Power
MVDD input Power
MVSS input Ground
Table 8-14 MSDLL Cell Size
Width 385um
Height 130um
Table 8-13 MSDLL Pin List (Continued)
General Inputs
SolvNet
DesignWare.com
8.3.3 MSDLL Control for Trim and Test
The performance and testing of the MSDLL can be accessed through the dll_ctrl bus. Many of these controls
are the same as the MSD_MDLL_DDR, therefore, this section only describes the settings that are different.
Table 8-15 MSDLL Control for Trim and Test
Static Input Field Description
Default
Value
See
dll_ctrl
[1:0] Reserved
[4:2] ipump_trm[2:0] Charge pump current trim
Section 8.2.3.1
(page 57)
[5] test_ctrl_en
Test control enable for analog and digital test
output
Section 8.3.3.1
(page 65)
Section 8.3.3.2
(page 66)
[8:6] test_ctrl_d[2:0]
Digital test control. Selects the digital signal to
be viewed at the digital test output
[10:9] test_ctrl_a[1:0]
Analog test control. Selects the analog signal to
be viewed at the analog test output
[11] test_ctrl_switch
Test control switch. Selects the analog and
digital test signals of master or slave
[14:12] bias_trm[2:0] Master bias generator frequency trim
Section 8.2.3.4
(page 58)
[19,15] fdtrm[1:0] Master bypass fixed delay trim
Section 8.3.4
(page 68)
[18:16] bias_trm[6:4] Master bias generator control voltage trim
Section 8.2.3.4
(page 58)
[22:20] sl_bias_trm[2:0] Slave bias generator frequency trim
Section 8.2.3.4
(page 58)
[23] bps200 Bypass Frequency Select
Section 8.3.4
(page 68)
[26:24] sl_bias_trm[6:4] Slave bias generator control voltage trim
Section 8.2.3.4
(page 58)
[28:27] fdtrm_sl[1:0] Slave bypass fixed delay trim
Section 8.3.4
(page 68)
[29] lock_det_en Lock detector enable
Section 8.3.3.3
(page 66)
[31:30] Reserved
[37:32] sl_fb_trm[5:0] Slave feedback delay adjust
Section 8.2.3.5
(page 58)
[43:38] fb_trm[5:0] Master feedback delay adjust
[45:44] sl_bypass_start_up[1:0] Slave auto-startup bypass
Section 8.3.3.4
(page 67)
[49:46] sl_phase_trm[3:0] Slave phase lock trim
Section 8.3.3.5
(page 67)
[50] test_hizb_a Analog test output tri-stated control
Section 8.3.3.2
(page 66)
[51] dll_ctrl Locked loopback test mode select
Section 8.3.3.6
(page 68)
SolvNet
DesignWare.com
8.3.3.1 MSDLL Test Control
Table 8-16 shows the digital test control for the Master-Slave DLL.
Notes:
1. Bits [2:0] select signal to be viewed at test_out_d[1]. test_out_d[0] will output clk_0 when enabled by test_ctrl_en.
Table 8-16 MSDLL Digital Test Control
test_ctrl_en test_ctrl_switch test_ctrl_d[2:0] Function Suggested Default
0 X XXX digital test outputs disabled (drive '0') 0, 0, 000
1
0
000
0
o
output clock (clk_0)
1 001
90
o
1 010
180
o
1 011
270
o
1 100
360
o
internal clock (clk_360_int)
1 101 Master speed-up pulse (spdup)
1 110 Master slow-down pulse (slwdn)
1 111 Output clock (cclk_0)
1
1
000 Input signal dqs
1 001 Slave input clock reference (clk_90_in)
1 010 Slave internal feedback clock (clk_0_out)
1 011 Output signal dqsb_90
1 100 Output signal dqs_90
1 101 Slave speed-up pulse (spdup)
1 110 Slave slow-down pulse (slwdn)
1 111 Auto-lock enable signal
SolvNet
DesignWare.com
8.3.3.2 MSDLL Analog Test Control
Table 8-17 shows the analog test control for the Master-Slave DLL.
8.3.3.3 MSDLL Lock Detector Enable
This setting enables start of the slave DLL section after the master DLL section has reached lock.
Characteristics of the DLL that may warrant an adjustment of this trim value include the slave DLL delay
remaining in its reset state (minimum delay, much less than 90 degrees) after the DLL lock time provided in
DLL DC and AC Characteristics on page 71.
Table 8-17 MSDLL Analog Test Control
test_hizb_a test_ctrl_en test_ctrl_switch test_ctrl_a[1:0] Function
Suggested
Default
0 X X XX Tri-state 0, 0, 0, 00
1 0 X XX MVSS
1 1
0
00 Master Replica bias output for
PMOS (Vbp)
1 1 01 Master Replica bias output for
NMOS (Vbn)
1 1 10 Master Filter output (Vc)
1 1 11 MVDD
1 1
1
00 Slave Replica bias output for
PMOS (Vbp)
1 1 01 Slave Replica bias output for
NMOS (Vbn)
1 1 10 Slave Filter output (Vc)
1 1 11 MVDD
Table 8-18 MSDLL Lock Detector Enable
lock_det_en
0 Disable lock detector 0
1 Enable lock detector
SolvNet
DesignWare.com
8.3.3.4 Slave Auto-Startup Bypass
By default, the slave DLL automatically starts to lock during the time the master is locking, after the master
has begun to approach lock. This setting permits the user to manually start-up the slave DLL. To bypass the
automatic startup, this setting should be set to '10'. Once the specified number of clocks has passed for the
master DLL to achieve lock, the user sets this field to '11' to permit the slave DLL to startup. The user then
waits for the specified number of clocks for the slave DLL to lock before proceeding. Characteristics of the
slave DLL that might warrant a manual startup of the slave DLL include the inability for the slave DLL to
produce a consistent and/or correct phase difference between the input signal and the output signal.
8.3.3.5 Slave DLL Phase Trim
Selects the phase difference between the input signal and the corresponding output signal of the slave DLL.
This setting applies to the dqs to dqs_90 and dqsb to dqsb_90 paths. The nominal phase difference is 90
degrees. Users may elect to modify this value to account for factors external to the DLL, which require the
DLL to produce a delay of greater than or less than the nominal 90 degrees. When modifying the value of
these bits, the user does not need to issue a reset to the DLL but should wait the equivalent of the DLL lock
time before the slave DLL circuitry is used (such as, receiving Read data from an SDRAM) to ensure the
DLL has adequate time to stabilize with the new settings.
Table 8-19 Slave Auto_Startup Bypass
sl_bypass_start_up[1:0] Function Suggested Default
0X Slave DLL automatically starts up 00
10 Slave DLLs automatic startup is disabled; the phase detector is disabled
11 Slave DLLs automatic startup is disabled; the phase detector is enabled
Table 8-20 Slave DLL Phase Trim
sl_phase_trm[3:0] Phase Difference (degrees) Suggested Default
0000 90 0000
0001 72
0010 54
0011 36
0100 108
0101 90
0110 72
0111 54
1000 126
1001 108
1010 90
1011 72
1100 144
SolvNet
DesignWare.com
8.3.3.6 Locked Loopback Test Mode
This control bit is used to select the locked loopback test mode. In locked loopback test mode the MDLL
operates in normal locked mode while the SDLL generates a low dqs to dqs90 delay. This allows write data
to be looped back and captured in the receiver. Note that loopback test mode is not sensitive to the value of
rstb.
8.3.4 MSDLL Bypass Mode
The DLL has a bypass mode which allows phased clocks to be generated with analog locking circuitry
disabled. This mode may be used for low-speed functional testing and for IDDq testing. Bypass mode can
also be used when operating with Mobile DDR SDRAMs (see Section 8.4 on page 70). When bypass mode is
enabled, all analog circuitry is disabled, and all static current paths are shut down. Phased outputs are
generated during bypass with inverters and standard delays:
The absolute delay of clk_0, cclk_0, clk_90, clk_180 and clk_270 relative to clk_in in bypass mode is specified
in DLL DC and AC Characteristics on page 71. Bypass mode operation is not affected by the state of
rstb/srstb.
Bypass mode has two settings for the clk_90 delay to optimize it for two different frequency ranges.
Table 8-11 shows how to select these two ranges.
1101 126
1110 108
1111 90
Table 8-21 Locked loopback test mode select
lltm Function Suggested Default
0 Normal mode
0
1 Loopback test mode
Table 8-20 Slave DLL Phase Trim (Continued)
sl_phase_trm[3:0] Phase Difference (degrees) Suggested Default
clk90
clk180
clk270
clk0
clkin
dqs_90 = delayed version of dqs
dqsb_90 = delayed version of dqsb
SolvNet
DesignWare.com
It is also possible to trim the 90-degree delay using the fdtrm control bits as shown in Table 8-12:
8.3.5 MSDLL Reset Operation
When reset is asserted and bypass is not asserted, the Master DLL and Slave DLL output clocks are active
with minimum fix delay between various outputs.
8.3.6 MSDLL Reset Requirements
Reset issued to the MSD_MSDLL_DDR must always meet the same requirements specified for
MSD_MDLL_DDR.
Table 8-22 Bypass Mode Frequency Range
bps200
0 0 to 100MHz
0
1 0 to 200MHz
Table 8-23 fdtrm Control Bits
fdtrm[1:0]
00 nominal delay
00
01 nominal delay 10%
Note Note Note Note
Because both edges of clk_in are used to generate active edges of the output clocks, the duty cycle of
clk_in impacts the tBYPxxx timing values. An input duty cycle of 48%/52% or better is recommended.
SolvNet
DesignWare.com
8.4 Mobile DDR
When using this PHY in a Mobile DDR system, you can choose between three timing modes:
The Bypass200 mode is convenient in that it allows the operating frequency to be swept from DC to 200MHz
without the need to change operating mode. However, because clk_90, clk_180, and clk_270 are generated
by a fixed delay optimized for 200MHz operation and subject to PVT variation, the overall system timing
margin is lower than in the other modes.
The Bypass100 mode is convenient if 100MHz is the highest operating frequency required as it affords
larger system timing margin than the Bypass200 mode due to the fact that the fixed delay is optimized for
100MHz operation.
The Locked mode generates the most system timing margin as clk_90, clk_180, and clk_270 are generated
according to the actual operating frequency and with full PVT compensation. However, the lowest
frequency of operation is 100MHz. To determine which mode or modes can be used in any particular
application, refer to the tBYP data in DLL DC and AC Characteristics on page 71.
Mode Description Frequency Range Comments
Locked DLLs placed in normal (locked) mode 100 to 200MHz Maximum system timing margin
Bypass100 DLLs placed in bypass mode DC to 100MHz Good system timing margin
Bypass200 DLLs placed in bypass mode DC to 200MHz Adequate system timing margin
Note Note Note Note
It is possible to switch between these timing modes provided the memory system is placed in a state
where glitches on CK/CKb will not cause memory content corruption.
SolvNet
DesignWare.com
8.5 DLL DC and AC Characteristics
The DC and AC characteristics for the DLL Library are detailed in the following subsections:
Recommended Operating Conditions
DC Specifications
AC Specifications on page 72
Working with SDRAM Jitter Specifications on page 76
8.5.1 Recommended Operating Conditions
The following table provides the supply values for DC design criteria only. These values represent the DC
supply limits at the devices internal to the design, including the effects of internal IR drop.
8.5.2 DC Specifications
The following tables provide maximum DC current and power when all inputs are quiet/static: typical
process, nom VDD, and temperature 25C; fast process, max VDD [VDD+10%], and temperature 125C. These
parameters are simulated. In the event of test silicon, these parameters may not be measured.
Table 8-24 DLL Recommended Operating Conditions
Symbol Parameter Min Nom Max Units
V
DD
Core supply voltage 0.99 1.1 1.21 V
T
J
Junction temperature -40 25 125 C
Table 8-25 MDLL DC Specifications
PBYPM Static bypass mode 2.59 89.76 uW
PRSTM Total power, reset asserted 10.46 16.04 mW
Table 8-26 MSDLL DC Specifications
PBYPMS Static (leakage current) bypass mode 4.31 148.76 uW
PRSTMS Total power, reset asserted 18.78 29.10 mW
SolvNet
DesignWare.com
8.5.3 AC Specifications
8.5.3.1 Operating Conditions
The following table provides AC operating conditions of MDLL and MSDLL. The minimum and maximum
values represent external-to-the-chip requirements that have to be met to achieve the specified performance.
Some parameters are simulated. In the event of test silicon, these parameters may not be measured.
8.5.3.2 Performance Summary
The following table provides brief performance characteristics of MDLL and MSDLL based on 400 MHZ
simulation in locked conditions, with output loaded with 0.1pF capacitance. The lock time increases with
increase of input clock frequency. The maximum locking time is simulated parameter at maximum
operating frequency (533 MHz).
Output period jitter is the maximum deviation in the output clock period from the nominal clock period
value based on an input clock with no jitter. Actual output period jitter is equal to output period jitter plus
input period jitter. Some parameters are simulated. In the event of test silicon, these parameters may not be
measured.
Table 8-27 DLL Operating Conditions
f
REF
Input source clock frequency 100 533 MHz
t
IDC
Input source clock duty cycle 40 60 %
t
IDC_BYPM
Input source clock duty cycle, bypass mode 48 52 %
t
PW
Input dqs/dqsb signal pulse width - high and low 0.75 ns
t
IJITT
Input period jitter -50 50 ps
V
RIPP
Power/ground supply rail ripple 20 mV
Table 8-28 MDLL/MSDLL Performance
t
LOCK_MDLL
MDLL Lock time 2.56 us
t
LOCK_MSDLL
MSDLL Lock time 5.12 us
t
ODC
Output duty cycle 45 55 %
t
ERR Output static phase error
1
1. The DLL phase error is the possible error between any two of the four phased output clocks of the DLL (0/90/180/270).
The error can be any value in this range. The clk_0 and cclk_0 would not have this error factor as they are copies of
each other.
-10 10 degrees
t
OJITT
Output period jitter -50 50 ps
SolvNet
DesignWare.com
8.5.3.3 Propagation Delay
The following table provides a summary of timing information of MDLL and MSDLL in bypass mode and
in locked mode. The parameters are obtained by simulation with an output load of 0.1 pF and input
transition 40ps. The max parameters were obtained using slow conditions (process=slow, V=VDD(nom)-
10%, T=125C). The min parameters were obtained using fast conditions (process=fast, V=VDD(nom)+10%,
T=-40C). In the event of test silicon, these parameters may not be measured.
Note Note Note Note
In the Bypass Mode propagation delay data in the following table, the clk_in rising edge to clk_180
and clk_270 falling edges are specified. This reflects the way these clocks are generated in Bypass
Mode. Because the ITM library cells use the rising edge of these clocks, you have to add the high
period of your clk_in waveform to the data provided in order to determine the clk_in rising edge to
clk_180 and clk_270 rising edge delays.
Table 8-29 Propagation Delay, 0-100 MHz Bypass Mode Operation (bps200=0)
t
BYP0
Bypass mode, clk_in to clk_0 , 100MHz 0.18 0.28 0.48 ns
t
BYPC0
Bypass mode, clk_in to cclk_0 , 100MHz 0.18 0.28 0.49 ns
t
BYP90
t
BYP180
t
BYP270
t
BYPDQS
Bypass mode, dqs to dqs_90, 100MHZ 1.49 2.27 3.66 ns
t
BYPDQSB
Bypass mode, dqsb to dqsb_90, 100MHZ 1.49 2.26 3.65 ns
Table 8-30 Propagation Delay, 0-200 MHz Bypass Mode Operation (bps200=1)
t
BYP0
t
BYPC0
Bypass mode, clk_in to cclk_0 , 200MHz 0.18 0.28 0.49 ns
t
BYP90
t
BYP180
t
BYP270
t
BYPDQS
Bypass mode, dqs to dqs_90, 200MHZ 0.74 1.14 1.84 ns
t
BYPDQSB
Bypass mode, dqsb to dqsb_90, 200MHZ 0.74 1.13 1.84 ns
SolvNet
DesignWare.com
Table 8-31 Propagation Delay, Locked Mode Operation 100-533 MHz
t
PROP100
DLL locked, clk_in to clk_0 , 100MHz 1.71 2.22 3.07 ns
t
PROP125
t
PROP133
t
PROP166
t
PROP200
t
PROP233
t
PROP266
t
PROP300
t
PROP333
t
PROP400
t
PROP433
t
PROP533
SolvNet
DesignWare.com
8.5.3.4 AC Power Dissipation
The following tables provide the power dissipation for MDLL and MSDLL in locked conditions and bypass
mode. The parameters are obtained by simulation: typical process, nom VDD, and temperature 25C;
VDD+10% and Fast process, 125C, with an output load of 0.1 pF. In the event of test silicon, these
parameters may not be measured.
To calculate an estimate of bypass mode power, extrapolate a value for PBYPMSS using the two frequency
points provided.
Note Note Note Note
PACTMS is a linear extrapolation of total MDLL power versus frequency. It is only valid in the
frequency range noted. To calculate a conservative normal mode power estimate use PACTMS to
derate the total power at the maximum frequency down to any particular operating frequency.
For example:
Total Power@400MHz = PACTM - (533-400)* PACTMS /1000 mW
Table 8-32 MDLL
P
ACTM
Total power, normal mode, 533MHz 5.64 7.55 mW
P
ACTM
Total power, normal mode, 100MHz to 533MHz 9.98 12.42 uW/MHz
P
BYPM
Total power, bypass mode, 100MHz 0.29 0.48 mW
P
BYPM
Table 8-33 MSDLL (output clocks and input read DQS clocks toggling)
P
ACTMS
P
ACTMS
P
BYPMS
P
BYPMS
Table 8-34 MSDLL (output clock toggling, input read DQS clocks static)
P
ACTMS
P
ACTMS
P
BYPMS
P
BYPMS
SolvNet
DesignWare.com
8.5.4 Working with SDRAM Jitter Specifications
SDRAMs specify input clock jitter in a couple different manners. As an example, typical DDR2-800 jitter
specifications might be:
Period Jitter (PJ) = 100ps
Period Jitter during DLL locking period (PJlck) = 80ps
Cycle-to-Cycle Period Jitter (C2C) = 200ps
Cycle-to-Cycle Period Jitter during DLL locking period (C2Clck) = 160ps
Cumulative error across 2 cycles (ERR2) = 150ps
The SDRAM specifications tend to have the period jitter (PJ) and cycle-to-cycle (C2C) jitter directly related.
Using the above examples, SDRAM PJ is 100ps, meaning the clock period can be up to either -100ps or
+100ps from the nominal average period. The C2C jitter is 200ps, which in this case is based from the PJ
where you could encounter one clock period at -100ps from the nominal average and the next at +100ps
from the nominal average, for a total delta of +200ps between these consecutive cycles. Turning this
scenario around, encountering one clock period at +100ps from the nominal average and the next at -100ps
from the nominal average, the total delta would be -200ps between these consecutive cycles. Given these
example jitter specifications, if you meet the PJ specification you also meet the C2C specification. It is
important to understand that measurements of PJ and/or C2C do not require knowledge of nominal clock
edge positions, only clock periods.
The use of the term nominal average in the above description is significant. JEDEC, as an example, specifies
DDR2 SDRAM clock jitter measurements be performed over a sample of 200 clock cycles, and be compared
to the average clock period, which is also obtained by sampling 200 clock cycles. The number '200' has no
known significance other than to represent a short-term duration that combined with the peak-to peak
specification style is a simplification of the specifications that can make them easier to measure with lower
complexity test equipment. An alternative specification style, although not the one we have to work with
but one which many people are familiar with, would have been to describe the Gaussian distribution of the
clock jitter in terms of a mean and standard deviation.
The PJ and C2C may also be specified separately for the locking period of the SDRAMs DLL (PJlck and
C2Clck). SDRAM manufacturers tend to agree that relatively minor violations of the PJ and C2C
specifications after the DLL is locked is not a major concern, as long as the locking period specifications are
met. This is to ensure the DLL is provided a stable environment during this locking time. After achieving
lock, the DLL can handle greater disturbances without fault. The host system is quiet (little or no activity)
during the SDRAMs DLL locking time resulting in very low output jitter, which normally allows these
locking period specifications to be easily achieved.
There may be further jitter specifications for the SDRAM relating to the clock edge positions, normally
deemed Cumulative error or alternatively Time Interval error. Cumulative error refers to the ideal nominal
location of the clock edge versus the actual location of the clock edge after a given number of consecutive
clock cycles, and is typically specified in terms of the amount of allowable total delta. These specifications
help prevent the SDRAMs input clock from wandering too much in one direction too quickly, thus aiding
the SDRAMs DLL in maintaining lock. The example specifications provided above show that cumulative
error can be larger than the period jitter. To describe this, assume a consecutive sequence of, for example, 10
clock periods where each of these clock periods is 30ps shorter than the nominal average clock period. Each
SolvNet
DesignWare.com
clock period is well within the period jitter specification, but the actual 10th clock edge is 30 x 10ps = 300ps
earlier than the nominal ideal position of the 10th clock edge (+300ps cumulative error) assuming each of
these 10 clock periods had been equal to the nominal ideal period. Modifying this example and assuming
the first five clock cycles were each 30ps shorter than the nominal average, and the next 5 cycles were each
30ps longer than the nominal average, the cumulative error for the 10 cycles would be 0ps.
The use of a DLL within the PHY provides a highly effective timing solution but also results in a system of
additive jitter. The input reference clock (clk_in pin) jitter is added to the DLL's own jitter contribution to
result in the output jitter to the SDRAM. Although the actual output jitter is not an exact addition of the two
sources, it is an adequate approximation. As an example, to meet an SDRAM input period jitter requirement
of 100ps, and assuming the DLL output jitter specification is 50ps, then the maximum input reference
clock jitter should be 50ps. This would place operation in theory at the edge of the SDRAM specification, so
aiming at a input reference clock jitter less than 50ps will add margin.
A common method to estimate jitter performance is to measure the deviation of a clock edge, either rising or
falling. It should be noted that when using this method, the appropriate measurement would be the
maximum deviation of the rising clock edge jitter or the falling clock edge jitter.
The SDRAM datasheet jitter specifications are primarily presented as a means to help ensure the SDRAMs
datasheet timing specifications are properly bounded. The SDRAM should be designed with adequate
margins to ensure it's DLL can withstand spurious events (such as, power supply spikes) after the DLL is
locked which may result in timing deviations without failing.
SolvNet
DesignWare.com
SolvNet
DesignWare.com
9
ITM Library
ITM Library Overview on page 80
ITMs for Byte Lane on page 89
ITMs for Command Lane on page 110
DC and AC Characteristics on page 120
Placement Specifications on page 126
ITM Library DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
9.1 ITM Library Overview
This chapter describes the Synopsys DDRn SDRAM ITMs, which are timing translation components used in
a DDR2/3-Lite/mDDR between memory controller logic and DDRn-specific SSTL I/Os. The ITM library is
supplied as hard-IP.
Interfacing to high-speed (such as, greater than 200 MHz) external DDRn SDRAMs introduces critical
system timing issues:
The data stream is operating at double data rate, such as 1066 Mb/s for a 533 MHz clock rate.
The SDRAM consumes a large portion of the available bit period for setup, hold, and output skew
specifications.
Wide data word applications are common, increasing pin to pin skew offsets.
Mainstream use of multiple memory devices to permit width and depth expansion, which results in
unbalanced signal loading.
Board-level signal matching limitations and crosstalk reduce the available data eye.
The SDRAM provides non-periodic, non-centered capture strobes with read data.
The memory system is subject to timing drift, complicating transporting read data back to the
controller clock domain.
Previous solutions to memory interfacing have involved synthesis and automated place and route solutions
up to the I/O cells. At high clock rates, the narrow data eyes are reduced even further by a variety of system
timing skews. Limited standard cell performance combined with the pseudo-random nature of automated
synthesis and place and route tools result in interface designs that are complex to implement and rarely
achieve desired operation rates in actual system use.
The Synopsys memory interface and control solution solves these problems by providing hard-IP
components for the PHY, which results in an easy to implement, correct-by-construction system. All
problematic timing closure issues at the external interface are resolved with this system. The ITM
components are a key element in the PHY.
A general DDRn controller system can be divided into three sections:
Control logic
Byte lane physical interface (PHY)
Command lane PHY
Figure 9-1 on page 81 shows the DDR2/3-Lite/mDDR, Memory Controller, and related components.
DDR multiPHY for SMIC40LL25 Databook ITM Library
SolvNet
DesignWare.com
Figure 9-1 DesignWare Cores DDRn SDRAM PHY and Control Diagram
SolvNet
DesignWare.com
9.1.1 Key Features
The Synopsys DDR2/3-Lite/mDDR ITM Library includes the following features:
Operating range beyond 533MHz permits interfacing to various speed grades of DDRn SDRAMs
Translates memory write and control data and output enable timing from a single-clock
synchronous domain to DDRn timing format
Translates read data timing from a DDRn timing format to a single-clock synchronous domain
Permits fine-tuning of read data and read data strobe relationship on a per-bit basis
Synchronous internal controller interface
Embedded DLL output clock distribution to ensure low pin to pin skews and reduce
implementation effort
Hard-IP format providing signal to signal patch matching for minimal pin to pin skew
Fully abutting design with filler cells to permit a variety of I/O pad pitches
Automatically formats all timing to SDRAMs
Embedded drift analysis logic to aid in proper detection of read DQS strobes from SDRAM
The process information of the ITM is included in Table 9-1.
Notes:
1. Please contact your sales representative for availability in alternate process nodes/variants..
9.1.3 Metal Layer Usage
The ITM components use the first four metal layers of the process. The fourth metal layer is a shield layer,
allowing the user to route above the DLL components in all remaining metal layers of the process. The ITM
components are designed assuming the first four metal layers of the process are thin.
Table 9-1 Process Information
SMIC 40nm LL 0.9V 2.5V low-K 5 or more
SolvNet
DesignWare.com
9.1.4 Deliverables
Deliverables described in Table 9-2 include all views required to support a typical ASIC design flow.
Table 9-2 Deliverables
Behavioral Verilog
Timing Synopsys lib
Layout Abstract LEF
LVS Netlist SPICE
Documentation Detailed datasheet, physical implementation guide
SolvNet
DesignWare.com
9.1.5 ITM Cell List
Table 9-3 shows the cell list for the ITM.
Table 9-3 ITM Cell List
Byte Lane ITMs
Cell Name Description Width Height
MSD_ITMD ITM for data 30um
81.2um
MSD_ITMS ITM for strobe 30um
MSD_ITMBB ITM byte lane clock buffer 30um
MSD_ITMBENDCAP ITM byte lane endcap cell 5um
MSD_ITMBFILL_1 Byte lane fill cell, 0.1um
0.1um
1
1. If FILL cells are used minimum FILL is 1um. This cell can be used in conjunction with other fill cells.
MSD_ITMBFILL1 Byte lane fill cell, 1um 1um
MSD_ITMBFILL30_BREAK Byte lane fill cell, 30um with clock break 30um
Command Lane ITMs
MSD_ITMC_D2 ITM for command /clock 30um
30um
MSD_ITMCB0 ITM command lane clock buffer, stage 0 30um
MSD_ITMCB1 ITM command lane clock buffer, stage 1 30um
MSD_ITMCENDCAP ITM command lane endcap cell 5um
MSD_ITMCFILL_1 Command lane fill cell, 0.1um
0.1um
1
MSD_ITMCFILL1 Command lane fill cell, 1um 1um
MSD_ITMCFILL30_BREAK Command lane fill cell, 30um with clock break 30um
SolvNet
DesignWare.com
9.1.6 Byte Lane PHY Construction with ITMs
This section gives a brief introduction to the byte lane PHY, and its construction with ITMs.
A DDRn byte lane has eight data bits (DQ), a data mask (DM), and complimentary strobes (DQS, DQS_b).
The general structure of a byte lane PHY is shown in Figure 9-2 on page 86. It has a master-slave DLL, ITMs,
and SSTL data and power I/Os. A byte lane PHY uses five different types of ITM cells:
ITM for data (MSD_ITMD) used for timing translation at all data (DQ) and data mask (DM) I/Os.
ITM byte lane clock buffer (MSD_ITMBB) used to relay clock and data strobe signals through the
byte lane. This cell should be placed within one I/O slot of the byte lane's physical center.
ITM for strobe (MSD_ITMS) used for timing translation at all data strobe (DQS, DQS_b) I/Os. The
MSD_ITMS blocks should be in the center of the byte lane, each on either side of a MSD_ITMBB cell.
ITM byte lane fill cells (MSD_ITMBFILL) come in different widths to accommodate byte lane
design in different I/O pitches, provide inter-ITM connection by abutment, and should be used to
fill empty spaces between ITMs. A fill cell with clock break is used between different abutting byte
lanes.
ITM byte lane endcap cells (MSD_ITMBENDCAP) placed by abutment at the end of a byte lane
when there is no abutting functional or filler cell.
Timing translation is done between the single clock ASIC domain and the external DDRn-compliant
domain. The library is designed to permit all critical timing connections between I/Os, ITMs, and DLL
within the PHY to be completed by abutment. To permit design flexibility, the PHY elements also permit a
non-abutting implementation.
SolvNet
DesignWare.com
Figure 9-2 Byte Lane Construction
SolvNet
DesignWare.com
Figure 9-3 Byte Lane ITM Timing Translation
9.1.7 Command Lane PHY Construction with ITMs
This section gives a brief introduction to the command lane PHY, and its construction with ITMs.
A typical DDRn command lane has multiple command outputs (RAS_b, CAS_b, WE_b, and so on), an
address bus (A), and a pair of output clocks (CK, CK_b). The general structure of a command lane PHY is
shown in Figure 9-4 on page 88. It has a master DLL, ITMs, and SSTL data and power I/Os. A command
lane PHY uses six different types of ITM cells:
ITM for command (MSD_ITMC_D2) used for timing translation at all I/Os, supports LPDDR2.
ITM command lane clock buffer stage 0 (MSD_ITMCB0) used to relay clock signals through the
command lane to the stage 1 buffers. This cell should be placed within one I/O slot of the command
lanes physical centre.
ITM command lane clock buffer stage 1 (MSD_ITMCB1) used twice in the command lane to relay
clock signals to the MSD_ITMC cells. This cell should be placed twice in a command lane, 25% from
each end of the command lane.
ITM command lane fill break cells (MSD_ITMCFILL_BREAK) used twice in a command lane, and
are placed in the first empty I/O slot outside each MSD_ITMCB1 cell.
ITM command lane fill cells (MSD_ITMCFILL) come in different widths to accommodate
command lane design in different I/O pitches, and to provide inter-ITM connection by abutment.
They should be used to fill empty spaces between ITMs.
ITM command lane endcap cells (MSD_ITMCENDCAP) used twice in each command lane and are
placed by abutment at either end.
Timing translation is performed between the single clock ASIC domain and the external DDRn SDRAM.
The library is designed to permit all critical timing connections between I/Os, ITMs, and DLL within the
PHY to be completed by abutment. To permit design flexibility, the PHY elements also permit a
non-abutting implementation.
SolvNet
DesignWare.com
Figure 9-4 Command Lane Construction
Figure 9-5 Command Lane ITM Timing Translation
Single Clock ASIC Domain
clock
ras_b
a
etc.
ras0 ras1 ras2
a0 a1 a2
command
Clock Centered in Data Eyes
CK
CK_b
RAS_b ras0 ras1 ras2
a0 a1 a2 A
SolvNet
DesignWare.com
9.2 ITMs for Byte Lane
This section describes the components that make up the ITM:
ITM for Data (MSD_ITMD)
ITM for Strobe (MSD_ITMS) on page 95
ITM Byte Lane Clock Buffer (MSD_ITMBB) on page 105
ITM Byte Lane Fill Cells on page 107
9.2.1 ITM for Data (MSD_ITMD)
The ITM for data (MSD_ITMD) is a timing translation component used when interfacing to DDRn
SDRAMs. MSD_ITMD translates data and control timing from control logic into a properly formatted DDR
data stream for output to the SDRAMs. This component also receives a DDR data stream from the SDRAMs
and translates it for delivery to the control logic. This component is used with the data signals DQ and DM.
Figure 9-6 ITM for Data (MSD_ITMD)
dout[1:0]
io_oe
io_do
oe_set_b
oe_rst_b
Double Data Rate Buffer
do_set_b
do_rst_b
oe[1:0]
srst_b
rst_b
di_trm[3:0]
Read FIFO
di[1:0]
valid
read
rclk
io_di
clk_0
clk_90
clk_180
clk_270
dqs_90
dqsb_90
M
V
D
D
M
V
S
S

connect by abutment
i
n
t
e
r
f
a
c
e
t
o
S
S
T
L
I
/
O
i
n
t
e
r
f
a
c
e
t
o
c
o
n
t
r
o
l
l
e
r
SolvNet
DesignWare.com
9.2.1.1 Output Operation
The ITM for data (MSD_ITMD) provides two main functions: internal-to-external (write data and
command) timing translation, and external-to-internal (read data) timing translation. This section covers
internal-to-external timing translation.
The DDRn timing margins are optimized when the clock or data strobe signal is centered within the
associated data eye. The MSD_ITMD and associated ITM for Strobe (MSD_ITMS) components use four
phases of the clock to generate correct data and phase shifted strobe transitions. The clk_0 and clk_180
inputs are used to drive output data to the SSTL I/Os in the ITMD, while clk_90 and clk_270 inputs are used
to drive the output strobe to the SSTL I/Os in the ITMS, which allows the creation of a data strobe that is
centered within the data eye.
Functionality and timing for internal-to-external operation is shown in Figure 9-7 and Figure 9-8 on page 91.
Figure 9-7 MSD, ITMD Internal-to-External Data Output Functional Timing
tCK tCH
clk_0
clk_90
clk_180
clk_270
1
rst_b
dout[1:0] dout3,dout2 dout1,dout0
1
do_set_b
1
do_rst_b
io_do
dout0 dout1 dout2 dout3
tCL
tCKPH tCKPH tCKPH tCKPH
tSU tHD
tPROP0 tPROP180

SolvNet
DesignWare.com
Figure 9-8 MSD, ITMD Internal-to-External Data Output Set/Reset Timing
9.2.1.2 Input Operation
The ITM for data (MSD_ITMD) provides two main functions: internal-to-external (write data and
command) timing translation and external-to-internal (read data) timing translation. This section deals with
external-to- internal timing translation.
The DDRn read timing specification states that data (DQ) and associated strobe (DQS/DQS_b) are driven
by the SDRAM, where transitions of data and strobe are edge aligned. The byte lane master-slave DLL
delays the data strobes (DQS, DQS_b) by 90
(25% of the clock cycle), generating delayed strobes dqs_90 and

dqsb_90. These delayed strobes are used to latch the incoming data.
The 90
data strobe position in the data eye can be further tuned in MSD_ITMD by adjusting di_trm.
Normally, the delay on each data bit is matched to the delay of the data strobes through the slave DLL and
clock tree. The di_trm trim input allows this delay to be slightly increased if required. The nominal delay
setting should work for most systems. In cases where these delays need to be adjusted, the user should
perform test reads to determine the best tuning values. The lower two bits of di_trm control the delay for the
data clocked by dqs_90, while the higher two bits control the delay for the data clocked by dqsb_90. Valid
settings for each two-bit control field are as follows:
Strobed read data is written to a four-entry FIFO as shown in Figure 9-9. Rising edges of dqs_90 and
dqsb_90 write data to the FIFO, and the rising edge of dqsb_90 also increases the write pointer value. The
output FIFO valid flag is raised synchronous to the first rising rclk edge after the rising edge of dqsb_90
when the write pointer and read pointer values are different. At this same time, data is driven from ITMD
on output di synchronous to rclk. Asserting read synchronous to rclk increases the read pointer value.
Note Note Note Note
The functionality and timing of the output enable path (OE) is the same as the data output path
functionality and timing represented in the previous figures. AC timing parameters are provided in DC
and AC Characteristics on page 120.
00 = nominal delay 01 = nominal delay + 1 step 10 = nominal delay + 2 steps 11 = nominal delay + 3 steps
clk_0
clk_90
clk_180
clk_270
rst_b / srst_b
io_do
dout[1:0]
do_set_b
do_rst_b
X
tSRPW
tSRPW
tSRPW
tPROPS
tPROPR

SolvNet
DesignWare.com
A FIFO read should be issued in the same clock cycle that valid is asserted. The FIFO provides one clock
cycle margin for skew between different bits of a byte lane. This allows the controller to receive valid from
all ITMDs, capturing all the data at the same time, and to send one common read to all ITMDs.
Figure 9-9 Read FIFO Operation
Figure 9-10 MSD_ITMD External-to-Internal Memory Read Timing
SolvNet
DesignWare.com
9.2.1.3 MSD_ITMD Pin List
Table 9-4 MSD_ITMD Pin List
General Outputs
clk_0 input Control clock, no phase shift
clk_90 input Control clock, shifted 90from clk_0
rst_b input Asynchronous reset. Active low. When 0, resets all FIFO pointers to the default value.
srst_b input Asynchronous soft reset. Active low. When 0, resets all FIFO pointers to the default value.
Internal Controller Interface Enable
oe[1:0] input Output enable control for I/O. Synchronous to clk_0.
oe[0] is output enable generated by the first clk_0 rising edge after the clk_0 rising edge which captured
oe[0]
oe[1] is output enable generated by the second clk_180 rising edge after the clk_0 rising edge which
captured oe[1]
oe_set_b input Output enable set control for I/O. Asynchronous. Active low.
When oe_set_b is 0, output io_oe is set to 1.
oe_rst_b input Output enable reset control for I/O. Asynchronous. Active low. When oe_rst_b is 0 and oe_set_b
is 1, output io_oe is reset to 0.
Internal Controller Interface Write
dout[1:0] input Data output for I/O. Synchronous to clk_0.
dout[0] is data output generated by the first clk_0 rising edge after the clk_0 rising edge which captured
dout[0]
dout[1] is data output generated by the second clk_180 rising edge after the clk_0 rising edge which
captured dout[1]
do_set_b input Data output set control for I/O. Asynchronous. Active low.
do_rst_b input Data output reset control for I/O. Asynchronous. Active low.
Internal Controller Interface Read
dqs_90 input Read (input) data strobe. Ideally delayed 90 degrees from native (board-level) dqs input
dqsb_90 input Read (input) data strobe. Ideally delayed 90 degrees from native (board-level) dqs_b input
di_trm[3:0] input Data input window placement trim for data latched on dqs and dqs_b.
bits 3:2 are strobe placement trim for data latched by dqsb_90.
bits 1:0 are strobe placement trim for data latched by dqs_90.
rclk input Read clock.
read input Read FIFO control. Synchronous to rclk.
valid output FIFO valid indicator. Synchronous to rclk.
di[1:0] output Read data (VALID DATA) is valid only while valid signal is HIGH and is synchronous to rclk
(see note 1).
SolvNet
DesignWare.com
Notes:
1. Transitions may occur on these outputs outside the VALID DATA window.
External I/O Interface
io_do output Data output (for write) to I/O. Double data rate, synchronous to clk_0 and clk_180.
io_di input Data input (for read) from I/O. Double data rate, synchronous to dqs_90 and dqsb_90.
io_oe output Data output enable to I/O. Double data rate, synchronous to clk_0 and clk_180.
Supply
MVDD input power
MVSS input ground
Table 9-4 MSD_ITMD Pin List (Continued)
SolvNet
DesignWare.com
9.2.2 ITM for Strobe (MSD_ITMS)
The Synopsys ITM for Strobe (MSD_ITMS) is a timing translation component used when interfacing to
DDRn SDRAMs. MSD_ITMS translates data strobe timing from control logic into a properly formatted DDR
data steam for output to the SDRAMs. This component also receives the data strobe from the SDRAMs,
providing required gating functions and timing drift indication. This component is used with the data
strobe signals DQS and DQS_b.
Figure 9-11 ITM for Strobe (MSD_ITMS)
clk_180
clk_270
clk_0
clk_90
dqs_90
dqsb_90
dqs_en
phase_sel[1:0]
dqs_config
dqs_dis
ddr_mode
dqs_dis_polarity
dqs
dqs_drift[1:0]
dqs_trm[2:0]
rst_b
srst_b
Clock Gating & Drift Selection
oe[1:0]
oe_set_b
oe_rst_b
dout[1:0]
do_set_b
do_rst_b
io_oe
io_do
io_di_0
i
n
t
e
r
f
a
c
e
t
o
S
S
T
L
I
/
O
i
n
t
e
r
f
a
c
e
t
o
c
o
n
t
r
o
l
l
e
r
M
V
S
S
i
o
_
d
i
_
0
i
o
_
d
i
_
1
connect by abutment
connect within
ITMS pair
M
V
D
D

SolvNet
DesignWare.com
The description of output operation for MSD_ITMS is similar to that previously described for MSD_ITMD.
The relevant difference is that transitions of io_do and io_oe are triggered by rising edges of clk_0 and
clk_180 for MSD_ITMD, and these same transitions are triggered by rising edges of clk_90 and clk_270 for
MSD_ITMS. Figure 9-12 shows the output timing for ITMS. The figure of set/reset timing for the output
function of MSD_ITMD also applies to the output function of MSD_ITMS.
Figure 9-12 MSD_ITMS Internal-to-External Data Output Functional Timing
9.2.2.2 Input Operation and DQS Gating
DDRn systems use a bidirectional data strobe which is driven by the host during memory writes, and by the
SDRAM during memory reads. During active read commands, the ITMS basically acts as a buffer for the
incoming DQS/DQS_b. A turn-around time exists between operations when neither device is driving the
bus, and the strobe traces are held by termination circuitry at a mid-rail voltage.
While the DQS lines are held at mid-rail during inactive periods, an unknown value X is being received by
the SSTL inputs. To prevent X from causing false transitions and other negative effects within the read path,
the input read dqs strobe path is disabled when there is no active read data. The ITMS provides the
functions to enable/disable this path, while the control of these functions is provided by the memory
controller logic. A basic view of the enable/disable requirements is shown in Figure 9-13 on page 97.
tCK tCH
clk_0
clk_90
clk_180
clk_270
1
rst_b
dout[1:0] dout3,dout2 dout1,dout0
1
do_set_b
1
do_rst_b
io_do
tCL
tSU tHD
tPROP90 tPROP270

SolvNet
DesignWare.com
Figure 9-13 Strobe Gating Requirements During Read Operations
After a read is issued, the SDRAM drives DQS and DQS_b for a number of clock cycles equal to the read
burst length. Differing SDRAM CAS latencies, clock cycle times, board trace lengths, and other analog
factors between controller and SDRAM result in a variable latency between when the read was issued, and
when the returning DQS/DQS_b strobes reach the ITMS. The goal of DQS gating is to control a window,
which enables and disables the input read dqs path only when the DQS lines are active, not when they are at
mid-rail. There is a pre-amble and post-amble surrounding the active DQS edges that is used as the point to
perform the enabling and disabling of this window.
SolvNet
DesignWare.com
9.2.2.2.1 DQS Gating Windowing Schemes
There are two windowing schemes supported by the ITMS passive windowing and active windowing
which are selected by input dqs_config.
Passive Windowing
In the passive windowing mode (dqs_config = 1), the controller asserts dqs_en at the start of the window
and de-asserts dqs_en at the end of the window. This provides the course (clock-cycle) position of the
enable and disable edges. Fine tuning (1/4 clock cycle) of the window placement is selected by
phase_sel[1:0]. The operation of passive windowing is shown in Figure 9-14 on page 98.
Figure 9-14 DQS Gating Passive Windowing Mode
A normal read data training sequence consists of writing a set of data patterns to the memory and then
looping through read commands while testing different settings of dqs_en window position (clock cycle
increments) and different settings of phase_sel (1/4 clock cycle increments). By following this approach, the
user will encounter a fail region when the window is positioned too early, a pass region, and another fail
region when the window is positioned too late. The optimal window setting is in the middle of the pass
region.
The phase_sel[1:0] settings are provided in Table 9-5 on page 99.
Note Note Note Note
The dqs_en driven to the ITMS from the controller logic clock domain is first registered by clk_0 to
place it in a clock domain relative to the byte lane before being used within the ITMS.
SolvNet
DesignWare.com
Because the DDR memory system is operating at high data rates, a dynamic compensation system can be
employed with the controller and the ITMS to track and adjust for the amount of timing drift accumulated
in the system due to voltage and temperature changes. After the initial read data training sequence is
completed, this system can be used to dynamically update the settings for dqs_en and phase_sel offsets to
maintain the optimal window position. This is described further in Dynamic Strobe Drift Detection on
page 100. This applies to both the passive and active window modes.
Active Windowing
The active windowing mode addresses the fact that the postamble is shorter than the preamble. As can be
seen from Figure 9-14 on page 98, the optimal window position for the preamble and postamble are not
necessarily the same. In the active windowing mode (dqs_config = 0), the controller asserts dqs_en for one
clock cycle at the start of the window and asserts dqs_dis for one clock cycle at the end of the window.
Internal to ITMS, the assertion of dqs_dis is shifted by a further 180 degrees to account for the fact that
DQS_b occurs 180 degrees later than DQS. This provides the course (clock-cycle) position of the enable and
disable edges.
Fine tuning (1/4 clock cycle) of the window placement is selected by phase_sel[1:0]. The effective window is
opened in the same manner as in the passive windowing mode, such as dqs_en assertion plus the phase_sel
offset. To close the window, the controller asserts dqs_dis to inform the ITMS to expect the last DQS_b
rising edge of the burst. The phase_sel setting is applied to this to set the effective time at which to expect
the last DQS_b rising edge. The last DQS_b rising edge of the burst is also the last data of the burst. This last
DQS_b rising edge is used to close the window. Thus, the window is self-closing. The operation of active
windowing is shown in Figure 9-15.
Table 9-5 phase_sel[1:0] Phase Selection
phase_sel[1:0] Phase Selection
Setting Selected Phase Offset
00 clk_0 + 180 degrees 1/2 clock cycle
01 clk_0 + 270 degrees 3/4 clock cycle
10 clk_0 + 360 degrees 1 clock cycle
11 clk_0 + 450 degrees 1 1/4clock cycle
Note Note Note Note
The dqs_en and dqs_dis driven to the ITMS from the controller logic clock domain are first registered
by clk_0 to place them in a clock domain relative to the byte lane before being used within the ITMS.
SolvNet
DesignWare.com
Figure 9-15 DQS Gating Active Windowing Mode
9.2.2.3 Dynamic Strobe Drift Detection
As illustrated in Figure 9-16, DDRn systems can have a long round-trip path from the controller clock
output (CK), to the SDRAM, and back to the controller data strobe input (DQS). The sum of potential
variations in this path can exceed 25% of a clock cycle at high frequencies (>300MHz), so some
compensation should be made if the path delay increases or decreases slowly, but significantly, during
normal operation.
Figure 9-16 Clock Round-Trip Path During Read
The MSD_ITMS component has a two-bit strobe drift indicator (dqs_drift), which changes value in grey
code if the returning strobe drifts across internal 90 timing reference boundaries. The absolute value of this
indicator is not important, but the change in value over time is.
Note Note Note Note
The indicator changes value if the strobe has crossed an internal reference boundary relative to
input clk_0 and clk_90. Table 9-6 on page 101 shows the correlation between drift indication, drift
direction, and required correction.
DDR3/2 DDRn
SolvNet
DesignWare.com
9.2.2.4 Delay Trimming
The 90
o
data strobe position in the data eye can be further tuned in MSD_ITMS by adjusting dqs_trm, in a
similar fashion as the di_trm function provided with MSD_ITMD. Normally the delay on each data bit is
matched to the delay of the data strobes through the slave DLL and clock tree. The dqs_trm trim input
allows this delay to be slightly increased or decreased, if required. The nominal delay setting should work
for most systems. In cases where these delays need to be adjusted, the user should perform test reads to
determine the best tuning values. Valid settings for the three-bit control field are defined in Table 9-7.
Table 9-6 Drift Indicators
dqs_drift[1:0]
DQS Drift Direction Required Changes
Old Value New Value
00
01 forward increase read data latency by 90 degrees
10 backward decrease read data latency by 90 degrees
01
10
11
Table 9-7 Delay Trimming
dqs_trm[2:0] Function Suggested Default
000 nominal delay - 3 steps
001 nominal delay - 2 steps
010 nominal delay - 1 step
011 nominal delay 011
100 nominal delay + 1 step
101 nominal delay + 2 steps
SolvNet
DesignWare.com
9.2.2.5 DDR Read Path Operating Mode
The MSD_ITMS component provides circuitry to derive the DQS_b signal from the DQS signal for use
within the MSD_ITMD components when notified the system uses Mobile DDR SDRAMs.
Because the ITMS also disables the incoming read data strobe path when not active, it is desirable to have
the dqs output from the ITMS settle to a correct state when disabled.
The inputs ddr_mode, dqs_dis_polarity, io_di_0, and io_di_1 are used to permit the correct resolution of
DDR2/3-Lite/mDDR modes. Table 9-8 provides the correct connectivity for the system.
The SSTL input buffer connected to system-level DQS is connected to io_di_0 of ITMS instance for dqs
(named here itms_dqs) and to io_di_1 of ITMS instance for dqsb (named here itms_dqsb). The SSTL input
buffer connected to system-level DQS_b is connected to io_di_1 of ITMS instance for dqs and to io_di_0 of
ITMS instance for dqsb. A signal named ddr_mode is connected to the ddr_mode input for both instances of
ITMS. This ddr_mode signal is 0 for normal and 1 for Mobile DDR mode.
Figure 9-17 provides an example of ITMS io_di_0/_1 interconnectivity.
Figure 9-17 ITMS Interconnectivity
In normal mode, the DQS signal, when enabled, will pass through itms_dqs; the DQS_b signal will pass
through itms_dqsb. In Mobile DDR mode, the DQS signal, when enabled, will pass through itms_dqs. The
DQS signal will be inverted as it passes through itms_dqsb. In Mobile DDR mode, DQS_b is not used.
When disabled, itms_dqs will drive its DQS output to 0 and itms_dqsb will drive its DQS output to 1.
Table 9-8 MDS_ITMS Connectivity
Instance ddr_mode dqs_dis_polarity io_di_0 io_di_1
itms_dqs ddr_mode (signal) 0 DQS DQS_b
itms_dqsb ddr_mode (signal) 1 DQS_b DQS
SolvNet
DesignWare.com
9.2.2.6 MSD_ITMS Pin List
Table 9-9 MSD_ITMS Pin List
General Outputs
rst_b input Asynchronous reset. Active low. Resets dqs gating logic. On reset, dqs path through ITMS
is disabled.
srst_b input Asynchronous reset. Active low. Resets dqs gating logic. On reset, dqs path through ITMS
is disabled.
dqs_90 input Feed-through strobe. Connects by abutment to other byte lane ITMs.
dqsb_90 input Feed-through strobe. Connects by abutment to other byte lane ITMs.
Controller Interface Enable
oe[1:0] input Output enable control for I/O. Synchronous to clk_0.
oe[0] is output enable generated by the first clk_90 rising edge after the clk_0 rising edge which
captured oe[0]
oe[1] is output enable generated by the first clk_270 rising edge after the clk_0 rising edge which
captured oe[1]
oe_set_b input Output enable set control for I/O. Asynchronous. Active low.
oe_rst_b input Output enable reset control for I/O. Asynchronous. Active low.
Controller Interface Write (Output Data)
dout[0] is data output generated by the first clk_90 rising edge after the clk_0 rising edge which
captured dout[0]
captured dout[1]
Controller Interface Read (Input Data)
dqs_en input DQS strobe enable. Synchronous to clk_0. Opens the window for enabling the input read
dqs strobe path. This input is used to gate input io_di, which is a buffered version of the
bidirectional system- level DQS (or DQS_b). The system-level DQS and DQS_b are valid
input strobes only during memory reads, and the latency relative to the issue of a memory
read instruction varies with trace lengths to/from the memory and other analog factors. This
input must be used in conjunction with input phase_sel[1:0] to correctly capture the data.
The dqs_en provides coarse (cycle) positioning of the strobe gating, and phase_sel[1:0]
provides fine (90
resolution) positioning.
SolvNet
DesignWare.com
phase_sel[1:0] input DQS strobe phase select control. Synchronous to clk_0. This input is used to gate input
io_di, which is a buffered version of the bidirectional global DQS (or DQS_b). Global IOs
DQS and DQS_b are valid input strobes only during memory reads, and the latency relative
to the issue of a memory read instruction varies with trace lengths to/from the memory and
other analog factors. This input must be used in conjunction with inputs dqs_en and dqs_dis
to correctly capture the data. The inputs dqs_en and dqs_dis provide coarse (cycle)
positioning of the strobe gating, and phase_sel[1:0] provides fine (90deg resolution)
positioning.
dqs_config input DQS window mode select. Selects one of two methods provided by the ITMS for controlling
the window which enables and disables the input read dqs strobe path. When set to 0
dqs_en and dqs_dis are used together with phase_sel to control the window. This is known
as the active windowing mode. When set to 1 dqs_en and phase_sel are used to control the
window. This is known as the passive windowing mode.
dqs_dis input DQS strobe disable. Synchronous to clk_0. Closes the window for enabling the input read
dqs strobe path.
This input is used to gate input io_di, which is a buffered version of the bidirectional system-
level DQS (or DQS_b). The system-level DQS and DQS_b are valid input strobes only
during memory reads, and the latency relative to the issue of a memory read instruction
varies with trace lengths to/from the memory and other analog factors. This input must be
used in conjunction with input phase_sel[1:0] to correctly capture the data. The dqs_dis
provides coarse (cycle) positioning of the strobe gating, and phase_sel[1:0] provides fine
(90deg resolution) positioning.
ddr_mode input Input data (at I/O interface) select input. Asynchronous. Only one of the two inputs io_di_1
and io_di_0 is valid, depending on setting of ddr_mode and dqs_dis_polarity. This input
should be driven to logic 0 for normal mode and logic 1 for Mobile DDR mode.
dqs output Data strobe output. Normally connected to DLL to be delayed by 90 degrees before being
used by MSD_ITMD for input read data capture.
dqs_dis_polarity input DQS identifier. Signifies to the ITMS if it is for DQS or DQS_b. Also sets the polarity of ITMS
output dqs when the read dqs strobe path is not enabled. This input must be tied to logic 0
for the dqs ITMS instance, and tied to logic 1 for the dqsb ITMS instance.
dqs_drift[1:0] output DQS drift indicator. Asynchronous.
This two-bit indicator can be used to detect forward or backward drift of global dqs relative
to internal clk_0. A change in value of dqs_drift indicates a forward or backwards relative
drift.
dqs_trm[2:0] input DQS delay trimming. Permits finer alignment of DQ and DQS. See Delay Trimming on
page 101 for details.
io_di_1
io_di_0
input Data input (for read) from I/O. Only one of these two input is valid, depending on setting of
ddr_mode and dqs_dis_polarity.
io_oe output Data output enable to I/O. Double data rate, synchronous to clk_90 and clk_270.
Supply
MVDD input Power
MVSS input Ground
Table 9-9 MSD_ITMS Pin List (Continued)
SolvNet
DesignWare.com
9.2.3 ITM Byte Lane Clock Buffer (MSD_ITMBB)
The Synopsys ITM byte lane clock buffer is used in a byte lane PHY for distribution of clocks and data
strobes to ITMs.
One MSD_ITMBB block is used per byte lane. Inputs are designed to allow connectivity by abutment to the
byte lane Master-Slave DLL (MSD_MSDLL_DDR). Outputs connect by abutment to other byte lane ITMs.
Figure 9-18 Byte Lane Clock Buffer (MSD_ITMBB)
AC specifications for MSD_ITMBB are outlined in DC and AC Characteristics on page 120. Placement
limitations within a byte lane are outlined in Placement Specifications on page 126.
SolvNet
DesignWare.com
9.2.3.1 MSD_ITMBB Pin List
Table 9-10 MSD_ITMBB Pin List
Input Clocks Connected to byte Lane Master/Slave DLL
in_clk_0 input Input clock.
in_clk_90 input Input clock, phase shifted 90from in_clk_0.
in_dqs_90 input Input data strobe, shifted 90relative to ITMD incoming DQ data (associated with DQS).
in_dqsb_90 input Input data strobe, shifted 90relative to ITMD incoming DQ data (associated with DQS_b).
Output Clocks Connected by Abutment to Other Byte Lane ITMs
clk_0 output Output clock. Buffered version of in_clk_0.
dqs_90 output Output data strobe. Buffered version of in_dqs_90.
dqsb_90 output Output data strobe. Buffered version of in_dqsb_90.
Supply
MVDD input Power
MVSS input Ground
SolvNet
DesignWare.com
9.2.4 ITM Byte Lane Fill Cells
The Synopsys ITM byte lane fill cells (MSD_ITMBFILLxx) connect clocks and data strobes by abutment
between other byte lane ITMs. These blocks have no functional behavior. The MSD_ITMBFILLxx cells are
provided in different widths to allow PHY construction with different I/O pitches.
Figure 9-19 ITM Byte Lane Fill Cells (MSD_ITMBFILLxx)
Table 9-11 ITM Byte Lane Fill Cell (MSD_ITMBFILLxx) Pin List
clk_0 input
Feed-through Clocks
Connected by abutment to other Command Lane ITMs
clk_90 input
clk_180 input
clk_270 input
dqs_90 input
dqsb_90 input
MVDD input
MVSS input
Note Note Note Note
This Fill Cell does not have any active device, connectivity by abutment only.
The pin direction is chosen input for verilog compiling tools convenience, but the functionality is
feed-through
SolvNet
DesignWare.com
The ITM byte lane fill clock break cell (MSD_ITMBFILL_BREAK) provides a break in the global byte lane
clock and data strobe lines. This cell is used to separate clocks and data strobes between adjacent byte lanes.
This block has no functional behavior or pins.
The ITM byte lane endcap cell (MSD_ITMBENDCAP) provides a means to ensure no design rule violations
at the ends of the byte lanes, when there is no abutting byte lane ITM cell. This block has no functional
behavior or pins.
Figure 9-20 ITM Byte Lane Fill Cell (MSD_ITMBFILLxx_BREAK)
Note Note Note Note
This fill cell does not have any active device, connectivity by abutment only.
The pins direction is chosen input for verilog compiling tools convenience, but the functionality is
feed-through for power only, clocks are not-connected.
Table 9-12 ITM Byte Lane Fill Cell (MSD_ITMBFILL35_BREAK) Pin List
MVDD input Feed through Clocks
Connected by abutment to other Byte Lane ITMs
MVSS input
SolvNet
DesignWare.com
The ITM byte lane endcap cell (MSD_ITMBENDCAP) provides a means to ensure no design rule violations
at the ends of the byte lanes, when there is no abutting byte lane ITM cell. This block has no functional
behavior or pins.
Figure 9-21 ITM Byte Lane File Cell (MSD_ITMBENDCAP)
Note Note Note Note
This Fill Cell is an isolation cell and does not have any pins.
SolvNet
DesignWare.com
9.3 ITMs for Command Lane
This section describes the ITM components of the command lane:
ITM for Command (MSD_ITMC_D2)
Command Lane Clock Buffer, Stage 0 (MSD_ITMCB0) on page 115
Command Lane Clock Buffer, Stage 1 (MSD_ITMCB1) on page 117
ITM Command Lane Fill Cells on page 118
9.3.1 ITM for Command (MSD_ITMC_D2)
The ITM for command and clock (MSD_ITMC_D2) is a timing translation component used when interfacing
to DDRn SDRAMs. MSD_ITMC_D2 translates address, command, and clock timing from control logic into a
properly formatted data steam for output to the SDRAMs. This component is used with the remaining
SDRAM signals not covered by MSD_ITMD or MSD_ITMS.
Figure 9-22 MSD_ITMC_D2 Timing Translation
The MSD_ITMC_D2 component is used to generate internal-to-external (write data and command) timing
translation for either single data rate or double data rate command timing.
9.3.1.1.1 LPDDR2 Operation
The address and command signals operate in double data rate in LPDDR2 mode. The Timing Mode Select
Line signal (tmsel) controls whether the address and command signals operate at single data rate or double
data rate.
buffer
buffer
oe
dout[1:0]
di
clk_0
clk_90
clk_180
clk_270
pre_clk_0
pre_clk_90
pre_clk_180
pre_clk_270
M
V
D
D
M
V
S
S
io_oe
io_do
io_di
I
n
t
e
r
f
a
c
e
t
o
C
o
n
t
r
o
l
l
e
r
I
n
t
e
r
f
a
c
e
t
o
S
S
T
L
I
/
O
connect to abutment
do_set_b
do_rst_b
tmsel
SolvNet
DesignWare.com
Example connections using ITMC_D2 to create CK, CK_b, and single or double data rate command/address
outputs, depending on the tmsel signal settings (see MSD_ITMC_D2 Pin List on page 114), are shown in
Figure 9-23 on page 111.
Figure 9-23 ITMC_D2 Connectivity
The timing relationships of ITMC_D2 differ slightly from ITMD/ITMS to properly align the output
transitions. In all ITM cells, dout[1:0] is first captured by a rising edge on clk_0. In ITMC_D2, dout[1] is the
first data to be output on the first rising edge of clk_270 following the rising edge of clk_0, which captured
this data. In ITMC_D2, dout[0] is the second data to be output on the second rising edge of clk_90 following
the rising edge of clk_0, which captured this data.
For single data rate address/command (for example DDR2 or DDR3 applications), dout[0] and dout[1] are
driven by the same value to create single data rates (refer to Figure 9-23 on page 111). In single data rate
address/command signals, the tmsel signal is set to 0.
For double data rate address/command (for example, LPDDR2 applications), dout[0] and dout[1] have the
values of beat 0 and beat 1 of the double data rate output. In double data rate, the tmsel signal is set to 1.
CK and CK_b are always double data rate outputs, regardless of whether it is a single or double data rate
address/command application.
dout[1]
dout[0]
ITMC_D2
ctrl_a_0[0]
dout[1]
dout[0]
CK
dout[1]
dout[0]
dout[1]
dout[0]
RAS_b
ctrl_rasb[0]
1'b0 1'b1

CK_b
ctrl_a_0[1]
tmsel = 1
A[0] a_0
ck
ck_b
ras_b
tmsel = 0
ITMC_D2
ITMC_D2
ITMC_D2
ctrl_rasb[1]
tmsel = 0
tmsel = 1
SolvNet
DesignWare.com
Functionality and timing for internal-to-external operation for creating CK and CK_b is shown in
Figure 9-24 on page 112.
Figure 9-24 ITMC_D2 Internal-to-External Data Output Functional Timing
Functionality and timing for internal-to-external operation for creating double data rate address/command,
for example in an LPDDR2 application is shown in Figure 9-25 on page 112
Figure 9-25 ITMC_D2 Internal-to-External Data Output Functional Timing, Double Data Rate (tmsel = 1)
tCK tCH
clk_0
clk_90
clk_180
clk_270
tCL
dout3,dout2 dout1,dout0
1
1
dout[1:0]
do_set_b
do_rst_b
io_do
tSU tHD
tPROP270 tPROP90

tCK tCH
clk_0
clk_90
clk_180
clk_270
tCL
1
1
dout[1:0]
do_set_b
do_rst_b
io_do
tSU tHD
tPROP270 tPROP90

SolvNet
DesignWare.com
Functionality and timing for internal-to-external operation for creating single data rate address/command,
for example in an DDR2 and DDR3 applications is shown in Figure 9-26 on page 113
Figure 9-26 MSD_ITMC_D2 Internal-to-External Data Output Functional Timing, Single Data Rate (tmsel = 0)
Functionality and timing for internal-to-external operation for output set/reset is shown in Figure 9-27.
Figure 9-27 MSD_ITMC_D2 Internal-to-External Data Output Set/Reset Timing
9.3.1.2 External-to-Internal Timing Translation
Unlike bidirectional data and data strobe I/Os, DDR2 command I/Os are output only. Therefore, no high
performance external-to-internal timing translation is required. The ITMC_D2 component buffers io_di
(from the data I/O) through to internal interface port di. This circuitry can be used if low-speed,
bidirectional functional testing of the command I/Os is required.
clk_0
clk_90
clk_180
clk_270
1
1
dout[1:0]
do_set_b
do_rst_b
io_do
tSU tHD
tPROP270
dout0 dout1

clk_0
clk_90
clk_180
clk_270
io_do
do_set_b
do_rst_b
X
dout[1:0]
tSRPW
tSRPW
tPROPS
tPROPR

SolvNet
DesignWare.com
9.3.1.3 MSD_ITMC_D2 Pin List
Table 9-13 shows the pin list for the MSD_ITMC_D2 component.
Table 9-13 MSD_ITMC_D2 Pin List
General Inputs
pre_clk_0 input Feed-through clock. Connects by abutment.
tmsel input Timing Mode Select Line
0=Single Data Rate, 1=Double Data Rate
Internal Controller Interface Enable
oe input Output enable control for I/O. Asynchronous.
Data Out
dout[0] is data output generated by the second clk_90 rising edge after the clk_0 rising edge which
captured dout[0]
captured dout[1]
Data In
di output Data input from I/O. Asynchronous. Buffered version of input io_di.
io_di input Data input from I/O. Asynchronous.
io_oe output Data output enable to I/O. Asynchronous
Supply
MVDD input Power
MVSS input Ground
SolvNet
DesignWare.com
9.3.2 Command Lane Clock Buffer, Stage 0 (MSD_ITMCB0)
The Synopsys ITM command lane clock buffer, Stage 0 (MSD_ITMCB0) is used in a command lane PHY for
distribution of clocks to the command lane clock buffer, Stage 1 (MSD_ITMCB1).
One MSD_ITMCB0 block is used per command lane. Inputs are designed to allow connectivity by abutment
to the command lane Master DLL (MSD_MDLL_DDR). Outputs connect by abutment to other command
lane ITMs.
AC specifications for MSD_ITMCB0 are outlined in DC and AC Characteristics on page 120. Placement
limitations within a command lane are outlined in Placement Specifications on page 126.
Figure 9-28 Command Lane Clock Buffer, Stage 0 (MSD_ITMCB0)
SolvNet
DesignWare.com
Table 9-14 MSD_ITMCB0 Pin List
Input Clocks Connected to Byte Lane Master/Slave DLL
in_clk_0 input Input clock.
in_clk_180 input Input clock, phase shifted 180from in_clk_0
in_clk_270 input Input clock, phase shifted 270from in_clk_0
Feed-Through Clocks Connected by Abutment to other Command Lane ITMs
clk_0 input Feed-through clock.
Output Clocks Connected by Abutment to other Command Lane ITMs
pre_clk_0 output Output clock. Buffered version of in_clk_0.
Supply
MVDD input Power
MVSS input Ground
SolvNet
DesignWare.com
9.3.3 Command Lane Clock Buffer, Stage 1 (MSD_ITMCB1)
The Synopsys ITM command lane clock buffer stage 1 (MSD_ITMCB1) is used in a command lane PHY for
distribution of clocks to command lane ITMs. Two MSD_ITMCB1 blocks are used per command lane, and
clock inputs and outputs connect by abutment to other command lane ITMs.
AC specifications for MSD_ITMCB1 are outlined in DC and AC Characteristics on page 120. Placement
limitations within a command lane are outlined in Placement Specifications on page 126.
Figure 9-29 Command Lane Clock Buffer, Stage 1 (MSD_ITMCB1)
Table 9-15 MSD_ITMCB1 Pin List
Input Clocks Connected by Abutment to Other Command Lane ITMs
pre_clk_0 input Input pre-drive clock.
pre_clk_90 input Input pre-drive clock, phase shifted 90from pre_clk_0.
pre_clk_180 input Input pre-drive clock, phase shifted 180from pre_clk_0
pre_clk_270 input Input pre-drive clock, phase shifted 270from pre_clk_0
Output Clocks Connected by Abutment to Other Command Lane ITMs
clk_0 output Output clock. Buffered version of pre_clk_0.
Supply
MVDD input Power
MVSS input Ground
SolvNet
DesignWare.com
9.3.4 ITM Command Lane Fill Cells
The Interface Timing Module Command Lane Fill Cells connect clocks by abutment between other
Command Lane ITMs.
The MSD_ITMCFILLxx cells have no functional behavior. The MSD_ITMCFILLxx cells are provided in
different widths to allow PHY construction with different I/O pitches.
Figure 9-30 ITM Command Lane Fill Cells (MSD_ITMCFILLxx)
The MSD_ITMCFILLxx_BREAK cell creates a break in the predrive clock tracks, and is placed in the first
blank ITM spot outside the MSD_ITMCB1 block within a Command Lane PHY.
This cell drives the disconnected portions of the predrive clock tracks to logic 0.
Table 9-16 ITM Command Lane Fill Cell (MSD_ITMCFILLxx) Pin List
clk_0 input
Feed-through Clocks
Connected by abutment to other Command Lane ITMs
clk_90 input
clk_180 input
clk_270 input
pre_clk_0 input
pre_clk_90 input
pre_clk_180 input
pre_clk_270 input
MVSS input Supply: Power
MVDD input Supply: Ground
SolvNet
DesignWare.com
Figure 9-31 ITM Command Lane Fill Cells (MSD_ITMCFILLxx_BREAK)
The ITM command lane Endcap Cell (MSD_ITMCENDCAP) provides a means to ensure no design rule
violations at the ends of the command lane. This block has no functional behavior or pins.
Figure 9-32 ITM Command Lande Endcap Cell (MSD_ITMCENDCAP)
Table 9-17 ITM Command Lane Fill Cell (MSD_ITMCFILLxx_BREAK) Pin List
clk_0 input
Feed through Clocks
Connected by abutment to other Command
Lane ITMs
clk_90 input
clk_180 input
clk_270 input
pre_clk_0 output
Output Predrive Clocks
Driven to static logic 0
pre_clk_90 output
pre_clk_180 output
pre_clk_270 output
MVDD input Supply: Power
MVSS input Supply: Ground
SolvNet
DesignWare.com
9.4 DC and AC Characteristics
This table provides the supply values for DC design criteria only. These values represent the DC supply
limits at the devices internal to the design, including the effects of internal IR drop.
The following table provides maximum DC current and power when all inputs are quiet/static: typical
process, nom VDD, and temperature 25C; fast process, max VDD [VDD+10%], and temperature 125C. These
parameters are simulated. In the event of test silicon, these parameters may not be measured.
Table 9-18 Recommended Operating Conditions
V
DD Supply voltage
1
1. The power supply values specified in the table are DC design criteria only. They represent the DC supply limits at
the devices internal to the design, including the effects of internal IR drop.
0.99 1.10 1.21 V
T
J
Junction temperature -40 25 125

C
Table 9-19 ITM Leakage Current
I
LEAK
Leakage Power msd_itmd 0.33 39.3008 uW
I
LEAK
Leakage Power msd_itms 0.275 35.4167 uW
I
LEAK
Leakage Power msd_itmc_D2_tmsel=0 0.077 10.527 uW
I
LEAK
Leakage Power msd_itmc D2_tmsel=1 0.077 10.648 uW
I
LEAK
Leakage Power msd_itmbb 0.187 22.0583 uW
I
LEAK
Leakage Power msd_itmcb0 0.242 29.4151 uW
I
LEAK
Leakage Power msd_itmcb1 0.242 29.403 uW
SolvNet
DesignWare.com
9.4.3.1 Clock and Reset Timing Restrictions
This table provides clock timing restrictions applicable to clk_0, clk_90, clk_180, and clk_270 inputs on
MSD_ITMD, MSD_ITMS, MSD_ITMC_D2, as well to rclk input on MSD_ITMD. The minimum values
represents external to the chip requirements that have to be met to achieve the specified performance. Some
parameters are simulated. In the event of test silicon these parameters may not be measured.
Table 9-20 Clock and Reset Timing Restrictions
Symbol Parameter Min Max Units
Clocks
t
CK
Clock cycle 1.875 ns
t
CH
Clock high pulse width
625 ps
t
CL
Clock low pulse width
t
CKPH
Delay between adjacent clock phase rising edges
clk_0 to clk_90
clk_90 to clk_180
clk_180 to clk_270
clk_270 to clk_0
300 ps
Set/Reset t
SRPW
Set / reset pulse width
Applies to all rst_b, srst_b, do_rst_b, do_set_b,
oe_rst_b, oe_set_b inputs of all modules.
4
clock
cycles
SolvNet
DesignWare.com
9.4.3.2 Setup and Hold Times
The following table provides brief performance characteristics of the ITMs based on 533 MHz slow
conditions, input transition of 40ps (30%-70%), and 25fF load. Note that setup and hold values can be
adjusted from the default value listed by changing MSD_ITMD input trim bits di_trm[1:0] for data latched
by dqs and di_trm[3:2] for data latched by dqsb:
ITMD (dqs_90/dqsb_90, msd_itmbb) is simulated using 240fF capacitive load (approximation of
complete byte lane).
ITMC_D2 (msd_itmcb0, msd_itmsb1) is simulated using 380 fF capacitive load (approximation of
complete command lane).
The parameters are simulated. In the event of test silicon, these parameters may not be measured.
Table 9-21 Setup and Hold Times
Symbol Cell Data Related Clock Setup (ns) Hold (ns)
t
SU
/t
HD
ITMS
dqs_dis clk_0 -0.16 0.29
dqs_en clk_0
phase_sel clk_0 -0.05 0.18
oe clk_0 0.04 0.1
dout clk_0 -0.01 0.1
ITMD
read rclk 0.12 -0.04
io_di dqs_90 0.8 -0.71
io_di dqsb_90
oe clk_0 0.05 0.09
dout clk_0
ITMD2 dout clk_0 0.01 0.13
SolvNet
DesignWare.com
9.4.3.3 Propagation Delays
The following table provides a summary of timing information of the ITMs for the Byte Lane. Note that
delay values to the dqs pin can be adjusted from the default value listed by changing MSD_ITMD input trim
bits dqs_trm[2:0]. The parameters are obtained by simulation using slow conditions (process=slow,
V=VDD(nom)-10%, T=125C), 40ps(30%-70%) input transition, and 25 fF load.. In the event of test silicon,
these parameters may not be measured.
Table 9-22 Propagation Delays
Cell Symbol From Pin To Pin Delay Max (ps)
MSD_ITMS
io_di_1 dqs
726.40
io_di_0 dqs
clk_90 io_do
766.80
clk_270 io_do
MSD_ITMD
tPROP0 clk_0 io_do
791.0
tPROP180 clk_180 io_do
clk_0 io_oe
clk_180 io_oe
tPROPV rclk valid 276.10
tPROPD rclk di 587.40
MSD_ITMC_D2_tmsel=0
io_di di
114.40
oe io_oe
t
PROP90
clk_90 io_do
766.40
t
PROP270
clk_270 io_do
MSD_ITMC_D2_tmsel=1
io_di di
114.40
oe io_oe
t
PROP90
clk_90 io_do
787.60
t
PROP270
clk_270 io_do
MSD_ITMBB
in_clk_0 clk_0
91.41
in_clk_90 clk_90
in_clk_180 clk_180
in_clk_270 clk_270
in_dqs_90 dqs_90
in_dqsb_90 dqsb_90
SolvNet
DesignWare.com
9.4.3.4 ITM Trim Control
The following table provides delay specifications for data and strobe trim step size. The parameters are
obtained by simulation; in the event of test silicon, these parameters may not be measured.
MSD_ITMCB0
in_clk_0 pre_clk_0
87.21
in_clk_90 pre_clk_90
MSD_ITMCB1
pre_clk_0 clk_0
87.40
pre_clk_90 clk_90
pre_clk_180 clk_180
pre_clk_270 clk_270
Table 9-23 ITM Trim Control
Description Control Signal Cell Min Typ Units
Delay Step Size dqs_trm ITMS 15.51 23.89 ps
Table 9-22 Propagation Delays (Continued)
Cell Symbol From Pin To Pin Delay Max (ps)
SolvNet
DesignWare.com
9.4.3.5 AC Power Dissipation
The following tables provide the power dissipation for ITM cells. The parameters are obtained by
simulation: typical process, nom VDD, and temperature 25C; VDD+10%, Fast process, 125C, f=533 MHz. In
the event of test silicon, these parameters may not be measured.
Table 9-24 AC Power Specifications
PAC_ITMD_ACT0 Total active power (msd_itmd), rdqs not
toggling,output not toggling, input not
toggling
0.68 0.96 uW/MHz
PAC_ITMD_ACT1 Total active power (msd_itmd), rdqs not
toggling,output toggling, input toggling
1.03 1.42 uW/MHz
PAC_ITMD_ACT2 Total active power (msd_itmd), rdqs
toggling,output not toggling, input not
toggling
1.1 1.51 uW/MHz
toggling,output not toggling, input toggling
1.4 1.91 uW/MHz
toggling,output toggling, input toggling
1.57 2.13 uW/MHz
PAC_ITMS_ACT0 Total active power (msd_itms), DQS output
toggling
1.2 1.7 uW/MHz
PAC_ITMS_ACT1 Total active power (msd_itms), DQS input
toggling
1.27 1.82 uW/MHz
PAC_ITMS_ACT2 Total active power (msd_itms), DQS output
and input toggling
1.43 2 uW/MHz
PAC_ITMS_ACT3 Total active power (msd_itms), DQS not
toggling
1.05 1.51 uW/MHz
PAC_ITMCD2_S0_MAX Total active power (msd_itmc_D2), data
toggling 100% tmsel=0
0.45 0.62 uW/MHz
PAC_ITMCD2_S0_MIN Total active power (msd_itmc_D2), data not
toggling tmsel=0
0.29 0.4 uW/MHz
PAC_ITMCD2_S1_MAX Total active power (msd_itmc_D2), data
toggling 100% tmsel=1
0.45 0.62 uW/MHz
PAC_ITMCD2_S1_MIN Total active power (msd_itmc_D2), data not
toggling tmsel=1
0.29 0.4 uW/MHz
PAC_ITMBB Total active power (msd_itmbb) 2.53 3.28 uW/MHz
PAC_ITMB0 Total active power (msd_itmcb0) 2.85 3.78 uW/MHz
PAC_ITMB1 Total active power (msd_itmcb1) 2.16 2.97 uW/MHz
SolvNet
DesignWare.com
9.5 Placement Specifications
Table 9-25 shows the placement specifications of the ITM.
Table 9-25 Placement Specifications
Variable Cell Minimum Maximum Units
B Byte lane length 2000 um
B0 Distance from byte lane edge to MSD_ITMBB center 0.47 0.53 % byte lane length
B1 Fill distance between byte lane ITMs 1 um
C Command lane length 4000 um
C0 Distance from command lane edge to MSD_ITMCB0
center
0.48 0.52 % Command lane length
C1 Distance from MSD_ITMCB0 center to MSD_ITMCB1
center
0.20 0.30 % Command lane length
C2 Fill distance between command lane ITMs 1 um
SolvNet
DesignWare.com
Figure 9-33 Byte and Command Lane PHY Placement Specifications
SolvNet
DesignWare.com
SolvNet
DesignWare.com
10
SSTL I/O Library
This chapter discusses the following topics concerning the Synopsys DDRn series SSTL (Stub Series
Terminated Logic):
SSTL I/O Library Overview on page 130
Bi-Directional Buffer (MSD_D3R_PDDRIO) on page 136
Differential Bi-Directional Buffer (MSD_D3R_PDIFF) on page 140
ZQ Calibration Cell (MSD_D3R_PZQ) on page 144
Impedance Calibration Circuit on page 149
Impedance Control Logic (MSD_D3R_zctrl) on page 156
Reference Voltage Cell (MSD_D3R_PVREF) on page 160
Retention Latch Enable Input - External (MSD_D3R_PRETLEX) on page 169
Retention Latch Enable Input - Core (MSD_D3R_PRETLEC) on page 176
Analog Signal Cell (MSD_D3R_PAIO) on page 178
Power/Ground Supply Cells on page 179
Corner and Filler Cells on page 181
Wire Bond Pad Cells with Decoupling on page 183
SnapCap Cells on page 185
SSTL I/O DC and AC Characteristics on page 190
Power-Up/Power-Down Sequence Requirements on page 219
SolvNet
DesignWare.com
10.1 SSTL I/O Library Overview
The DDR2/3-Lite/mDDRs SSTL I/O library elements support the following JEDEC specifications:
DDR2
DDR3
DDR3L
LPDDR (referred to as Mobile DDR)
LPDDR2
This library supports operational data rates up to 1600 Mb/s per I/O, permitting an 800 MHz memory
system operating in double-data rate (DDR) mode. It also supports PVT compensated on-die termination
(ODT) and output impedance. For an illustration of the SSTL I/O in the DWC DDR3/2 SDRAM PHY
solution, refer to Figure 1-1 on page 14.
10.1.1 Key Features
The DDR2/3-Lite/mDDRs SSTL I/O includes the following features:
DDR2/DDR3LPDDR2/Mobile DDR operating modes
Programmable input termination (ODT)
DDR3: 40/60/120 ohms
DDR2: 50/75/150 ohms
Programmable output impedance
PVT-compensated ODT and output impedance
Driver and receiver power-down control
Embedded boundary scan support logic
PAD and internal loopback modes
Supports in-line and staggered wirebond, and flip-chip applications
Library complete with functional, power, analog, fill, and corner cells
Retention feature maintains I/O cell state during VDD power down
The following table shows the process information for the SSTL I/Os.
Notes:
Please contact your sales representative for availability in alternate process nodes/variants.
Table 10-1 Process Information
SMIC 40nm LL 0.99V 2.5V low-K 6/7/8/9
DDR multiPHY for SMIC40LL25 Databook SSTL I/O Library
SolvNet
DesignWare.com
10.1.3 I/O Metal Stacks
The following table lists the I/O library metal stack otions provided with this DWC DDR PHY release.
Please contact your sales representative if your metal stack option is not listed.
Table 10-2 Metal Stack Options
DWC DDR
PHY Metal Stack
1
1. Metal stack naming convention:
a) The foundry's metal stack naming convention is used as the basis for the Synopsys naming convention
b) The AP layer is not included in the total metal count used for the metal stack name
c) 0 values are suppressed
d) The metal stack name reflects the actual layers delivered in the SSTL library GDS and not necessarily the metal
stack of the IC in which it can be used
e) If there is no suffix on the metal stack name then it contains wire bond pads for use in fully stacking wire bond ICs
only. The IO cells can be used in either fully stacking wire bond ICs or FC (Flip Chip) ICs while the bond pads can
only be used in fully stacking wire bond ICs.
f) If there is a _cup suffix on the metal stack name then it contains wire bond pads for use in CUP wire bond ICs
only. The IO cells can be used in either CUP wire bond ICs or FC ICs while the wire bond pads can only be used
in CUP wire bond ICs. Note that the total number of metal layers included in a _cup metal stack name (Xm)
refers to the combination of the IO cells and the wire bond pads. So the IO cells contain X-2 metal layers and the
wire bond pad contains metal layers X and X-1.
g) If there is a _fc suffix then the metal stack is not included in the foundry's list of supported metal stacks.
Additional metal layers must be added at the chip level to make it match one of the foundry's supported metal
stacks. Such metal stacks can only be used for FC ICs and, therefore, do not include any wire bond pads. Note
that the FC bump pads are NOT included in these or any other metal stacks.
Top Metal
in I/O
Cells
Pad Metal in
Bond Pads
2
2. This column indicates which PAD pin metal layers are present in the bond pad under the passivation opening. All bond
pads supplied with this IP, whatever the suffix, are compliant with the CUP pad DRC rules, not the fully stacking pad
DRC rules. The bond pads supplied for fully stacking bond pad ICs do not comply with the fully stacking bond pad DRC
rules as m1 and m2 are not connected to the PAD pin and there are active circuits under the bond pad. m1, m2 and the
active circuitry are associated with the VDDQ/VSSQ decoupling included in these bond pads. However, while all bond
pads are technically CUP bond pads, there are two distinct bond pad types in the DWC DDRn SSTL libraries - those
designed for fully stacking bond pad ICs (named PPADCWxxx) and those for CUP bond pad ICs (named PPADCxxx).
See the next two notes for the details. Note that more and thicker metals in the fully stacking wire bond pads and the IO
cells will reduce their IR drop and increase their EM limit.
Fully
Stacking
Wire Bond
IC
3
3. This column indicates if the metal stack can be used in a fully stacking wire bond IC - the fully stacking wire bond pad
includes all metal layers plus the AP layer. It is placed as a linear extension of the IO cell and abutted to it. Its advantage
is that it does not require any additional metal layers but it does increase the effective height of the IO cell. It has the
additional advantage of including a significant amount of VDDQ/VSSQ decoupling.
CUP Wire
Bond IC
4
4. This column indicates if the metal stack can be used in a CUP wire bond IC - the wire bond pad includes only the top two
metal layers plus the AP layer. It is placed on top of the IO cell with its origin aligned with the IO cell's origin. Its
advantage is that it does not increase the effective height of the IO cell but it does use two additional metal layers. It does
NOT include any VDDQ/VSSQ decoupling - if additional VDDQ/VSSQ decoupling is required the PSCAP cells can be
used.
Flip Chip IC
5
Included
Bond Pads
SMIC40LL25 9m2t 9 3,4,5,6,7,8,9 Yes No Yes PPADCWxxx
SSTL I/O Library DDR multiPHY for SMIC40LL25 Databook
SolvNet
DesignWare.com
10.1.4 Deliverables
Table 10-3 provides the deliverables include all views required to support a typical ASIC design flow.
5. This column indicates if the metal stack can be used in a Flip Chip (FC) IC. Bond pads are not allowed in a FC IC -
connection from the PAD pin of the IO cell to the package is made by using higher metal layers and/or a redistribution
(RDL) layer to route from the PAD pin of the IO to a FC bump pad. This is similar to CUP in that it avoids an increase in
the effective height of the IO cell but requires additional metal and/or RDL layers. FC can have the advantage over wire
bond (fully stacked and CUP) of higher interconnect density and better signal integrity if properly implemented. If
additional VDDQ/VSSQ decoupling is required the PSCAP cells can be used.
Table 10-3 Deliverables
Deliverable Description
Behavioral Verilog
Timing Synopsys lib
Layout Abstract LEF
LVS Netlist
1
1. The cells in the SSTL I/O library are designed to be used to create an I/O ring for the PHY. Running DRC/LVS
on individual cells will report violations.
Spice
System Design Model IBIS
Encrypted HSPICE Netlist HSPICE simulation netlist
RTL (ZQ Impedance Control Logic) Verilog
IBIS Models IBIS models of the PDDRIO, and PDIFF cells
Documentation *.pdf files, namely this databook and the Implementation Guide
SolvNet
DesignWare.com
10.1.5 Cell List
The following table provides the cell list for the SSTL I/Os.
Table 10-4 SSTL I/O Cell List
MSD_D3R_PDDRIO Bi-directional SSTLcell for address, control, clock,
data, and data strobes
30um 260um
MSD_D3R_PDIFF Differential bi-directional cell, used with external
source clocks
30um 260um
MSD_D3R_PDQSR PU/PD Resistor cell used with PDIFF cells 30um 260um
MSD_D3R_PDQSR_VSSQ PU/PD resistor cell used PDIFF cells. Secondary
function: VSSQ I/O ground cell (0V)
30um 260um
MSD_D3R_PZQ ZQ calibration cell (external precision resistor to
ground)
30um 260um
MSD_D3R_PAIO Analog signal cell 30um 260um
MSD_D3R_PRETLEC Retention Latch Enable cell with core side control 30um 260um
MSD_D3R_PRETLEX Retention Latch Enable cell with external control 30um 260um
MSD_D3R_PVAA Analog power cell 30um 260um
MSD_D3R_PVAA_PLL PLL supply cell 30um 260um
MSD_D3R_PVSS_PLL PLL ground cell 30um 260um
MSD_D3R_PVDD VDD core supply cell 30um 260um
MSD_D3R_PVSS VSS core ground cell 30um 260um
MSD_D3R_PVREF VREF SSTL reference supply cell (nominally 0.5 *
VDDQ)
30um 260um
MSD_D3R_PVDDQ VDDQ I/O supply cell (1.5V or 1.8V) 30um 260um
MSD_D3R_PVSSQ VSSQ I/O ground cell (0V) 30um 260um
MSD_D3R_PVSSQ_RDIS VSSQ I/O ground cell (0V) with Retention Disable 30um 260um
MSD_D3R_PVSSQZB VSSQ I/O ground cell (0V) with ZIOH impedance
control bus break
30um 260um
MSD_D3R_PEND End cap cell to define end of DDR interface
segment without continuing any power / signal
connectivity
5um 260um
MSD_D3R_PEND_P End cap cell to define end of DDR interface
segment without
continuing any power / signal connectivity, except
MVSS and
LENH
5um 260um
MSD_D3R_PFILL_1 0.1 um spacer cell
0.1um
1
260um
SolvNet
DesignWare.com
MSD_D3R_PFILL_5 0.5 um spacer cell
0.5um
1
260um
MSD_D3R_PFILL1 1 um spacer cell 1um 260um
MSD_D3R_PFILL5 5 um spacer cell 5um 260um
MSD_D3R_PFILL5_ISO 5.0 um spacer cell with VDDQ break 5um 260um
MSD_D3R_PFILL_1_RES 0.1 um spacer cell used with PDQSR cell only
0.1um
2
260um
MSD_D3R_PFILL_5_RES 0.5 um spacer cell used with PDQSR cell only
0.5um
2
260um
MSD_D3R_PFILL1_RES 1 um spacer cell used with PDQSR cell only 1um 260um
MSD_D3R_PFILL5_RES 5 um spacer cell used with PDQSR cell only 5um 260um
MSD_D3R_PFILL5_LENHB 5.0 um spacer cell with LENH break 5um 260um
MSD_D3R_PCORNER corner cell 260um 260um
MSD_D3R_PPADCWI30_CUP wirebond pad (inner) for 30um staggered
applications
30um 171um
MSD_D3R_PPADCWO30_CUP wirebond pad (outer) for 30 um staggered
applications
30um 171um
MSD_D3R_PPADCWI30_VDDQ wirebond pad (inner) for 30um staggered
applications, for VDDQ cell
30um 171um
MSD_D3R_PPADCWO30_VDDQ wirebond pad (outer) for 30um staggered
applications, for VDDQ cell
30um 171um
MSD_D3R_PPADCWI30_VSSQ wirebond pad (inner) for 30um staggered
applications, for VSSQ cell
30um 171um
MSD_D3R_PPADCWO30_VSSQ wirebond pad (outer) for 30um staggered
applications, for VSSQ cell
30um 171um
MSD_D3R_PPADCW30_FILL5 wirebond pad 5um spacer cell 5um 171um
MSD_D3R_PPADCW30_FILL1 wirebond pad 1um spacer cell 1um 171um
MSD_D3R_PPADCW30_FILL_5 wirebond pad 0.5um spacer cell 0.5um 171um
MSD_D3R_PPADCW30_FILL_1 wirebond pad 0.1um spacer cell 0.1um 171um
MSD_D3R_PPADCW30_FILL5_ISO wirebond pad 5.0 um spacer cell with VDDQ
break
5um 171um
MSD_D3R_PPADCW30_END End cap cell to define end of 30umstaggered PAD
interface segment
5um 171
MSD_D3R_PSCAP_CUP VDDQ-VSSQ decoupling cap cell 30um 30um
MSD_D3R_PSCAP_VDDQ VDDQ-VSSQ decoupling cap cell abutting to
PVDDQ cell
30um 30um
MSD_D3R_PSCAP_VSSQ VDDQ-VSSQ decoupling cap cell abutting to
PVSSQ cell
30um 30um
Table 10-4 SSTL I/O Cell List (Continued)
SolvNet
DesignWare.com
10.1.6 Cell Position
Some cells must be flipped when they are placed at the left hand end of an SSTL segment or sub-segment.
Refer to the DesignWare Cores DDR2/3-Lite/mDDR/multiPHY SDRAM PHY Implementation Guide for more
information.
MSD_D3R_PSCAP_FILL5 5 um spacer cell for PSCAPs 5um 30um
MSD_D3R_PSCAP_FILL1 1 um spacer cell for PSCAPs 1um 30um
MSD_D3R_PSCAP_FILL_5 0.5 um spacer cell for PSCAPs 0.5um 30um
MSD_D3R_PSCAP_FILL_1 0.1 um spacer cell for PSCAPs 1um 30um
MSD_D3R_PSCAP_FILL5_ISO 5 um spacer cell for PSCAPs with VDDQ break 5um 30um
MSD_D3R_PSCAP_END End cap cell to define end of PSCAP segment 5um 30um
1. If "FILL" cells are used minimum "FILL" is 1um. This cell can be used in conjunction with other fill cells.
2. If DQSR "FILL" cells are used minimum "FILL" is 1um. This cell can be used in conjunction with other DQSR fill cells.
3. CUP pads are not automatically delivered with every metal stack option in a library; to request CUP pads, please contact
your sales representative.
Table 10-4 SSTL I/O Cell List (Continued)
SolvNet
DesignWare.com
10.2 Bi-Directional Buffer (MSD_D3R_PDDRIO)
This section includes the following subsections:
General Description
Pin List on page 137
Operating Modes on page 139
10.2.1 General Description
Figure 10-1 Bi-Directional SSTL Buffer (MSD_D3R_PDDRIO)
PAD
ESD1 IOM
ESD2
M
V
S
S
TE
DI
L
E
N
H
OUTBUF
ODT
OJ
DOUT
SJ
INBUF
M
V
R
E
F
M
V
D
D
Q
M
V
S
S
Q
M
V
D
D
Z
I
O
H
[
6
3
:
0
]
DT
ET
LB
DJ
OE
1
0
0
1
0
1
PDD
PDR
The bidirectional SSTL buffer
(MSD_D3R_PDDRIO) is a
1.2V/1.35V/1.5V/1.8V DDR specific
SSTL compatible high-speed bidirectional
buffer with programmable ODT,
programmable output impedance, and
embedded boundary scan support logic.
An impedance control bus ZIOH[63:0] is
embedded within the SSTL I/O cells.
Connectivity of this embedded bus is
completed by abutting the SSTL cells.
ZIOH[63:0] is driven in the VDDQ voltage
domain by drivers in the
MSD_D3R_PVREF cell and should never
be connected to devices operating at core
logic voltage (VDD).
Inputs are provided for independently
setting the pull-up (ZIOH[31:16]) and
pull-down (ZIOH[15:0]) output
impedance. These settings can be static or,
when coupled with an impedance control
loop, can be used to permit controlled
PVT-compensation. These busses are
modified-thermometer encoded.
Inputs are provided for independently setting the pull-up (ZIOH[63:48]) and pull-down (ZIOH[47:32]) ODT
value. These settings can be static or, when coupled with an impedance control loop, can be used to permit
controlled PVT-compensation. These busses are modified-thermometer encoded.
For IDDQ testing, the SSTL differential input receiver and the high-speed output driver level shifter can be
disabled to remove their DC current paths. When the SSTL input receiver is disabled, a Mobile DDR mode is
enabled permitting a data flow from bond-pad to core for test purposes. When the high-speed output driver
level shifter is disabled a lower-performance level shifter with no static DC current paths is enabled. ODT is
automatically disabled when operating in Mobile DDR mode.
MUX functions are included to allow the selection of the normal mission-mode paths for output data and
output enable (DOUT and OE) or test paths (DJ and OJ). The test output paths support boundary scan
connectivity or other test functions required by the user. A decoupled path for input data (DT) is included
along with an enable function (ET) to disable this path when not required. The test input path supports
boundary scan connectivity, or other test functions required by the user.
SolvNet
DesignWare.com
Selection of either DDR3 or DDR2 operating modes is established by the voltage applied to MVDDQ: 1.5V
nominal for DDR3 and 1.8V nominal for DDR2. This ensures proper interface levels at startup/initialization
without requiring software initialization to set the proper operating mode.
10.2.2 Pin List
Table 10-5 shows the pin list for the MSD_D3R_PDDRIO buffer.
Table 10-5 MSD_D3R_PDDRIO Pin List
DI output Data In: data path from bond pad to core
DT output Test Data In: data path from bond pad to core with disable capability
ET input Test Data In Enable: set to '1' to enable or '0' to disable the test data input path
DOUT input Data Out: data path from core to bond pad
DJ input Test Data Out: data path from core to bond pad
SJ input Test Select: set to '0' to select normal paths or '1' to select test paths for output data and
output enable
OE input Output Enable: Active-high output enable.
1 = output driver is enabled
0 = output driver is disabled.
ODT is automatically disabled when output driver is enabled.
OJ input Test Output Enable: Active-high output enable.
0 = output driver is disabled
PAD inout Bond Pad
IOM input I/O Mode: I/O Mode select
0 = DDR2/DDR3/LPDDR2 mode
1 = Mobile DDR mode
PDD input Power Down Driver: Active high driver power down
0 = normal operation
1 = output driver powered down
When PDD is asserted, the output driver still operates and passes data from the core side
to the pad pin. When the cell is in output mode, the driver still drives the pad pin. All DC
currents are disabled when PDD is asserted and the output only functions at a very low
frequency. If the signal being driven is terminated externally, the I/O cell continues to draw
DC current even when PDD is asserted due to the external termination. ODT is
automatically disabled when the output driver is powered down.
PDR input Power Down Receiver: Active high receiver power down
1 = input buffer powered down
DI and DT are set to logic 0 when the receiver is powered down. The receiver is non-
functional when PDR is asserted.
SolvNet
DesignWare.com
LB input Loopback: Active high internal loopback enable
1 = loopback DOUT to DI in core voltage logic
Note that DOUT data will also appear on the PAD pin if OE is high and PDD is low
ZIOH[63:0] input Impedance Control: Thermometer encoded bus that controls the value of ODT and output
impedance. Note this bus is driven in the VDDQ voltage domain by drivers in the cell
MSD_D3R_PVREF. This bus should not connect to devices operating in the core logic
voltage domain (VDD).
ZIOH[63:48]: Used to select the pull-up termination impedance. For details, see Section
Impedance Divide Ratios.
ZIOH[47:32]: Used to select the pull-down termination impedance. For details, see Section
ZIOH[31:16]: Used to select the pull-up output impedance. For details, see Section
ZIOH[15:0]: Used to select the pull-down output impedance. For details, see Section
TE input On-Die Termination Enable. Active-high signal.
1 = ODT is enabled
0 = ODT is disabled
ODT is also disabled when OE is high and SJ is low or OJ is high and SJ is high regardless
of the value of TE.
LENH Input Latch Enable: Active high retention latch enable. Note this signal is driven in the VDDQ
voltage domain by drivers in the cell , MSD_D3R_PRETLEX and MSD_DSR_PRETLEC.
This signal should not be connected to devices operating in the core logic voltage domain
(VDD).
0 = Retention Latch Disabled (normal mode)
1 = Retention Latch Enabled (retention mode)
In retention mode, the values of the control and DOUT inputs are latched so that the state
of the PAD pin is retained if the core supply (VDD) is removed.
MVDDQ input I/O supply connection (1.2V/1.35V1.5V/1.8V)
MVREF input VREF SSTL reference supply connection
MVSSQ input I/O ground connection (0V)
MVDD input Core supply connection
MVSS input Core ground connection
Table 10-5 MSD_D3R_PDDRIO Pin List (Continued)
SolvNet
DesignWare.com
10.2.3 Operating Modes
Table 10-6 shows the operating modes of the MSD_D3R_PDDRIO buffer.
Legend:
X = don't care
V = Valid data, input or output
Z = Tristate
R = Value prior to assertion of LENH
Vin = Valid data input
Vout = Valid data output
0 = Low
1 = High
Notes
1. Output Only Mode can be used for Address and Command outputs to save power in the SSTL receiver.
2. PDR=1 and PDD=1 are preferable for power saving purpose
3. The DDR2/DDR3/DDR3L mode descriptions are valid for LPDDR2 mode as well with exception that TE should be always 0.
Table 10-6 MSD_D3R_PDDRIO Operating Modes
Mode
Controls Input In/Out Input Controls Outputs Controls
Note LENH PDR PDD LB DOUT PAD DJ OE OJ SJ IOM DI DT ET TE
DDR2/DDR3/DDR3L mission
mode input ODT-OFF
0 0 0 0 X V (in) X 0 X 0 0 V 0 0 0
mode input ODT-ON
0 0 0 0 X V (in) X 0 X 0 0 V 0 0 1
mode output
0 0 0 0 V V (out) X 1 X 0 0 V 0 0 X
mode output only
0 1 0 0 V V (out) X 1 X 0 0 0 0 X X
DDR2/DDR3/DDR3L standby:
Output enable asserted
0 1 1 0 V V (out) X 1 X 0 0 0 0 X X
DDR2/DDR3/DDR3L standby:
Output enable deasserted
0 1 1 0 X Z X 0 X 0 0 0 0 X X
DDR2/DDR3/DDR3L core
loopback
0 X X 1 V Z X 0 X 0 0 V 0 0 0 2
DDR2/DDR3/DDR3L boundary
scan input ODT-ON
0 0 0 0 X V (in) X X 0 1 0 V V 1 1
DDR2/DDR3/DDR3L boundary
scan output
0 0 0 0 X V (out) V X 1 1 0 V V 1 X
Mobile DDR input 0 0 X 0 X V (in) X 0 X 0 1 V 0 0 0
Mobile DDR output 0 0 X 0 V V (out) X 1 X 0 1 V 0 0 X
Mobile DDR standby: Output
enable asserted (output only)
0 1 X 0 V V (out) X 1 X 0 1 0 0 X X 1
Mobile DDR standby: Output
enable deasserted
0 1 X 0 X Z X 0 X 0 1 0 0 X X
Mobile DDR core loopback 0 X X 1 V Z X 0 X 0 1 V 0 0 0 2
Mobile DDR boundary scan
input
0 0 X 0 X V (in) X X 0 1 1 V V 1 0
Mobile DDR boundary scan
output
0 0 X 0 X V (out) V X 1 1 1 V V 1 X
Retention 1 X X X X R X X X X X R R X X
SolvNet
DesignWare.com
10.3 Differential Bi-Directional Buffer (MSD_D3R_PDIFF)
General Description
Figure 10-2 Differential Bi-Directional Buffer (MSD_D3R_PDIFF)
IOM
TE
DI
PAD
ESD1
ESD2
M
V
S
S
M
V
R
E
F
M
V
D
D
Q
L
E
N
H
0
1
OUTBUF
ODT
OJ
DOUT
SJ
INBUF
Z
I
O
H
[
6
3
:
0
]
DT
ET
LB
DJ
OE
1
0
M
V
S
S
Q
M
V
D
D
D
F
I
D
F
O
D
F
I
D
F
O
1
0
PDD
PDR
The SSTL differential bi-directional
buffer (MSD_D3R_PDIFF) is one
half of a full 1.2V/1.35V/1.5V/1.8V
differential I/O buffer, primarily
used to supply the clock when an
external differential clock source is
used. It occupies one I/O slot and is
easily connected to another identical
cell, either by abutment or across
short distances, to create a full
differential I/O buffer.
An impedance control bus
(ZIOH[63:0]) is embedded within
the SSTL I/O cells. Connectivity of
this embedded bus is completed by
abutting the SSTL cells. ZIOH[63:0]
is driven in the VDDQ voltage
domain by drivers in the
MSD_D3R_PVREF cell and should
never be connected to devices
operating at core logic voltage
(VDD).
Inputs are provided for independently setting the pull-up (ZIOH[31:16]) and pull-down (ZIOH[15:0]) driver
output impedance (Zo). These settings can be direct set values or, when coupled with the impedance
controller circuit (MSD_D3R_zctrl), they enable sequential Zo impedance calibration for PVT compensation.
These busses are modified-thermometer encoded.
Inputs are provided for independently setting the pull-up (ZIOH[63:48]) and pull-down (ZIOH[47:32]) for
on-die termination value (ODT). These settings can be direct set values or, when coupled with the
impedance controller circuit (MSD_D3R_zctrl), they enable sequential ODT impedance calibration for PVT
compensation. These busses are modified-thermometer encoded.
The boundary scan support functions, Mobile DDR mode, and DDR3/DDR2 operation selection for this cell
is the same as previously described for the cell Bi-Directional Buffer (MSD_D3R_PDDRIO) on page 136.
This cell is used in pairs to create a differential I/O, permitting a variety of implementation styles and pad
pitches. Examples of such variations include inserting a power/ground supply pad between the pair of cells
or placing filler cells between the cells to create a larger pad pitch. To create a differential I/O, two of these
cells are instantiated with the DFO of the first cell connected to the DFI of the second cell, and the DFI of the
first cell connected to the DFO of the second cell. The DFO/DFI pins are located on both sides of the cell, in
reverse order such that two cells placed beside each other with the same orientation will properly connect
by abutment with no external routing required. All other SSTL I/O library cells contain a routing void in the
area where these pins are located such that when filler or power cells separate the pair of cells, an auto
SolvNet
DesignWare.com
router can automatically connect the DFI/DFO signals without requiring an additional metal layer above
the highest metal layer used by the SSTL library.
10.3.2 Pin List
Table 10-7 shows the pin list for the MSD_D3R_PDIFF buffer.
Table 10-7 MSD_D3R_PDIFF Pin List
DI output Data In: data path from bond pad to core
DT output Test Data In: data path from bond pad to core with disable capability
ET input Test Data In Enable: set to 1 to enable or 0 to disable the test data input path
DOUT input Data Out: data path from core to bond pad
DJ input Test Data Out: data path from core to bond pad
SJ input
Test Select: set to 0 to select normal paths or 1 to select test paths for output data and
output enable
OE input
Output Enable: Active-high output enable.
OJ input
Test Output Enable: Active-high output enable.
PAD inout Bond Pad
DFI input Differential Input. Analog input from adjacent differential buffer.
DFO output Differential Output. Analog output to adjacent differential buffer.
IOM input
I/O Mode: IO Mode select
0 = DDR2/DDR3/LPDDR2 mode
1 = Mobile DDR mode
PDD input
Power Down Driver: Active high driver power down
1 = output driver powered down
When PDD is asserted, the output driver still operates and passes data from the core
side to the pad pin. When the cell is in output mode, the driver still drives the pad pin. All
DC currents are disabled when PDD is asserted and the output only functions at a very
low frequency. If the signal being driven is terminated externally, the I/Ocell continues to
draw DC current even when PDD is asserted due to the external termination. ODT is
automatically disabled when the output driver is powered down.
SolvNet
DesignWare.com
PDR input
Power Down Receiver: Active high receiver power down
1 = input buffer powered down
DI and DT are set to logic 0 when the receiver is powered down. The receiver is non-
functional when PDR is asserted.
LB input
Loopback: Active high internal loopback enable
1 = loopback DOUT to DI in core voltage logic
Note that DOUT data will also appear on the PAD pin if OE is high and PDD is low
ZIOH[63:0] input
Impedance Control: Thermometer encoded bus which controls the value of ODT and
output impedance. Note this bus is driven in the VDDQ voltage domain by drivers in the
cell MSD_D3R_PVREF.
This bus should not connect to devices operating in the core logic voltage domain
(VDD).
ZIOH[47:32]: Used to select the pull-down termination impedance. For details, see
Section Impedance Divide Ratios.
TE input
On-Die Termination Enable. Active-high signal.
1 = ODT is enabled
0 = ODT is disabled
ODT is also disabled when OE is high and SJ is low or OJ is high and SJ is high
regardless of the value of TE.
LENH Input
Latch Enable: Active high retention latch enable. Note this signal is driven in the VDDQ
voltage domain by drivers in the MSD_D3R_PRETLEX and MSD_DSR_PRETLEC
cells. This signal should not be connected to devices operating in the core logic voltage
domain (VDD).
In retention mode the values of the control and DOUT inputs are latched so that the
state of the PAD pin is retained if the core supply (VDD) is removed
MVDDQ input I/O supply connection (1.2V/1.35V/1.5V/1.8V)
Table 10-7 MSD_D3R_PDIFF Pin List (Continued)
SolvNet
DesignWare.com
10.3.3 Differential Cell Usage
When more than one differential I/O is to be implemented in the design, special attention should be placed
on the floor planning. Some guidelines are as follows:
Because the DFO/DFI connectivity is created by abutment, never allow the pair of PDIFF cells
required for one differential I/O to abut with the pair of PDIFF cells required for a second
differential I/O.
Always separate the pairs with at least one non-PDIFF cell, which can be any other cell in the library
including filler cells.
When the pair of PDIFF cells are placed in the design without abutting, a restriction should be
followed on the distance between the pair of PDIFF cells in order to create a larger pad pitch or to
insert a power pad in between.
The total distance between a pair of PDIFF cells should not exceed 60um.
Figure 10-3 on page 143 provides implementation examples using the PDIFF cell.
Figure 10-3 MSD_D3R_PDIFF Implementation Examples
Note Note Note Note
The PAD pins on abutted PDIFF cells do not short to each other as the left and right hand pins are on
different metal.
DFI
DFO DFI
DFO DFI
DFO DFI
DFO DFI
DFO DFI
DFO DFI
DFO DFI
DFO
1um to 60um
A differential pair created
by 2 abutted PDIFF cells
A differential pair created with 2
PDIFF cells without abutting
including DFO/DFI routing
PDIFF PDIFF PDIFF PDIFF
PAD PAD PAD PAD PAD PAD PAD PAD
SolvNet
DesignWare.com
10.4 ZQ Calibration Cell (MSD_D3R_PZQ)
This section includes the following topics:
General Description
ZPROG Settings for Zo and ODT on page 148
The cell MSD_D3R_PZQ provides independent calibration capability for the pull-up and pull-down input
termination and output impedances of the functional SSTL cells.
The user connects the PAD pin through an external 240ohm 1% resistor (RZQ) to ground. There are four
sense blocks that provide independent sense capability for each impedance element:
Pull-up termination impedance
Pull-down termination impedance
Pull-up output impedance
Pull-down output impedance
These four elements are calibrated in series using the calibration select input ZCAL[1:0]. The calibration
sequence is:
1. Output impedance pulldown
2. Output impedance pull-up
3. On-Die termination (ODT) pull-down
4. ODT pull-up
Figure 10-4 on page 145 shows a block diagram of the MSD_D3R_PZQ buffer.
SolvNet
DesignWare.com
Figure 10-4 ZQ Calibration Cell (MSD_D3R_PZQ)
An impedance control bus (ZIOH[63:0]) is embedded within the SSTL I/O cells and connectivity of this
embedded bus is completed by abutment of the SSTL cells. This bus is driven in the VDDQ voltage domain
by drivers in the MSD_D3R_PVREF cell and should never be connected to devices operating at core logic
voltage (VDD). This bus permits independent setting of the pull-up (ZIOH[63:48]) and pull-down
(ZIOH[47:32]) ODT values and independent setting of the pull-up (ZIOH[31:16]) and pulldown
(ZIOH[15:0]) output impedance values. The impedance control logic drives an impedance code to the
PVREF cell, which translates that impedance code from binary format to modified thermometer encoding
and level shifts it from the VDD domain to the VDDQ domain, resulting in the impedance control bus
ZIOH[63:0]. The PZQ cell uses this code information to determine the response to return to the impedance
control logic.
The impedance values are selected by sending a divide ratio (ZPROG[7:0]) to the PZQ cell. The sense
circuitry receives a four-bit divide ratio code (ZPROG[7:4]) for ODT and ZPROG[3:0] for output impedance,
which together with the value of the external resistor determine the desired impedance value. The sense
circuitry outputs a signal (ZCOMP) to inform the impedance control logic how the current impedance code
being provided by the impedance control logic matches the resistor value based on the divide ratio. This
ZCAL[1:0]
M
V
R
E
F
M
V
D
D
M
V
S
S
M
V
D
D
Q
M
V
S
S
Q
PD
2
4
0
o
h
m
s
+
/
-
1
%
ICAL
ZPROG[7:0]
ZCOMP
Z
I
O
H
[
6
3
:
0
]
ZQ_OFF
PAD
ESD1
LENH
SolvNet
DesignWare.com
signal is 0 if the impedance code is too high, 1 if the impedance code is too low, and toggles when the best
match has been determined. The impedance code value is inversely related to the actual impedance value.
Two independent enable inputs (ZQ_OFF and PD) are provided to allow the DC current paths to be
disabled when a calibration is not occurring. This permits a greater degree of power savings when the
impedance values are updated on an interval basis instead of continuous on-the-fly.
10.4.2 Pin List
Table 10-8 provides the pin list for the MSD_D3R_PZQ buffer.
Table 10-8 MSD_D3R_PZQ Pin List
ZPROG[7:0] input Select ZPROG value in conjunction with external reference resistor to be used to set the
output impedance and the On-Die Termination. For details, Section Impedance Divide
Ratios.
ZPROG[7:4] = On-Die Termination divide select
ZPROG[3:0] = output impedance divide select
ZCAL[1:0] Input Impedance Calibration Select: selects which impedance element is to be calibrated.
00: Output impedance pull-down
01: Output impedance pull-up
10: On-Die Termination pull-down
11: On-Die Termination pull-up
ZCOMP output Impedance Compare: informs the impedance control logic how the current impedance code
matches the resistor value based on the divide ratio.
0: if the impedance code is too high
1: if the impedance code is too low toggle when the best match has been determined
ZIOH[63:0] input Impedance Control: Thermometer encoded bus which controls the value of ODT and output
impedance. Note this bus is driven in the VDDQ voltage domain by drivers in the cell
MSD_D3R_PVREF. This bus should not connect to devices operating in the core logic
voltage domain (VDD).
ZIOH[47:32]: Used to select the pull-down termination impedance. For details, see Section
PAD in Bond Pad
ZQ_OFF Input ZQ Off: Active-high ZQ disable. When asserted, all DC current paths are disabled and the
PAD pin is placed into High-Z. Some time is required for the cell to settle when it is
re-enabled, approximately 50ns should be allowed.
PD input Power Down: Active-high ZQ disable. When asserted, all DC current paths are disabled and
the PAD pin is placed into High-Z. Some time is required for the cell to settle when it is
re-enabled, approximately 50ns should be allowed.
SolvNet
DesignWare.com
LENH Input Latch Enable: Active high retention latch enable. Note this signal is driven in the VDDQ
voltage domain by drivers in the MSD_D3R_PRETLEX and MSD_DSR_PRETLEC cells.
This signal should not be connected to devices operating in the core logic voltage domain
(VDD).
In retention mode the values of the control inputs are latched so that the state of the cell is
retained if the core supply (VDD) is removed
Table 10-8 MSD_D3R_PZQ Pin List (Continued)
SolvNet
DesignWare.com
10.4.3 ZPROG Settings for Zo and ODT
Table 10-8 provides the ZPROG settings of the MSD_D3R_PZQ buffer.
Notes:
1. Using different RZQ values in range of 240-300 ohms, users can obtain different impedance values.
2. ODT and Driver Output Impedance is calibrated independently.
3. For the detailed calibration procedure, see the Impedance Calibration Circuit.
4. Even though the code for ODT pull-up and pull-down is common, the calibration is performed independently for pull-up
and pull-down, similar to Driver Output Impedance.
Table 10-9 ZPROG Settings for Standard Zo and ODT Values
RZQ = 240 +/- 1% Programmed Zo
ZPROG[3:0]
Index (decimal) DDR3/DDR3L (ohms) DDR2 (ohms) LPDDR2 (ohms)
5 - - 80
7 - - 60
9 - - 48
11 40 40 40
13 34 - -
- - 18 -
For programming 18 ohms, use Custom Calibration Method using zctrl_ovrd_data[19:0]
Programmed ODT
ZPROG[7:4]
Index (decimal) DDR3/DDR3L (ohms) DDR2 (ohms) LPDDR2 (ohms)
1 120 150 -
4 - 75 -
5 60 - -
6 - 50 -
8 40 - -
SolvNet
DesignWare.com
10.5 Impedance Calibration Circuit
The impedance calibration circuit, which controls the impedance values for ODT and driver output
impedance, consists of the following components:
ZQ calibration cell - MSD_D3R_PZQ
External RZQ precision resistor
Impedance control logic (RTL) - MSD_D3R_zctrl
VREF cell (for code encoding and level shifting) - MSD_D3R_PVREF
Functional I/O cells - MSD_D3R_PDDRIO/MSD_D3R_PDIFF
The connectivity of these components is shown in Figure 10-5.
Figure 10-5 Impedance Calibration Circuit
A single calibration cell (MSD_D3R_PZQ) is used for the interface. One or multiple VREF cells exist in the
interface, depending on the total data width of the interface. The ZCTRL bus from the impedance control
logic is connected to all VREF cells in the interface. It is not permitted to have a VREF cell in the interface
that is not connected to the impedance control logic.
The impedance control logic sends an impedance code through the ZCTRL bus to the VREF cells. The VREF
cells encodes this data, level shifts it to the VDDQ power domain, and sends it to both the functional I/O
cells and the MSD_D3R_PZQ cell through the ZIOH bus embedded within the SSTL library cells. The
MSD_D3R_PZQ cell also receives the desired divide ratios from the Memory Controller or the user logic.
The MSD_D3R_PZQ cell compares the impedance control code received from the PVREF cell with the
external resistor, taking into account the selected divide ratio. The MSD_D3R_PZQ cell then sends ZCOMP
back to the impedance control logic to relay information about impedance matching. The impedance control
logic then sends a new impedance code to the PVREF cells. This results in a closed-loop system.
PVREF
PVREF
PDDRIO
PDDRIO
PDDRIO
PDDRIO
zctrl_start
zctrl_ovrd_en
r
s
t
_
b
z
c
t
r
l
_
c
l
k
_
s
e
l
c
l
k
s
c
a
n
_
t
e
s
t
Z
I
O
H
[
6
3
:
0
]
2
4
0
+
/
-
1
%
Impedance
RTL
zcomp
zcal[1:0]
zq_off
ZPROG[7:0]
z
c
t
r
l
[
1
5
:
0
]
;
z
l
s
b
[
3
:
0
]
z
c
t
r
l
_
s
t
a
t
u
s
[
3
1
:
0
]
zctrl_ovrd-data[19:0]
PZQ
Controller
PUBL
SolvNet
DesignWare.com
The four impedance elements (output impedance pull-down/up and ODT pull-down/up) are calibrated
sequentially. The ZPROG bus is used to signal which element is being calibrated. The state machine is
implemented on the Impedance Controller RTL block.
The impedance control logic connects to the Memory Controller or customer logic to allow full
controllability and observability of the loop operation.
The impedance control loop operates with a low bandwidth as compared to the memory system, thus the
impedance control logic contains a clock divider to permit operation at a reduced clock frequency.
There are three basic modes of operation:
Direct Calibration -uses ZPROG settings.
Override Setting - uses ctrl_ovrd_data settings.
Custom Calibration - extends calibration beyond the values available on ZPROG
10.5.1 Direct Calibration
In this mode, the user is setting independently the value for ODT (ZPROG[7:4]) and Output Impedance
(ZPROG[3:0]) and runs the calibration sequence described in ZQ Calibration Cell (MSD_D3R_PZQ).
10.5.2 Override Setting
In this mode, the user is not using the calibration loop, and instead directly controls the impedance control
using zctrl_ovrd_data[19:0] bus, which is parsed in four nibbles that independently control Driver
pulldown/up and ODT pulldown/up impedance in 31 steps.
For example, assuming one step is associated to current I and the calibration voltage is VREF, the
programmed impedance for index N is:
Z
PROG
= k * VREF/(N * I)
Based on the formula, it can be concluded that if index N is increased, then the impedance is decreased. The
following table shows an example of values obtained with 240 ohms RZQ and typical PVT parameters.
Note Note Note Note
Internally, the pull-down/up are calibrated independently to the value that is programmed.
Note Note Note Note
K is correction factor, which is approximately equal to 1.
SolvNet
DesignWare.com
Table 10-10 Example of Values from 240 ohms RZQ and PVT Parameter - Typical Corner at 25C
ODT Pull-Up zctrl_ovrd_data[19:15] ZIOH[63:48]
Impedance DRV Impedance ODT
ODT Pull-Dwn zctrl_ovrd_data[14:10] ZIOH[47:32]
DRV Pull-Up zctrl_ovrd_data[9:5] ZIOH[31:16]
DRV Pull-Dwn zctrl_ovrd_data[4:0] ZIOH[15:0] DDR3 DDR3L DDR2 LPDDR2 DDR3 DDR3L DDR2
Index (dec)
Modified Gray
Code(hex)
Modified Thermometer
Encoding (hex) (ohms) (ohms) (ohms) (ohms) (ohms) (ohms) (ohms)
0 00 0000 - - - - -
- -
1 01 0001 388.9 422.4 346.9 471.7 302.7 337.3 259.6
2 02 0002 196.1 212.8 175.2 237.3 153.4 170.9 132.2
3 03 0003 131.8 142.9 117.9 159.2 103.9 115.6 89.9
4 06 0006 99.7 107.9 89.3 120.1 79.1 87.8 68.4
5 07 0007 80.4 87.0 72.1 96.7 64.2 71.3 55.8
6 04 000E 67.6 73.0 60.7 81.1 54.3 60.1 47.1
7 05 000F 58.4 63.1 52.5 70.0 47.2 52.3 41.2
8 0C 001E 51.5 55.6 46.4 61.6 41.9 46.3 36.5
9 0D 001F 46.2 49.8 41.6 55.1 37.7 41.7 33.0
10 0E 003E 41.9 45.1 37.8 49.9 34.4 38.0 30.1
11 0F 003F 38.4 41.3 34.7 45.6 31.7 35.0 27.8
12 0A 007E 35.5 38.2 32.1 42.1 29.5 32.4 25.9
13 0B 007F 33.0 35.5 29.9 39.1 27.6 30.3 24.2
14 08 00FE 30.9 33.2 28.1 36.6 25.9 28.5 22.8
15 09 00FF 29.1 31.2 26.5 34.3 24.5 26.9 21.6
16 18 01FE 27.5 29.5 25.0 32.4 23.2 25.5 20.5
17 19 01FF 26.1 28.0 23.8 30.7 22.1 24.3 19.6
18 1A 03FE 24.9 26.6 22.7 29.2 21.1 23.1 18.7
19 1B 03FF 23.7 25.4 21.7 27.8 20.3 22.2 18.0
20 1E 07FE 22.7 24.3 20.8 26.6 19.5 21.3 17.3
21 1F 07FF 21.8 23.3 20.0 25.5 18.8 20.5 16.7
22 1C 0FFE 21.0 22.4 19.3 24.5 18.1 19.8 16.1
23 1D 0FFF 20.3 21.6 18.6 23.6 17.5 19.1 15.6
24 14 1FFE 19.6 20.9 18.0 22.7 17.0 18.5 15.1
25 15 1FFF 19.0 20.2 17.4 22.0 16.5 17.9 14.7
26 16 3FFE 18.4 19.5 16.9 21.3 16.0 17.4 14.3
27 17 3FFF 17.8 19.0 16.4 20.6 15.6 16.9 14.0
28 12 7FFE 17.3 18.4 16.0 20.0 15.2 16.5 13.6
29 13 7FFF 16.9 17.9 15.6 19.4 14.8 16.1 13.3
30 10 FFFE 16.4 17.4 15.2 18.9 14.5 15.7 13.0
31 11 FFFF 16.0 17.0 14.8 18.4 14.2 15.3 12.7
SolvNet
DesignWare.com
Table 10-11 Example of Values from 240 ohms RZQ and PVT Parameter - Fast Corner at 125C
Index (dec)
Modified Gray
Code(hex)
0 00 0000 - - - - -
- -
1 01 0001 363.7 383.7 327.6 415.5 262.0 282.3 233.0
2 02 0002 183.3 193.3 165.5 209.0 135.1 143.8 118.8
3 03 0003 123.2 129.8 111.4 140.2 91.7 97.5 80.8
4 06 0006 93.2 98.1 84.3 105.9 69.8 74.2 61.6
5 07 0007 75.2 79.1 68.1 85.3 56.7 60.3 50.2
6 04 000E 63.2 66.4 57.3 71.6 47.9 50.9 42.5
7 05 000F 54.6 57.4 49.6 61.8 41.7 44.3 37.1
8 0C 001E 48.2 50.6 43.8 54.4 37.0 39.3 32.9
9 0D 001F 43.2 45.3 39.3 48.7 33.4 35.4 29.7
10 0E 003E 39.2 41.1 35.7 44.2 30.4 32.3 27.2
11 0F 003F 35.9 37.7 32.8 40.4 28.1 29.7 25.1
12 0A 007E 33.2 34.8 30.3 37.3 26.1 27.6 23.3
13 0B 007F 30.9 32.4 28.3 34.7 24.4 25.8 21.9
14 08 00FE 28.9 30.3 26.5 32.4 22.9 24.3 20.6
15 09 00FF 27.2 28.5 25.0 30.5 21.7 22.9 19.5
16 18 01FE 25.7 26.9 23.6 28.8 20.6 21.7 18.5
17 19 01FF 24.4 25.5 22.4 27.3 19.6 20.7 17.7
18 1A 03FE 23.2 24.3 21.4 25.9 18.7 19.8 16.9
19 1B 03FF 22.2 23.2 20.4 24.8 18.0 19.0 16.3
20 1E 07FE 21.3 22.2 19.6 23.7 17.3 18.2 15.6
21 1F 07FF 20.4 21.3 18.8 22.7 16.7 17.5 15.1
22 1C 0FFE 19.7 20.5 18.1 21.8 16.1 16.9 14.6
23 1D 0FFF 19.0 19.8 17.5 21.0 15.6 16.4 14.1
24 14 1FFE 18.3 19.1 16.9 20.3 15.1 15.8 13.7
25 15 1FFF 17.7 18.5 16.4 19.6 14.6 15.4 13.3
26 16 3FFE 17.2 17.9 15.9 19.0 14.2 14.9 13.0
27 17 3FFF 16.7 17.3 15.5 18.4 13.9 14.5 12.6
28 12 7FFE 16.2 16.8 15.0 17.9 13.5 14.2 12.3
29 13 7FFF 15.8 16.4 14.6 17.4 13.2 13.8 12.0
30 10 FFFE 15.4 16.0 14.3 16.9 12.9 13.5 11.8
31 11 FFFF 15.0 15.6 13.9 16.5 12.6 13.2 11.5
SolvNet
DesignWare.com
Table 10-12 Example of Values from 240 ohms RZQ and PVT Parameter - Fast Corner -40C
Index (dec)
Modified Gray
Code(hex)
0 00 0000 - - - - -
- -
1 01 0001 281.5 295.8 257.2 319.3 217.8 234.0 195.6
2 02 0002 142.1 149.2 130.0 160.9 111.0 118.6 99.4
3 03 0003 95.6 100.3 87.6 108.1 75.5 80.4 67.6
4 06 0006 72.4 75.9 66.4 81.7 57.4 61.2 51.5
5 07 0007 58.4 61.2 53.6 65.9 46.8 49.7 42.0
6 04 000E 49.2 51.5 45.2 55.3 39.5 42.0 35.6
7 05 000F 42.5 44.5 39.1 47.8 34.5 36.6 31.1
8 0C 001E 37.5 39.3 34.6 42.1 30.6 32.5 27.6
9 0D 001F 33.7 35.2 31.1 37.7 27.7 29.3 25.0
10 0E 003E 30.6 32.0 28.2 34.2 25.2 26.7 22.8
11 0F 003F 28.1 29.3 25.9 31.4 23.3 24.6 21.1
12 0A 007E 26.0 27.1 24.0 29.0 21.7 22.9 19.6
13 0B 007F 24.2 25.2 22.4 27.0 20.3 21.4 18.4
14 08 00FE 22.7 23.6 21.0 25.2 19.1 20.2 17.4
15 09 00FF 21.4 22.3 19.8 23.7 18.1 19.1 16.5
16 18 01FE 20.2 21.0 18.8 22.4 17.2 18.1 15.6
17 19 01FF 19.2 20.0 17.8 21.3 16.4 17.2 14.9
18 1A 03FE 18.3 19.0 17.0 20.2 15.6 16.5 14.3
19 1B 03FF 17.5 18.2 16.3 19.3 15.0 15.8 13.7
20 1E 07FE 16.8 17.4 15.6 18.5 14.4 15.2 13.2
21 1F 07FF 16.1 16.7 15.0 17.8 13.9 14.6 12.8
22 1C 0FFE 15.5 16.1 14.5 17.1 13.5 14.1 12.3
23 1D 0FFF 15.0 15.5 14.0 16.5 13.0 13.7 12.0
24 14 1FFE 14.5 15.0 13.6 15.9 12.6 13.2 11.6
25 15 1FFF 14.0 14.5 13.1 15.4 12.3 12.9 11.3
26 16 3FFE 13.6 14.1 12.8 14.9 11.9 12.5 11.0
27 17 3FFF 13.2 13.7 12.4 14.5 11.6 12.2 10.7
28 12 7FFE 12.9 13.3 12.1 14.1 11.3 11.9 10.4
29 13 7FFF 12.5 13.0 11.8 13.7 11.1 11.6 10.2
30 10 FFFE 12.2 12.6 11.5 13.3 10.8 11.3 10.0
31 11 FFFF 11.9 12.3 11.2 13.0 10.6 11.1 9.8
SolvNet
DesignWare.com
Table 10-13 Example of Values from 240 ohms RZQ and PVT Parameter - Slow Corner at 125C
Index (dec)
Modified Gray
Code(hex)
0 00 0000 - - - - -
- -
1 01 0001 581.6 647.0 503.2 695.5 464.7 539.3 381.0
2 02 0002 292.8 325.4 253.8 350.0 235.0 272.1 193.2
3 03 0003 196.5 218.1 170.6 234.8 158.7 183.6 130.7
4 06 0006 148.4 164.6 129.0 177.2 120.5 139.2 99.5
5 07 0007 119.5 132.4 104.0 142.7 97.6 112.6 80.7
6 04 000E 100.3 111.0 87.4 119.7 82.3 94.8 68.2
7 05 000F 86.5 95.7 75.6 103.2 71.4 82.1 59.3
8 0C 001E 76.2 84.2 66.7 90.8 63.2 72.6 52.6
9 0D 001F 68.2 75.3 59.7 81.3 56.8 65.2 47.4
10 0E 003E 61.8 68.1 54.2 73.6 51.7 59.2 43.2
11 0F 003F 56.6 62.3 49.7 67.3 47.6 54.4 39.8
12 0A 007E 52.2 57.4 45.9 62.1 44.1 50.4 36.9
13 0B 007F 48.5 53.3 42.7 57.6 41.2 47.0 34.5
14 08 00FE 45.4 49.8 40.0 53.8 38.6 44.0 32.5
15 09 00FF 42.6 46.8 37.7 50.6 36.4 41.5 30.7
16 18 01FE 40.2 44.1 35.6 47.7 34.5 39.2 29.1
17 19 01FF 38.1 41.8 33.8 45.2 32.8 37.3 27.7
18 1A 03FE 36.3 39.7 32.2 42.9 31.3 35.5 26.5
19 1B 03FF 34.6 37.8 30.7 40.9 30.0 34.0 25.4
20 1E 07FE 33.1 36.1 29.4 39.1 28.7 32.5 24.4
21 1F 07FF 31.7 34.6 28.3 37.5 27.6 31.3 23.5
22 1C 0FFE 30.5 33.2 27.2 36.0 26.6 30.1 22.7
23 1D 0FFF 29.4 32.0 26.2 34.6 25.7 29.1 21.9
24 14 1FFE 28.3 30.8 25.3 33.4 24.9 28.1 21.3
25 15 1FFF 27.4 29.8 24.5 32.2 24.1 27.2 20.6
26 16 3FFE 26.5 28.8 23.8 31.2 23.4 26.4 20.0
27 17 3FFF 25.7 27.9 23.1 30.2 22.8 25.6 19.5
28 12 7FFE 24.9 27.1 22.4 29.3 22.1 24.9 19.0
29 13 7FFF 24.3 26.3 21.8 28.4 21.6 24.2 18.6
30 10 FFFE 23.6 25.6 21.3 27.6 21.0 23.6 18.1
31 11 FFFF 23.0 24.9 20.7 26.9 20.5 23.0 17.7
SolvNet
DesignWare.com
Table 10-14 Example of Values from 240 ohms RZQ and PVT Parameter - Slow Corner at -40C
Index (dec)
Modified Gray
Code(hex)
0 00 0000 - - - - -
- -
1 01 0001 438.3 486.9 383.7 568.0 360.5 417.3 300.9
2 02 0002 220.8 245.0 193.6 285.4 182.6 210.9 152.7
3 03 0003 148.3 164.4 130.3 191.2 123.6 142.4 103.6
4 06 0006 112.1 124.1 98.6 144.1 93.9 108.1 78.9
5 07 0007 90.3 99.9 79.6 115.9 76.2 87.6 64.2
6 04 000E 75.9 83.8 67.0 97.0 64.4 73.8 54.3
7 05 000F 65.5 72.3 57.9 83.6 56.0 64.1 47.3
8 0C 001E 57.8 63.7 51.1 73.5 49.6 56.7 42.0
9 0D 001F 51.7 57.0 45.9 65.7 44.7 51.0 37.9
10 0E 003E 46.9 51.6 41.7 59.4 40.7 46.4 34.6
11 0F 003F 43.0 47.2 38.2 54.3 37.5 42.7 31.9
12 0A 007E 39.7 43.6 35.4 50.0 34.8 39.6 29.7
13 0B 007F 36.9 40.5 33.0 46.4 32.5 36.9 27.8
14 08 00FE 34.6 37.8 30.9 43.3 30.6 34.7 26.2
15 09 00FF 32.5 35.6 29.1 40.7 28.9 32.7 24.8
16 18 01FE 30.7 33.6 27.5 38.3 27.4 31.0 23.5
17 19 01FF 29.1 31.8 26.2 36.3 26.1 29.5 22.4
18 1A 03FE 27.7 30.2 24.9 34.4 24.9 28.1 21.4
19 1B 03FF 26.5 28.8 23.8 32.8 23.9 26.9 20.6
20 1E 07FE 25.3 27.6 22.9 31.3 22.9 25.8 19.8
21 1F 07FF 24.3 26.4 22.0 30.0 22.1 24.8 19.1
22 1C 0FFE 23.4 25.4 21.2 28.8 21.3 23.9 18.4
23 1D 0FFF 22.6 24.5 20.4 27.7 20.6 23.1 17.8
24 14 1FFE 21.8 23.6 19.8 26.7 19.9 22.3 17.3
25 15 1FFF 21.1 22.8 19.1 25.8 19.3 21.6 16.8
26 16 3FFE 20.4 22.1 18.6 24.9 18.8 21.0 16.3
27 17 3FFF 19.8 21.4 18.0 24.1 18.3 20.4 15.9
28 12 7FFE 19.3 20.8 17.5 23.4 17.8 19.8 15.5
29 13 7FFF 18.7 20.2 17.1 22.7 17.3 19.3 15.2
30 10 FFFE 18.3 19.7 16.7 22.1 16.9 18.9 14.8
31 11 FFFF 17.8 19.2 16.3 21.5 16.5 18.4 14.5
SolvNet
DesignWare.com
10.5.3 Custom Calibration
This mode is a two-step procedure combining the previous two modes.
1. The user provides a Direct Calibration using a convenient value and records the Impedance control
results from status register.
2. The user applies the correction factor that provides the custom impedance.
The following example assumes that it is required to program Driver Output Impedance to 18 ohms.
1. The user performs a Direct Calibration for driver Zo=36 ohms. For example, assume the result
shows that Driver pull-up index is 12, and Driver pull-down index is 13.
2. Calculate and apply the Override Data for 18 ohm impedance adjustment as follows:
(<cal_value>/<req_value>) * <cal_index>
Driver pull-down (36/18) * 13 = 26
Driver pull-up (36/18) * 12 = 24
10.6 Impedance Control Logic (MSD_D3R_zctrl)
General Description
Functional Operation on page 159
10.6.1 Applicability
The MSD_D3R_zctrl module is only required when the legacy system architecture is used between the
Synopsys PHY and Synopsys memory or protocol controller. For more information on the implementation
options, refer to Controller Solutions on page 15.
For instance, if the Synopsys PCTL or MCTL controllers are used with the PHY then the zctrl module is
required to implement the impedance control algorithm. However, if the Synopsys PUBL is included in the
system solution then the zctrl module is not required and this section can be skipped.
Note Note Note Note
The resulting index from the pervious example has to be smaller than 31 according to the allowable
range of the hardware support.
SolvNet
DesignWare.com
MSD_D3R_zctrl is a Verilog RTL module, which is
used to provide the necessary impedance control
functions to enable the programmable and
PVT-compensated ODT and output impedance of
the functional SSTL cells.
The impedance control logic provides the
following control options:
Sample-based tracking of RZQ to permit
stable signaling at the SSTL and lowest
power operation for the impedance loop
circuitry
Impedance code override to allow direct
control of the impedance codes
Impedance code output to permit
monitoring of the control loop operation
Programmable divide on the input clock
signal to permit stable operation with a full range of input clock frequencies
Automatic sequencing for independent impedance compensation for each of the four impedance
elements (ODT pull-up/pull-down, output impedance pull-up/pull-down)
A clock is provided to the impedance control logic that is used as the sampling clock for the loop. Typically,
the control loop operates with a relatively low clock rate for stable operation because the loop is not
designed for, and does not require, high-speed operation. Typical operation frequencies of less than 25 MHz
are desirable. Because this module is normally connected to the memory controller clock (although may be
connected to any other clock source), the module contains a programmable clock divider to permit options
of divide-by-32 and divide-by-64 from the input clock.
All inputs to the control logic, with the exception of zcomp, are considered asynchronous. The zcomp signal
is registered on the falling edge of the divided clock. All outputs are synchronous to the rising edge of the
divided clock.
The module contains embedded registers for storing the impedance codes. There is an output provided to
permit monitoring of the control loop operation or to override the logic with specific code values.
10.6.3 Pin List
Table 10-15 shows the pin list for the MSD_D3R_zctrl module.
Table 10-15 MSD_D3R_zctrl Pin List
clk input
Input clock. Divide function is included to allow this clock to be divided
down to less than 25MHz.
rst_b input Synchronous to clk on de-assertion, asynchronous on assertion; active low
zctrl_start input
Calibration Start: active high signal which is asserted when the user wishes
to run an impedance calibration sequence. Must be kept asserted until
zctrl_done is asserted.
Figure 10-6 Impedance Control Logic (MSD_D3R_zctrl)
Impedance
Control
Logic
zq_off
zlsb[3:0]
clk
zctrl_ovrd_en
zctrl_ovrd_data[19:0]
zctrl_clk_sel
zctrl_start
rst_b
scan_test
zcal[1:0]
zctrl[15:0]
zctrl_status[31:0]
zcomp
SolvNet
DesignWare.com
zctrl_ovrd_en input
Impedance Over-ride: active high signal which allows the user to directly
drive the zctrl impedance output bus using the zctrl_ovrd_data input bus
zctrl_ovrd_data[19:0] input
Impedance Over-ride Data: data to be used when directly driving the zctrl
and zlsb output bus as follows:
zctrl_ovrd_data[19:15]: Used to select the pull-up on-die termination
impedance
zctrl_ovrd_data[14:10]: Used to select the pull-down on-die termination
impedance
zctrl[9:5]: Used to select the pull-up output impedance
zctrl_ovrd_data[4:0]: Used to select the pull-down output impedance
zctrl_clk_sel input Clock Divide Select: 0 = divide-by-32; 1 = divide-by-64
zctrl_status[31:0] output
Calibration Status: information on the impedance control loop status
[19:0] ZCTRL Impedance Control: Current value of impedance
control.
[21:20] ZQPD Output impedance pull-down calibration status.
Valid status encodings are:
00 = Completed with no errors
01 = Overflow error
10 = Underflow error
11 = Calibration in progress
[23:22] ZQPU Output impedance pull-up calibration status. Similar
status encodings as ZQPD.
[25:24] ODTPD On-die termination (ODT) pull-down calibration status.
Similar status encodings as ZQPD.
[27:26] ODTPU On-die termination (ODT) pull-up calibration status.
Similar status encodings as ZQPD.
[29:28] - Reserved. Return zeros on reads.
[30] ZQERR Impedance Calibration Error: If set, indicates that
there was an error during impedance calibration.
[31] ZQDONE Impedance Calibration Done: Indicates that
impedance calibration has completed.
scan_test input
Scan mode flag: active high signal used to bypass clock division for logic
scan.
zcal[1:0] output
Calibration Select: selects which of the four impedance elements is to be
calibrated. The sequence is:
0: Output impedance pull-down
1: Output impedance pull-up
2: On-Die Termination pull-down
3: On-Die Termination pull-up
zctrl[15:0] output
Impedance Code: controls the value of ODT and output impedance:
zctrl[15:12]: Used to select the pull-up on-die termination impedance
zctrl[11:8]: Used to select the pull-down on-die termination impedance
zctrl[7:4]: Used to select the pull-up output impedance
zctrl[3:0]: Used to select the pull-down output impedance
Table 10-15 MSD_D3R_zctrl Pin List (Continued)
SolvNet
DesignWare.com
10.6.4 Functional Operation
The user selects a clock divide ratio (zctrl_clk_sel) for the input clock that results in a divided clock
frequency of 25 MHz or less. The user also selects the desired divide ratios, ZPROG[7:0] of the cell
MSD_D3R_PZQ, which set the desired impedance values. The start signal (zctrl_start) is asserted and held
in that state until the calibration sequence is completed, signaled by zctrl_status[31] being asserted. As the
calibration sequence runs, it sequentially steps through independent calibration sequences for each of the
four impedance elements in the following order:
1. Output impedance pull-down
2. Output impedance pull-up
3. ODT pull-down
4. ODT pull-up
An impedance code (zctrl[15:0]) is output and correspondingly feedback is returned (zcomp) to provide
information about the matching of the current impedance code, which the logic uses to determine what
code to output next. When the best match has been achieved, the logic begins calibration of the next
impedance element.
When the calibration of all four elements is complete, the logic asserts the done signal (zctrl_status[31]), at
which time the user can de-assert the start signal (zctrl_start).
At any time, the user can monitor the loop status for errors via the status output zctrl_status[30]. If a
calibration error is detected, more information about what the error is can be obtained by viewing the status
outputs zctrl_status[27:0]. If an error is triggered, the error flag is automatically reset when the impedance
calibration is re-triggered via zctrl_start. The user can also override the impedance control logic with direct
programming of the impedance codes using the override inputs zctrl_ovrd_en and zctrl_ovrd_data[19:0].
zlsb[3:0] output
Fine control of ODT and Output Impedance (LSB binary)
zlsb[3] pull-up ODT
zlsb[2] pull-down ODT
zlsb[1] pull-up Output Impedance
zlsb[0] pull-down Output Impedance
zq_off output
ZQ Off: active-high ZQ disable. When asserted, all DC current paths of the
MSD_D3R_PZQ cell are disabled and the PAD pin is placed into High-Z.
zcomp input
Impedance Compare: informs the impedance control logic how the current
impedance code matches the resistor value based on the divide ratio
- '0' if the impedance code is too high
- '1' if the impedance code is too low
- toggle when the best match has been determined
Table 10-15 MSD_D3R_zctrl Pin List (Continued)
SolvNet
DesignWare.com
10.7 Reference Voltage Cell (MSD_D3R_PVREF)
This section includes the following sections:
General Description
Pin List
Requirements for Powering Up/Powering Down PVREF on page 161
10.7.1 General Description Figure 10-7 Reference Voltage Cell (MSD_D3R_PVREF)
Thermometer
Encoder
PAD
zctrl[15:0]
zlsb[3:0]
Z
I
O
H
[
6
3
:
0
]
MVDDQ
M
V
R
E
F
M
V
D
D
Q
M
V
S
S
Q
M
V
D
D
M
V
S
S
ESD2 ESD1
L
E
N
H
MSD_D3R_PVREF is used to
provide the input switching
reference voltage to the SSTL I/Os.
A second function of this cell is to
provide the thermometer encoding
and level shifting for the
impedance control bus.
The recommendation for VREF cell
insertion is 1 VREF cell for every
3mm of pad frame length,
approximately centered within the 3mm section. This results in a maximum distance from the VREF cell to
any other SSTL cell of 1.5mm.
One or multiple VREF cells will exist in the interface, depending on the total data width of the interface. The
ZCTRL bus from the impedance control logic is connected to all VREF cells in the interface. It is not
permitted to have a VREF cell in the interface which is not connected to the impedance control logic.
10.7.2 Pin List
Table 10-16 shows the pin list for the MSD_D3R_PVREF cell.
Table 10-16 MSD_D3R_PVREF Pin List
PAD in Bond Pad
zctrl[15:0] input Impedance Control: Controls the value of ODT and output impedance in conjunction
with ZLSB ZCTRL[15:12]: Controls the pull-up ODT impedance
ZCTRL[11:8]: Controls the pull-down ODT impedance
ZCTRL[7:4]: Controls the pull-up output ODT
ZCTRL[3:0]: Controls the pull-down output ODT
zlsb[3:0] input Fine control of the value of ODT and Output Impedance (binary LSB)
ZLSB[3] pull-up ODT
ZLSB[2] pull-down ODT
ZLSB[1] pull-up output impedance
ZLSB[0] pull-down output impedance
ZIOH[63:0] output Encoded Impedance Control: Thermometer encoded bus which controls the value of
ODT and output impedance. Note this bus is driven in the VDDQ voltage domain. This
bus should not connect to devices operating in the core logic voltage domain (VDD).
MVDDQ input I/O supply connection (1.2V/1.35V/1.5V1.8V)
MVREF output VREF SSTL reference supply connection
SolvNet
DesignWare.com
10.7.3 Requirements for Powering Up/Powering Down PVREF
When powering up/powering down the PVREF supply, consider the following recommendations:
VREF should not be applied without VDDQ being energized.
VREF may remain at GROUND.
During power up VREF should either be applied coincidently with or after VDDQ.
During power down VREF should either be removed coincidently with or before VDDQ.
LENH input Latch Enable: Active high retention latch enable. Note this signal is driven in the
VDDQ voltage domain by drivers in the MSD_D3R_PRETLEX and
MSD_DSR_PRETLEC cells. This signal should not be connected to devices operating
in the core logic voltage domain (VDD).
In retention mode, the values of the control inputs are latched so that the ZIOH[63:0]
value is retained if the core supply (VDD) is removed.
Table 10-16 MSD_D3R_PVREF Pin List (Continued)
SolvNet
DesignWare.com
10.8 Retention Latch Enable Input (MSD_D3R_PRETLE)
General Description
Pin List
Retention Functional Description
The Retention Latch Enable Input (MSD_D3R_PRETLE) is a special inverting input cell used to receive an
external Data_Retention_N signal and distribute it, by abutment, to all other I/O cells. The input is an
LVCMOS buffer operating at the VDDQ level. The output, LENH, is an LVCMOS signal also operating at
the VDDQ voltage level.
Provision is made for the user to hardwire an internal pull up or pull down on the cell PAD pin. It is also
possible to drive the PAD pin or the PADI internal node from a VDDQ level internal signal via a core side
pin. External or internal input signals are mutually exclusive options.
When the Data_Retention_N signal is asserted (low), the internal LENH signal is driven high, which closes
latches on all control and/or data inputs from the core to I/O cells. Consequently, the output state of all I/O
cells is frozen even if the VDD supply is removed. The purpose of this is to retain a known state on the
signals to the SDRAMs, while the host IC is placed in a low power mode.
10.8.2 Pin List
Caution
The PRETLE cell is not recommended for new designs as it has features that are not optimal for
use in an SoC flow. Existing designs can continue using PRETLE as there are no functional issues
with it, but new designs should use MSD_D3R_PRETLEX (external control) or
MSD_D3R_PRETLEC (internal control) instead.
The differences are as follows:
PRETLE featured a built-in, selectable, Data_Retention_N pull up or pull down option which is
not available on PRETLEX or PRETLEC
PRETLE could be controlled from either an external or internal signal while the PRETLEX has
an external control only and PRETLEC has an internal control only
PRETLE's internal Data_Retention_N (PADI) signal had to be driven at the IO supply voltage
(VDDQ) level. PRETLEC's control signal can be driven at the core supply voltage (VDD) or IO
supply voltage (VDDQ) levels.
Table 10-17 MSD_D3R_PRETLE Pin List
PAD input Data_Retention_N input, active low: control path from bond pad into the cell
0 = Retention Mode, LENH driven high
1 = Normal Mode, LENH driven low
SolvNet
DesignWare.com
10.8.3 Retention Functional Description
The purpose of the retention function is to retain a known state on the signals to the SDRAMs while the host
IC is placed in a low power mode, specifically when the core VDD supply is powered down. The general
concept is that an external input signal (Data_Retention_N) is driven low to put the SSTL I/O cells into
retention mode shortly before the core VDD supply is powered down. The user must set the SSTL I/O
outputs in the state required during power down before asserting Data_Retention_N. This ensures that the
output state of all SSTL I/Os are held static in the desired state while core VDD is power down. After core
VDD is restored, the user must re-initialize the core logic to a known state before de-asserting the
Data_Retention_N signal.
This feature is implemented using a special input cell (MSD_D3R_PRETLE) to receive and distribute the
Data_Retention_N signal by abutment. Also, all SSTL I/O library cells that have control inputs and/or data
inputs from the core have latches that are closed with the assertion of Data_Retention_N to retain the input
value. Because the input state to the I/O cell is held static, the output state will also be static, such as output
impedance settings, PAD pin values, etc. Because the PAD pin input is not latched, an SSTL I/O cell in
input mode will still respond to changes in the external signal attached to PAD. However, once core VDD is
powered down, DI will be indeterminate because it is powered from this supply. When Data_Retention_N
is deasserted, the latches are in transparent mode and have no impact on the operation of the cells.
There is also a special VSSQ cell called MSD_D3R_PVSSQ_RDIS that should be used whenever there is not
an MSD_D3R_PRETLE cell in the design to disable the internal retention signal (LENH) using a pull down
resistor. Only one MSD_D3R_PRETLE or one MSD_D3R_PVSSQ_RDIS cell should be used in any
LENH output Latch Enable High Voltage, active high: control signal distributed to all IO cells by
abutment, using a high-drive buffer (max load 6pF). Note this signal is driven in the
VDDQ voltage domain by drivers in the cells MSD_D3R_PRETLEX and
MSD_DSR_PRETLEC. This signal should not be connected to devices operating in the
core logic voltage domain (VDD).
PADI input PAD Internal: path from the core side to the input buffer (after the ESD protection
circuitry)
PU_A inout Pull Up pin A: short to PU_B to hardwire a pull up on PAD
PU_B inout Pull Up pin B: short to PU_A to hardwire a pull up on PAD
PD_A inout Pull Down pin A: short to PD_B to hardwire a pull down on PAD
PD_B inout Pull Down pin B: short to PD_A to hardwire a pull down on PAD
ZIOH[63:0] input Impedance Control: Thermometer encoded bus that controls the value of ODT and
cell MSD_D3R_PVREF. This bus should not connect to devices operating in the core
logic voltage domain (VDD).
MVDDQ input supply connection (1.35V/1.5V/1.8V)
Table 10-17 MSD_D3R_PRETLE Pin List (Continued)
SolvNet
DesignWare.com
contiguous SSTL I/O library cell section. All I/O library cells, including corner and spacer cells, provide a
pass-through for the LENH signal so that the user has no need to route LENHit is all handled by
abutment.
Figure 10-8 provides an example of the I/O cell arrangement with retention. Figure 10-8 shows an example
without retention. Figure 10-9 provides a sequence of events to enter and exit retention.
Figure 10-8 Example of I/O Cell Arrangement with Retention
PZQ
PRETLE
PDDRIO
PVSS
PVDD
PDIFFI
PVSSQ
PDIFFO
PVSSQ
PVREF
PVDDQ
PAIO
Data_Retention_N
LENH
SolvNet
DesignWare.com
Figure 10-9 Example of I/O Cell Arrangement without Retention
Figure 10-10 Sequence of Events to Enter and Exit Retention
The sequence of events is:
1. Enter self-refresh mode using the Self-Refresh Command
2. Set CKE low
3. Stop CK/CKB
4. Assert Data_Retention_N (low)
PZQ
PDDRIO
PVSS
PVDD
PDIFFI
PVSSQ
PDIFFO
PVSSQ_RDIS
PVREF
PVDDQ
PAIO
LENH
PD
Set I/O State
Reset I/O State
Data_Ret_N
VDD
0V
SolvNet
DesignWare.com
5. Power-Off
6. Power-On
7. After reset is released, execute initialization
8. De-assert_Data_Retention_N (high)
9. Start CK/CKB
10. Set CKE high
11. Exit self-refresh mode
10.8.3.1 CKE Retention Mode
An alternative CKE retention mode is also supported by this library. This scheme works by placing the
SDRAMs into self-refresh mode and then driving the CKE signal low. Core VDD and VDDQ can then both
be powered down except for a small VDDQ island supplying the CKE output cell. Two of the special 5um
spacer cells MSD_D3R_PFILL5_ISO are used to break the VDDQ rail in order to create a separate CKE
VDDQ island, which is kept powered while core VDD and the main VDDQ are powered down. A
minimum of two MSD_D3R_PVDDQ cells are required to be within the VDDQ island. Each
MSD_D3R_PVDDQ cell in the VDDQ island must be connected in the package.
For DDR3 SDRAM support, the IO cell driving the RESET# signal must also be placed in the CKE VDDQ
island.
In all cases, a PVREF cell must be included within the CKE VDDQ island to ensure that Zo of the PDDRIO
cells within the island is maintained when VDDQ to the rest of the DDR IO segment is powered down. This
is required because the PVREF cell drives the ZIOH bus to all IO cells to set the Zo and ODT values and the
ZIOH bus value is not latched into each IO cell when LENH is asserted. Since there can be more than one
PVREF cell in a contiguous DDR IO segment, care has to be taken to isolate the ZIOH bus of the powered
PVREF cells from unpowered PVREF cells. This is done by replacing one PVSSQ between the PVREF cells
with a PVSSQZB cell.
The following describes the possible scenarios:
1. Three or more VREFs (see Figure 10-11)
There will most likely be VREF cells in the unpowered segments to the left and right of the CKE
VDDQ island. Therefore, switch one PVSSQ cell on the left and one PVSSQ on the right of the
CKE VDDQ island to a PVSSQZB cell.
2. Two PVREFs (see Figure 10-12)
There is only be one unpowered VREF. It will be to the left or right of the CKE VDDQ island.
Therefore, switch one PVSSQ cell on the left or right of the CKE VDDQ island to a PVSSQZB cell
as appropriate.
3. One PVREF (see Figure 10-13)
There is no unpowered VREF cells as the one VREF cell must be in the CKE VDDQ island.
Therefore, no PVSSQZB cells should be used.
Figure 10-11, Figure 10-12, and Figure 10-13 show the different scenarios. The placement of the PVSSQZB
cell also needs to take the max VREF spacing rule into account. It dictates that a PVREF should be placed
every ~3mm and be responsible for driving ~1.5mm of the ZIOH bus on either side. Accordingly, the
PVSSQZB cells should be placed in such a way as to avoid any one PVREF driving more than ~1.5mm of
ZIOH bus on either side.
SolvNet
DesignWare.com
Figure 10-11 Example of I/O Cell Arrangement for CKE Retention Mode - Three or more VREF Cells
Figure 10-12 Example of I/O Cell Arrangement for CKE Retention Mode - Two VREF Cells
SolvNet
DesignWare.com
Figure 10-13 Example of I/O Cell Arrangement for CKE Retention Mode - One VREF Cells
Note Note Note Note
The VREF input to all the PVREF cells (including the PVREF in the CKE VDDQ island) is common.
VREF should track VDDQ supplied to the PVDDQ cells outside the CKE retention island as it is
removed and restored. This will result in VREF being removed from the CKE retention island during
retention but as it only contains outputs no functional impact will result. A PVREF cell is required
inside the CKE retention island for its secondary function of driving the ZIOH bus (this is unaffected by
the state of VREF).
Caution
A minimum of two MSD_D3R_PVDDQ cells are required to be within the VDDQ island. Each
SolvNet
DesignWare.com
10.9 Retention Latch Enable Input - External (MSD_D3R_PRETLEX)
General Description
Pin List
The Retention Latch Enable Input (MSD_D3R_PRETLEX) is a special inverting input cell used to receive an
external Data_Retention_N signal and distribute it, by abutment, to all other I/O cells. The input is an
LVCMOS buffer operating at the VDDQ level. The output, LENH, is an LVCMOS signal also operating at
the VDDQ voltage level.
When the Data_Retention_N signal is asserted (low), the internal LENH signal is driven high, which closes
latches on all control and/or data inputs from the core to I/O cells. Consequently, the output state of all I/O
cells is frozen even if the VDD supply is removed. The purpose of this is to retain a known state on the
signals to the SDRAMs, while the host IC is placed in a low power mode.
10.9.2 Pin List
Table 10-18 MSD_D3R_PRETLEX Pin List
PAD input Data_Retention_N input, active low: control path from bond pad into the cell
0 = Retention Mode, LENH driven high
1 = Normal Mode, LENH driven low
MVDDQ input supply connection (1.2V/1.35V/1.5V/1.8V)
SolvNet
DesignWare.com
The purpose of the retention function is to retain a known state on the signals to the SDRAMs while the host
IC is placed in a low power mode, specifically when the core VDD supply is powered down. The general
concept is that an external input signal (Data_Retention_N) is driven low to put the SSTL I/O cells into
retention mode shortly before the core VDD supply is powered down. The user must set the SSTL I/O
outputs in the state required during power down before asserting Data_Retention_N. This ensures that the
output state of all SSTL I/Os are held static in the desired state while core VDD is power down. After core
VDD is restored, the user must re-initialize the core logic to a known state before de-asserting the
Data_Retention_N signal.
This feature is implemented using a special input cell (MSD_D3R_PRETLEX) to receive and distribute the
Data_Retention_N signal by abutment. Also, all SSTL I/O library cells that have control inputs and/or data
inputs from the core have latches that are closed with the assertion of Data_Retention_N to retain the input
value. Because the input state to the I/O cell is held static, the output state will also be static, such as output
impedance settings, PAD pin values, etc. Because the PAD pin input is not latched, an SSTL I/O cell in
input mode will still respond to changes in the external signal attached to PAD. However, once core VDD is
powered down, DI will be indeterminate because it is powered from this supply. When Data_Retention_N
is deasserted, the latches are in transparent mode and have no impact on the operation of the cells.
There is also a special VSSQ cell called MSD_D3R_PVSSQ_RDIS that should be used whenever there is not
a MSD_D3R_PRETLE, MSD_D3R_PRETLEX or MSD_D3R_PRETLEC cell in the design to disable the
internal retention signal (LENH) using a pull down resistor. Only one MSD_D3R_PRETLE,
MSD_D3R_PRETLEX (or MSD_D3R_PRETLEC) or one MSD_D3R_PVSSQ_RDIS cell should be used in any
contiguous SSTL I/O library cell section. All I/O library cells, including corner and spacer cells, provide a
pass-through for the LENH signal so that the user has no need to route LENHit is all handled by
abutment.
Figure 10-14 provides an example of the I/O cell arrangement with retention. Figure 10-15 shows an
example without retention. Figure 10-16 provides a sequence of events to enter and exit retention.
SolvNet
DesignWare.com
Figure 10-14 Example of I/O Cell Arrangement with Retention
Figure 10-15 Example of I/O Cell Arrangement without Retention
PZQ
PRETLEX
PDDRIO
PVSS
PVDD
PDIFFI
PVSSQ
PDIFFO
PVSSQ
PVREF
PVDDQ
PAIO
Data_Retention_N
LENH
PZQ
PDDRIO
PVSS
PVDD
PDIFFI
PVSSQ
PDIFFO
PVSSQ_RDIS
PVREF
PVDDQ
PAIO
LENH
PD
SolvNet
DesignWare.com
Figure 10-16 Sequence of Events to Enter and Exit Retention
The sequence of events is:
1. Enter self-refresh mode using the Self-Refresh Command
2. Set CKE low
3. Stop CK/CKB
4. Assert Data_Retention_N (low)
5. Power-Off
6. Power-On
7. After reset is released, execute initialization
8. De-assert_Data_Retention_N (high)
9. Start CK/CKB
10. Set CKE high
11. Exit self-refresh mode
10.9.3.1 CKE Retention Mode
An alternative CKE retention mode is also supported by this library. This scheme works by placing the
SDRAMs into self-refresh mode and then driving the CKE signal low. Core VDD and VDDQ can then both
be powered down except for a small VDDQ island supplying the CKE output cell. Two of the special 5um
spacer cells MSD_D3R_PFILL5_ISO are used to break the VDDQ rail in order to create a separate CKE
VDDQ island, which is kept powered while core VDD and the main VDDQ are powered down. A
minimum of two MSD_D3R_PVDDQ cells are required to be within the VDDQ island. Each
For DDR3 SDRAM support, the IO cell driving the RESET# signal must also be placed in the CKE VDDQ
island.
In all cases, a PVREF cell must be included within the CKE VDDQ island to ensure that Zo of the PDDRIO
cells within the island is maintained when VDDQ to the rest of the DDR IO segment is powered down. This
Set I/O State
Reset I/O State
Data_Ret_N
VDD
0V
SolvNet
DesignWare.com
is required because the PVREF cell drives the ZIOH bus to all IO cells to set the Zo and ODT values and the
ZIOH bus value is not latched into each IO cell when LENH is asserted. Since there can be more than one
PVREF cell in a contiguous DDR IO segment, care has to be taken to isolate the ZIOH bus of the powered
PVREF cells from unpowered PVREF cells. This is done by replacing one PVSSQ between the PVREF cells
with a PVSSQZB cell.
The following describes the possible scenarios:
1. Three or more VREFs (see Figure 10-17)
There will most likely be VREF cells in the unpowered segments to the left and right of the CKE
VDDQ island. Therefore, switch one PVSSQ cell on the left and one PVSSQ on the right of the
CKE VDDQ island to a PVSSQZB cell.
2. Two PVREFs (see Figure 10-18)
There is only be one unpowered VREF. It will be to the left or right of the CKE VDDQ island.
Therefore, switch one PVSSQ cell on the left or right of the CKE VDDQ island to a PVSSQZB cell
as appropriate.
3. One PVREF (see Figure 10-20)
There is no unpowered VREF cells as the one VREF cell must be in the CKE VDDQ island.
Therefore, no PVSSQZB cells should be used.
Figure 10-17, Figure 10-18, and Figure 10-20 show the different scenarios. The placement of the PVSSQZB
cell also needs to take the max VREF spacing rule into account. It dictates that a PVREF should be placed
every ~3mm and be responsible for driving ~1.5mm of the ZIOH bus on either side. Accordingly, the
PVSSQZB cells should be placed in such a way as to avoid any one PVREF driving more than ~1.5mm of
ZIOH bus on either side.
SolvNet
DesignWare.com
Figure 10-17 Example of I/O Cell Arrangement for CKE Retention Mode - Three or more VREF Cells
Figure 10-18
Figure 10-19 Example of I/O Cell Arrangement for CKE Retention Mode - Two VREF Cells
SolvNet
DesignWare.com
Figure 10-20 Example of I/O Cell Arrangement for CKE Retention Mode - One VREF Cells
Note Note Note Note
The VREF input to all the PVREF cells (including the PVREF in the CKE VDDQ island) is common.
VREF should track VDDQ supplied to the PVDDQ cells outside the CKE retention island as it is
removed and restored. This will result in VREF being removed from the CKE retention island during
retention but as it only contains outputs no functional impact will result. A PVREF cell is required
inside the CKE retention island for its secondary function of driving the ZIOH bus (this is unaffected by
the state of VREF).
Caution
A minimum of two MSD_D3R_PVDDQ cells are required to be within the VDDQ island. Each
SolvNet
DesignWare.com
10.10 Retention Latch Enable Input - Core (MSD_D3R_PRETLEC)
General Description
Pin List
The Retention Latch Enable Input (MSD_D3R_PRETLEC) is a special input cell used to receive an internal
Data_Retention signal and distribute it, by abutment, to all other I/O cells. The input is a differential
LVCMOS buffer operating at the VDD level. The output, LENH, is an LVCMOS signal operating at the
VDDQ voltage level.
When the Data_Retention signals RET/RET_B are asserted (high/low), the internal LENH signal is driven
high, which closes latches on all control and/or data inputs from the core to I/O cells. Consequently, the
output state of all I/O cells is frozen even if the VDD supply is removed. The purpose of this is to retain a
known state on the signals to the SDRAMs, while the host IC is placed in a low power mode.
10.10.2 Pin List
Table 10-19 MSD_D3R_PRETLEC Pin List
RET/RET_B inputs Differential Data_Retention input, active high
0/1 = Normal mode, LENH driven low
1/0 = Retention Mode, LENH driven high
MVDDQ input supply connection (1.2V/1.35V/1.5V/1.8V)
PAD inout I/O ground connection (0V)
SolvNet
DesignWare.com
The retention function operates in exactly the same manner when using a PRETLEC cell as it does when
using a PRETLEX cell. The only difference is that the Data_Retention signal is sourced externally through a
package pin for PRETLEX and internally from the SoC logic for PRETLEC.
Please refer Retention Latch Enable Input - External (MSD_D3R_PRETLEX) on page 169 for more
information.
Note Note Note Note
When using the PRETLEC cell, the Data_Retention signal must be supplied from logic
powered by an isolated VDD supply which is not removed during retention. This also
applies to any buffers between the Data_Retention logic and the PRETLEC cell.
SolvNet
DesignWare.com
10.11 Analog Signal Cell (MSD_D3R_PAIO)
This section includes the following sections:
General Description
Pin List
10.11.1 General Description Figure 10-21 Analog Signal Cell (MSD_D3R_PAIO)
AT
AE
PAD
ESD1
M
V
R
E
F
M
V
D
D
Q
M
V
S
S
Q
M
V
D
D
M
V
S
S
Z
I
O
H
[
6
3
:
0
]
L
E
N
H
MSD_D3R_PAIO is an interface cell used to provide
on- or off-chip access to an analog signal. Analog
signal connections are supported through an ESD
resistor and CMOS transmission gate. The
transmission gate allows the analog signal to be
disconnected from the bondpad.
10.11.2 Pin List
Table 10-20 provides the pin list for the MSD_D3R_PAIO cell.
Table 10-20 MSD_D3R_PAIO Pin List
AE input Analog signal enable. Active high: '0' disables path between AT and PAD, '1' enables
path between AT and PAD
AT inout Analog signal connection: core-side connection point. Note that the maximum
allowable voltage on this pin is equal to VDDQ.
PAD inout Bond Pad
ZIOH[63:0] input Impedance Control: Thermometer encoded bus which controls the value of ODT and
output impedance. Note this bus is driven in the VDDQ voltage domain by drivers in
the cell MSD_D3R_PVREF. This bus should not connect to devices operating in the
core logic voltage domain (VDD).
LENH input Latch Enable: Active high retention latch enable. Note this signal is driven in the
MSD_DSR_PRETLEC cells. This signal should not be connected to devices
operating in the core logic voltage domain (VDD).
In retention mode, the value of the signal AE is latched.
SolvNet
DesignWare.com
10.12 Power/Ground Supply Cells
General Description
Cell List
10.12.1 General Description Figure 10-22 General Power and Ground Supply Cells
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
ESD1
ESD1
ESD1
ESD1
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
ESD1
ESD1
ESD1
Z
I
O
H
[
6
3
:
0
]
Z
I
O
H
[
6
3
:
0
]
Z
I
O
H
[
6
3
:
0
]
Z
I
O
H
[
6
3
:
0
]
Z
I
O
H
[
6
3
:
0
]
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
Z
I
O
H
[
6
3
:
0
]
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
Z
I
O
H
[
6
3
:
0
]
L
E
N
H
L
E
N
H
L
E
N
H
L
E
N
H
L
E
N
H
L
E
N
H
L
E
N
H
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
ESD2 ESD1
Z
I
O
H
[
6
3
:
0
]
L
E
N
H
MVREF
MSD_D3R_PVREF
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
M
V
D
D
ESD1
M
V
D
D
L
E
N
H
Z
I
O
H
[
6
3
:
0
]
MVSS MVSS
MVDDQ
MVSSQ
MVDD MVDD
MVSS_PLL
MVAA_PLL
MSD_D3R_PVAA_PLL
MSD_D3R_PVSS_PLL
VAA VAA
MSD_D3R_PVAA
MSD_D3R_PVDD
MSD_D3R_PVSS
MSD_D3R_PVDDQ
MVAA_PLL
MVSS_PLL
MSD_D3R_PVSSQ
M
V
D
D
Q
M
V
S
S
Q
M
V
R
E
F
M
V
S
S
MSD_D3R_PVSSQ_RDIS
MVSSQ
Five main power supply I/O cells are available:
MSD_D3R_PVAA is for analog supplies
MSD_D3R_PVDD is for core power (MVDD)
MSD_D3R_PVSS is for core ground (MVSS)
MSD_D3R_PVDDQ is for I/O power (MVDDQ)
MSD_D3R_PVSSQ is for I/O ground (MVSSQ)
There are also specialty power supply cells:
MSD_D3R_PVSSQZB is for I/O ground
(MVSSQ) and does not contain any ZIOH busing
to act as a ZIOH break cell
MSD_D3R_PVAA_PLL is an isolated high
voltage supply for the PLL
MSD_D3R_PVSS_PLL is an isolated ground for
the PLL
MSD_D3R_PVSSQ_RDIS is for I/O ground and
also pulls down the internal Retention Latch
Enable signal to disable retention; used whenever
there is noPRETLEX/PRETLEC cells in the
design
For connectivity/LVS purposes, the I/O supply
names MVDD, MVSS, MVDDQ, and MVSSQ are not
treated as global nets. This prevents name-space
conflicts for designs using a variety of I/O types,
voltages, and/or standards. As a result, explicit
instantiation of these nets in a netlist is required.
MSD_D3R_PVAA is an interface cell used to supply
an isolated voltage supply. Analog power
connections are supported by a direct connection
between the bond pad to the core, which does not
connect to any of the power rails within the I/O ring.
SolvNet
DesignWare.com
10.12.2 Cell List
Table 10-21 shows the cell list for the power supply I/O cells.
Table 10-21 Power Supply I/O Cell List
Cell Description Pin List
MSD_D3R_PVAA Analog supply cell
MVDD, MVSS, MVDDQ, MVSSQ, MVREF, VAA,
ZIOH[63:0], LENH
MSD_D3R_PVDD VDD core supply cell
MVDD, MVSS, MVDDQ, MVSSQ, MVREF,
ZIOH[63:0], LENH
MSD_D3R_PVSS VSS core ground cell
ZIOH[63:0], LENH
MSD_D3R_PVDDQ
VDDQ I/O supply cell
(1.2V/1.35V/1.5V/1.8V)
ZIOH[63:0], LENH
MSD_D3R_PVSSQ VSSQ I/O ground cell (0V)
ZIOH[63:0], LENH
MSD_D3R_PVSSQ_RDIS
VSSQ I/O ground cell (0V) with
retention disable
ZIOH[63:0], LENH
MSD_D3R_PVSSQZB VSSQ I/O ground cell (0V) MVDD, MVSS, MVDDQ, MVSSQ, MVREF, LENH
MSD_D3R_PVAA_PLL PLL supply cell (2.5V)
ZIOH[63:0], MVAA_PLL, LENH
MSD_D3R_PVSS_PLL PLL ground cell (0V)
ZIOH[63:0], MVSS_PLL, LENH
Note Note Note Note
VAA is subject to the same Absolute Maximum DC Ratings and Recommended Operating Conditions
as VDD.
SolvNet
DesignWare.com
10.13 Corner and Filler Cells
This section contains the following topics:
General Description
Cell List
There is one corner cell that should be used to continue an SSTL I/O segment around any corner on a die.
The corner cell provides pass-through connectivity for all the common I/O rails: MVDD, MVSS, MVDDQ,
MVSSQ, MVREF, ZIOH[63:0], and LENH.
Table 10-22 shows a range of filler cells provided to allow customers to meet their bond pad pitch
requirements. All filler cells (unless otherwise noted) provide pass-through connectivity for all the common
I/O rails: MVDD, MVSS, MVDDQ, MVSSQ, MVREF, ZIOH[63:0], and LENH.
10.13.2 Cell List
Table 10-22 shows the cell list for all corner and filler cells.
Table 10-22 Corner and Filler Cell List
MSD_D3R_PCORNER Corner cell MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
MSD_D3R_PFILL_1 0.1um spacer cell MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
MSD_D3R_PFILL_5 0.5um spacer cell MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
SolvNet
DesignWare.com
MSD_D3R_PFILL1 1.0um spacer cell MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
MSD_D3R_PFILL5 5.0um spacer cell MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
MSD_D3R_PFILL5_ISO 5.0um spacer cell with VDDQ break MVDD
MVSS
MVDDQ
MVSSQ
MVREF
ZIOH[63:0]
LENH
Table 10-22 Corner and Filler Cell List (Continued)
SolvNet
DesignWare.com
10.14 Wire Bond Pad Cells with Decoupling
In traditional wirebond designs, the PPADCWxxx_type cells provide both the bond pad and increased on-
die VDDQ/VSSQ decoupling. The decoupling capacitors are connected to MVSSQ and MVDDQ busses that
run laterally through the cells and automatically connect by abutment. These busses are tied into the I/O
cell MVDDQ and MVSSQ busses at the PVDDQ and PVSSQ cells respectively. The appropriate
PPADCWxxx_type cell type must be used with each IO cell to form a contiguous row (see Table 10-23 for
details).
Table 10-23 shows the I/O cell to PPADCWxxx_type bond pad mapping.
Table 10-23 I/O Cell to PPADCWxxx_type Bond Pad Mapping
Synopsys IO Cell Name Associated PPADCW Cells Alternative PPADCW Cell
MSD_D3R_PDQSR_VSSQ MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PRETLEC MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PVSSQ MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PVSSQ_RDIS MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PVSSQZB MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PVDDQ MSD_D3R_PPADCWxxx_VDDQ
MSD_D3R_PFILLx MSD_D3R_PPADCWxxx_PFILLx
MSD_D3R_PFILLx_RES MSD_D3R_PPADCWxxx_PFILLx
MSD_D3R_PFILL5_LENHB MSD_D3R_PPADCWxxx_PFILL5
MSD_D3R_PEND MSD_D3R_PPADCWxxx_END
MSD_D3R_PCORNER MSD_D3R_PPADCWxxx_END
MSD_D3R_PAIO MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PDDRIO MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PDIFF MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PDQSR MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PRETLE MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PRETLEX MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVAA_PLL MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVDD MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVREF MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVSS MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVSS_PLL MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PVAA MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PZQ MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PFILL5_ISO None MSD_D3R_PPADCWxxx_FILL5_ISO
SolvNet
DesignWare.com
Figure 10-23 Figure 10-23 provides an example of the placement of PPADCWxxx_type bond pad cells with
respect to an IO cell ring which includes an SSTL corner cell.Using PPADCWxxx_type Bond Pads
Note Note Note Note
Since the wire bond pads do not extend into the corner cell, use the PPADCW_END cell to
terminate PPADCW row.
CORNER
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S S T L
S S T L
S S T L
S S T L
S S T L
S S T L
PPADCWxxx_type Cell Height
lO Cell Height
S
S
T
L
MSD_D3R_PDDRlO,
MSD_D3R_PDlFF,
MSD_D3R_PVDD,
MSD_D3R_PVSS, etc.
S
S
T
L
MSD_D3R_PVDDQ
S
S
T
L
MSD_D3R_PVSSQ,
MSD_D3R_PDQSR_VSSQ,
MSD_D3R_PRETLEC,
MSD_D3R_PVSSQ_RDlS or
MSD_D3R_PVSSQZB
Legend
MSD_D3R_PPADCWxxx_CUP
MSD_D3R_PPADCWxxx_VDDQ
MSD_D3R_PPADCWxxx_VSSQ
MSD_D3R_PPADCW_END
lntegrated Bond Pad
SolvNet
DesignWare.com
Figure 10-24 shows the placement of PPADCWxxx_type bond pad cells with respect to an IO cell ring which
includes a CKE Retention VDDQ island. The key point to note is that in order to maintain the isolation of
MVDDQ within the retention island a gap must be left in the PPADCWxxx_type row unless the
PPADCW_ISO cell is available in the SSTL library. In this case the PPADCWxxx_FILL5_ISO cell can be
placed in the PPADCW row adjacent to the PFILL5_ISO cell in the IO ring.
Figure 10-24 Using PPADCWxxx_type bond pads around the VDDQ Island
10.15 SnapCap Cells
In CUP wirebond and Flip Chip designs, SnapCap cells can be used to increase the on-die VDDQ/VSSQ
decoupling by stacking them on the outer end of IO cells in a contiguous row.
Multiple rows can be stacked to increase the total decoupling as the SnapCaps abut vertically as well as
horizontally. The decoupling capacitors are connected to MVSSQ and MVDDQ busses that run laterally
through the cells and automatically connect by abutment. These busses are tied into the I/O cell MVDDQ
and MVSSQ busses at the PVDDQ and PVSSQ cells respectively. The appropriate PSCAP_type cell type
must be used with each IO cell to form a contiguous row (see Table 10-24 for details).
Table 10-24 shows the I/O to SnapCap cell mapping.
Note Note Note Note
There should be at least one MSD_D3R_PPADCWxxx_VSSQ cell and one
MSD_D3R_PADDCWxxx_VDDQ cell (and their matching I/O cells) inside the island.
Table 10-24 I/O Cell to SnapCap Cell Mapping
Synopsys IO Cell Name Associated PSCAP Cells Alternative PSCAP Cell
MSD_D3R_PDQSR_VSSQ MSD_D3R_PSCAP_VSSQ
MSD_D3R_PRETLEC MSD_D3R_PSCAP_VSSQ
MSD_D3R_PVSSQ MSD_D3R_PSCAP_VSSQ
MSD_D3R_PVSSQ_RDIS MSD_D3R_PSCAP_VSSQ
MSD_D3R_PVSSQZB MSD_D3R_PSCAP_VSSQ
MSD_D3R_PVDDQ MSD_D3R_PSCAP_VDDQ
VDDQ
lsland
D
3
R
_
P
F
I
L
L
5
_
I
S
O
D
3
R
_
P
F
I
L
L
5
_
I
S
O
lO Ring lO Ring
PPADCWxxx row PPADCWxxx row should be broken here and the
space should be left blank unless the
PPADCWxxx_FlLL5_lSO cell is available in the library
SolvNet
DesignWare.com
MSD_D3R_PFILLx MSD_D3R_PSCAP_PFILLx
MSD_D3R_PFILLx_RES MSD_D3R_PSCAP_PFILLx
MSD_D3R_PFILL5_LENHB MSD_D3R_PSCAP_PFILL5
MSD_D3R_PEND MSD_D3R_PSCAP_END
MSD_D3R_PCORNER MSD_D3R_PSCAP_END
MSD_D3R_PAIO MSD_D3R_PSCAP_CUP
MSD_D3R_PDDRIO MSD_D3R_PSCAP_CUP
MSD_D3R_PDIFF MSD_D3R_PSCAP_CUP
MSD_D3R_PDQSR MSD_D3R_PSCAP_CUP
MSD_D3R_PRETLE MSD_D3R_PSCAP_CUP
MSD_D3R_PRETLEX MSD_D3R_PSCAP_CUP
MSD_D3R_PVAA_PLL MSD_D3R_PSCAP_CUP
MSD_D3R_PVDD MSD_D3R_PSCAP_CUP
MSD_D3R_PVREF MSD_D3R_PSCAP_CUP
MSD_D3R_PVSS MSD_D3R_PSCAP_CUP
MSD_D3R_PVSS_PLL MSD_D3R_PSCAP_CUP
MSD_D3R_PVAA MSD_D3R_PSCAP_CUP
MSD_D3R_PZQ MSD_D3R_PSCAP_CUP
MSD_D3R_PFILL5_ISO None MSD_D3R_PPADCWxxx_FILL5_ISO
Table 10-24 I/O Cell to SnapCap Cell Mapping
Synopsys IO Cell Name Associated PSCAP Cells Alternative PSCAP Cell
SolvNet
DesignWare.com
Table 10-22 provides an example of the placement of PSCAP_type bond pad cells when CUP/BOAC bond
pads are used with respect to an I/O cell ring which includes an SSTL corner cell.
Figure 10-25 SnapCap Cells When CUP/BOAC Bond Pads are Used
CORNER
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S S T L
S S T L
S S T L
S S T L
S S T L
S S T L
PSCAP Cell Height
lO Cell Height
1 row of PSCAP
PSCAP Cell Height
1 row of PSCAP
Add as many rows (n) of
SnapCap cells as determined
necessary by the user.
n=0, 1, 2, ...
MSD_D3R_PSCAP_CUP
MSD_D3R_PSCAP_VDDQ
MSD_D3R_PSCAP_VSSQ
MSD_D3R_PSCAP_END
S
S
T
L
MSD_D3R_PDDRlO,
MSD_D3R_PDlFF,
MSD_D3R_PVDD,
MSD_D3R_PVSS, etc.
S
S
T
L
MSD_D3R_PVDDQ
S
S
T
L
MSD_D3R_PVSSQ,
MSD_D3R_PDQSR_VSSQ,
MSD_D3R_PRETLEC,
MSD_D3R_PVSSQZB
Legend
CUP pad
SolvNet
DesignWare.com
Figure 10-26 provides an example of the placement of PSCAP_type bond pad cells when a flip chip package
is used.
Figure 10-26 SnapCap Cells When Flip Chip Package is Used
CORNER
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S
S
T
L
S S T L
S S T L
S S T L
S S T L
S S T L
S S T L
PSCAP Cell Height
lO Cell Height
1 row of PSCAP
PSCAP Cell Height 1 row of PSCAP
MSD_D3R_PSCAP_CUP
MSD_D3R_PSCAP_VDDQ
MSD_D3R_PSCAP_VSSQ
MSD_D3R_PSCAP_END
S
S
T
L
MSD_D3R_PDDRlO,
MSD_D3R_PDlFF,
MSD_D3R_PVDD,
MSD_D3R_PVSS, etc.
S
S
T
L
MSD_D3R_PVDDQ
S
S
T
L
MSD_D3R_PVSSQ,
MSD_D3R_PDQSR_VSSQ,
MSD_D3R_PRETLEC,
MSD_D3R_PVSSQZB
Legend
Add as many rows (n) of SnapCap cells
as determined necessary by the user.
n=0, 1, 2, ...
SolvNet
DesignWare.com
Figure 10-27 shows the placement of PSCAP_type bond pad cells with respect to an IO cell ring which
includes a CKE Retention VDDQ island. The key point to note is that in order to maintain the isolation of
MVDDQ within the retention island a gap must be left in the PSCAP_type row unless the
PSCAP_FILL5_ISO cell is available in the SSTL library. In this case the PSCAP_FILL5_ISO cell can be placed
in the PSCAP row adjacent to the PFILL5_ISO cell in the IO ring.
Figure 10-27 Using SnapCap Cells Around the VDDQ Island
Note Note Note Note
There should be at least one MSD_D3R_PSCAP_VSSQ cell and one MSD_D3R_PSCAP_VDDQ cell
(and their matching I/O cells) inside the island.
VDDQ
lsland
D
3
R
_
P
F
I
L
L
5
_
I
S
O
D
3
R
_
P
F
I
L
L
5
_
I
S
O
lO Ring lO Ring
PSCAP row
PSCAP row should be broken here and the space should be left
blank unless the PSCAP__FlLL5_lSO cell is available in the library
SolvNet
DesignWare.com
10.16 SSTL I/O DC and AC Characteristics
Recommended Operating Conditions
DC Specifications on page 191
AC Specifications on page 211
Decoupling Capacitance on page 216
ESD and LU Performance on page 218
The power supply values specified in the following table are DC design criteria only. They represent the DC
supply limits at the devices internal to the design, including the effects of internal IR drop. VREF of the
receiving device(s) should track the variations in the DC value of VDDQ of the sending device for best noise
margins. The user selects the value of VREF, which provides optimum noise margin in the use conditions
specified by the user. Peak-to-peak noise on VREF may not exceed 5% VREF (DC).
Table 10-25 Recommended Operating Conditions
V
DD
Core supply voltage 0.99 1.10 1.21 V
V
DDQ
SSTL output supply voltage (DDR3) 1.425 1.50 1.575 V
V
DDQ
SSTL output supply voltage (DDR2) 1.70 1.80 1.90 V
V
DDQ
SSTL output supply voltage (DDR3L) 1.283 1.35 1.45 V
V
DDQ
SSTL output supply voltage (MDDR) 1.65 1.80 1.95 V
V
DDQ
SSTL output supply voltage (LPDDR2) 1.14 1.20 1.30 V
V
REF
SSTL reference supply voltage 0.49 * V
DDQ
0.5 * V
DDQ
0.51 * V
DDQ
V
V
TT
External termination voltage V
REF
- 40mV V
REF
V
REF
+ 40mV V
T
J
Junction temperature -40 25 125 C
SolvNet
DesignWare.com
The following sections provide the DC specifications for the SSTL I/O.
10.16.2.1 DDR3 Mode
10.16.2.1.1 DC Specifications
The following table provides input and output DC threshold values and On-DIE-Termination (ODT)
recommended values. The conditions for the output threshold values are unterminated outputs loaded with
1 pF capacitor load. The ODT values are measured after impedance calibration.
10.16.2.1.2 Current Specifications
The following table provides the current value ranges of the power supply and the output ignoring the
current direction (absolute value), output impedance calibrated to Zout=34 ohms. The values are simulated
parameters; in the event of test silicon, this parameter may not be measured. The leakage current is specified
at 125C junction temperature.
Table 10-26 DDR3 Mode DC Specifications
V
IH(DC)
DC input voltage High V
REF
+ 0.100 V
DDQ
V
V
IL(DC)
DC input voltage Low V
SSQ
- 0.3 V
REF
- 0.100 V
V
OH
DC output logic High 0.8*V
DDQ
V
V
OL
DC output logic Low 0.2 * V
DDQ
V
R
TT
Input termination resistance (ODT) to V
DDQ
/2 100
54
36
120
60
40
140
66
44
ohm
Table 10-27 DDR3 Mode Current Specifications
I
OHL(DC)
PAD pin, 34 Output source/sink DC current, Rtt=120 5.04 5.44 mA
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
DDQ
VDDQ standby current; ODT OFF 0.11 37.08 uA
I
DDQ
Output Low Drv/Rtt=34/60, IDDQ DC current 9.77 11.21 mA
I
DDQ
Output High Drv/Rtt=34/60, IDDQ DC current 1.15 1.86 mA
SolvNet
DesignWare.com
10.16.2.1.3 DC Receive Mode Power Specifications
The following table provides the DC power only for the I/O in receive mode for different system
configurations. The parameters are simulated values; in the event of test silicon, this parameter may not be
measured. For the total power, the designer should sum DC power and AC power.
I
DDQ
Input Low ODT/Drv=60/34, IDDQ DC current 6.60 8.49 mA
I
DDQ
Input High ODT/Drv=60/34, IDDQ DC current 12.40 14.75 mA
I
LS
Input leakage current, SSTL mode, unterminated 0.13 61.01 uA
Table 10-28 DC Receive Mode Power Dissipation DDR3 Mode
P
RCV
Input mode DC power dissipation, ODT=OFF 1.75 3.19 mW
P
RCV
Input mode DC power dissipation, ODT/Drv=120/34 8.92 14.82 mW
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
Input mode DC power dissipation, VDD rail 0.11 11.87 uW
Table 10-27 DDR3 Mode Current Specifications (Continued)
SolvNet
DesignWare.com
10.16.2.1.4 DC Drive Mode Power Specifications
The following table provides the DC power only for the I/O in drive mode for different system
measured. For the total power, the designer should sum DC power and AC power. The standby mode
power is specified for 125 degC junction temperature.
Table 10-29 DC Drive Mode Power Dissipation (PDR=0) DDR3 Mode
P
DRV
Output mode DC power dissipation, Rtt=OFF 1.76 3.19 mW
P
DRV
Output mode DC power dissipation, Drv/Rtt=34/120 2.49 3.93 mW
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
Output mode DC power dissipation, VDD rail 0.11 11.65 uW
Table 10-30 DC Drive Mode Power Dissipation (PDR=1) DDR3 Mode
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
STB
Standby mode DC power dissipation (VDDQ rail) 0.17 58.40 uW
SolvNet
DesignWare.com
Table 10-31 I/O Cells Power Specifications DDR3 Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR, and
PDQSR_VSSQ)
P
WRQ_PZQ_STBY
PZQ VDDQ Standby Power 0.03 13.33 uW
P
WR_PZQ_STBY
PZQ VDD Standby Power 0.03 4.09 uW
P
WRQ_PDQSR_STBY
PDQSR VDDQ Standby Power 0.01 7.35 uW
P
WR_PDQSR_STBY
PDQSR VDD Standby Power 0.04 5.78 uW
P
WRQ_PDQSRq_STBY
PDQSR_VSSQ VDDQ Standby Power 0.01 7.35 uW
P
WR_ DQSRq_STBY
PDQSR_VSSQ VDD Standby Power 0.04 5.78 uW
P
WRQ_PRETLE_STBY
PRETLE VDDQ Standby Power 0.02 6.46 uW
P
WR_PRETLE_STBY
PRETLE VDD Standby Power 0 0 uW
P
WRQ_PRETLEX_STBY
PRETLEX VDDQ Standby Power 0.02 6.46 uW
P
WR_PRETLEX_STBY
PRETLEX VDD Standby Power 0 0 uW
P
WRQ_PRETLEC_STBY
PRETLEC VDDQ Standby Power 0.01 3.24 uW
P
WR_PRETLEC_STBY
PRETLEC VDD Standby Power 0 0 uW
P
WRQ_PVREF_STBY
PVREF VDDQ Standby Power 0.06 25.84 uW
P
WR_PVREF_STBY
PVREF VDD Standby Power 0.03 4.15 uW
Table 10-32 PZQ Power Specifications DDR3 Mode (ZQ_OFF deasserted)
P
DR_VQ_34
VDDQ Power ZQ_OFF deasserted drive 34 45.92 53.29 mW
P
DR_VQ_40
P
DR_VQ_50
P
RC_VQ_40
VDDQ Power ZQ_OFF deasserted odt 40 30.72 37.95 mW
P
RC_VQ_60
P
RC_VQ_120
P
RCV
VDD Power ZQ_OFF deasserted - Divide Ratio 1.0-8.0 0.03 4.51 uW
SolvNet
DesignWare.com
10.16.2.2 DDR3L Mode
recommended values. The conditions for the output threshold values are un-terminated outputs loaded
with 1 pF capacitor load. The ODT values are measured after impedance calibration.
Table 10-33 DC Specifications DDR3L Mode
V
IH(DC)
DC input voltage High V
REF
+ 0.09 VDDQ V
V
IL(DC)
DC input voltage Low VSSQ -0.3 V
REF
-0.09 V
V
OH
DC output logic High 0.8 * V
DDQ
V
V
OL
DDQ
V
R
TT
Input termination resistance (ODT) to VDDQ/2
100
54
36
120
60
40
140
66
44

SolvNet
DesignWare.com
Table 10-34 Current Specifications DDR3L Mode
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
DDQ
VDDQ standby current; ODT OFF 0.10 33.87 uA
I
DDQ
I
DDQ
I
DDQ
I
DDQ
I
LS
SolvNet
DesignWare.com
10.16.3 DC Drive Mode Power Specifications
Table 10-35 DC Receive Mode Power Dissipation DDR3L Mode
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
Table 10-36 DC Drive Mode Power Dissipation (PDR=0) DDR3L Mode
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
SolvNet
DesignWare.com
Table 10-37 DC Drive Mode Power Dissipation (PDR=1) DDR3L Mode
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
PSTB Standby mode DC power dissipation (VDDQ rail) 0.14 49.11 uW
Table 10-38 IO Cells, Power Specifications DDR3L Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
P
WRQ_PZQ_STBY
P
WR_PZQ_STBY
P
WRQ_PDQSR_STBY
P
WR_PDQSR_STBY
P
WRQ_PDQSRq_STBY
P
WR_ DQSRq_STBY
P
WRQ_PRETLE_STBY
P
WR_PRETLE_STBY
P
WRQ_PRETLEX_STBY
P
WR_PRETLEX_STBY
P
WRQ_PRETLEC_STBY
P
WR_PRETLEC_STBY
P
WRQ_PVREF_STBY
P
WR_PVREF_STBY
SolvNet
DesignWare.com
Table 10-39 PZQ Power Specifications DDR3L Mode (ZQ_OFF deasserted)
P
DR_VQ_34
VDDQ current ZQ_OFF deasserted drive 34 35.7 45.73 mW
P
DR_VQ_40
P
DR_VQ_50
P
RC_VQ_40
VDDQ current ZQ_OFF deasserted odt 40 26.62 32.11 mW
P
RC_VQ_60
VDDQ current ZQ_OFF deasserted odt 60 19.6 24.93 mW
P
RC_VQ_120
VDDQ current ZQ_OFF deasserted odt 120 10 15.01 mW
P
RCV
VDD current ZQ_OFF deasserted 0.03 4.51 uW
SolvNet
DesignWare.com
10.16.3.1 DDR2 Mode
recommended values. The conditions for the output threshold values are unterminated outputs loaded with
1 pF capacitor load. The ODT values are measured after impedance calibration.
Table 10-40 DC Specifications DDR2 Mode
V
IH(DC)
DC input voltage High VREF + 0.125 VDDQ + 0.3 V
V
IL(DC)
DC input voltage Low VSSQ - 0.3 VREF - 0.125 V
V
OH
DC output logic High VDDQ - 0.28 V
V
OL
DC output logic Low VSSQ + 0.28 V
RTT Input termination resistance (ODT) to VDDQ / 2 120
60
40
150
75
50
180
90
60
ohm
Table 10-41 Current Specifications DDR2 Mode
I
OHL(DC)
PAD pin, 18- Output source/sink DC current, Rtt=150 5.40 5.75 mA
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
OHL(DC)
I
DDQ
VDDQ standby current, ODT OFF 0.14 46.27 uA
I
DDQ
I
DDQ
I
DDQ
I
DDQ
SolvNet
DesignWare.com
configuration. The parameters are simulated values; in the event of test silicon, this parameter may not be
10.16.3.1.4 DC Drive Mode Power Specifications
I
LS
Table 10-42 DC Receive Mode Power Dissipation DDR2 Mode
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
P
RCV
Table 10-43 DC Drive Mode Power Dissipation (PDR = 0) DDR2 Mode
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
Table 10-41 Current Specifications DDR2 Mode (Continued)
SolvNet
DesignWare.com
P
DRV
Output mode DC power dissipation (VDD rail) 0.11 11.65 uW
Table 10-44 DC Drive Mode Power Dissipation (PDR = 1) DDR2 Mode
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
DRV
P
STB
Standby mode DC power dissipation (VDDQ rail) 0.25 87.91 uW
Table 10-45 Cells Power Specifications - DDR2 Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
P
WRQ_ PZQ_STBY
P
WR _PZQ_STBY
P
WRQ_ PDQSR_STBY
P
WR _PDQSR_STBY
P
WRQ _PDQSRq_STBY
P
WR _PDQSRq_STBY
P
WRQ_PRETLE_STBY
P
WR_PRETLE_STBY
P
WRQ_ PRETLEX_STBY
P
WR_ PRETLEX_STBY
P
WRQ_ PRETLEC_STBY
Table 10-43 DC Drive Mode Power Dissipation (PDR = 0) DDR2 Mode (Continued)
SolvNet
DesignWare.com
P
WR_ PRETLEC_STBY
P
WRQ_PVREF_STBY
P
WR_PVREF_STBY
Table 10-46 PZQ Power Specifications - DDR2 Mode (ZQ_OFF deasserted)
P
DRVQ_40
VDDQ pwr ZQ_OFF deasserted drive 40 59.08 71.94 mW
P
RCVQ_50
VDDQ pwr ZQ_OFF deasserted odt 50 39.31 50.06 mW
P
RCVQ_75
P
RCVQ_150
P
RCV
Table 10-45 Cells Power Specifications - DDR2 Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
SolvNet
DesignWare.com
10.16.3.2 Mobile DDR Mode
The following table provides input and output DC threshold recommended values. This mode uses rail-to-
rail signal swing, and the I/O supply VDDQ is 1.8V nominal. The conditions for the output threshold
values are un-terminated outputs loaded with 1 pF capacitor load. The control signals for the I/O: IOM=1,
OE=0, PDD=1, PDR=1, and DOUT=1/0. The quiescent current is specified with junction temperature
125 degC.
Table 10-47 Mobile DDR Mode
V
IH(DC)
DC Input logic threshold High 0.7* VDDQ V
V
IL(DC)
DC Input logic threshold Low 0.3* VDDQ V
V
IH(AC)
AC Input logic High 0.8* VDDQ V
V
IL(AC)
AC Input logic Low 0.2* VDDQ V
V
OH
DC output logic High (IOH=-0.1mA) 0.9*VDDQ V
V
OL
DC output logic Low (IOL=0.1mA) 0.1 *VDDQ V
I
LL
Input leakage current 0.175 80.13 nA
I
DDQ1
VDDQ quiescent current 0.08 29.46 uA
I
DD1
VDD quiescent current 0.08 9.22 uA
Table 10-48 DC Power Specifications - Mobile DDR Mode
P
WR_VDDQ
VDDQ power 0.14 57.44 uW
P
WR_VDD
VDD power 0.09 11.15 uW
Table 10-49 Cells Power Specifications - Mobile DDR Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
P
WRQ_ PZQ_STBY
P
WR _PZQ_STBY
P
WRQ_ PDQSR_STBY
P
WR _PDQSR_STBY
P
WRQ _PDQSRq_STBY
SolvNet
DesignWare.com
P
WR _PDQSRq_STBY
P
WRQ_PRETLE_STBY
P
WR_PRETLE_STBY
P
WRQ_ PRETLEX_STBY
P
WR_ PRETLEX_STBY
P
WRQ_ PRETLEC_STBY
P
WR_ PRETLEC_STBY
P
WRQ_PVREF_STBY
P
WR_PVREF_STBY
Table 10-50 PZQ Power Specifications - Mobile DDR Mode (ZQ_OFF deasserted)
P
DRVQ_ZQOFF
P
DRV_ZQOFF
VDD pwr ZQ_OFF deasserted - Divide Ratio 1.0-8.0 0.03 4.51 uW
Table 10-49 Cells Power Specifications - Mobile DDR Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
SolvNet
DesignWare.com
10.16.3.3 LPDDR2 Mode
The following table provides input and output DC threshold recommended values. This mode uses rail-to-
rail signal swing, and the I/O supply VDDQ is 1.2V nominal. The conditions for the output threshold
values are un-terminated outputs loaded with 1 pF capacitor load. The control signals for the I/O: IOM=0,
OE=0, PDD=1, PDR=1, and DOUT=1/0. The quiescent current is specified with junction temperature 125
degC.
The following table provides the current value ranges of the power supply ignoring the current direction
(absolute value), output impedance calibrated to Zout=40 ohms. The values are simulated parameters; in
the event of test silicon, this parameter may not be measured. The leakage current is specified at 125C
junction temperature.
Table 10-51 DC Specifications LPDDR2 Mode
V
IH(DC)
DC input voltage High VREF + 0.13 VDDQ V
V
IL(DC)
DC input voltage Low VSSQ -0.3 VREF- 0.13 V
V
OH
DC output logic High 0.9 * V
DDQ
V
V
OL
DDQ
V
Table 10-52 Current Specification - LPDDR2 Mode
IDDQ VDDQ quiescent current 0.08 30.21 uA
IDDQ VDDQ quiescent current 0.08 9.31 uA
IDDQ Output Low IDDQ DC current 537 1156 uA
IDDQ Output High IDDQ DC current 501 1048 uA
IDDQ Input Low IDDQ DC current 535 1110 uA
IDDQ Input High IDDQ DC current 500 1045 uA
ILL
1
1. Standby modes are defined in Table 10-6 on page 139
Input leakage current 0.095 48.91 uA
SolvNet
DesignWare.com
10.16.3.3.3 DC Power Specifications
The following table provides the DC power only for the I/O, output impedance calibrated to Zout=40
ohms. The parameters are simulated values; in the event of test silicon, this parameter may not be
power is specified for 125C junction temperature.
Table 10-53 DC Power Dissipation (PDR=0) LPDDR2 Mode
P
RCV
Input mode DC power dissipation, VDDQ rail 0.62 1.51 mW
P
RCV
P
DRV
Output mode DC power dissipation, VDDQ rail 0.62 1.5 mW
P
DRV
PSTB Standby mode DC power dissipation, VDDQ rail 0.096 39.273 uW
Table 10-54 DC Power Dissipation (PDR=1) LPDDR2 Mode
P
DRV
Output mode DC power dissipation, VDDQ rail 1.46 96.47 uW
P
DRV
Table 10-55 Cells Power Specifications - LPDDR2 Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ)
P
WRQ_ PZQ_STBY
P
WR _PZQ_STBY
P
WRQ_ PDQSR_STBY
P
WR _PDQSR_STBY
P
WRQ _PDQSRq_STBY
P
WR _PDQSRq_STBY
P
WRQ_PRETLE_STBY
P
WR_PRETLE_STBY
P
WRQ_ PRETLEX_STBY
P
WR_ PRETLEX_STBY
SolvNet
DesignWare.com
P
WRQ_ PRETLEC_STBY
PRETLEC VDDQ Standby Power 0 2.25 uW
P
WR_ PRETLEC_STBY
P
WRQ_PVREF_STBY
P
WR_PVREF_STBY
Table 10-56 PZQ Power Specifications - LPDDR2 Mode (ZQ_OFF deasserted)
P
DRVQ_34
P
DRVQ_40
P
DRVQ_50
P
DRVQ_60
P
DRVQ_80
P
DRV
Table 10-55 Cells Power Specifications - LPDDR2 Mode (ZQ_OFF, PD are asserted for PZQ , PDQSR and
PDQSR_VSSQ) (Continued)
SolvNet
DesignWare.com
10.16.3.4 Power Grid Support Data
The following table provides the impedance of different I/O cells using metal-stack and 125 degC junction
temperature. For PPAD* cells, the values are provided for a leg of bondpad only. The actual bondwire
landing area is negligible. The values are obtained from simulation; in the event of test silicon, this
parameter may not be measured.
Table 10-57 Power Grid Support Data
Symbol Parameter Typical Units
R
PWR
Impedance, MSD_ D3R_PVAA, pad to VAA 0.29
R
PWR
Impedance, MSD_ D3R_PVAA_PLL, pad to MVAA_PLL 0.29
R
PWR
Impedance, MSD_ D3R_PVDD, pad to MVDD 0.29
R
PWR
Impedance, MSD_ D3R_PVSS, pad to MVSS 0.29
R
PWR
Impedance, MSD_ D3R_PVSS_PLL, pad to MVSS_PLL 0.29
R
PWR
Impedance, MSD_ D3R_PVDDQ, pad to MVDDQ 0.29
R
PWR
Impedance, MSD_ D3R_PVSSQ, pad to MVSSQ 0.29
R
PAD
Impedance, MSD_D3R_PPADCWI30 0.001
R
PAD
Impedance, MSD_D3R_PPADCWO30 0.40
SolvNet
DesignWare.com
10.16.3.5 Electro-Migration (EM) Compliance
The following table provides the Electro-Migration compliance 100,000 POH at degC for the I/O cells,
using metal stack. These values are simulated; In the event of test silicon, this parameter may not be
measured.
Table 10-58 EM Compliance
Symbol Parameter Max Units
EM
DC
Electromigration current limit, MSD_D3R_D3R_PVAA, pad to VAA 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVAA_PLL, pad to MVAA_PLL 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVDD, pad to MVDD 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVSS, pad to MVSS 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVSS_PLL, pad to MVSS_PLL 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVDDQ, pad to MVDDQ 217 mA
EM
DC
Electromigration current limit, MSD_ D3R_PVSSQ, pad to MVSS 217 mA
EM
DC
Electromigration current limit, MSD_D3R_PPADCWI30 56 mA
EM
DC
Electromigration current limit, MSD_D3R_PPADCWO30 56 mA
SolvNet
DesignWare.com
The following sections provide details for the AC specifications of the SSTL I/Os.
10.16.4.1 DDR3 Mode
The following table provides AC characteristics for the I/O cell in mission mode (SJ=0, ET=0), using 60
ohms termination to VDDQ. The min, nom, and max values are simulated parameters across three
corners (fast, typical, and slow). The rate is an average value of rising and falling edges measured between
VILAC and VIHAC levels at input pin of emulated SDRAM, with 11 cm long. Ideal 60-ohm transmission
line interconnect between Driver and SDRAM. The output timing parameters are simulated using 40 fF load
when driving core logic and using calibrated output impedance Zout=34 ohms and termination calibrated
[ODT=60 ohms] when interfacing with SDRAM. The table shows the AC power of the I/O cell only, and it
does not include power of termination or power of current due to termination.
Table 10-59 DDR3 Mode (PDR=0)
V
IH(AC)
Input logic threshold High VREF + 175mV mV
V
IL(AC)
Input logic threshold Low VREF - 175mV mV
t
PDRV
Output delay 804.50 1292.00 ps
SR Output driver slew rate (at SDRAM pin) 3.34 3.69 V/ns
t
PVZ
Output tri-state delay - valid data to Z 818.50 1310.00 ps
t
PZV
Output tri-state delay - Z to valid data 782.00 1292.00 ps
t
PRCV
Input delay 436.15 671.90 ps
T
ODT_ON
TE-ON to ODT-ON delay 853.20 1479.00 ps
T
ODT_OFF
TE-OFF to ODT-OFF delay 757.70 1259.00 ps
C
IO
I/O capacitance (equivalent at VDDQ/2) 2.39 2.48 pF
F
MAX
Maximum operating frequency 800 MHz
D
MAX
Maximum operating data rate 1600 Mb/s
P
RCV
Input mode AC power (VDDQ rail) 0.78 0.92 uW/MHz
P
RCV
Input mode AC power (VDD rail) 0.14 0.17 uW/MHz
P
DRV
Output mode AC power (VDDQ rail) 9.00 10.92 uW/MHz
P
DRV
Output mode AC power (VDD rail) 0.52 0.66 uW/MHz
P
DRV
P
DRV
SolvNet
DesignWare.com
10.16.4.2 DDR3L Mode
The following table provides AC characteristics for the I/O cell using 60 ohms termination to 1/2VDDQ, in
mission mode (SJ=0, ET=00). The min, nom, and max values are simulated parameters across three corners
(fast, typical and slow). The output delay is specified using 40fF load in core logic. The slew rate is an
average value of rising and falling edges measured between VILAC and VIHAC levels at input pin of
emulated SDRAM. Ideal 60-ohm transmission line, 11cm long, used as interconnect between Driver and
SDRAM. The output timing parameters are simulated using calibrated output impedance Zout=34 ohms
and termination calibrated ODT=60 ohms. The table provides the AC power of the I/O cell only; it does not
include power of termination or power of current due to termination.
Table 10-61 DDR3L Mode (PDR=0)
V
IH(AC)
V
IL(AC)
t
PDRV
t
PVZ
t
PZV
T
ODT_ON
T
ODT_OFF
t
PRCV
C
IO
F
MAX
D
MAX
P
RCV
P
RCV
P
DRV
P
DRV
Table 10-62 DDR3L Mode (PDR=1)
P
DRV
P
DRV
SolvNet
DesignWare.com
10.16.4.3 DDR2 Mode
The following table below provides AC characteristics for the I/O cell using 75 ohms termination to
1/2VDDQ, in mission mode (SJ=0, ET=0). The min, nom, and max values are simulated parameters across 3
corners (fast, typical and slow). The output delay is specified using 40fF load in core logic. The slew rate is
an average value of rising and falling edges. Measured between VILAC and VIHAC levels at input pin of
emulated SDRAM. Ideal 60-ohm transmission line, 11cm long, used as interconnect between Driver and
SDRAM. The output timing parameters are simulated using calibrated output impedance Zout=18 ohms
and termination calibrated ODT=75 ohms. The table provides AC power of the I/O cell only; it does not
include power of termination or power of current due to termination.
V
IH(AC)
V
IL(AC)
t
PDRV
t
PVZ
t
PZV
T
ODT_ON
T
ODT_OFF
t
PRCV
C
IO
F
MAX
D
MAX
P
RCV
P
RCV
P
DRV
P
DRV
P
DRV
P
DRV
SolvNet
DesignWare.com
10.16.4.4 Mobile DDR Mode
The following table provides AC characteristics for the I/O cell using 5 pF load, in mission mode (SJ=0;
ET=0). The min, nom, and max values are simulated parameters across three corners (fast, typical, and
slow). The output delay is specified using 40fF load in core logic. The slew rate is an average value of rising
and falling edges. The output timing parameters are simulated using calibrated output impedance Zout=50
ohms and no-termination. The table provides AC power of the I/O cell only; it does not include power of
termination or power of current due to termination.
Table 10-65 Mobile DDR Mode (PDR=0)
t
PDRV
SR Output driver slew rate 2.47 3.02 V/ns
t
PRCV
F
MAX
D
MAX
P
RCV
P
RCV
P
DRV
P
DRV
Table 10-66 Mobile DDR Mode (PDR=1)
P
DRV
P
DRV
SolvNet
DesignWare.com
10.16.4.5 LPDDR2
The following table provides AC characteristics for the I/O cell using 5 pF load, in mission mode (SJ=0;
ET=0). The min, nom, and max values are simulated parameters across three corners (fast, typical, and
slow). The output delay is specified using 40fF load in core logic. The slew rate is an average value of rising
and falling edges. The output timing parameters are simulated using calibrated output impedance
Zout=40 ohms. The table provides AC power of the I/O cell only; it does not include power of termination
or power of current due to termination.
Table 10-67 LPDDR2 Mode (PDR=0)
V
IH_AC
Input logic threshold High VREF +
220mV
mV
V
IL_AC
Input logic threshold Low VREF -
220mV
mV
t
PDRV
Output delay 1075.5 1738 ps
SR Output driver slew rate 1.585 1.88 V/ns
t
PRCV
F
MAX
D
MAX
P
RCV
P
RCV
P
DRV
P
DRV
Table 10-68 LPDDR2 Mode (PDR=1)
P
DRV
P
DRV
SolvNet
DesignWare.com
10.16.5 Decoupling Capacitance
The following table provides extracted decoupling capacitance between the supply voltage rails and
reference voltage rails. The capacitance values are obtained using extraction tool; in the event of test silicon,
this parameter may not be measured.
Table 10-69
Cell
Decoupling [pF]
MVDDQ MVSSQ MVDD MVSS
MVREF
MVSSQ
MVREF
MVDDQ
MSD_D3R_PAIO 12.03 1.04 0.68 0.66
MSD_D3R_PCORNER 32.14 0.00 0.00 0.00
MSD_D3R_PDDRIO 0.37 0.00 0.00 0.00
MSD_D3R_PDIFF 0.37 0.00 0.00 0.00
MSD_D3R_PVAA 0.62 0.62 0.68 0.66
MSD_D3R_PVDD 1.57 0.62 0.58 0.57
MSD_D3R_PVDDQ 1.18 0.62 0.58 0.57
MSD_D3R_PVSS 12.96 0.62 0.68 0.66
MSD_D3R_PVSSQ 12.96 0.62 0.68 0.66
MSD_D3R_PVSSQZB 12.96 0.62 0.68 0.66
MSD_D3R_PVAA_PLL 1.57 0.62 0.00 0.00
MSD_D3R_PVSS_PLL 8.27 0.62 0.68 0.66
MSD_D3R_PVSSQ_RDIS 12.88 0.62 0.68 0.66
MSD_D3R_PDQSR 2.21 0.00 0.68 0.66
MSD_D3R_PDQSR_VSSQ 2.21 0.00 0.68 0.66
MSD_D3R_PRETLE 8.55 0.62 0.68 0.66
MSD_D3R_PRETLEX 8.55 0.62 0.68 0.66
MSD_D3R_PRETLEC 12.92 0.62 0.68 0.66
MSD_D3R_PPADCWI30_CUP 14.71 0.00 0.00 0.00
MSD_D3R_PPADCWO30_CUP 14.71 0.00 0.00 0.00
MSD_D3R_PPADCWI30_VDDQ 14.71 0.00 0.00 0.00
MSD_D3R_PPADCWO30_VDDQ 14.71 0.00 0.00 0.00
MSD_D3R_PPADCWI30_VSSQ 14.71 0.00 0.00 0.00
MSD_D3R_PPADCWO30_VSSQ 14.71 0.00 0.00 0.00
MSD_D3R_PPADCW30_FILL5 2.45 0.00 0.00 0.00
MSD_D3R_PSCAP_CUP 2.57 0.00 0.00 0.00
SolvNet
DesignWare.com
MSD_D3R_PSCAP_VDDQ 2.57 0.00 0.00 0.00
MSD_D3R_PSCAP_VSSQ 2.57 0.00 0.00 0.00
MSD_D3R_PSCAP_FILL5 0.42 0.00 0.00 0.00
MSD_D3R_PSCAP_PFILL5 0.01 0.00 0.00 0.00
MSD_D3R_PZQ 0.00 0.00 0.00 0.00
MSD_D3R_PVREF 0.00 0.00 0.00 0.00
Table 10-69
Cell
Decoupling [pF]
MVDDQ MVSSQ MVDD MVSS
MVREF
MVSSQ
MVREF
MVDDQ
SolvNet
DesignWare.com
10.16.6 ESD and LU Performance
10.16.6.1 Human Body Model
The following table lists the Human Body Model (HBM). This model is the most common mechanism for
characterizing an ESD event: The charged human body is modeled by a 100pF capacitor and a 1,500ohms
discharging resistance (MIL-STD-883G). The discharge itself is a double exponential waveform with a rise
time of 2-10ns and a pulse duration of approximately 150ns. (JESD625-A).
10.16.6.2 Machine Model
The following table lists the Machine Model (MM). This model simulates a more rapid electrostatic
discharge from a charged machine, fixture, or tool. The MM test circuit consists of a charged 200pF capacitor
that is discharged directly into the device being tested with zero ohms of series resistance.
10.16.6.3 Charged Device Model
The following table lists the Charged Device Model (CDM). This model is a specified circuit characterizing
an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or
electrostatic induction processes and then abruptly touches a grounded object or surface.
10.16.6.4 Latch Up
The following table lists the Latch-up. This model is a state in which a low-impedance path, resulting from
an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering
condition.
Table 10-70 Human body Model (HBM)
Voltage Level Category Standard
+/-2kV Class 2 JESD22-A114D
Table 10-71 Machine Model (MM)
+/-200V Class B JESD22-A115-A
Note Note Note Note
CDM is highly dependent on the device package type and packaging technology and results may vary
for each design.
Table 10-72 Charged Device Model (CDM)
+/-500V Class III JESD22-C101C
Table 10-73 Latch Up
Current Stress Temperature Category Standard
+/-200mA 125 deg C Class II / Level A JESD78A
SolvNet
DesignWare.com
10.17 Power-Up/Power-Down Sequence Requirements
There are no specific requirements for VDD and VDDQ power sequencing. The latch-up immunity of the
cells is not dependent on the power-up sequencing. The user should be aware that if the I/O (VDDQ) is
powered up before the core (VDD), there can be large current draws between these two events because the
I/O is powered-up but is not supplied with valid control signals, thus it can be in an undefined high-current
state. Conversely, if the core (VDD) is powered up before the I/O (VDDQ), the core may consume a slightly
higher current than normal due to not being supplied with valid CMOS level signals from the I/O, but this
will be a low additional current draw. It is generally recommended that the VDD and VDDQ supplies be
powered-up together, and it is generally also acceptable for the VDD supply to power-up a very short time
before the VDDQ supply. If the VDDQ supply must power-up before the VDD supply, it is advised to keep
the time between these two events less than 100ms to limit excessive VDDQ current draws.
SolvNet
DesignWare.com

DWC DDR MultiPHY Smic40ll25 DB

Uploaded by

Copyright:

Available Formats

DWC DDR MultiPHY Smic40ll25 DB

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DWC DDR MultiPHY Smic40ll25 DB

Uploaded by

Copyright:

Available Formats

What are the ESD models discussed in the document?

What are the power sequencing recommendations mentioned?

July 29, 2011

PHY Version: 1.00a

(25% of the clock cycle), generating delayed strobes dqs_90 and

196 Synopsys, Inc. July 29, 2011

You might also like