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Verilog Code For Decoder

The document provides a Verilog code and schematic diagram for a 2:4 decoder. The Verilog code defines a module with two inputs (a and b) and four outputs (y[3:0]). It uses NOT, AND gates to decode the inputs such that only one output is high based on the input values. The schematic diagram depicts the logic gate implementation of the 2:4 decoder.

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meaow88
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© Attribution Non-Commercial (BY-NC)
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3K views

Verilog Code For Decoder

The document provides a Verilog code and schematic diagram for a 2:4 decoder. The Verilog code defines a module with two inputs (a and b) and four outputs (y[3:0]). It uses NOT, AND gates to decode the inputs such that only one output is high based on the input values. The schematic diagram depicts the logic gate implementation of the 2:4 decoder.

Uploaded by

meaow88
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VERILOG CODE FOR 2:4DECODER

module deco1(y, a,b);

output [3:0] y;

input a,b;

not(a_bar,a),(b_bar,b);

and(y[0],a_bar,b_bar),(y[1],a_bar,b),(y[2],a,b_bar),(y[3],a,b);

endmodule

(a)

(b)

FIG SCHEMATIC DIAGRAM FOR 2:4DECODER


FIG SCHEMATIC DIAGRAM FOR 2:4DECODER

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