Digital Electronics

UNIT III
HALF ADDER
A key requirement of digital computers is the ability to use logical functions to perform
arithmetic operations. The basis of this is addition; if it is possible to add two binary
numbers, it is just as easily subtract them, or get a little fancier and perform multiplication
and diision. Then how to add two binary numbers!
"et#s start by adding two binary bits. $ince each bit has only two possible alues, % or
&, there are only four possible combinations of inputs. These four possibilities, and the
resulting sums, are'
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
The aboe fourth line indicates that we hae to account for two output bits when we
add two input bits' the sum and a possible carry. "et#s set this up as a truth table with two
inputs and two outputs,
INPUTS OUTPUTS
A B CARRY SUM
% % % %
% & % &
& % % &
& & & %
(rom the aboe table it is clear that, the )arry output is a simple A*D function, and
the $um is an E+clusie,-.. Thus, two gates can be used to add these two bits together.
The resulting circuit is shown below.
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1n a computer, it is ery much necessary to add multi,bit numbers together. 1f each
pair of bits can produce an output carry, it must also be able to recogni2e and include a carry
from the ne+t lower order of magnitude. This is the same requirement as adding decimal
numbers ,, if you hae a carry from one column to the ne+t; the ne+t column has to include
that carry. 3e hae to do the same thing with binary numbers, for the same reason. As a
result, the circuit to the left is known as a 4half adder,4 because it only does half of the job.
There is need a circuit that will do the entire job.
To construct a full adder circuit, we#ll need three inputs and two outputs. $ince we#ll
hae both an input carry and an output carry, we#ll designate them as )1* and )-0T. At the
same time, we#ll use $ to designate the final $um output. The resulting truth table is shown
below.
INPUTS OUTPUTS
A B CIN COUT S
% % % % %
% % & % &
% & % % &
% & & & %
& % % % &
& % & & %
& & % & %
& & & & &
This is looking a bit messy. 1t looks as if )-0T may be either an A*D or an -.
function, depending on the alue of A, and $ is either an 5-. or an 5*-., again
depending on the alue of A. "ooking a little more closely, howeer, we can note that the $
output is actually an 5-. between the A input and the half,adder $06 output with 7 and
)1* inputs. Also, the output carry will be true if any two or all three inputs are logic &.
3hat this suggests is also intuitiely logical' we can use two half,adder circuits. The
first will add A and 7 to produce a partial $um, while the second will add )1* to that $um to
produce the final $ output. 1f either half,adder produces a carry, there will be an output
carry. Thus, )-0T will be an -. function of the half,adder )arry outputs. The resulting full
adder circuit is shown below.
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Digital Electronics
The circuit aboe is really too complicated to be used in larger logic diagrams, so a
separate symbol, shown below, is used to represent a one,bit full adder. 1n fact, it is
common practice in logic diagrams to represent any comple+ function as a 4black bo+4 with
input and output signals designated. 1t is, after all, the logical function that is important, not
the e+act method of performing that function.
HALF SUBTRACTOR
3e hae seen how simple logic gates can perform the process of binary addition. 1t
is only logical to assume that a similar circuit could perform binary subtraction.
1f we look at the possibilities inoled in subtracting one &,bit number from another,
we can quickly see that three of the four possible combinations are easy and straight,
forward. The fourth one inoles a bit more'
% , % 8 %
& , % 8 &
& , & 8 %
% , & 8 &, with a borrow bit.
That borrow bit is just like a borrow in decimal subtraction' it subtracts from the
ne+t higher order of magnitude in the oerall number. "et#s see what the truth table looks
like.
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Digital Electronics
INPUTS OUTPUTS
A B BORROW A - B
% % % %
% & & &
& % % &
& & % %
This is an interesting result. The difference, A,7, is still an E+clusie,-. function, just
as the sum was for addition. The borrow is still an A*D function, but is A#7 instead of A7.
3hat we#d like to do, now, is find an easy way to use the binary adder to perform
subtraction as well. 3e already hae half of it working' the difference output. )an we simply
inert the A input so the A*D gate will hae the right signals! *o, we can#t, because that
would inert the sense of the E+clusie,-. function.
3hat would be really nice is to conert 7 to the negatie equialent of its alue, and
then use the basic adder just as it stands. To see if we can do that, let#s consider negatie
binary numbers below.
The half adder circuit can be designed as designed as follows,
As like as the normal subtraction it is possible to perform the subtraction between
three binary numbers. 1t is necessary since when multi,bit subtraction is going to be
performed the borrow will be transferred to the ne+t bit subtraction on some occasions. The
full subtractor circuit is show in the below figure.
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Digital Electronics
The input and output of the full subtractor is gien below as a truth table,
INPUTS OUTPUTS
A B BorrIN BorrOUT Diff
% % % % %
% % & % &
% & % % &
% & & & %
& % % % &
& % & & %
& & % & %
& & & & &
PARALLEL ADDER
*ow we can add two binary bits together, accounting for a possible carry from the ne+t
lower order of magnitude, and sending a carry to the ne+t higher order of magnitude. To perform
multi,bit addition the way a computer would, a full adder must be allocated for each bit to be
added simultaneously. Thus, to add two 9,bit numbers to produce a 9,bit sum :with a possible
carry;, you would need four full adders with carry lines cascaded, as shown below. (or two <,bit
numbers, you would need eight full adders, which can be formed by cascading two of these 9,bit
blocks. 7y e+tension, two binary numbers of any si2e may be added in this manner.
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Digital Electronics
1t is also quite possible to use this circuit for binary subtraction. 1f a negatie number is
applied to the B inputs, the resulting sum will actually be the difference between the two
numbers.
1n a modern computer, the adder circuitry will include the means of negating one of the
input numbers directly, so the circuit can perform either addition or subtraction on demand.
-ther functions are commonly included in modern implementations of the adder circuit,
especially in modern microprocessors.
4-BIT BINARY ADDER/SUBTRACTOR
*ow that we hae an easy way to obtain the negatie of any number, we can conert
our original 9,bit adder circuit to an adder=subtractor. 7y leaing the inputs unchanged, we
get the result of A > 7. 7ut if we inert 7 and add & with the low,order )in, we get the result
of A , 7.
3e can use E+clusie,-. gates, as shown below, to control whether we will add or
subtract on any gien occasion. 3ith a control input of %, the 5-. gates will leae the 7
input number unchanged, and will also apply a logic % as the initial input carry. This is
e+actly what we want in order to add the two numbers. ?oweer, if we apply a logic & to
the control input, the 5-. gates will inert the 7 input number to form its one#s
complement, and will also add & through the initial input carry. This changes 7 to its two#s
complement. Thus, the output result will actually be A , 7. :*ote that in two#s complement
addition, the output carry is ignored. @ou can also think of it as an inerted 4borrow4 bit
rather than as a carry, so that a carry of & corresponds to a borrow of %. That logic also holds
for the input carry, which also represents an input borrow bit of %.;
3hen we add or subtract signed numbers, we need to introduce a new concept'
overflow. -erflow occurs when the result has the wrong sign bit for the operation that was
performed. (or e+ample, if we add two positie numbers :A and B;, we should get a positie
result :&C;. ?oweer, using 9,bit binary numbers, we would add %&&& to %&&% and get &&%&
as the result. 1n signed notation, this is a result of ,C, not >&C. Therefore, an oerflow has
occurred, where the result would hae to hae more bits than the original two numbers.
This is not as much of a problem as you might think. An <,bit number can hae
signed alues in the range ,&D< to >&DA. A &B,bit signed number may hold any alue from
,CD,AB< to >CD,ABA. These ranges are sufficient for most practical applications. 3here they
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Digital Electronics
are not, modern computers can easily use CD,bit numbers :ED.&9 F &%
G
; or B9,bit numbers
:EG.DD F &%
&<
; for the purpose.
1f we add a positie number to a negatie number, oerflow cannot occur. "ikewise,
if we are subtracting two numbers of the same sign, oerflow is impossible. 7ut if we add
like,signed numbers or subtract unlike,signed numbers, we must be aware of the possibility
of oerflow, and recogni2e when it occurs.
6odern microprocessors are designed to recogni2e and report when oerflow occurs
in any arithmetic operation.
MULTIPLEXER
-ne circuit 1#e receied a number of requests for is the multiplexer circuit. This is a
digital circuit with multiple signal inputs, one of which is selected by separate address
inputs to be sent to the single output. 1t#s not easy to describe without the logic diagram, but
is easy to understand when the diagram is aailable.
The 9+& multiple+er circuit is shown in the below figure,
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The multiple+er circuit is typically used to combine two or more digital signals onto a
single line, by placing them there at different times. Technically, this is known as time-division
multiplexing.
1nput A is the addressing input, which controls which of the two data inputs, 5% or 5&,
will be transmitted to the output. 1f the A input switches back and forth at a frequency more
than double the frequency of either digital signal, both signals will be accurately reproduced,
and can be separated again by a Demultiplexer circuit synchroni2ed to the multiple+er.
This is not as difficult as it may seem at first glance; the telephone network combines
multiple audio signals onto a single pair of wires using e+actly this technique, and is readily
able to separate many telephone conersations so that eeryone#s oice goes only to the
intended recipient. 3ith the growth of the 1nternet and the 3orld 3ide 3eb, most people hae
heard about T& telephone lines. A T& line can transmit up to D9 indiidual telephone
conersations by multiple+ing them in this manner.
Hery common application for this type of circuit is found in computers, where dynamic
memory uses the same address lines for both row and column addressing. A set of multiple+ers is
used to first select the row address to the memory, then switch to the column address. This
scheme allows large amounts of memory to be incorporated into the computer while limiting the
number of copper traces required to connect that memory to the rest of the computer circuitry. 1n
such an application, this circuit is commonly called a data selector.
6ultiple+ers are not limited to two data inputs. 1f we use two addressing inputs, we can
multiple+ up to four data signals. 3ith three addressing inputs, we can multiple+ eight signals. 1f
you would like to see a demonstration of a four,input multiple+er.
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Digital Electronics
DEMULTIPLEXER/DECODER
The opposite of the multiple+er circuit, logically enough, is the demultiplexer. This
circuit takes a single data input and one or more address inputs, and selects which of multiple
outputs will receie the input signal. The same circuit can also be used as a decoder, by using the
address inputs as a binary number and producing an output signal on the single output that
matches the binary address input. 1n this application, the data input line functions as a circuit
enabler I if the circuit is disabled, no output will show actiity regardless of the binary input
number.
This circuit uses the same A*D gates and the same addressing scheme as the two,input
multiple+er circuit shown in these pages. The basic difference is that it is the inputs that are
combined and the outputs that are separate. 7y making this change, we get a circuit that is the
inerse of the two,input multiple+er. 1f you were to construct both circuits on a single
breadboard, connect the multiple+er output to the data 1* of the Demultiple+er, and drie the
Address inputs of both circuits with the same signal, you would find that the initial 5% input
would be transmitted to -0T% and the 5& input would reach only -0T&.
The one problem with this arrangement is that one of the two outputs will be inactie
while the other is actie. To retain the output signal, we need to add a latch circuit that can follow
the data signal while it#s actie, but will hold the last signal state while the other data signal is
actie. An e+cellent circuit for this is the D :or Data; "atch. 7y placing a latch after each output
and using the Addressing input :or its inerse; to control them, we can maintain both output
signals at all times. 1f the Address input changes much more rapidly than the data inputs, the
output signals will match the inputs faithfully.
A D,to,9 line decoder=Demultiple+er is shown below.
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"ike the multiple+er circuit, the decoder=Demultiple+er is not limited to a single address
line, and therefore can hae more than two outputs. 3ith two, three, or four addressing lines, this
circuit can decode a two, three, or four,bit binary number, or can Demultiple+er up to four, eight,
or si+teen time,multiple+ed signals.
As a decoder, this circuit takes an n,bit binary number and produces an output on one of
2
n
output lines. 1t is therefore commonly defined by the number of addressing input lines and the
number of data output lines. Typical decoder=Demultiple+er 1)s might contain two D,to,9 line
circuits, a C,to,< line circuit, or a 9,to,&B line circuit. -ne e+ception to the binary nature of this
circuit is the 9,to,&% line decoder=Demultiple+er, which is intended to conert a 7)D :7inary
)oded Decimal; input to an output in the %,G range.
1f you use this circuit as a Demultiple+er, you may want to add data latches at the outputs
to retain each signal while the others are being transmitted. ?oweer, this does not apply when
you are using this circuit as a decoder I then you will want only a single actie output to match
the input code.
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