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EES424 Study Unit 1

VHDL design notes

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Martin Roestorff
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77 views20 pages

EES424 Study Unit 1

VHDL design notes

Uploaded by

Martin Roestorff
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EES424 Specialisation Johan Schoeman 2012 7/24/12 (1)

Study Unit 1: Diital Desin Usin !"D# and $#Ds


%utcomes &o' the study unit

Discuss diital systems and thei' modelin(

Discuss the )a'ious le)els o& a*st'action usin the +,cha't(

Discuss the !"D#/$#D desin methodoloy(

Discuss the ad)antaes o& the !"D#/$#D desin


methodoloy(

Discuss the concepts o& !"D# &o' synthesis and !"D# &o'
simulation(
Study Unit 1: Diital Desin Usin !"D# and $#Ds
-hat is !"D# and .hy is it use&ul/

0n inte'national 1EEE standa'd speci&ication lanuae (1EEE


1072,1334) &o' desc'i*in diital ha'd.a'e used *y indust'y
.o'ld.ide

0c'onym &o' !"S15 (!e'y "ih Speed 1nte'ated 5i'cuit)


"a'd.a'e Desc'iption #anuae

Ena*le ha'd.a'e modelin &'om the ate to the system le)el

$'o)ides a mechanism &o' diital desin and 'eusa*le desin


documentation
EES424 Specialisation Johan Schoeman 2012 7/24/12 (2)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
"isto'ical o)e')ie.

Ea'ly 13607s 8 !"S15 p'o'am *y the U(S( DoD

!"D# o'iinated &'om !"S15

1369 8 U(S( DoD 'eleased !"D# &o' pu*lic use

1367 8 :odi&ied )e'sion is standa'di;ed 1EEE Std 1072,1367

1366 8 :ilStd494 'e<ui'ed that all 0S15s *e desc'i*ed in


!"D#

1EEE standa'd 1124 included sinal d'i)e st'enths

1EEE standa'd 1072(1 &o' analo/mi=ed,sinal e=tension

1EEE standa'd 1072(2 &o' 'eal/comple= data types

1EEE standa'd 1072(4 &o' sined/unsined types (a'ithmetic)

1334 8 Second issue o& 1EEE 1072 .ith &u'the' updates in


2000> 2002> 2002 and 2006

1337 8 1EEE std 1072(2,1333 &o' ?@# synthesis


EES424 Specialisation Johan Schoeman 2012 7/24/12 (4)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
Diital systems modelin

-hat is a diital system/

$'ocesses and sto'es data

"ie'a'chically composed system

-hat a'e the ad)antaes o& this systematic app'oach/

Desin independence o& components

Desin/in&o'mation simplicity

@he te'm model

%u' unde'standin o& a system

?ep'esents 'ele)ant in&o'mation and a*st'acts a.ay &'om


the i''ele)ant
EES424 Specialisation Johan Schoeman 2012 7/24/12 (4)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
0d)antaes o& modelin diital systems

5la'i&y use'7s 'e<ui'ements &o' the desin eninee'

5ommunicate unde'standin o& the system7s &unction to the


use'

0llo.s &o' testin and )e'i&ication o& a desin usin


simulation

0llo.s &o' automatic synthesis o& ci'cuits

0llo.s &o' &o'mal )e'i&ication 'e<ui'in a mathematical


statement desc'i*in the &unction o& the system
-e aim to achie)e ma=imum 'elia*ility &o' minimum cost and
desin time
EES424 Specialisation Johan Schoeman 2012 7/24/12 (9)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e)els and domains o& a*st'action
EES424 Specialisation Johan Schoeman 2012 7/24/12 (2)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e)els and domains o& a*st'action (e=ample)
5onside' a sinle,chip mic'ocont'olle' system used
as the cont'olle' &o' some measu'ement inst'ument>
.ith data input connections and some &o'm o&
display &o' the outputs( @he output is a scaled
)e'sion o& the input(
EES424 Specialisation Johan Schoeman 2012 7/24/12 (7)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
E=ample (cont()
0 possi*le &unctional/*eha)io'al desc'iption on an
alo'ithmic le)el could *e
EES424 Specialisation Johan Schoeman 2012 7/24/12 (6)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
E=ample (cont()
0 possi*le st'uctu'al desc'iption on a $'ocesso',
:emo'y,S.itch ($:S) le)el could *e
EES424 Specialisation Johan Schoeman 2012 7/24/12 (3)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
E=ample (cont()
0 possi*le eomet'ical desc'iption on the top le)el
could *e a silicon die &loo'plan
EES424 Specialisation Johan Schoeman 2012 7/24/12 (10)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
E=ample (cont()
Second le)el o& a*st'action
?eiste' @'ans&e' #anuae ?eiste' @'ans&e'
EES424 Specialisation Johan Schoeman 2012 7/24/12 (11)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
5omponent model o& a diital (su*)system desc'i*ed
*y !"D#
Generics
Ports
Entity
Architecture
(Dataflow)
Architecture
(Behavioral)
Architecture
(Structural)
Concurrent
Statements
Process
Sequential Statements
Concurrent
Statements
Package
EES424 Specialisation Johan Schoeman 2012 7/24/12 (12)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
!"D#/$#D desin methodoloy uses:

!"D# to desc'i*e systems and test*enches

So&t.a'e simulation tool

So&t.a'e synthesis tool

So&t.a'e place,and,'oute tool

$#D implementation

1n&o'mation in the con&iu'ation &ile to p'o'am the $#D


EES424 Specialisation Johan Schoeman 2012 7/24/12 (14)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
!"D#/$#D desin &lo.
EES424 Specialisation Johan Schoeman 2012 7/24/12 (14)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
0d)antaes o& the !"D#/$#D desin methodoloy

Ease the manaement o& comple= desins

0 sinle comp'ehensi)e desin lanuae

0 non,p'op'ieta'y lanuae

-ide selection o& tools

De)ice independent desin

?apid p'ototypin
EES424 Specialisation Johan Schoeman 2012 7/24/12 (19)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e=ical elements: Identifiers
They are used to name items

:ay only contain alpha*etic lette's (707 to 7A7 and 7a7 to 7;7)>
decimal diits (707 8 737) and the unde'line cha'acte' (7B7)

:ust sta't .ith an alpha*etic lette' ($o'tB1 )s 1B$o't )s B$o't)

:ay not end .ith an unde'line cha'acte' ($o'tB0 )s $o't0B)

:ay not include t.o successi)e unde'line cha'acte's ($o'tBB0)


Cote that !"D# is not case sensiti)e
EES424 Specialisation Johan Schoeman 2012 7/24/12 (12)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e=ical elements: Reserved words
Some identifiers that are reserved for special use
EES424 Specialisation Johan Schoeman 2012 7/24/12 (17)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e=ical elements: Special symbols
Reserved and special symbols

D E F 7 ( ) G H , > ( / : I J K L / M N O P Q

KL GG :K /K LK JK JL // /K //K /L /J /LK /JK JJ LL


#e=ical elements: Numbers
Real and integer literals exist

240> 49E4> 2E1101E

0(9> 9E,1> 6E0(4E> 4(141B932B2


EES424 Specialisation Johan Schoeman 2012 7/24/12 (16)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e=ical elements: Characters
Any printable character enclosed in single quotation marks

707> 7<7

7M7> 797
#e=ical elements: Strings
Any printable characters enclosed in double quotation marks

770 st'in .ith p'intin cha'acte's (e((> RSMFG)77

7777 ,, an empty st'in

770 st'in in a st'in: 77770 st'in7777( 77

771& a st'in is too lon> 77


F 77.e can split it into sepa'ate lines( 77
EES424 Specialisation Johan Schoeman 2012 7/24/12 (13)
Study Unit 1: Diital Desin Usin !"D# and $#Ds
#e=ical elements: Bit Strings
A string of bits

T &o' *ina'y

% &o' octal (*ase 6)

D &o' decimal (*ase 10)

U &o' he=adecimal (*ase 12)


Examples:

T77010001177

%7747277 ,, e<ui)alent to T77011B111B01077

D772477 ,, e<ui)alent to T771011177

U7704,,77 ,, e<ui)alent to T7710100011,,,,,,,,77 .ith don7t ca'es


EES424 Specialisation Johan Schoeman 2012 7/24/12 (20)

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