You can read the recommendations in the user guide, the technical guide or the installation guide for

MATLAB FILTER DESIGN

HDL CODER 2. You'll find the answers to all your questions on the MATLAB FILTER DESIGN HDL CODER 2 in the user
manual (information, specifications, safety advice, size, accessories, etc.). Detailed instructions for use are in the User's Guide.
User manual MATLAB FILTER DESIGN HDL CODER 2
User guide MATLAB FILTER DESIGN HDL CODER 2
Operating instructions MATLAB FILTER DESIGN HDL CODER 2
Instructions for use MATLAB FILTER DESIGN HDL CODER 2
Instruction manual MATLAB FILTER DESIGN HDL CODER 2
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Manual abstract:
com/contact_TS.html Technical Support www.mathworks.com comp.soft-sys.matlab [email protected] [email protected] [email protected]
[email protected] info@mathworks.
com Product enhancement suggestions Bug reports Documentation error reports Order status, license renewals, passcodes Sales, pricing, and general
information 508-647-7000 (Phone) 508-647-7001 (Fax) The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098 For contact information about
worldwide offices, see the MathWorks Web site. Filter Design HDL CoderTM User's Guide COPYRIGHT 20042010 by The MathWorks, Inc. The software
described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement.
No part of this manual may be photocopied or reproduced in any form without prior written consent from The MathWorks, Inc. FEDERAL ACQUISITION:
This provision applies to all acquisitions of the Program and Documentation by, for, or through the federal government of the United States. By accepting
delivery of the Program or Documentation, the government hereby agrees that this software or documentation qualifies as commercial computer software or
commercial computer software documentation as such terms are used or defined in FAR 12.212, DFARS Part 227.72, and DFARS 252.
227-7014. Accordingly, the terms and conditions of this Agreement and only those rights specified in this Agreement, shall pertain to and govern the use,
modification, reproduction, release, performance, display, and disclosure of the Program and Documentation by the federal government (or other entity
acquiring for or through the federal government) and shall supersede any conflicting contractual terms or conditions. If this License fails to meet the
government's needs or is inconsistent in any respect with federal procurement law, the government agrees to return the Program and Documentation, unused,
to The MathWorks, Inc. Trademarks MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See www.mathworks.com/trademarks for a list
of additional trademarks. Other product or brand names may be trademarks or registered trademarks of their respective holders. Patents The MathWorks
products are protected by one or more U.S.
patents. Please see www.mathworks.com/patents for more information. Revision History June 2004 October 2004 March 2005 September 2005 March 2006
September 2006 March 2007 September 2007 March 2008 October 2008 March 2009 September 2009 March 2010 Online only Online only Online only
Online only Online only Online only Online only Online only Online only Online only Online only Online only Online only New for Version 1.0 (Release 14)
Updated for Version 1.1 (Release 14SP1) Updated for Version 1.2 (Release 14SP2) Updated for Version 1.3 (Release 14SP3) Updated for Version 1.4
(Release 2006a) Updated for Version 1.
5 (Release 2006b) Updated for Version 2.0 (Release 2007a) Revised for Version 2.1 (Release 2007b) Revised for Version 2.2 (Release 2008a) Revised for
Version 2.3 (Release 2008b) Revised for Version 2.
4 (Release 2009a) Revised for Version 2.5 (Release 2009b) Revised for Version 2.6 (Release 2010a) Contents Getting Started 1 Product Overview .
Automated HDL Code Generation Expected Users . Key Features and Components Generate HDL Dialog Box -- the GUI .
Command-Line Interface . Quantized Filters -- the Input . Filter Properties -- Input Parameters . Generated HDL Files -- the Output Installation . Checking
Product Requirements . Installing the Software . Getting Help Information Overview Online Help Using "What's This?" Context-Sensitive Help . Demos and
Tutorials . Applying HDL Code Generation to the Hardware Design Process 1-2 1-2 1-3 1-3 1-5 1-6 1-7 1-9 1-10 1-11 1-11 1-11 1-12 1-12 1-13 1-13 1-14
1-15 Tutorials: Generating HDL Code for Filters 2 Creating a Folder for Your Tutorial Files Basic FIR Filter Tutorial .
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Designing a Basic FIR Filter in FDATool 2-2 2-3 2-3 v Quantizing the Basic FIR Filter Configuring and Generating the Basic FIR Filter's VHDL Code
Getting Familiar with the Basic FIR Filter's Generated VHDL Code Verifying the Basic FIR Filter's Generated VHDL Code Optimized FIR Filter Tutorial
Designing the FIR Filter in FDATool .
Quantizing the FIR Filter . Configuring and Generating the FIR Filter's Optimized Verilog Code . Getting Familiar with the FIR Filter's Optimized
Generated Verilog Code . Verifying the FIR Filter's Optimized Generated Verilog Code IIR Filter Tutorial . Designing an IIR Filter in FDATool Quantizing
the IIR Filter . Configuring and Generating the IIR Filter's VHDL Code Getting Familiar with the IIR Filter's Generated VHDL Code Verifying the IIR
Filter's Generated VHDL Code 2-5 2-8 2-16 2-18 2-24 2-24 2-26 2-29 2-39 2-41 2-48 2-48 2-50 2-54 2-60 2-62 Generating HDL Code for a Filter Design 3
Overview of Generating HDL Code for a Filter Design Opening the Generate HDL Dialog Box Opening the Generate HDL Dialog Box from FDATool .
Opening the Generate HDL Dialog Box from the filterbuilder GUI Opening the Generate HDL Dialog Box Using the fdhdltool Command . 3-2 3-4 3-4 3-9
3-11 vi Contents What Is Generated by Default? Default Settings for Generated Files Default Generation of Script Files Default Settings for Register Resets
Default Settings for General HDL Code . Default Settings for Code Optimizations . Default Settings for Test Benches What Are Your HDL Requirements? .
Setting the Target Language Setting the Names and Location for Generated HDL Files Default File Names and Locations Setting Filter Entity and General
File Naming Strings . Setting the Location of Generated Files . Setting the Postfix String for VHDL Package Files Splitting Entity and Architecture Code into
Separate Files Customizing Reset Specifications . Setting the Reset Type for Registers Setting the Asserted Level for the Reset Input Signal Suppressing
Generation of Reset Logic Customizing the HDL Code . Specifying a Header Comment .
Specifying a Prefix for Filter Coefficients Setting the Postfix String for Resolving Entity or Module Name Conflicts . Setting the Postfix String for Resolving
HDL Reserved Word Conflicts Setting the Postfix String for Process Block Labels Setting a Prefix for Component Instance Names Setting a Prefix for Vector
Names Naming HDL Ports Specifying the HDL Data Type for Data Ports Suppressing Extra Input and Output Registers . Representing Constants with
Aggregates Unrolling and Removing VHDL Loops Using the VHDL rising_edge Function 3-14 3-14 3-15 3-15 3-15 3-17 3-17 3-19 3-25 3-26 3-26 3-27 3-29
3-30 3-31 3-33 3-33 3-34 3-35 3-37 3-38 3-39 3-41 3-42 3-45 3-47 3-48 3-49 3-50 3-52 3-53 3-54 3-55 vii Suppressing the Generation of VHDL Inline
Configurations Specifying VHDL Syntax for Concatenated Zeros . Suppressing Verilog Time Scale Directives . Specifying Input Type Treatment for Addition
and Subtraction Operations Using Complex Data and Coefficients .
Specifying Programmable Filter Coefficients for FIR Filters Specifying Programmable Filter Coefficients for IIR Filters Capturing Code Generation Settings
to a Script Generating Code for Multirate Filters . Supported Multirate Filter Types Generating Multirate Filter Code Code Generation Options for Multirate
Filters Generating Code for Cascade Filters Supported Cascade Filter Types .
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Generating Cascade Filter Code . Generating Code for Polyphase Sample Rate Converters Overview HDL Implementation for Polyphase Sample Rate
Converter Generating Code for Multirate Farrow Sample Rate Converters Overview Generating Code for mfilt.farrowsrc Filters at the Command Line
Generating Code for mfilt.farrowsrc Filters in the GUI . Generating Code for Single-Rate Farrow Filters Overview Code Generation Properties for Farrow
Filters GUI Options for Farrow Filters Farrow Filter Code Generation Mechanics . 3-57 3-58 3-59 3-60 3-62 3-64 3-77 3-85 3-86 3-86 3-86 3-87 3-93 3-93
3-93 3-97 3-97 3-97 3-101 3-101 3-101 3-103 3-105 3-105 3-105 3-107 3-110 viii Contents Customizing the Test Bench Renaming the Test Bench . Specifying
a Test Bench Type Splitting Test Bench Code and Data into Separate Files Configuring the Clock Configuring Resets Setting a Hold Time for Data Input
Signals Setting an Error Margin for Optimized Filter Code Setting an Initial Value for Test Bench Inputs Setting Test Bench Stimuli . Setting a Postfix for
Reference Signal Names .
Generating HDL Cosimulation Blocks for Use with HDL Simulators . Generating a Simulink Model for Cosimulation with an HDL Simulator . 3-112 3-112
3-114 3-115 3-117 3-119 3-122 3-125 3-126 3-127 3-129 3-130 3-133 Generating the HDL Code 3-142 Generating Scripts for EDA Tools . Overview
Defaults for Script Generation . Custom Script Generation Properties for Controlling Script Generation . Controlling Script Generation with the EDA Tool
Scripts Dialog Box . Mixed-Language Scripts 3-143 3-143 3-143 3-144 3-145 3-148 3-157 Optimizing Generated HDL Code 4 Setting Optimizations
Optimizing Generated Code for HDL Optimizing Coefficient Multipliers Multiplier Input and Output Pipelining for FIR Filters 4-2 4-3 4-4 4-6 ix Optimizing
Final Summation for FIR Filters . Speed vs. Area Optimizations for FIR Filters . Overview of Speed vs.
Area Optimizations . Parallel and Serial Architectures . Specifying Speed vs. Area Tradeoffs via generatehdl Properties . Selecting Parallel and Serial
Architectures in the Generate HDL Dialog Box Distributed Arithmetic for FIR Filters .
Distributed Arithmetic Overview . Requirements and Considerations for Generating Distributed Arithmetic Code DALUTPartition Property DARadix
Property . Special Cases . Distributed Arithmetic Options in the Generate HDL Dialog Box . Optimizing the Clock Rate with Pipeline Registers .
Setting Optimizations for Synthesis . 4-8 4-10 4-10 4-11 4-15 4-19 4-27 4-27 4-29 4-30 4-34 4-34 4-35 4-40 4-42 Testing a Filter Design 5 Testing with an
HDL Test Bench Overview Generating the Filter and Test Bench HDL Code Starting the Simulator . Compiling the Generated Filter and Test Bench Files
Running the Test Bench Simulation 5-2 5-2 5-3 5-6 5-7 5-8 x Contents Property Reference 6 Language Selection Properties . 6-2 6-2 6-2 6-3 6-4 6-5 6-6 6-7
6-9 File Naming and Location Properties Reset Properties . Header Comment and General Naming Properties Port Properties Advanced Coding Properties
Optimization Properties Test Bench Properties . . . Script Generation Properties . xi Properties -- Alphabetical List 7 Function Reference 8 Examples A
Tutorials Basic FIR Filter Tutorial .
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Optimized FIR Filter Tutorial A-2 A-2 A-2 A-2 A-3 IIR Filter Tutorial .
Speed vs. Area Optimizations for FIR Filters . Index xii Contents 1 Getting Started "Product Overview" on page 1-2 "Installation" on page 1-11 "Getting
Help" on page 1-12 "Applying HDL Code Generation to the Hardware Design Process" on page 1-15 1 Getting Started Product Overview In this section.
"Automated HDL Code Generation" on page 1-2 "Expected Users" on page 1-3 "Key Features and Components" on page 1-3 "Generate HDL Dialog Box --
the GUI" on page 1-5 "Command-Line Interface" on page 1-6 "Quantized Filters -- the Input" on page 1-7 "Filter Properties -- Input Parameters" on page
1-9 "Generated HDL Files -- the Output" on page 1-10 Automated HDL Code Generation Hardware description language (HDL) code generation accelerates
the development of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs and bridges the gap between system-
level design and hardware development. Traditionally, system designers and hardware developers use HDLs, such as very high speed integrated circuit
(VHSIC) hardware description language (VHDL) and Verilog, to develop hardware designs. Although HDLs provide a proven method for hardware design,
the task of coding filter designs, and hardware designs in general, is labor intensive and the use of these languages for algorithm and system-level design is
not optimal. Users of the Filter Design HDL CoderTM product can spend more time on fine-tuning algorithms and models through rapid prototyping and
experimentation and less time on HDL coding. Architects and designers can efficiently design, analyze, simulate, and transfer system designs to hardware
developers. In a typical use scenario, an architect or designer uses Filter Design ToolboxTM GUIs (FDATool or filterbuilder) to design a filter. Then, a
designer uses the Filter Design HDL Coder GUI or command-line interface to configure code generation options and generate a VHDL or Verilog
implementation of the design and a corresponding test bench.
The generated code adheres to a clean HDL coding style that enables architects and designers to quickly address 1-2 Product Overview customizations, as
needed. The test bench feature increases confidence in the correctness of the generated code and saves potential time spent on test bench implementation.
Expected Users The Filter Design HDL Coder software is a tool for system and hardware architects and designers who develop, optimize, and verify
hardware signal filters. These designers are experienced with VHDL or Verilog, but can benefit greatly from a tool that automates HDL code generation. The
Filter Design HDL Coder interface provides designers with efficient means for creating test signals and test benches that verify algorithms, validating models
against standard reference designs, and translate legacy HDL descriptions into system-level views.
Users are expected to have prerequisite knowledge in the following subject areas: Hardware design and system integration VHDL or Verilog HDL
simulators Users are also expected to have experience with the following products: MATLAB Filter Design Toolbox Key Features and Components Key
features of the Filter Design HDL Coder software include the following: Graphical user interface (GUI) accessible from Filter Design and Analysis Tool
(FDATool), filterbuilder, or MATLAB command line MATLAB command-line interface Support for the following discrete-time filter structures: - Finite
impulse response (FIR) Antisymmetric FIR 1-3 1 Getting Started - Transposed FIR Symmetric FIR Second-order section (SOS) infinite impulse response (IIR)
Direct Form I SOS IIR Direct Form I transposed SOS IIR Direct Form II SOS IIR Direct Form II transposed Discrete-Time Scalar Delay filter Farrow
(fractional delay) filter Cascaded Integrator Comb (CIC) interpolation Cascaded Integrator Comb (CIC) decimation Direct-Form Transposed FIR Polyphase
Decimator Direct-Form FIR Polyphase Interpolator Direct-Form FIR Polyphase Decimator FIR Hold Interpolator FIR Linear Interpolator Direct-Form FIR
Polyphase Sample Rate Converter Farrow sample rate converter Support for the following multirate filter structures: Support for cascade filters (multirate
and discrete-time) Generation of code that adheres to a clean HDL coding style Options for optimizing numeric results of generated HDL code Options
for specifying parallel, serial (fully, partly or cascade), or distributed arithmetic architectures for FIR filter realizations Options for controlling the contents
and style of the generated HDL code and test bench Test bench generation for validating the generated HDL filter code 1-4 Product Overview Test bench
optionally partitioned into code, data, and helper function files Complex coefficients and complex input signals supported for fully parallel FIR, CIC, and
some other filter structures Support for programmable coefficients for FIR and IIR filter coefficients VHDL and Verilog test bench options Automatic
generation of scripts for third-party simulation and synthesis tools Automatic generation of a script that captures all non-default GUI settings for HDL code
and test bench generation Automatic generation of HDL Cosimulation blocks for use with third-party HDL simulators Automatic generation of a Simulink
model that is configured for both Simulink simulation of your filter design, and cosimulation of your design with an HDL simulator Generate HDL Dialog Box
-- the GUI You access the Filter Design HDL Coder GUI from the FDATool Targets menu, the filterbuilder GUI, or the MATLAB command line.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Given that you have designed a filter object, you can generate HDL code for that filter with the Generate HDL dialog box. The main dialog box displays the
filter's structure and order in the title bar. The following figure indicates that the input is a Direct Form FIR filter with an order of 50. 1-5 1 Getting Started
To learn how to use the GUI to customize HDL code generation to meet project-specific requirements, see Chapter 3, "Generating HDL Code for a Filter
Design".
Command-Line Interface You also have the option of generating HDL code for a filter with the Filter Design HDL Coder command-line interface. You can
apply functions interactively at the MATLAB command line or programmatically in a MATLAB program. The following table lists available functions with
brief descriptions. For more detail, see Chapter 8, "Function Reference". 1-6 Product Overview Function generatehdl fdhdltool generatetb
generatetbstimulus Purpose Generate HDL code for quantized filter Open Generate HDL dialog box for quantized filter Generate test bench for quantized
filter Generate and return test bench stimuli Quantized Filters -- the Input The input to the coder is a quantized filter that you design and quantize using one
of the following products: Filter Design Toolbox Signal Processing ToolboxTM HDL code generation is supported for the following filter structures.
Discrete-time: - Finite impulse response (FIR) Antisymmetric FIR Transposed FIR Symmetric FIR Second-order section (SOS) infinite impulse response (IIR)
Direct Form I SOS IIR Direct Form I transposed SOS IIR Direct Form II SOS IIR Direct Form II transposed Discrete-Time Scalar Delay filter Farrow
(fractional delay) filter Cascaded Integrator Comb (CIC) interpolation Multirate: 1-7 1 Getting Started - Cascaded Integrator Comb (CIC) decimation
Direct-Form Transposed FIR Polyphase Decimator Direct-Form FIR Polyphase Interpolator Direct-Form FIR Polyphase Decimator FIR Hold Interpolator
FIR Linear Interpolator Direct-Form FIR Polyphase Sample Rate Converter Farrow sample rate converter Cascade filters (multirate and discrete-time)
Each of these structures (with the exception of the CIC filter structures) supports fixed-point and floating-point (double) realizations. The CIC filter types
support only fixed-point realizations. The FIR structures also support unsigned fixed-point coefficients. Note The coder does not support zero order filters,
both in FIR and IIR sections. The quantized filter must have the following data format characteristics: Fixed-point Double floating-point precision
However, use of complex input data and complex coefficients is supported for some filter types.
(See "Using Complex Data and Coefficients" on page 3-62.) When designing a filter for HDL code generation, consider how filter coefficients are specified. If
the coefficients for a filter are small in value and the word size and binary point are large, it is possible for the coder to compute integer coefficients that are
numerically inaccurate. Double-precision coefficients support up to 53 bits of precision. 1-8 Product Overview For information on how to design filter objects
and specify filter coefficients, see the documentation for the following products: Filter Design Toolbox Signal Processing Toolbox Filter Properties -- Input
Parameters The coder generates filter and test bench HDL code for a specified quantized filter based on the settings of a collection of property name and
property value pairs. The properties and their values Contribute to the naming of language elements Specify port parameters Determine the use of
advanced HDL coding features All properties have default settings. However, you can customize the HDL output to meet project specifications by adjusting
the property settings with the GUI or command-line interface. The GUI enables you to set properties associated with The HDL language specification File
name and location specifications Reset specifications HDL code customizations HDL code optimizations Test bench customizations Generation of script
files for third-party Electronic Design Automation (EDA) tools You can set the same filter properties by specifying property name and property value pairs
with the functions generatehdl, generatetb, and generatetbstimulus interactively at the MATLAB command line or in a MATLAB program.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
1-9 1 Getting Started The property names and property values are not case sensitive and, when specifying them, you can abbreviate them to the shortest
unique string. For lists and descriptions of the properties and functions, see Chapter 6, "Property Reference" and Chapter 8, "Function Reference",
respectively.
Generated HDL Files -- the Output Based on the options and input data you specify, the coder generates filter and filter test bench HDL files as output. If the
filter design requires a VHDL package, the coder also generates a package file. The GUI generates all output files at the end of a dialog session. If you
choose to use the command-line interface, you generate the filter and test bench HDL files separately with calls to the functions generatehdl and generatetb.
By default, the coder writes output files in a subfolder named hdlsrc, under the current working folder, and names the files as follows, where name is the value
of the Name property.
Language Verilog VHDL File Filter Filter test bench Filter Filter test bench Filter package (if required) Name name.v name_tb.v name.vhd name_tb.vhd
name_pkg.
vhd 1-10 Installation Installation In this section. "Checking Product Requirements" on page 1-11 "Installing the Software" on page 1-11 Checking Product
Requirements The coder requires the following software from The MathWorksTM: MATLAB Fixed-Point ToolboxTM Signal Processing Toolbox Filter
Design Toolbox VHDL and Verilog Language Support The coder generates code that is compatible with HDL compilers, simulators and other tools that
support VHDL versions 87, 93, and 02. Exception: VHDL test benches using double precision data types do not support VHDL version 87. (See also
"Compiling the Generated Filter and Test Bench Files" on page 5-7.) Verilog-2001 (IEEE 1364-2001) or later. Installing the Software For information on
installing the required software listed above, and optional software, see the Installation Guide for your platform. 1-11 1 Getting Started Getting Help In this
section. "Information Overview" on page 1-12 "Online Help" on page 1-13 "Using "What's This?" Context-Sensitive Help" on page 1-13 "Demos and
Tutorials" on page 1-14 Information Overview The following information is available with this product: Chapter 1, "Getting Started" Explains what the
product is, how to install it, its applications in the hardware design process, and how to access product documentation and online help. Guides you through
the process of generating HDL code for a sampling of filters. Explains how to set code generation options and generate HDL code for a filter design.
Explains options and techniques you can use to optimize generated HDL code for speed, area, latency, and other characteristics, and the tradeoffs involved in
the use of optimizations. Explains how to apply generated test benches. Lists filter properties by category. Chapter 2, "Tutorials: Generating HDL Code for
Filters" Chapter 3, "Generating HDL Code for a Filter Design" Chapter 4, "Optimizing Generated HDL Code" Chapter 5, "Testing a Filter Design" Chapter
6, "Property Reference" 1-12 Getting Help Chapter 7, "Properties -- Alphabetical List" Chapter 8, "Function Reference" Provides descriptions of properties
organized alphabetically by property name. Provides descriptions of the functions available in the product's command-line interface. Online Help The
following online help is available: Online help in the MATLAB Help browser. Click the Filter Design HDL Coder link in the browser's Contents pane.
Context-sensitive "What's This?" help for options that appear in the Filter Design HDL Coder GUI. Click a GUI Help button or right-click on a GUI option to
display help on that dialog, or item. For more information on using the context-sensitive help, see "Using "What's This?" Context-Sensitive Help" on page
1-13.
Help for the command-line interface functions generatehdl, generatetb, fdhdltool, and generatetbstimulus is accessible with the doc and help commands.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
For example: doc generatehdl help generatehdl Using "What's This?" Context-Sensitive Help "What's This?" context-sensitive help topic is available for each
dialog box, pane, and option in the GUI. Use the "What's This?" help as needed while using the GUI to configure options that control the contents and style of
the generated HDL code and test bench. To use the "What's This?" help, do the following: 1 Place your cursor over the label or control for an option or in the
background for a pane or dialog box. 1-13 1 Getting Started 2 Right-click.
A What's This? button appears. The following display shows the What's This? button appearing after a right-click on the Folder option in the Target pane of
the Generate HDL dialog box. 3 Click What's This? to view context-sensitive help that describes the option, or dialog box. Demos and Tutorials Demos and
tutorials provided with the product will help you get started. The demos give you a quick view of the product's capabilities and examples of how you might
apply the product.
You can run them with limited product exposure. The tutorials provide procedural instruction on how to apply product features. The following topics, in
Chapter 2, "Tutorials: Generating HDL Code for Filters", guide you through three tutorials: "Basic FIR Filter Tutorial" on page 2-3 "Optimized FIR Filter
Tutorial" on page 2-24 "IIR Filter Tutorial" on page 2-48 1-14 Applying HDL Code Generation to the Hardware Design Process Applying HDL Code
Generation to the Hardware Design Process The workflow for applying HDL code generation to the hardware design process requires the following steps: 1
Design a filter. 2 Quantize the filter. 3 Review the default property settings that the coder applies to generated HDL code. 4 Adjust property settings to
customize the generated HDL code, as necessary. 5 Generate the filter and test bench code. 6 Consider and, if appropriate, apply optimization options. 7 Test
the generated code in a simulation. 1-15 1 Getting Started The following figure shows these steps in a flow diagram.
Design filter Quantized? Yes Set HDL properties No HDL property defaults OK? Yes Generate HDL code for filter and test bench No Quantize filter
Optimize? No Simulate Yes Set optimization properties Done 1-16 2 Tutorials: Generating HDL Code for Filters "Creating a Folder for Your Tutorial Files"
on page 2-2 "Basic FIR Filter Tutorial" on page 2-3 "Optimized FIR Filter Tutorial" on page 2-24 "IIR Filter Tutorial" on page 2-48 2 Tutorials:
Generating HDL Code for Filters Creating a Folder for Your Tutorial Files Set up a writable working folder outside your MATLAB installation folder to store
files that will be generated as you complete your tutorial work. The tutorial instructions assume that you create the folder hdlfilter_tutorials on drive C. 2-2
Basic FIR Filter Tutorial Basic FIR Filter Tutorial In this section. "Designing a Basic FIR Filter in FDATool" on page 2-3 "Quantizing the Basic FIR Filter"
on page 2-5 "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8 "Getting Familiar with the Basic FIR Filter's Generated VHDL
Code" on page 2-16 "Verifying the Basic FIR Filter's Generated VHDL Code" on page 2-18 Designing a Basic FIR Filter in FDATool This tutorial guides
you through the steps for designing a basic quantized discrete-time FIR filter, generating VHDL code for the filter, and verifying the VHDL code with a
generated test bench. This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool). The following
instructions guide you through the procedure of designing and creating a basic FIR filter using FDATool: 1 Start the MATLAB software. 2 Set your current
folder to the folder you created in "Creating a Folder for Your Tutorial Files" on page 2-2. 2-3 2 Tutorials: Generating HDL Code for Filters 3 Start the
FDATool by entering the fdatool command in the MATLAB Command Window.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The Filter Design & Analysis Tool dialog box appears. 4 In the Filter Design & Analysis Tool dialog box, check that the following filter options are set: 2-4
Basic FIR Filter Tutorial Option Response Type Design Method Filter Order Options Frequency Specifications Value Lowpass FIR Equiripple Minimum
order Density Factor: 20 Units: Hz Fs: 48000 Fpass: 9600 Fstop: 12000 Magnitude Specifications Units: dB Apass: 1 Astop: 80 These settings are for the
default filter design that the FDATool creates for you.
If you do not need to make any changes and Design Filter is grayed out, you are done and can skip to "Quantizing the Basic FIR Filter" on page 2-5. 5 If you
modified any of the options listed in step 4, click Design Filter. The FDATool creates a filter for the specified design and displays the following message in the
FDATool status bar when the task is complete. Designing Filter. Done For more information on designing filters with the FDATool, see "Using FDATool with
Filter Design Toolbox Software" in the Filter Design Toolbox documentation.
Quantizing the Basic FIR Filter You should quantize filters for HDL code generation. To quantize your filter, 1 Open the basic FIR filter design you created
in "Designing a Basic FIR Filter in FDATool" on page 2-3 if it is not already open. 2-5 2 Tutorials: Generating HDL Code for Filters 2 Click the Set
Quantization Parameters button in the left-side toolbar. The FDATool displays a Filter arithmetic menu in the bottom half of its dialog box. 3 Select Fixed-
point from the Filter arithmetic list.
Then select Specify all from the Filter precision list. The FDATool displays the first of 2-6 Basic FIR Filter Tutorial three tabbed panels of quantization
parameters across the bottom half of its dialog box. You use the quantization options to test the effects of various settings with a goal of optimizing the
quantized filter's performance and accuracy. 4 Set the quantization parameters as follows: 2-7 2 Tutorials: Generating HDL Code for Filters Tab Coefficients
Parameter Numerator word length Best-precision fraction lengths Use unsigned representation Scale the numerator coefficients to fully utilize the entire
dynamic range Setting 16 Selected Cleared Cleared Input/Output Input word length Input fraction length Output word length 16 15 16 Floor Saturate 40
Filter Internals Rounding mode Overflow mode Accum. word length 5 Click Apply. For more information on quantizing filters with the FDATool, see "Using
FDATool with Filter Design Toolbox Software" in the Filter Design Toolbox documentation. Configuring and Generating the Basic FIR Filter's VHDL Code
After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This section guides you through the procedure
for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the basic FIR filter you designed
and quantized in "Designing a Basic FIR Filter in FDATool" on page 2-3 and "Quantizing the Basic FIR Filter" on page 2-5. 1 Start the Filter Design HDL
Coder GUI by selecting Targets ] Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.
2-8 Basic FIR Filter Tutorial 2 Find the Filter Design HDL Coder online help. Use the online help to learn about product details or to get answers to
questions as you work with the designer. a In the MATLAB window, click the Help button in the toolbar or click Help ] Product Help. b In the Help browser's
Contents pane, select the Filter Design HDL Coder entry. c Minimize the Help browser. 3 In the Generate HDL dialog box, click the Help button. A small
context-sensitive help window opens. The window displays information about the dialog box. 2-9 2 Tutorials: Generating HDL Code for Filters 4 Close the
Help window. 5 Place your cursor over the Folder label or text box in the Target pane of the Generate HDL dialog box, and right-click.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
A What's This? button appears. 6 Click What's This? The context-sensitive help window displays information describing the Folder option. Use the context-
sensitive help as needed while using the GUI to configure the contents and style of the generated HDL code. A help topic is available for each option. 7 In the
Name text box of the Target pane, replace the default name with basicfir.
This option names the VHDL entity and the file that is to contain the filter's VHDL code. 8 Select the Global settings tab of the GUI. Then select the General
tab of the Additional settings section of the GUI. Type Tutorial - Basic FIR Filter in the Comment in header text box. The coder adds the comment to the end
of the header comment block in each generated file.
2-10 Basic FIR Filter Tutorial 9 Select the Ports tab of the Additional settings section of the GUI. 2-11 2 Tutorials: Generating HDL Code for Filters 10
Change the names of the input and output ports. In the Input port text box, replace filter_in with data_in. In the Output port text box, replace filter_out with
data_out. 11 Clear the check box for the Add input register option. The Ports pane should now look like the following. 2-12 Basic FIR Filter Tutorial 12 Click
on the Test Bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with basicfir_tb. This option names the generated
test bench file. 2-13 2 Tutorials: Generating HDL Code for Filters 13 Click Generate to start the code generation process.
The coder displays messages in the MATLAB Command Window as it generates the filter and test bench VHDL files: ### Starting VHDL code generation
process for filter: basicfir ### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd ### Starting generation of basicfir VHDL entity ### Starting generation
of basicfir VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: basicfir ### Starting
generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3429 samples. ### Generating Test bench:
C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd ### Please wait . 2-14 Basic FIR Filter Tutorial ### Done generating VHDL Test Bench ]] As the messages
indicate, the coder creates the folder hdlsrc under your current working folder and places the files basicfir.vhd and basicfir_tb.vhd in that folder. Observe that
the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the
MATLAB Editor. The generated VHDL code has the following characteristics: VHDL entity named basicfir.
Registers that use asynchronous resets when the reset signal is active high (1). Ports have the following names: VHDL Port Input Output Clock input Clock
enable input Reset input Name data_in data_out clk clk_enable reset An extra register for handling filter output. Clock input, clock enable input and reset
ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR. Coefficients are named coeffn, where n is the coefficient
number, starting with 1. Type safe representation is used when zeros are concatenated: '0' & '0'.
Registers are generated with the statement ELSIF clk'event AND clk='1' THEN rather than with the rising_edge function. 2-15 2 Tutorials: Generating HDL
Code for Filters The postfix string _process is appended to process names. The generated test bench: Is a portable VHDL file. Forces clock, clock enable,
and reset input signals. Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds. Forces the reset signal for two cycles plus a hold time of 2
nanoseconds. Applies a hold time of 2 nanoseconds to data input signals. For a FIR filter, applies impulse, step, ramp, chirp, and white noise stimulus
types.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
14 When you have finished generating code, click Close to close the Generate HDL dialog box. Getting Familiar with the Basic FIR Filter's Generated
VHDL Code Get familiar with the filter's generated VHDL code by opening and browsing through the file basicfir.vhd in an ASCII or HDL simulator editor:
1 Open the generated VHDL filter file basicfir.vhd. 2 Search for basicfir. This line identifies the VHDL module, using the string you specified for the Name
option in the Target pane.
See step 5 in "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8. 3 Search for Tutorial. This is where the coder places the text you
entered for the Comment in header option. See step 10 in "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8. 4 Search for HDL
Code. This section lists coder options you modified in "Configuring and Generating the FIR Filter's Optimized Verilog Code" on page 2-29. 2-16 Basic FIR
Filter Tutorial 5 Search for Filter Settings. This section describes the filter design and quantization settings as you specified in "Designing a Basic FIR Filter
in FDATool" on page 2-3 and "Quantizing the Basic FIR Filter" on page 2-5. 6 Search for ENTITY. This line names the VHDL entity, using the string you
specified for the Name option in the Target pane.
See step 5 in "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8. 7 Search for PORT. This PORT declaration defines the filter's
clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, and reset signals are named with default strings. The ports for
data input and output are named with the strings you specified for the Input port and Output port options on the Ports tab of the Generate HDLdialog box.
See step 12 in "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8. 8 Search for Constants. This is where the coefficients are
defined. They are named using the default naming scheme,coeffn, where n is the coefficient number, starting with 1. 9 Search for Signals.
This is where the filter's signals are defined. 10 Search for process. The PROCESS block name Delay_Pipeline_process includes the default PROCESS block
postfix string _process. 11 Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the
PROCESS block applies the default asynchronous reset style when generating VHDL code for registers. 12 Search for ELSIF. This is where the VHDL code
checks for rising edges when the filter operates on registers. The default ELSIF clk'event statement is used instead of the optional rising_edge function.
13 Search for Output_Register. This is where filter output is written to an output register. Code for this register is generated by default. In step 13 in
"Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8, you cleared the Add input register option, but left the Add output register
selected. Also note that the PROCESS block name Output_Register_process includes the default PROCESS block postfix string _process. 2-17 2 Tutorials:
Generating HDL Code for Filters 14 Search for data_out. This is where the filter writes its output data. Verifying the Basic FIR Filter's Generated VHDL
Code This section explains how to verify the basic FIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses the
Mentor Graphics ModelSim software as the tool for compiling and simulating the VHDL code, you can use any VHDL simulation tool package. To verify
the filter code, complete the following steps: 1 Start your simulator.
When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears. 2 Set the current folder to the folder that contains
your generated VHDL files. For example: cd c:/hdlfilter_tutorials/hdlsrc 3 If necessary, create a design library to store the compiled VHDL entities,
packages, architectures, and configurations.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
In the Mentor Graphics ModelSim simulator, you can create a design library with the vlib command. vlib work 2-18 Basic FIR Filter Tutorial 4 Compile the
generated filter and test bench VHDL files.
In the Mentor Graphics ModelSim simulator, you compile VHDL code with the vcom command. The following commands compile the filter and filter test
bench VHDL code. vcom basicfir.vhd vcom basicfir_tb.vhd The following screen display shows this command sequence and informational messages displayed
during compilation.
5 Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim
simulator, you load the test bench for simulation with the vsim command. For example: vsim work.basicfir_tb 2-19 2 Tutorials: Generating HDL Code for
Filters The following figure shows the results of loading work.basicfir_tb with the vsim command. 6 Open a display window for monitoring the simulation as
the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you can use the following command to open a wave window to view the results
of the simulation as HDL waveforms: add wave * 2-20 Basic FIR Filter Tutorial The following wave window displays. 7 To start running the simulation, issue
the appropriate command for your simulator. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run command.
2-21 2 Tutorials: Generating HDL Code for Filters The following display shows the run -all command being used to start a simulation. As your test bench
simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code
generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter
VHDL code. Note The failure message that appears in the preceding display is not flagging an actual error. If the message includes the string Test Complete,
the test bench has successfully run to completion. The Failure part of the message is tied to the mechanism that the coder uses to end the simulation. 2-22
Basic FIR Filter Tutorial The following wave window shows the simulation results as HDL waveforms. 2-23 2 Tutorials: Generating HDL Code for Filters
Optimized FIR Filter Tutorial In this section. "Designing the FIR Filter in FDATool" on page 2-24 "Quantizing the FIR Filter" on page 2-26 "Configuring
and Generating the FIR Filter's Optimized Verilog Code" on page 2-29 "Getting Familiar with the FIR Filter's Optimized Generated Verilog Code" on page
2-39 "Verifying the FIR Filter's Optimized Generated Verilog Code" on page 2-41 Designing the FIR Filter in FDATool This tutorial guides you through the
steps for designing an optimized quantized discrete-time FIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test
bench.
This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool). 1 Start the MATLAB software. 2 Set
your current folder to the folder you created in "Creating a Folder for Your Tutorial Files" on page 2-2. 2-24 Optimized FIR Filter Tutorial 3 Start the
FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.
4 In the Filter Design & Analysis Tool dialog box, set the following filter options: 2-25 2 Tutorials: Generating HDL Code for Filters Option Response Type
Design Method Filter Order Options Frequency Specifications Value Lowpass FIR Equiripple Minimum order Density Factor: 20 Units: Hz Fs: 48000
Fpass: 9600 Fstop: 12000 Magnitude Specifications Units: dB Apass: 1 Astop: 80 These settings are for the default filter design that the FDATool creates for
you. If you do not need to make any changes and Design Filter is grayed out, you are done and can skip to "Quantizing the FIR Filter" on page 2-26.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
5 Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is
complete.
Designing Filter. Done For more information on designing filters with the FDATool, see "Using FDATool with Filter Design Toolbox Software" in the Filter
Design Toolbox documentation. Quantizing the FIR Filter You should quantize filters for HDL code generation. To quantize your filter, 1 Open the FIR filter
design you created in "Optimized FIR Filter Tutorial" on page 2-24 if it is not already open. 2-26 Optimized FIR Filter Tutorial 2 Click the Set Quantization
Parameters button in the left-side toolbar. The FDATool displays a Filter arithmetic menu in the bottom half of its dialog box. 2-27 2 Tutorials: Generating
HDL Code for Filters 3 Select Fixed-point from the list. Then select Specify all from the Filter precision list. The FDATool displays the first of three tabbed
panels of quantization parameters across the bottom half of its dialog box. You use the quantization options to test the effects of various settings with a goal of
optimizing the quantized filter's performance and accuracy.
4 Set the quantization parameters as follows: 2-28 Optimized FIR Filter Tutorial Tab Coefficients Parameter Numerator word length Setting 16 Best-
precision fraction lengths Use unsigned representation Scale the numerator coefficients to fully utilize the entire dynamic range Input/Output Input word
length Input fraction length Output word length Filter Internals Rounding mode Overflow mode Accum. word length 5 Click Apply. Selected Cleared Cleared
16 15 16 Floor Saturate 40 For more information on quantizing filters with the FDATool, see "Using FDATool with Filter Design Toolbox Software" in the
Filter Design Toolbox documentation. Configuring and Generating the FIR Filter's Optimized Verilog Code After you quantize your filter, you are ready to
configure coder options and generate the filter's Verilog code. This section guides you through the process for starting the GUI, setting some options, and
generating the Verilog code and a test bench for the FIR filter you designed and quantized in "Designing the FIR Filter in FDATool" on page 2-24 and
"Quantizing the FIR Filter" on page 2-26. 2-29 2 Tutorials: Generating HDL Code for Filters 1 Start the Filter Design HDL Coder GUI by selecting Targets
] Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box. 2 Select Verilog for the Language option, as shown in the
following figure. 2-30 Optimized FIR Filter Tutorial 3 In the Name text box of the Target pane, replace the default name with optfir. This option names the
Verilog module and the file that is to contain the filter's Verilog code.
4 In the Filter architecture pane, select the Optimize for HDL option. This option is for generating HDL code that is optimized for performance or space
requirements. When this option is enabled, the coder makes tradeoffs concerning data types and might ignore your quantization settings to achieve
optimizations. When you use the option, keep in mind that you do so at the cost of potential numeric differences between filter results produced by the original
filter object and the simulated results for the optimized HDL code. 5 Select CSD for the Coefficient multipliers option.
This option optimizes coefficient multiplier operations by instructing the coder to replace them with additions of partial products produced by a canonic
signed digit (CSD) technique. This technique minimizes the number of addition operations required for constant multiplication by representing binary
numbers with a minimum count of nonzero digits. 6 Select the Add pipeline registers option. For FIR filters, this option optimizes final summation. The coder
creates a final adder that performs pair-wise addition on successive products and includes a stage of pipeline registers after each level of the tree.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
When used for FIR filters, this option also has the potential for producing numeric differences between results produced by the original filter object and the
simulated results for the optimized HDL code. 7 The Generate HDL dialog box should now appear as shown in the following figure. 2-31 2 Tutorials:
Generating HDL Code for Filters 8 Select the Global settings tab of the GUI. Then select the General tab of the Additional settings section. In the Comment in
header text box, type Tutorial - Optimized FIR Filter. The coder adds the comment to the end of the header comment block in each generated file. 2-32
Optimized FIR Filter Tutorial 9 Select the Ports tab of the Additional settings section of the GUI. 2-33 2 Tutorials: Generating HDL Code for Filters 10
Change the names of the input and output ports. In the Input port text box, replace filter_in with data_in. In the Output port text box, replace filter_out with
data_out.
2-34 Optimized FIR Filter Tutorial 11 Clear the check box for the Add input register option. The Ports pane should now look like the following. 12 Click on
the Test Bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with optfir_tb. This option names the generated test
bench file. 2-35 2 Tutorials: Generating HDL Code for Filters 13 In the Test Bench pane, click the Configuration tab. Observe that the Error margin (bits)
option is enabled. This option is enabled because previously selected optimization options (such as Add pipeline registers) can potentially produce numeric
results that differ from the results produced by the original filter object. You can use this option to adjust the number of least significant bits the test bench
will ignore during comparisons before generating a warning. 2-36 Optimized FIR Filter Tutorial 14 In the Generate HDL dialog box, click Generate to start
the code generation process.
When code generation completes, click Close to close the dialog box. The coder displays the following messages in the MATLAB Command Window as it
generates the filter and test bench Verilog files: ### Starting Verilog code generation process for filter: optfir ### Generating:
C:\hdlfilter_tutorials\hdlsrc\optfir.v ### Starting generation of optfir Verilog module ### Starting generation of optfir Verilog module body ### HDL latency
is 8 samples ### Successful completion of Verilog code generation process for filter: optfir ### Starting generation of VERILOG Test Bench ### Generating
input stimulus 2-37 2 Tutorials: Generating HDL Code for Filters ### Done generating input stimulus; length 3429 samples. ### Generating Test bench:
C:\hdlfilter_tutorials\hdlsrc\optfir_tb.v ### Please wait .
### Done generating VERILOG Test Bench As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the
files optfir.v and optfir_tb.v in that folder. Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these
hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated Verilog code has the following characteristics: Verilog module named optfir. Registers that use asynchronous resets when the reset signal is
active high (1). Generated code that optimizes its use of data types and eliminates redundant operations. Coefficient multipliers optimized with the CSD
technique. Final summations optimized using a pipelined technique. Ports that have the following names: Verilog Port Input Output Clock input Clock
enable input Reset input Name data_in data_out clk clk_enable reset An extra register for handling filter output. Coefficients named coeffn, where n is the
coefficient number, starting with 1. 2-38 Optimized FIR Filter Tutorial Type safe representation is used when zeros are concatenated: '0' & '0'. The postfix
string _process is appended to sequential (begin) block names.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The generated test bench: Is a portable Verilog file.
Forces clock, clock enable, and reset input signals. Forces the clock enable input signal to active high. Drives the clock input signal high (1) for 5
nanoseconds and low (0) for 5 nanoseconds. Forces the reset signal for two cycles plus a hold time of 2 nanoseconds. Applies a hold time of 2 nanoseconds
to data input signals. Applies an error margin of 4 bits. For a FIR filter, appplies impulse, step, ramp, chirp, and white noise stimulus types. Getting
Familiar with the FIR Filter's Optimized Generated Verilog Code Get familiar with the filter's optimized generated Verilog code by opening and browsing
through the file optfir.v in an ASCII or HDL simulator editor: 1 Open the generated Verilog filter file optcfir.v.
2 Search for optfir. This line identifies the Verilog module, using the string you specified for the Name option in the Target pane. See step 3 in "Configuring
and Generating the FIR Filter's Optimized Verilog Code" on page 2-29. 3 Search for Tutorial. This is where the coder places the text you entered for the
Comment in header option.
See step 9 in "Configuring and Generating the FIR Filter's Optimized Verilog Code" on page 2-29. 2-39 2 Tutorials: Generating HDL Code for Filters 4
Search for HDL Code. This section lists the coder options you modified in "Configuring and Generating the FIR Filter's Optimized Verilog Code" on page
2-29. 5 Search for Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in "Designing the FIR
Filter in FDATool" on page 2-24 and "Quantizing the FIR Filter" on page 2-26.
6 Search for module. This line names the Verilog module, using the string you specified for the Name option in the Target pane. This line also declares the list
of ports, as defined by options on the Ports pane of the Generate HDLdialog box. The ports for data input and output are named with the strings you specified
for the Input port and Output port options on the Ports tab of the Generate HDLdialog box. See steps 3 and 11 in "Configuring and Generating the FIR
Filter's Optimized Verilog Code" on page 2-29. 7 Search for input. This line and the four lines that follow, declare the direction mode of each port. 8 Search
for Constants. This is where the coefficients are defined. They are named using the default naming scheme, coeffn, where n is the coefficient number, starting
with 1.
9 Search for Signals. This is where the filter's signals are defined. 10 Search for sumvector1. This area of code declares the signals for implementing an
instance of a pipelined final adder. Signal declarations for four additional pipelined final adders are also included. These signals are used to implement the
pipelined FIR adder style optimization specified with the Add pipeline registers option. See step 7 in "Configuring and Generating the FIR Filter's Optimized
Verilog Code" on page 2-29. 11 Search for process. The block name Delay_Pipeline_process includes the default block postfix string _process. 12 Search for
reset.
This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the process applies the default asynchronous reset style
when generating code for registers. 2-40 Optimized FIR Filter Tutorial 13 Search for posedge. This Verilog code checks for rising edges when the filter
operates on registers.
14 Search for sumdelay_pipeline_process1. This block implements the pipeline register stage of the pipeline FIR adder style you specified in step 7 of
"Configuring and Generating the FIR Filter's Optimized Verilog Code" on page 2-29. 15 Search for output_register. This is where filter output is written to
an output register. The code for this register is generated by default.
In step 12 in "Configuring and Generating the FIR Filter's Optimized Verilog Code" on page 2-29 , you cleared the Add input register option, but left the Add
output register selected.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Also note that the process name Output_Register_process includes the default process postfix string _process. 16 Search for data_out. This is where the filter
writes its output data. Verifying the FIR Filter's Optimized Generated Verilog Code This section explains how to verify the FIR filter's optimized generated
Verilog code with the generated Verilog test bench. Although this tutorial uses the Mentor Graphics ModelSim simulator as the tool for compiling and
simulating the Verilog code, you can use any HDL simulation tool package. To verify the filter code, complete the following steps: 2-41 2 Tutorials:
Generating HDL Code for Filters 1 Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following
appears. 2 Set the current folder to the folder that contains your generated Verilog files. For example: cd hdlsrc 3 If necessary, create a design library to
store the compiled Verilog modules.
In the Mentor Graphics ModelSim simulator, you can create a design library with the vlib command. vlib work 4 Compile the generated filter and test bench
Verilog files. In the Mentor Graphics ModelSim simulator, you compile Verilog code with the vlog command. The following commands compile the filter and
filter test bench Verilog code. vlog optfir.v vlog optfir_tb.v 2-42 Optimized FIR Filter Tutorial The following screen display shows this command sequence
and informational messages displayed during compilation. 5 Load the test bench for simulation. The procedure for doing this varies depending on the
simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command.
For example: vsim optfir_tb 2-43 2 Tutorials: Generating HDL Code for Filters The following display shows the results of loading optfir_tb with the vsim
command. 2-44 Optimized FIR Filter Tutorial 6 Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor
Graphics ModelSim simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms: add wave
* The following wave window opens: 7 To start running the simulation, issue the appropriate command for your simulator. For example, in the Mentor
Graphics ModelSim simulator, you can start a simulation with the run command. 2-45 2 Tutorials: Generating HDL Code for Filters The following display
shows the run -all command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and
the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when
generating the filter Verilog code. 2-46 Optimized FIR Filter Tutorial The following wave window shows the simulation results as HDL waveforms. 2-47 2
Tutorials: Generating HDL Code for Filters IIR Filter Tutorial In this section.
"Designing an IIR Filter in FDATool" on page 2-48 "Quantizing the IIR Filter" on page 2-50 "Configuring and Generating the IIR Filter's VHDL Code" on
page 2-54 "Getting Familiar with the IIR Filter's Generated VHDL Code" on page 2-60 "Verifying the IIR Filter's Generated VHDL Code" on page 2-62
Designing an IIR Filter in FDATool This tutorial guides you through the steps for designing an IIR filter, generating Verilog code for the filter, and verifying
the Verilog code with a generated test bench. This section guides you through the procedure of designing and creating a filter for an IIR filter. This section
assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool). 1 Start the MATLAB software. 2 Set your
current folder to the folder you created in "Creating a Folder for Your Tutorial Files" on page 2-2.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
2-48 IIR Filter Tutorial 3 Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog
box appears. 4 In the Filter Design & Analysis Tool dialog box, set the following filter options: 2-49 2 Tutorials: Generating HDL Code for Filters Option
Response Type Design Method Filter Order Frequency Specifications Value Highpass IIR Butterworth Specify order: 5 Units: Hz Fs: 48000 Fc: 10800 5
Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is
complete.
Designing Filter. Done For more information on designing filters with the FDATool, see "Using FDATool with Filter Design Toolbox Software" in the Filter
Design Toolbox documentation. Quantizing the IIR Filter You should quantize filters for HDL code generation. To quantize your filter, 1 Open the IIR filter
design you created in "Designing an IIR Filter in FDATool" on page 2-48 if it is not already open. 2-50 IIR Filter Tutorial 2 Click the Set Quantization
Parameters button in the left-side toolbar. The FDATool displays the Filter arithmetic list in the bottom half of its dialog box. 2-51 2 Tutorials: Generating
HDL Code for Filters 3 Select Fixed-point from the list. The FDATool displays the first of three tabbed panels of its dialog box. You use the quantization
options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy. 4 Select the Filter Internals tab and set
Rounding mode to Floor and Overflow Mode to Saturate.
2-52 IIR Filter Tutorial 5 Click Apply. The quantized filter appears as follows. For more information on quantizing filters with the FDATool, see "Using
FDATool with Filter Design Toolbox Software" in the Filter Design Toolbox documentation. 2-53 2 Tutorials: Generating HDL Code for Filters Configuring
and Generating the IIR Filter's VHDL Code After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This
section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test
bench for the IIR filter you designed and quantized in "Designing an IIR Filter in FDATool" on page 2-48 and "Quantizing the IIR Filter" on page 2-50: 1
Start the Filter Design HDL Coder GUI by selecting Targets ] Generate HDL in the FDATool dialog box.
The FDATool displays the Generate HDL dialog box. 2 In the Name text box of the Target pane, type iir. This option names the VHDL entity and the file that
will contain the filter's VHDL code. 2-54 IIR Filter Tutorial 3 Select the Global settings tab of the GUI. Then select the General tab of the Additional settings
section.
In the Comment in header text box, type Tutorial - IIR Filter. The coder adds the comment to the end of the header comment block in each generated file. 4
Select the Ports tab. The Ports pane appears. 5 Clear the check box for the Add output register option. The Ports pane should now appear as in the following
figure. 2-55 2 Tutorials: Generating HDL Code for Filters 6 Select the Advanced tab. The Advanced pane appears. 2-56 IIR Filter Tutorial 7 Select the Use
'rising_edge' for registers option. The Advanced pane should now appear as in the following figure.
8 Click on the Test bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with iir_tb. This option names the
generated test bench file. 2-57 2 Tutorials: Generating HDL Code for Filters 9 In the Generate HDL dialog box, click Generate to start the code generation
process. When code generation completes, click OK to close the dialog box. The coder displays the following messages in the MATLAB Command Window as
it generates the filter and test bench VHDL files: ### Starting VHDL code generation process for filter: iir ### Starting VHDL code generation process for
filter: iir ### Generating: H:\hdlsrc\iir.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2
2-58 IIR Filter Tutorial ### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir
### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 2172 samples. ### Generating Test
bench: H:\hdlsrc\filter_tb.vhd ### Please wait . ### Done generating VHDL Test Bench ### Starting VHDL code generation process for filter: iir ###
Starting VHDL code generation process for filter: iir ### Generating: H:\hdlsrc\iir.
vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2
### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir As the messages
indicate, the coder creates the folder hdlsrc under your current working folder and places the files iir.vhd and iir_tb.vhd in that folder. Observe that the
messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB
Editor.
The generated VHDL code has the following characteristics: VHDL entity named iir. Registers that use asynchronous resets when the reset signal is active
high (1). Ports have the following default names: VHDL Port Input Output Name filter_in filter_out 2-59 2 Tutorials: Generating HDL Code for Filters
VHDL Port Clock input Clock enable input Reset input Name clk clk_enable reset An extra register for handling filter input. Clock input, clock enable input
and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR. Coefficients are named coeffn, where n is the
coefficient number, starting with 1.
Type safe representation is used when zeros are concatenated: '0' & '0'. Registers are generated with the rising_edge function rather than the statement
ELSIF clk'event AND clk='1' THEN. The postfix string _process is appended to process names. The generated test bench: Is a portable VHDL file. Forces
clock, clock enable, and reset input signals. Forces the clock enable input signal to active high. Drives the clock input signal high (1) for 5 nanoseconds
and low (0) for 5 nanoseconds. Forces the reset signal for two cycles plus a hold time of 2 nanoseconds. Applies a hold time of 2 nanoseconds to data input
signals. For an IIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
Getting Familiar with the IIR Filter's Generated VHDL Code Get familiar with the filter's generated VHDL code by opening and browsing through the file
iir.vhd in an ASCII or HDL simulator editor: 2-60 IIR Filter Tutorial 1 Open the generated VHDL filter file iir.vhd. 2 Search for iir. This line identifies the
VHDL module, using the string you specified for the Name option in the Target pane. See step 2 in "Configuring and Generating the IIR Filter's VHDL Code"
on page 2-54. 3 Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 5 in "Configuring and
Generating the IIR Filter's VHDL Code" on page 2-54. 4 Search for HDL Code.
This section lists coder options you modified in"Configuring and Generating the IIR Filter's VHDL Code" on page 2-54. 5 Search for Filter Settings. This
section of the VHDL code describes the filter design and quantization settings as you specified in "Designing an IIR Filter in FDATool" on page 2-48 and
"Quantizing the IIR Filter" on page 2-50. 6 Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the
Target pane.
See step 2 in "Configuring and Generating the IIR Filter's VHDL Code" on page 2-54.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
7 Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable,
reset, and data input and output signals are named with default strings. 8 Search for CONSTANT.
This is where the coefficients are defined. They are named using the default naming scheme, coeff_xm_sectionn, where x is a or b, m is the coefficient number,
and n is the section number. 9 Search for SIGNAL. This is where the filter's signals are defined. 10 Search for input_reg_process. The PROCESS block name
input_reg_process includes the default PROCESS block postfix string _process. This is where filter input is read from an input register. Code for this register
is generated by default. In step 7 in "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8, you cleared the Add output register option,
but left the Add input register option selected. 2-61 2 Tutorials: Generating HDL Code for Filters 11 Search for IF reset.
This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset
style when generating VHDL code for registers. 12 Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on
registers. The rising_edge function is used as you specified in the Advanced pane of the Generate HDLdialog box. See step 10 in "Configuring and
Generating the IIR Filter's VHDL Code" on page 2-54. 13 Search for Section 1. This is where second-order section 1 data is filtered. Similar sections of
VHDL code apply to another second-order section and a first-order section.
14 Search for filter_out. This is where the filter writes its output data. Verifying the IIR Filter's Generated VHDL Code This sections explains how to verify
the IIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses theMentor Graphics ModelSim simulator as the tool for
compiling and simulating the VHDL code, you can use any HDL simulation tool package. To verify the filter code, complete the following steps: 1 Start your
simulator.
When you start theMentor Graphics ModelSim simulator, a screen display similar to the following appears. 2-62 IIR Filter Tutorial 2 Set the current folder to
the folder that contains your generated VHDL files. For example: cd hdlsrc 3 If necessary, create a design library to store the compiled VHDL entities,
packages, architectures, and configurations. In theMentor Graphics ModelSim simulator, you can create a design library with the vlib command. vlib work 4
Compile the generated filter and test bench VHDL files.
In the Mentor Graphics ModelSim simulator, you compile VHDL code with the vcom command. The following the commands compile the filter and filter test
bench VHDL code. vcom iir.vhd vcom iir_tb.vhd 2-63 2 Tutorials: Generating HDL Code for Filters The following screen display shows this command
sequence and informational messages displayed during compilation. 5 Load the test bench for simulation. The procedure for doing this varies depending on
the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example: vsim
work.iir_tb 2-64 IIR Filter Tutorial The following display shows the results of loading work.
iir_tb with the vsim command. 6 Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim
simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms. add wave * 2-65 2 Tutorials:
Generating HDL Code for Filters The following wave window displays. 7 To start running the simulation, issue the appropriate command for your simulator.
For example, in theMentor Graphics ModelSim simulator, you can start a simulation with the run command.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
2-66 IIR Filter Tutorial The following display shows the run -all command being used to start a simulation. As your test bench simulation runs, watch for
error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected.
You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
Note The warning messages that note Time: 0 ns in the preceding display are not errors and you can ignore them. The failure message that appears in the
preceding display is not flagging an error. If the message includes the string Test Complete, the test bench has successfully run to completion. The Failure
part of the message is tied to the mechanism that the coder uses to end the simulation. 2-67 2 Tutorials: Generating HDL Code for Filters The following wave
window shows the simulation results as HDL waveforms.
2-68 3 Generating HDL Code for a Filter Design "Overview of Generating HDL Code for a Filter Design" on page 3-2 "Opening the Generate HDL
Dialog Box" on page 3-4 "What Is Generated by Default?" on page 3-14 "What Are Your HDL Requirements?" on page 3-19 "Setting the Target
Language" on page 3-25 "Setting the Names and Location for Generated HDL Files" on page 3-26 "Customizing Reset Specifications" on page 3-33
"Customizing the HDL Code" on page 3-37 "Capturing Code Generation Settings to a Script" on page 3-85 "Generating Code for Multirate Filters" on
page 3-86 "Generating Code for Cascade Filters" on page 3-93 "Generating Code for Polyphase Sample Rate Converters" on page 3-97 "Generating
Code for Multirate Farrow Sample Rate Converters" on page 3-101 "Generating Code for Single-Rate Farrow Filters" on page 3-105 "Customizing the
Test Bench" on page 3-112 "Generating the HDL Code" on page 3-142 "Generating Scripts for EDA Tools" on page 3-143 3 Generating HDL Code for a
Filter Design Overview of Generating HDL Code for a Filter Design Consider the following process as you prepare to use the Generate HDL dialog box to
generate VHDL code for your quantized filter: 1 Open the Generate HDL dialog box. 2 Review what the coder generates by default. 3 Assess whether the
default settings meet your application requirements. If they do, skip to step 6. 4 Review the customization checklist available in "What Are Your HDL
Requirements?" on page 3-19 and identify required customizations.
5 Modify the Generate HDL dialog box options to address your application requirements, as described in the sections beginning with "Setting the Target
Language" on page 3-25. 6 Generate the filter's HDL code and test bench. 3-2 Overview of Generating HDL Code for a Filter Design The following figure
shows the steps in a flow diagram. Open generate HDL dialog Review default output Meets requirements? Yes No Review customization checklist Modify
dialog settings Generate HDL filter code and test bench Done 3-3 3 Generating HDL Code for a Filter Design Opening the Generate HDL Dialog Box In this
section. "Opening the Generate HDL Dialog Box from FDATool" on page 3-4 "Opening the Generate HDL Dialog Box from the filterbuilder GUI" on page
3-9 "Opening the Generate HDL Dialog Box Using the fdhdltool Command" on page 3-11 Opening the Generate HDL Dialog Box from FDATool To open
the initial Generate HDL dialog box from FDATool, do the following: 1 Enter the fdatool command at the MATLAB command prompt. The FDATool displays
its initial dialog box. 3-4 Opening the Generate HDL Dialog Box 2 If the filter design is quantized, skip to step 3. Otherwise, quantize the filter by clicking the
Set Quantization Parameters button . The Filter arithmetic menu appears in the bottom half of the dialog box. 3-5 3 Generating HDL Code for a Filter Design
Note All supported filter structures allow fixed-point and floating-point (double) realizations.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
3 If necessary, adjust the setting of the Filter arithmetic option. The FDATool displays the first of three tabbed panes of its dialog. 3-6 Opening the Generate
HDL Dialog Box 4 Select Targets ] Generate HDL. The FDATool displays the Generate HDL dialog box. 3-7 3 Generating HDL Code for a Filter Design If
the coder does not support the structure of the current filter in the FDATool, an error message appears. For example, if the current filter is a quantized,
lattice-coupled, allpass filter, the following message appears. 3-8 Opening the Generate HDL Dialog Box Opening the Generate HDL Dialog Box from the
filterbuilder GUI If you are not familiar with the filterbuilder GUI, see "Designing a Filter in the Filterbuilder GUI" in the Filter Design Toolbox
documentation. To open the initial Generate HDL dialog box from the filterbuilder GUI, do the following: 1 At the MATLAB command prompt, type a
filterbuilder command appropriate to the filter response or filter object you want to design. The following figure shows the default settings of the main pane of
the filterbuilder Lowpass Filter Design dialog box. 3-9 3 Generating HDL Code for a Filter Design 2 Set the filter design parameters as required.
3 Click the Code Generation tab. This activates the Code Generation pane, shown in the following figure. 4 In the Code Generation pane, click the Generate
HDL button. This opens the Generate HDL dialog box, passing in the current filter object from filterbuilder. 3-10 Opening the Generate HDL Dialog Box 5
Set the desired code generation and test bench options and generate code in the Generate HDL dialog box.
Opening the Generate HDL Dialog Box Using the fdhdltool Command You can use the fdhdltool command to open the Generate HDL dialog box directly
from the MATLAB command line. The syntax is: fdhdltool(Hd) 3-11 3 Generating HDL Code for a Filter Design where Hd is any type of filter object that is
supported for HDL code generation. The fdhdltool function is particularly useful when you need to use the Filter Design HDL Coder GUI to generate HDL
code for filter structures that are not supported by FDATool or filterbuilder. For example, the following commands create a Farrow linear fractional delay
filter object Hd, which is passed in to the fdhdltool function: D = .3; farrowfilt = dfilt.
farrowlinearfd(D); farrowfilt.arithmetic = 'fixed'; fdhdltool(farrowfilt); fdhdltool operates on a copy of the filter object, rather than the original object in the
MATLAB workspace. Any changes made to the original filter object after invoking fdhdltool do not affect the copy and do not update the Generate HDL
dialog box. The naming convention for the copied object is filt_copy, where filt is the name of the original filter object. This naming convention is reflected in
the filter Name and test bench File name fields, as shown in the following figure. 3-12 Opening the Generate HDL Dialog Box 3-13 3 Generating HDL Code
for a Filter Design What Is Generated by Default? In this section. "Default Settings for Generated Files" on page 3-14 "Default Generation of Script Files"
on page 3-15 "Default Settings for Register Resets" on page 3-15 "Default Settings for General HDL Code" on page 3-15 "Default Settings for Code
Optimizations" on page 3-17 "Default Settings for Test Benches" on page 3-17 Default Settings for Generated Files By default, the coder Generates the
following files, where Hd is the name of the quantized filter: Language Verilog VHDL File Filter source Filter test bench Filter source Package (if needed)
Test bench Name Hd.v Hd_tb.v Hd.vhd Hd_pkg.
vhd Hd_tb.vhd Places generated files in a subfolder named hdlsrc, under your current working folder. Includes VHDL entity and architecture code in a
single source file. For information on modifying these settings, see "What Are Your HDL Requirements?" on page 3-19 and "Setting the Names and Location
for Generated HDL Files" on page 3-26.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
3-14 What Is Generated by Default? Default Generation of Script Files Using the defaults, you can automatically generate scripts for the following third-
party Electronic Design Automation (EDA) tools: Mentor Graphics ModelSim SE/PE HDL simulator The Synplify family of synthesis tools See
"Generating Scripts for EDA Tools" on page 3-143 for detailed information on generation and customization of scripts. Default Settings for Register Resets
By default, the coder Uses an asynchronous reset when generating HDL code for registers. Uses an active-high (1) signal for register resets. For
information on modifying these settings, see "What Are Your HDL Requirements?" on page 3-19 and "Customizing Reset Specifications" on page 3-33.
Default Settings for General HDL Code By default, the coder Names the generated VHDL entity or Verilog module with the name of the quantized filter.
Names a filter's HDL ports as follows: HDL Port Input Output Clock input Clock enable input Name filter_in filter_out clk clk_enable 3-15 3 Generating
HDL Code for a Filter Design HDL Port Reset input Fractional delay input (Farrow filters only) Name reset filter_fd Sets the data types for HDL ports as
follows: HDL Port Clock input Clock enable input Reset Data input Data output Fractional delay input (Farrow filters only) VHDL Type STD_LOGIC
STD_LOGIC STD_LOGIC STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR Verilog Type wire wire wire wire wire wire Names
coefficients as follows: For.
FIR filters IIR filters Names Coefficients. coeffn, where n is the coefficient number, starting with 1 coeff_xm_sectionn, where x is a or b, m is the coefficient
number, and n is the section number When declaring signals of type REAL, initializes the signal with a value of 0.0. Places VHDL configurations in any file
that instantiates a component. In VHDL, uses a type safe representation when concatenating zeros: '0' & '0'.
In VHDL, applies the statement ELSIF clk'event AND clk='1' THEN to check for clock events. In Verilog, uses time scale directives. 3-16 What Is
Generated by Default? Adds an extra input register and an extra output register to the filter code. Appends _process to process names. When creating
labels for VHDL GENERATE statements: - Appends _gen to VHDL section and block names.
Names VHDL output assignment blocks with the string outputgen. For information on modifying these settings, see "What Are Your HDL Requirements?" on
page 3-19 and "Customizing the HDL Code" on page 3-37. Default Settings for Code Optimizations By default, most code optimizations are disabled. The
coder Generates HDL code that is bit-true to the results produced by the original filter object and is not optimized for performance or space requirements.
Applies a linear final summation to FIR filters. This is the form of summation explained in most DSP text books. For FIR filters, generates a fully parallel
architecture (optimal for speed). Enables multiplier operations for a filter, as opposed to replacing them with additions of partial products. For information
on modifying these settings, see "What Are Your HDL Requirements?" on page 3-19 and "Setting Optimizations" on page 4-2. Default Settings for Test
Benches By default, the coder generates a VHDL test bench that inherits all the HDL settings that are applied to the filter's HDL code.
In addition, the coder generates a test bench that Is named filter_tb.vhd. Forces clock, clock enable, and reset input signals. Forces clock enable and reset
input signals to active high. Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds. 3-17 3 Generating HDL Code for a
Filter Design Forces reset signals for two cycles plus the hold time. Applies a hold time of 2 nanoseconds to filter reset and data input signals. The
generated test bench applies input stimuli based on the setting of the properties TestBenchStimulus and TestBenchUserStimulus.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The coder assigns default stimuli based on the filter type. The following choices of stimuli are available: 'impulse' 'step' 'ramp' 'chirp' 'noise' For
information on modifying these settings, see "What Are Your HDL Requirements?" on page 3-19 and "Customizing the Test Bench" on page 3-112.
3-18 What Are Your HDL Requirements? What Are Your HDL Requirements? As part of the process of generating HDL code for a filter design, review the
following checklist. The checklist will help you determine whether you need to adjust any of the HDL property settings. If your answer to any of the questions
in the checklist is "yes," go to the topic listed in the second column of the table for information on how to adjust the property setting to meet your project's
HDL requirements. HDL Requirements Checklist Requirement Language Selection Do you need to adjust the target language setting? "Setting the Target
Language" on page 3-25 "Setting the Names and Location for Generated HDL Files" on page 3-26 "Setting the Names and Location for Generated HDL
Files" on page 3-26 "Setting the Reset Type for Registers" on page 3-33 "Setting the Asserted Level for the Reset Input Signal" on page 3-34 "Suppressing
Generation of Reset Logic" on page 3-35 "Configuring Resets" on page 3-119 For More Information, See. File Naming and Location Specifications Do you
want to specify a unique name, which does not match the name of the quantized filter, for the VHDL entity or Verilog module that represents the filter? Do
you want the file type extension for generated HDL files to be a string other than .
vhd for VHDL or .v for Verilog? Do you want to use synchronous resets? Do you need the asserted level of the reset signal to be low (0)? Do you need to
suppress generation of reset logic for shift registers in FIR filters? Do you need to redefine the duration of the reset signal? Reset Specifications Header
Comment and General Naming Specifications 3-19 3 Generating HDL Code for a Filter Design HDL Requirements Checklist (Continued) Requirement Do
you want to add a specific string, such as a revision control string, to the end of the header comment block in each generated file? Do you want a string other
than coeff to be used as the base filter coefficient name? If your filter design requires a VHDL package file, do you want the name of the generated file to
include a string other than _pkg? Do you want a string other than _entity to be appended to VHDL entity or Verilog module names if duplicate names are
detected? Do you want a string other than _rsvd to be appended to specified names and labels that are HDL reserved words? Do you want a string other than
_process to be appended to HDL process names? Do you want the coder to write the entity and architecture parts of generated VHDL code to separate files?
Do you want a string other than u_ to be prefixed to component instance names? Do you want a string other than vector_of_ to be prefixed to vector names in
VHDL code? If the coder writes the entity and architecture parts of VHDL code to separate files, do you want strings other than _entity and _arch included in
the file names? For More Information, See. "Specifying a Header Comment" on page 3-38 "Specifying a Prefix for Filter Coefficients" on page 3-39 "Setting
the Postfix String for VHDL Package Files" on page 3-30 "Setting the Postfix String for Resolving Entity or Module Name Conflicts" on page 3-41 "Setting
the Postfix String for Resolving HDL Reserved Word Conflicts" on page 3-42 "Setting the Postfix String for Process Block Labels" on page 3-45 "Splitting
Entity and Architecture Code into Separate Files" on page 3-31 "Setting a Prefix for Component Instance Names" on page 3-47 "Setting a Prefix for Vector
Names" on page 3-48 "Splitting Entity and Architecture Code into Separate Files" on page 3-31 Port Specifications 3-20 What Are Your HDL Requirements?
HDL Requirements Checklist (Continued) Requirement Do you want the coder to use strings other than filter_in and filter_out to name HDL ports for the
filter's data input and output signals? Do you need the coder to declare the filter's data input and output ports with a VHDL type other than
STD_LOGIC_VECTOR? Do you want the coder to use strings other than clk and clk_enable to name HDL ports for the filter's clock and clock enable input
signals? Do you want the coder to use a string other than reset to name an HDL port for the filter's reset input signals? Do you want the coder to add an extra
input or output register to support the filter's HDL input and output ports? Do you want the coder to represent all constants as aggregates? Are you using an
EDA tool that does not support loops? Do you need to unroll and remove VHDL FOR and GENERATE loops? Do you want the coder to use the VHDL
rising_edge function to check for rising edges when the filter is operating on registers? Do you want to suppress Verilog time scale directives? Do you want
the coder to omit configurations from generated VHDL code? Are you going to create and store the filter's VHDL configurations in separate VHDL source
files? For More Information, See.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
"Naming HDL Ports" on page 3-49 "Specifying the HDL Data Type for Data Ports" on page 3-50 "Naming HDL Ports" on page 3-49 "Naming HDL Ports"
on page 3-49 "Suppressing Extra Input and Output Registers" on page 3-52 Advanced Coding Specifications "Representing Constants with Aggregates" on
page 3-53 "Unrolling and Removing VHDL Loops" on page 3-54 "Using the VHDL rising_edge Function" on page 3-55 "Suppressing Verilog Time Scale
Directives" on page 3-59 "Suppressing the Generation of VHDL Inline Configurations" on page 3-57 3-21 3 Generating HDL Code for a Filter Design HDL
Requirements Checklist (Continued) Requirement Do you want the coder to use the VHDL syntax "000000." to represent concatenated zeros instead of the
type safe representation '0' & '0'? Do you want to specify programmable coefficients for a FIR filter? Do you want to specify programmable coefficients for a
IIR filter? Do you want the coder to apply typical DSP processor treatment of input data types when generating code for addition and subtraction operations?
Does your filter design require use of complex coefficients or complex input data?? Do you need numeric results optimized, even if the results are not bit-true
to the results produced by the original filter object ? Do you want the coder to replace multiplier operations by applying canonic signed digit (CSD) and
factored CSD techniques? Do you need the coder to optimize the final summation for FIR filters? Do you need to specify an optimal FIR filter architecture
with respect to speed or chip area? Do you need to use a Distributed arithmetic architecture for a fixed-point FIR filter? Do you want to optimize your filter's
clock rate? For More Information, See.
"Specifying VHDL Syntax for Concatenated Zeros" on page 3-58 "Specifying Programmable Filter Coefficients for FIR Filters" on page 3-64 "Specifying
Programmable Filter Coefficients for IIR Filters" on page 3-77 "Specifying Input Type Treatment for Addition and Subtraction Operations" on page 3-60
"Using Complex Data and Coefficients" on page 3-62 "Optimizing Generated Code for HDL" on page 4-3 "Optimizing Coefficient Multipliers" on page 4-4
"Optimizing Final Summation for FIR Filters" on page 4-8 "Speed vs. Area Optimizations for FIR Filters" on page 4-10 "Distributed Arithmetic for FIR
Filters" on page 4-27 "Optimizing the Clock Rate with Pipeline Registers" on page 4-40 Optimization Specifications Multirate, Cascade, and Farrow Filter
Specifications 3-22 What Are Your HDL Requirements? HDL Requirements Checklist (Continued) Requirement Do you need to generate code for a multirate
filter ? Do you need to generate code for a polyphase sample rate converter or a multirate Farrow sample rate converter ? For More Information, See.
"Generating Code for Multirate Filters" on page 3-86 "Generating Code for Polyphase Sample Rate Converters" on page 3-97 "Generating Code for
Multirate Farrow Sample Rate Converters" on page 3-101 "Generating Code for Cascade Filters" on page 3-93 "Generating Code for Single-Rate Farrow
Filters" on page 3-105 Do you need to generate code for a cascade of filter objects? Do you need to generate code for a Farrow filter? Test Bench
Specifications Do you want the coder to write test bench helper functions, data, and test bench code to separate files? Do you want the generated test bench
file to include a string other than _tb? Do you want to generate a VHDL test bench? Do you want to generate a Verilog file test bench? Are you using a user-
defined external source to force clock enable input signals to a constant value? If the test bench is to force clock enable input signals, do you want it to force
the signals to active low (0)? Are you using a user-defined external source to force clock input signals? "Splitting Test Bench Code and Data into Separate
Files" on page 3-115 "Setting the Names and Location for Generated HDL Files" on page 3-26 "Specifying a Test Bench Type" on page 3-114 "Specifying a
Test Bench Type" on page 3-114 "Configuring the Clock" on page 3-117 "Configuring the Clock" on page 3-117 "Configuring the Clock" on page 3-117 3-23
3 Generating HDL Code for a Filter Design HDL Requirements Checklist (Continued) Requirement If the test bench is to force clock input signals, do you
want the signals to be driven high or low for a duration other than 5 nanoseconds? Do you want to delay the clock enable signal after the assertion of the
reset signal? Are you using a user-defined external source to force reset input signals? If the test bench is to force reset input signals, do you want it to force
the signals to active low (0)? If the test bench is to force reset input signals, do you want it to apply a hold time other than two cycles plus a hold time of 2
nanoseconds? Do you want to apply a hold time other than 2 nanoseconds to filter data input signals? Do you want to customize the stimulus to be applied by
the test bench? Do you want to set an initial value to be driven on test bench inputs? Do you want to cosimulate your filter with a third-party HDL simulator?
For More Information, See.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
"Configuring the Clock" on page 3-117 "Configuring the Clock" on page 3-117 "Configuring Resets" on page 3-119 "Configuring Resets" on page 3-119
"Configuring Resets" on page 3-119 "Setting a Hold Time for Data Input Signals" on page 3-122 "Setting Test Bench Stimuli" on page 3-127 "Setting an
Initial Value for Test Bench Inputs" on page 3-126 "Generating HDL Cosimulation Blocks for Use with HDL Simulators" on page 3-130 "Generating Scripts
for EDA Tools" on page 3-143 "Generating Scripts for EDA Tools" on page 3-143 "Capturing Code Generation Settings to a Script" on page 3-85 Script
Generation Specifications Do you want to customize script code that is auto-generated for third-party EDA tools? Do you want to customize script file names
for auto-generated EDA tool scripts? Do you want to generate a script that captures your nondefault option settings? 3-24 Setting the Target Language
Setting the Target Language HDL code is generated in either VHDL or Verilog. The language you choose for code generation is called the target language.
By default, the target language is VDHL. If you retain the VHDL setting, Generate HDL dialog box options that are specific to Verilog are disabled and are
not selectable. If you require or prefer to generate Verilog code, select Verilog for the Language option in the Target pane of the Generate HDL dialog box.
This setting causes the coder to enable options that are specific to Verilog and to gray out and disable options that are specific to VHDL. Command Line
Alternative: Use the generatehdl function with the TargetLanguage property to set the language to VHDL or Verilog.
3-25 3 Generating HDL Code for a Filter Design Setting the Names and Location for Generated HDL Files In this section. "Default File Names and
Locations" on page 3-26 "Setting Filter Entity and General File Naming Strings" on page 3-27 "Setting the Location of Generated Files" on page 3-29
"Setting the Postfix String for VHDL Package Files" on page 3-30 "Splitting Entity and Architecture Code into Separate Files" on page 3-31 Default File
Names and Locations By default, the coder creates the HDL files listed in the following table and places them in subfolder hdlsrc under your current working
folder. File names in generated HDL code derive from the name of the filter for which the HDL code is being generated and the file type extension .vhd or .v
for VHDL and Verilog, respectively. The table lists example file names based on filter name Hq. Language Verilog Generated File Source file for the
quantized filter Source file for the filter's test bench VHDL Source file for the quantized filter Source file for the filter's test bench Package file, if required by
the filter design File Name dfilt_name.v dfilt_name_tb.v dfilt_name.vhd dfilt_name_tb.
vhd Example Hq.v Hq_tb.v Hq.vhd Hq_tb.vhd dfilt_name_pkg.
vhd Hq_pkg.vhd The coder also uses the filter name to name the VHDL entity or Verilog module that represents the quantized filter in the HDL code.
Assuming a filter name of Hd, the name of the filter entity or module in the HDL code is Hd. 3-26 Setting the Names and Location for Generated HDL Files
By default, the code for a filter's VHDL entity and architectures is written to a single VHDL source file. Alternatively, you can specify that the coder write the
generated code for the entity and architectures to separate files.
For example, if the filter name is Hd, the coder writes the VHDL code for the filter to files Hd_entity.vhd and Hd_arch.vhd (see "Splitting Entity and
Architecture Code into Separate Files" on page 3-31). By default, the coder generates a single test bench file, containing all test bench helper functions, data,
and test bench code. You can split these elements into separate files, as described in "Splitting Test Bench Code and Data into Separate Files" on page 3-115.
Setting Filter Entity and General File Naming Strings To set the string that the coder uses to name the filter entity or module and generated files, specify a
new value in the Name field of the Filter settings pane of the Generate HDL dialog box.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The coder uses the Name string to Label the VHDL entity or Verilog module for your filter Name the file containing the HDL code for your filter Derive
names for the filter's test bench and package files By default, the filter HDL files are generated with a .vhd or .v file extension, depending on the language
selection. To change the file extension, 1 Select the Global Settings tab on the Generate HDL dialog box.
2 Select the General tab in theAdditional settings pane. 3 Type the new file extension in the Verilog file extension or VHDL file extension field. Based on the
following settings, the coder generates the filter file MyFIR.vhdl. 3-27 3 Generating HDL Code for a Filter Design Note When specifying strings for file
names and file type extensions, consider platform-specific requirements and restrictions. Also consider postfix strings that the coder appends to the Name
string, such as _tb and_pkg. Command Line Alternative: Use the generatehdl and generatetb functions with the Name property to set the name of your filter
entity and the base string for generated HDL file names. Specify the functions with the 3-28 Setting the Names and Location for Generated HDL Files
VerilogFileExtension or VHDLFileExtension property to specify a file type extension for generated HDL files. Setting the Location of Generated Files By
default, the coder places all generated HDL files in the subfolder hdlsrc under your current working folder. To direct the coder output to a folder other than
the default target folder, you can use either the Folder field or the Browse button in the Target pane of the Generate HDL dialog box.
Clicking on the Browse button opens a browser window that lets you select (or create) the folder to which generated code will be written. When the folder is
selected, the full path and folder name are automatically entered into the Folder field. Alternatively, you can enter the folder specification directly into the
Folder field. If you specify a folder that does not exist, the coder creates the folder for you before writing the generated files. Your folder specification can be
one of the following: Folder name.
In this case, the coder looks for, and if necessary, creates a subfolder under your current working folder. An absolute path to a folder under your current
working folder. If necessary, the coder creates the specified folder. A relative path to a higher level folder under your current working folder. For example, if
you specify ///myfiltvhd, the coder checks whether a folder named myfiltvhd exists three levels up from your current working folder, creates the folder if it does
not exist, and writes all generated HDL files to that folder.
In the following figure, the folder is set to MyFIRBetaVHDL. 3-29 3 Generating HDL Code for a Filter Design Given this setting, the coder creates the
subfolder MyFIRBetaVHDL under the current working folder and writes generated HDL files to that folder. Command Line Alternative: Use the generatehdl
and generatetb functions with theTargetDirectory property to redirect coder output. Setting the Postfix String for VHDL Package Files By default, the coder
appends the postfix _pkg to the base file name when generating a VHDL package file. To rename the postfix string for package files, do the following: 1 Select
the Global Settings tab on the Generate HDL dialog box. 2 Select the General tab in theAdditional settings pane. 3 Specify a new value in the Package postfix
field. 3-30 Setting the Names and Location for Generated HDL Files Note When specifying a string for use as a postfix in file names, consider the size of the
base name and platform-specific file naming requirements and restrictions. Command Line Alternative: Use the generatehdl and generatetb functions with the
PackagePostfix property to rename the file name postfix for VHDL package files. Splitting Entity and Architecture Code into Separate Files By default, the
coder includes a filter's VHDL entity and architecture code in the same generated VHDL file.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Alternatively, you can instruct the coder to place the entity and architecture code in separate files. For example, instead of all generated code residing in
MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd. The names of the entity and architecture files derive from The
base file name, as specified by the Name field in the Target pane of the Generate HDL dialog box Default postfix string values _entity and _arch The VHDL
file type extension, as specified by the VHDL file extension field on the General pane of the Generate HDL dialog box To split the filter source file, do the
following: 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the General tab in theAdditional settings pane. 3 Select Split entity and
architecture. The Split entity file postfix and Split arch. file postfix fields are now enabled.
3-31 3 Generating HDL Code for a Filter Design 4 Specify new strings in the postfix fields if you want to use postfix string values other than _entity and
_arch to identify the generated VHDL files. Note When specifying a string for use as a postfix value in file names, consider the size of the base name and
platform-specific file naming requirements and restrictions. Command Line Alternative: Use the generatehdl and generatetb functions with the property
SplitEntityArch to split the filter's VHDL code into separate files. Use properties SplitEntityFilePostfix and SplitArchFilePostfix to rename the file name
postfix for VHDL entity and architecture code components. 3-32 Customizing Reset Specifications Customizing Reset Specifications In this section.
"Setting the Reset Type for Registers" on page 3-33 "Setting the Asserted Level for the Reset Input Signal" on page 3-34 "Suppressing Generation of Reset
Logic" on page 3-35 Setting the Reset Type for Registers By default, generated HDL code for registers uses a asynchronous reset logic. Whether you should
set the reset type to asynchronous or synchronous depends on the type of device you are designing (for example, FPGA or ASIC) and preference. The
following code fragment illustrates the use of asynchronous resets. Note that the process block does not check for an active clock before performing a reset.
delay_pipeline_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline (0 To 50) [= (OTHERS =] (OTHERS =] '0')); ELSIF clk'event
AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) [= signed(filter_in) delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49); END IF; END
IF; END PROCESS delay_pipeline_process; To change the reset type to synchronous, select Synchronous from the Reset type menu in the Global settings
pane of the Generate HDL dialog box.
3-33 3 Generating HDL Code for a Filter Design Code for a synchronous reset follows. This process block checks for a clock event, the rising edge, before
performing a reset. delay_pipeline_process : PROCESS (clk, reset) BEGIN IF rising_edge(clk) THEN IF reset = '1' THEN delay_pipeline (0 To 50) [=
(OTHERS =] (OTHERS =] '0')); ELSIF clk_enable = '1' THEN delay_pipeline(0) [= signed(filter_in) delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49);
END IF; END IF; END PROCESS delay_pipeline_process; Command Line Alternative: Use the generatehdl and generatetb functions with the property
ResetType to set the reset style for your filter's registers. Setting the Asserted Level for the Reset Input Signal The asserted level for the reset input signal
determines whether that signal must be driven to active high (1) or active low (0) for registers to be reset in the filter design. By default, the coder sets the
asserted level to active high. For example, the following code fragment checks whether reset is active high before populating the delay_pipeline register: 3-34
Customizing Reset Specifications Delay_Pipeline_Process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 50) [= (OTHERS =]
(OTHERS =] '0')); .
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
To change the setting to active low, select Active-low from the Reset asserted level menu in the Global settings pane of the Generate HDL dialog box. With
this change, the IF statement in the preceding generated code changes to IF reset = '0' THEN Note The Reset asserted level setting also determines the rest
level for test bench reset input signals. Command Line Alternative: Use the generatehdl and generatetb functions with the property ResetAssertedLevel to set
the asserted level for the filter's reset input signal. Suppressing Generation of Reset Logic For some FPGA applications, it is desirable to avoid generation of
resets.
The Remove reset from option in the Global settings pane of the Generate HDL dialog box lets you suppress generation of resets from shift registers. 3-35 3
Generating HDL Code for a Filter Design To suppress generation of resets from shift registers, select Shift register from the Remove reset from pulldown
menu in the Global settings pane of the Generate HDL dialog box. If you do not want to suppress generation of resets from shift registers, leave Remove reset
from set to its default, which is None. Command Line Alternative: Use the generatehdl function with the property RemoveResetFrom to suppress generation of
resets from shift registers. 3-36 Customizing the HDL Code Customizing the HDL Code In this section. "Specifying a Header Comment" on page 3-38
"Specifying a Prefix for Filter Coefficients" on page 3-39 "Setting the Postfix String for Resolving Entity or Module Name Conflicts" on page 3-41 "Setting the
Postfix String for Resolving HDL Reserved Word Conflicts" on page 3-42 "Setting the Postfix String for Process Block Labels" on page 3-45 "Setting a Prefix
for Component Instance Names" on page 3-47 "Setting a Prefix for Vector Names" on page 3-48 "Naming HDL Ports" on page 3-49 "Specifying the HDL
Data Type for Data Ports" on page 3-50 "Suppressing Extra Input and Output Registers" on page 3-52 "Representing Constants with Aggregates" on page
3-53 "Unrolling and Removing VHDL Loops" on page 3-54 "Using the VHDL rising_edge Function" on page 3-55 "Suppressing the Generation of VHDL
Inline Configurations" on page 3-57 "Specifying VHDL Syntax for Concatenated Zeros" on page 3-58 "Suppressing Verilog Time Scale Directives" on page
3-59 "Specifying Input Type Treatment for Addition and Subtraction Operations" on page 3-60 "Using Complex Data and Coefficients" on page 3-62
"Specifying Programmable Filter Coefficients for FIR Filters" on page 3-64 "Specifying Programmable Filter Coefficients for IIR Filters" on page 3-77 3-37
3 Generating HDL Code for a Filter Design Specifying a Header Comment The coder includes a header comment block, such as the following, at the top of
the files it generates: -- --------------------------------------------------------------- Module: filter_tb_pkg --- Generated by MATLAB(R) 7.9 and the Filter Design
HDL Coder 2.5. --- Generated on: 2009-05-11 15:34:30 -- ------------------------------------------------------------- You can use the Comment in header option to
add a comment string, to the end of the header comment block in each generated file. For example, you might use this option to add the commentThis module
was automatically generated With this change, the preceding header comment block would appear as follows: --
--------------------------------------------------------------- Module: filter_tb_pkg --- Generated by MATLAB(R) 7.
9 and the Filter Design HDL Coder 2.5. --- Generated on: 2009-05-11 15:34:30 --- This module was automatically generated. ---
------------------------------------------------------------- To add a header comment, 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the
General tab in theAdditional settings pane.
3 Type the comment string in the Comment in header field, as shown in the following figure. 3-38 Customizing the HDL Code Command Line Alternative: Use
the generatehdl and generatetb functions with the property UserComment to add a comment string to the end of the header comment block in each generated
HDL file.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Specifying a Prefix for Filter Coefficients The coder declares a filter's coefficients as constants within an rtl architecture. The coder derives the constant
names adding the prefix coeff to the following: For. FIR filters IIR filters The Prefix Is Concatenated with.
Each coefficient number, starting with 1. Examples: coeff1, coeff22 An underscore (_) and an a or b coefficient name (for example, _a2, _b1, or _b2) followed
by the string _sectionn, where n is the section number. Example: coeff_b1_section3 (first numerator coefficient of the third section) 3-39 3 Generating HDL
Code for a Filter Design For example: ARCHITECTURE rtl OF Hd IS -- Type Definitions TYPE delay_pipeline_type IS ARRAY(NATURAL range []) OF
signed(15 DOWNTO 0);-- sfix16_En15 CONSTANT coeff1 CONSTANT coeff2 CONSTANT coeff3 CONSTANT coeff4 : signed(15 DOWNTO 0) :=
to_signed(-30, 16); -- sfix16_En15 : signed(15 DOWNTO 0) := to_signed(-89, 16); -- sfix16_En15 : signed(15 DOWNTO 0) := to_signed(-81, 16); --
sfix16_En15 : signed(15 DOWNTO 0) := to_signed(120, 16); -- sfix16_En15 To use a prefix other than coeff, 1 Select the Global Settings tab on the Generate
HDL dialog box. 2 Select the General tab in theAdditional settings pane. 3 Enter a new string in the Coefficient prefix field, as shown in the following figure.
The string that you specify Must start with a letter 3-40 Customizing the HDL Code Cannot end with an underscore (_) Cannot include a double
underscore (__) Note If you specify a VHDL or Verilog reserved word, the coder appends a reserved word postfix to the string to form a valid identifier. If you
specify a prefix that ends with an underscore, the coder replaces the underscore character with under. For example, if you specify coef_, the coder generates
coefficient names such as coefunder1. Command Line Alternative: Use the generatehdl and generatetb functions with the property CoeffPrefix to change the
base name for filter coefficients. Setting the Postfix String for Resolving Entity or Module Name Conflicts The coder checks whether multiple entities in VHDL
or multiple modules in Verilog share the same name.
If a name conflict exists, the coder appends the postfix _block to the second of the two matching strings. To change the postfix string: 1 Select the Global
Settings tab on the Generate HDL dialog box. 2 Select the General tab in theAdditional settings pane. 3 Enter a new string in the Entity conflict postfix field,
as shown in the following figure. 3-41 3 Generating HDL Code for a Filter Design Command Line Alternative: Use the generatehdl and generatetb functions
with the property EntityConflictPostfix to change the entity or module conflict postfix string. Setting the Postfix String for Resolving HDL Reserved Word
Conflicts The coder checks whether any strings that you specify as names, postfix values, or labels are VHDL or Verilog reserved words. See "Reserved Word
Tables" on page 3-43 for listings of all VHDL and Verilog reserved words. If you specify a reserved word, the coder appends the postfix _rsvd to the string.
For example, if you try to name your filter mod, for VHDL code, the coder adds the postfix _rsvd to form the name mod_rsvd. To change the postfix string: 1
Select the Global Settings tab on the Generate HDL dialog box.
2 Select the General tab in theAdditional settings pane. 3-42 Customizing the HDL Code 3 Enter a new string in the Reserved word postfix field, as shown in
the following figure. Command Line Alternative: Use the generatehdl and generatetb functions with the property ReservedWordPostfix to change the reserved
word postfix string. Reserved Word Tables The following tables list all VHDL and Verilog reserved words. VHDL Reserved Words abs and begin case downto
access architecture block component else after array body configuration elsif alias assert buffer constant end all attribute bus disconnect entity 3-43 3
Generating HDL Code for a Filter Design VHDL Reserved Words (Continued) exit generic in library mod not or postponed record return signal srl type
variable xnor file group inertial linkage nand null others procedure register rol shared subtype unaffected wait xor for guarded inout literal new of out
process reject ror sla then units when function if is loop next on package pure rem select sll to until while generate impure label map nor open port range
report severity sra transport use with Verilog Reserved Words always buf casez default else endgenerate endtask fork highz1 initial and bufif0 cell defparam
end endmodule event function if inout assign bufif1 cmos design endcase endprimitive for generate ifnone input automatic case config disable endconfig
endspecify force genvar incdir instance begin casex deassign edge endfunction endtable forever highz0 include integer 3-44 Customizing the HDL Code
Verilog Reserved Words (Continued) join macromodule nmos notif1 posedge pullup realtime rpmos showcancelled strong0 task tri trireg wand wor large
medium nor or primitive liblist module noshowcancelled output pull0 library nand not parameter pull1 localparam negedge notif0 pmos pulldown real rnmos
scalared specparam table tranif1 trior wait wire pulsestyle_onevent pulsestyle_ondetect rcmos reg rtran signed strong1 time tri0 unsigned weak0 xnor release
rtranif0 small supply0 tran tri1 use weak1 xor repeat rtranif1 specify supply1 tranif0 triand vectored while Setting the Postfix String for Process Block Labels
The coder generates process blocks to modify the content of a filter's registers.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The label for each of these blocks is derived from a register name and the postfix _process. For example, the coder derives the label delay_pipeline_process
in the following block from the register name delay_pipeline and the postfix string _process. delay_pipeline_process : PROCESS (clk, reset) BEGIN IF reset
= '1' THEN delay_pipeline (0 To 50) [= (OTHERS =] (OTHERS =] '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0)
[= signed(filter_in) delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49); 3-45 3 Generating HDL Code for a Filter Design END IF; END IF; END
PROCESS delay_pipeline_process; You can of set the postfix string to a value other than _process. For example, you might change it to _clkproc. To change
the string, 1 Select the Global Settings tab on the Generate HDL dialog box.
2 Select the General tab in theAdditional settings pane. 3 Enter a new string in the Clocked process postfix field, as shown in the following figure. Command
Line Alternative: Use the generatehdl and generatetb functions with the property ClockProcessPostfix to change the postfix string appended to process labels.
3-46 Customizing the HDL Code Setting a Prefix for Component Instance Names Instance prefix specifies a string to be prefixed to component instance names
in generated code. The default string is u_. You can of set the postfix string to a value other than u_. To change the string: 1 Select the Global Settings tab on
the Generate HDL dialog box. 2 Select the General tab in theAdditional settings pane. 3 Enter a new string in the Instance prefix field, as shown in the
following figure. Command Line Alternative: Use the generatehdl and generatetb functions with the property InstancePrefix to change the instance prefix
string.
3-47 3 Generating HDL Code for a Filter Design Setting a Prefix for Vector Names Vector prefix specifies a string to be prefixed to vector names in
generated VHDL code. The default string is vector_of_. Note VectorPrefix is supported only for VHDL code generation. You can set the prefix string to a
value other than vector_of_. To change the string: 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the General tab in theAdditional
settings pane. 3 Enter a new string in the Vector prefix field, as shown in the following figure. Command Line Alternative: Use the generatehdl and generatetb
functions with the property VectorPrefixto change the instance prefix string. 3-48 Customizing the HDL Code Naming HDL Ports The default names for filter
HDL ports are as follows: HDL Port Input port Output port Clock port Clock enable port Reset port Fractional delay port (Farrow filters only) Default Port
Name filter_in filter_out clk clk_enable reset filter_fd For example, the default VHDL declaration for entity Hd looks like the following. ENTITYHd IS PORT(
clk clk_enable reset filter_in filter_out ); ENDHd; : : : : : IN IN IN IN OUT std_logic; std_logic; std_logic; std_logic_vector (15 DOWNTO 0); -- sfix16_En15
std_logic_vector (15 DOWNTO 0); -- sfix16_En15 To change any of the port names, 1 Select the Global Settings tab on the Generate HDL dialog box.
2 Select the Ports tab in theAdditional settings pane. The following figure highlights the port name fields for Input port, Output port, Clock input port, Reset
input port, and Clock enable output port. 3-49 3 Generating HDL Code for a Filter Design 3 Enter new strings in the port name fields, as necessary
Command Line Alternative: Use the generatehdl and generatetb functions with the properties InputPort, OutputPort, ClockInputPort, ClockEnableInputPort,
and ResetInputPort to change the names of a filter's VHDL ports. Specifying the HDL Data Type for Data Ports By default, filter input and output data ports
have data type std_logic_vector in VHDL and type wire in Verilog. If you are generating VHDL code, alternatively, you can specify signed/unsigned, and for
output data ports, Same as input data type.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The coder applies type SIGNED or UNSIGNED based on the data type specified in the filter design. To change the VHDL data type setting for the input and
output data ports, 1 Select the Global Settings tab on the Generate HDL dialog box. 3-50 Customizing the HDL Code 2 Select the Ports tab in theAdditional
settings pane. 3 Select a data type from the Input data type or Output data type menu identified in the following figure. By default, the output data type is the
same as the input data type.
The type for Verilog ports is always wire, and cannot be changed. Note The setting of Input data type does not affect double-precision input, which is always
generated as type REAL for VHDL and wire[63:0] for Verilog. Command Line Alternative: Use the generatehdl and generatetb functions with the properties
InputType and OutputType to change the VHDL data type for a filter's input and output ports. 3-51 3 Generating HDL Code for a Filter Design Suppressing
Extra Input and Output Registers The coder adds an extra input register (input_register) and an extra output register (output_register) during HDL code
generation. These extra registers can be useful for timing purposes, but they add to the filter's overall latency. The following process block writes to extra
output register output_register when a clock event occurs and clk is active high (1): Output_Register_Process : PROCESS (clk, reset) BEGIN IF reset = '1'
THEN output_register [= (OTHERS =] '0'); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN output_register [= output_typeconvert; END IF;
END IF; END PROCESS Output_Register_Process; If overall latency is a concern for your application and you have no timing requirements, you can
suppress generation of the extra registers as follows: 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the Ports tab in theAdditional
settings pane. 3-52 Customizing the HDL Code 3 Clear Add input register and Add output register as required. The following figure shows the setting for
suppressing the generation of an extra input register. Command Line Alternative: Use the generatehdl and generatetb functions with the properties
AddInputRegister and AddOutputRegister to add an extra input or output register.
Representing Constants with Aggregates By default, the coder represents constants as scalars or aggregates depending on the size and type of the data. The
coder represents values that are less than 232 1 as integers and values greater than or equal to 232 1 as aggregates. The following VHDL constant
declarations are examples of declarations generated by default for values less than 32 bits: CONSTANT coeff1: signed(15 DOWNTO 0) := to_signed(-60,
16); -- sfix16_En16 CONSTANT coeff2: signed(15 DOWNTO 0) := to_signed(-178, 16); -- sfix16_En16 If you prefer that all constant values be represented
as aggregates, set the Represent constant values by aggregates as follows: 3-53 3 Generating HDL Code for a Filter Design 1 Select the Global Settings tab
on the Generate HDL dialog box. 2 Select the Advanced tab. 3 Select Represent constant values by aggregates, as shown the following figure. The preceding
constant declarations would now appear as follows: CONSTANT coeff1: signed(15 DOWNTO 0) := (5 DOWNTO 3 =] '0',1 DOWNTO 0 =] '0,OTHERS
=]'1'); CONSTANT coeff2: signed(15 DOWNTO 0) := (7 =] '0',5 DOWNTO 4 =] '0',0 =] '0',OTHERS =]'1'); Command Line Alternative: Use the
generatehdl and generatetb functions with the property UseAggregatesForConst to represent all constants in the HDL code as aggregates. Unrolling and
Removing VHDL Loops By default, the coder supports VHDL loops. However, some EDA tools do not support them. If you are using such a tool along with
VHDL, you might need 3-54 Customizing the HDL Code to unroll and remove FOR and GENERATE loops from your filter's generated VHDL code. Verilog
code is always unrolled.
To unroll and remove FOR and GENERATE loops, 1 Select the Global Settings tab on the Generate HDL dialog box.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
2 Select the Advanced tab. The Advanced pane appears. 3 Select Loop unrolling, as shown in the following figure. Command Line Alternative: Use the
generatehdl and generatetb functions with the property LoopUnrolling to unroll and remove loops from generated VHDL code.
Using the VHDL rising_edge Function The coder can generate two styles of VHDL code for checking for rising edges when the filter operates on registers. By
default, the generated code checks for a clock event, as shown in the ELSIF statement of the following VHDL process block. 3-55 3 Generating HDL Code for
a Filter Design Delay_Pipeline_Process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 50) [= (OTHERS =] (OTHERS =] '0'));
ELSEIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) [= signed(filter_in); delay_pipeline(1 TO 50) [= delay_pipeline(0 TO
49); END IF; END IF; END PROCESS Delay_Pipeline_Process ; If you prefer, the coder can produce VHDL code that applies the VHDL rising_edge
function instead. For example, the ELSIF statement in the preceding process block would be replaced with the following statement: ELSIF rising_edge(clk)
THEN To use the rising_edge function, 1 Click Global Settings in the Generate HDL dialog box. 2 Select the Advanced tab.
The Advanced pane appears. 3 Select Use 'rising_edge' for registers, as shown in the following dialog box. 3-56 Customizing the HDL Code Command Line
Alternative: Use the generatehdl and generatetb functions with the property UseRisingEdge to use the VHDL rising_edge function to check for rising edges
during register operations. Suppressing the Generation of VHDL Inline Configurations VHDL configurations can be either inline with the rest of the VHDL
code for an entity or external in separate VHDL source files. By default, the coder includes configurations for a filter within the generated VHDL code. If you
are creating your own VHDL configuration files, you should suppress the generation of inline configurations. To suppress the generation of inline
configurations, 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the Advanced tab. The Advanced pane appears. 3 Clear Inline
VHDL configuration, as shown in the following figure.
3-57 3 Generating HDL Code for a Filter Design Command Line Alternative: Use the generatehdl and generatetb functions with the property
InlineConfigurations to suppress the generation of inline configurations. Specifying VHDL Syntax for Concatenated Zeros In VHDL, the concatenation of
zeros can be represented in two syntax forms. One form, '0' & '0', is type safe. This is the default. The alternative syntax, "000000.", can be easier to read and
is more compact, but can lead to ambiguous types. To use the syntax "000000." for concatenated zeros, 1 Select the Global Settings tab on the Generate HDL
dialog box. 2 Select the Advanced tab. The Advanced pane appears.
3 Clear Concatenate type safe zeros, as shown in the following figure. 3-58 Customizing the HDL Code Command Line Alternative: Use the generatehdl and
generatetb functions with the property SafeZeroConcat to use the syntax "000000.", for concatenated zeros. Suppressing Verilog Time Scale Directives In
Verilog, the coder generates time scale directives (`timescale) , as appropriate, by default. This compiler directive provides a way of specifying different delay
values for multiple modules in a Verilog file.
To suppress the use of `timescale directives, 1 Select the Global Settings tab on the Generate HDL dialog box. 2 Select the Advanced tab. The Advanced pane
appears. 3 Clear Use Verilog `timescale directives, as shown in the following figure. 3-59 3 Generating HDL Code for a Filter Design Command Line
Alternative: Use the generatehdl and generatetb functions with the property UseVerilogTimescale to suppress the use of time scale directives.
Specifying Input Type Treatment for Addition and Subtraction Operations By default, generated HDL code operates on input data using data types as
specified by the filter design, and then converts the result to the specified result type.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Typical DSP processors type cast input data to the result type before operating on the data. Depending on the operation, the results can be very different. If
you want generated HDL code to handle result typing in this way, use the Cast before sum option as follows: 1 Select the Global Settings tab on the Generate
HDL dialog box. 2 Select the Advanced tab. The Advanced pane appears. 3 Select Cast before sum, as shown in the following figure. 3-60 Customizing the
HDL Code Command Line Alternative: Use the generatehdl and generatetb functions with the property CastBeforeSum to cast input values to the result type
for addition and subtraction operations. Relationship Between Cast Before Sum and Cast Before Accum. The Cast before sum property is related to the
FDATool setting for the quantization property Cast signals before accum.
as follows: Some filter object types do not have theCast signals before accum. property. For such filter objects, Cast before sum is effectively off when HDL
code is generated; it is not relevant to the filter. Where the filter object does have the Cast signals before accum. property, the coder by default follows the
setting of Cast signals before accum. in the filter object. This is visible in the GUI. If the you change the setting of Cast signals before accum., the coder
updates the setting of Cast before sum. However, by explicitly setting Cast before sum, you can override the Cast signals before accum.
setting passed in from FDATool. 3-61 3 Generating HDL Code for a Filter Design Using Complex Data and Coefficients The coder supports use of complex
coefficients and complex input signals for fully parallel FIR, CIC, and some other filter structures. In many cases, you can use complex data and complex
coefficients in combination. The following table shows the filter structures that support complex data and/or coefficients, and the permitted combinations.
Filter Structure Complex Data Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Complex Coefficients Y Y Y Y Y N/A N/A N/A Y Y Y Y N/A Y Y Y Y Y Both Complex Data
and Coefficients Y Y Y Y Y N/A N/A N/A Y Y Y Y N/A N/A Y Y Y Y dfilt.
dffir dfilt.dfsymfir dfilt.dfasymfir dfilt.dffirt dfilt.scalar dfilt.
delay mfilt.cicdecim mfilt.cicinterp mfilt.firdecim mfilt.firinterp mfilt.firsrc mfilt.firtdecim mfilt.linearinterp mfilt.holdinterp dfilt.df1sos dfilt.
df1tsos dfilt.df2sos dfilt.df2tsos 3-62 Customizing the HDL Code Enabling Code Generation for Complex Data The option you choose from the Input
complexity menu instructs the coder whether or not to generate the appropriate ports and signal paths for the real and imaginary components of a complex
signal. The default setting for Input complexity is Real, disabling generation of ports for complex input data. To enable generation of ports for complex input
data, set Input complexity to Complex. The corresponding command line property is InputComplex. By default, InputComplex is set to 'off', disabling
generation of ports for complex input data. To enable generation of ports for complex input data, set InputComplex to 'on', as in the following code example:
Hd = design(fdesign.lowpass,'equiripple','Filterstructure','dffir'); generatehdl(Hd, 'InputComplex', 'on'); The following VHDL code excerpt shows the entity
definition generated by the preceding commands: ENTITY Hd IS PORT( clk clk_enable reset filter_in_re filter_in_im filter_out_re filter_out_im ); : : : : : : :
IN IN IN IN IN OUT OUT std_logic; std_logic; std_logic; real; -- double real; -- double real; -- double real -- double END Hd; In the code excerpt, the port
names generated for the real components of complex signals are identified by the default postfix string'_re', and port names generated for the imaginary
components of complex signals are identified by the default postfix string '_im'. 3-63 3 Generating HDL Code for a Filter Design Setting the Port Name
Postfix for Complex Ports Two code generation properties let you customize naming conventions for the real and imaginary components of complex signals in
generated HDL code.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
These properties are: The Complex real part postfix option (corresponding to the ComplexRealPostfix command line property) specifies a string to be
appended to the names generated for the real part of complex signals. The default postfix is '_re'. See also ComplexRealPostfix. The Complex imaginary part
postfix option (corresponding to the ComplexImagPostfix command line property) specifies a string to be appended to the names generated for the imaginary
part of complex signals. The default postfix is '_im'.
See also ComplexImagPostfix. Specifying Programmable Filter Coefficients for FIR Filters By default, the coder obtains filter coefficients from a filter object
and hard-codes them into the generated code. An HDL filter realization generated in this way cannot be used with a different set of coefficients. For direct-
form FIR filters, the coder provides GUI options and corresponding command-line properties that let you: Generate an interface for loading coefficients
from memory. Coefficients stored in memory are called programmable coefficients.
Test the interface. To use programmable coefficients, a port interface (referred to as a processor interface) is generated for the filter entity or module.
Coefficient loading is assumed to be under the control of a microprocessor that is external to the generated filter. The filter uses the loaded coefficients for
processing input samples. If you choose one of the serial FIR filter architectures, you can also specify storage of programmable coefficients in your choice of
RAM (dual-port or single-port) or register file ( See "Using Programmable Coefficients with Serial FIR Filter Architectures" on page 3-70). 3-64
Customizing the HDL Code Note You can also generate a processor interface for loading IIR filter coefficients. See "Specifying Programmable Filter
Coefficients for IIR Filters" on page 3-77 for further information. Supported FIR Filter Types Programmable filter coefficients are supported for the following
direct-form FIR filter types: dfilt.dffir dfilt.dfsymfir dfilt.
dfasymfir Supported Parallel and Serial FIR Filter Architectures Programmable filter coefficients are supported for the following FIR filter architectures:
Fully parallel Fully serial Partly serial Cascade serial If you choose one of the serial filter architectures, see "Using Programmable Coefficients with
Serial FIR Filter Architectures" on page 3-70 for special considerations that apply to these architectures. Generating a Port Interface for Programmable FIR
Coefficients This section describes how to use the CoefficientSource property to specify that a processor interface for loading coefficients is generated. You
can also use the Coefficient source list on the Generate HDL dialog box for this purpose. The valid value strings for the property are: 3-65 3 Generating HDL
Code for a Filter Design 'Internal': (Default) Do not generate a processor interface. Coefficients are obtained from the filter object and hard-coded.
'ProcessorInterface': Generate a processor interface for coefficients. When you specify 'ProcessorInterface', the generated entity or module definition for the
filter includes the following port definitions: coeffs_in: Input port for coefficient data write_address: Write address for coefficient memory write_enable:
Write enable signal for coefficient memory write_done: Signal to indicate completion of coefficient write operation Example. In the following command-line
example, a processor interface is generated in VHDL code for a direct-form symmetric FIR filter with fully parallel (default) architecture. Hd =
design(fdesign.lowpass, 'equiripple', 'FilterStructure', 'dfsymfir'); generatehdl(Hd, 'CoefficientSource', 'ProcessorInterface'); The following listing shows the
VHDL entity definition generated for the filter object Hd.
ENTITY Hd IS PORT( clk clk_enable reset filter_in write_enable write_done write_address coeffs_in filter_out ); : : : : : : : : : IN IN IN IN IN IN IN IN OUT
std_logic; std_logic; std_logic; real; -- double std_logic; std_logic; real; -- double real; -- double real -- double END Hd; 3-66 Customizing the HDL Code
Generating a Test Bench for Programmable FIR Coefficients This section describes how to use the TestbenchCoeffStimulus property to specify how the test
bench drives the coefficient ports.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
You can also use the Coefficient stimulus option for this purpose. When a coefficient memory interface has been generated for a filter, all coefficient ports
have associated test vectors. The TestbenchCoeffStimulus property determines how the test bench drives the coefficient ports. The TestBenchStimulus property
determines the filter input stimuli, as with any filter.
The TestbenchCoeffStimulus property selects from two types of test benches. TestbenchCoeffStimulus takes a vector argument. The valid values are: []:
Empty vector. This is the default. When the value of TestbenchCoeffStimulus is unspecified (or set to the default value of []), the test bench loads the
coefficients from the filter object and then forces the input stimuli.
This shows the response to the input stimuli and verifies that the interface correctly writes one set of coefficients into the memory. [coeff1,coeff2, .coeffN]:
Vector of N coefficients, where N is determined as follows: - For symmetric filters, N must equal ceil(length(filterObj.Numerator)/2). For symmetric filters, N
must equal floor(length(filterObj.Numerator)/2). For other filters, N must equal the length of the filter object. In this case, the filter processes the input stimuli
twice. First, the test bench loads the coefficients from the filter object and forces the input stimuli to show the response. Then, the filter loads the set of
coefficients specified in the TestbenchCoeffStimulus vector, and shows the response by processing the same input stimuli for a second time.
In this case, the internal states of the filter, as set by the first run of the input stimulus, are retained. The test bench verifies that the interface writes two
different sets of coefficients into the coefficient memory. The test bench also provides 3-67 3 Generating HDL Code for a Filter Design an example of how the
memory interface can be used to program the filter with different sets of coefficients. Note If a coefficient memory interface has not been previously generated
for the filter, the TestbenchCoeffStimulus property is ignored. Example. In the following example, a processor interface is generated for a direct-form
symmetric FIR filter with fully parallel (default) architecture. The coefficients for the filter object are defined in the vector b. Test bench code is then
generated, using a second set of coefficients defined in the vector c. Note that c is trimmed to the effective length of the filter. b = [-0.
01 0.1 0.8 0.1 -0.01]; c = [-0.
03 0.5 0.7 0.5 -0.03]; c = c(1:ceil(length(c)/2)); hd = dfilt.
dfsymfir(b); generatehdl(hd, 'CoefficientSource', 'ProcessorInterface'); generatetb(hd,'VHDL', 'TestbenchCoeffStimulus', c); GUI Options for Programmable
Coefficients The following GUI options let you specify programmable coefficients: The Coefficient source list on the Generate HDL dialog box lets you
select whether coefficients are obtained from the filter object and hard-coded (Internal), or from memory (Processor interface). The default is Internal. The
corresponding command-line property is CoefficientSource (see "Generating a Port Interface for Programmable FIR Coefficients" on page 3-65). 3-68
Customizing the HDL Code The Coefficient stimulus option on the Test Bench pane of the Generate HDL dialog box lets you lets specify how the test bench
tests the generated memory interface. The corresponding command-line property is TestbenchCoeffStimulus (see "Generating a Test Bench for Programmable
FIR Coefficients" on page 3-67). 3-69 3 Generating HDL Code for a Filter Design Using Programmable Coefficients with Serial FIR Filter Architectures
This section discusses special considerations for using programmable filter coefficients with FIR filters that have one of the following serial architectures:
Fully serial 3-70 Customizing the HDL Code Partly serial Cascade serial Specifying Memory for Programmable Coefficients. By default, the processor
interface for programmable coefficients loads the coefficients from a register file.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The Coefficient memory pulldown menu lets you specify alternative RAM-based storage for programmable coefficients. Coefficient memory displays for FIR
filters, when both the following conditions are met: The Coefficient source option specifies Processor interface. The Architecture option specifies a Fully
serial, Partly serial, or Cascade serial architecture.
The following figure shows the Coefficient memory options for a fully serial FIR filter. 3-71 3 Generating HDL Code for a Filter Design The following table
summarizes the Coefficient memory options. 3-72 Customizing the HDL Code Coefficient Memory Pulldown Selection Registers Single Port RAMs
Description default: Store programmable coefficients in a register file. Store programmable coefficients in single-port RAM. The coder writes RAM interface
code to one or more separate files, depending on the filter partitioning. Dual Port RAMs Store programmable coefficients in dual-port RAM. The coder writes
RAM interface code to one or more separate files, depending on the filter partitioning. You can also use the CoefficientMemory command-line property to
specify alternative RAM-based storage for programmable coefficients. The following table summarizes the options. CoefficientMemory Setting
'CoefficientMemory', 'Registers' 'CoefficientMemory', 'SinglePortRAMs' Description default: Store programmable coefficients in a register file.
Store programmable coefficients in single-port RAM. The coder writes RAM interface code to one or more separate files, depending on the filter partitioning.
'CoefficientMemory', 'DualPortRAMs' Store programmable coefficients in dual-port RAM. The coder writes RAM interface code to one or more separate files,
depending on the filter partitioning. 3-73 3 Generating HDL Code for a Filter Design The commands in the following example create an asymmetric filter Hd,
and generate VHDL code for the filter using a partly serial architecture, with a dual-port RAM interface for programmable coefficients.
coeffs = fir1(22,0.45); Hd = dfilt.dfasymfir(coeffs); Hd.arithmetic = 'fixed'; generatehdl(Hd,'SerialPartition',[7 4],'CoefficientSource',.
'ProcessorInterface','CoefficientMemory','DualPortRAMs'); Tip When you use this property, be sure to set CoefficientSource to'ProcessorInterface'.
The coder ignores CoefficientMemory unless it is generating an interface for programmable coefficients. Timing Considerations. In a serial implementation
for a FIR filter, the rate of the system clock (clk) is generally a multiple of the filter's input data rate (i.e., the nominal sample rate of the filter). The exact
relationship between the clock rate and the filter's data rate is determined by the choice of serial architecture and partitioning. Programmable coefficients
load into the coeffs_in port at either the system clock rate (faster) or the input data (slower) rate. If your design requires loading of coefficients at the faster
rate, observe the following points: When write_enable asserts, coefficients load from thecoeffs_in port into coefficient memory at the address specified by
write_address. write_done can assert on any clock cycle for any duration. If write_done asserts at least two clk cycles before the arrival of the next data
input value, new coefficients will be applied with the next data sample.
Otherwise, new coefficients will be applied for the data after the next sample. The next two code generation examples illustrate how serial partitioning affects
the timing of coefficient loading. Both examples generate code for a filter Hd. Hd is an asymmetric filter that requires 11 coefficients. The following code
creates the filter Hd: rand('state',13893); 3-74 Customizing the HDL Code b = rand(1,23); Hd = dfilt.dfasymfir(b); Hd.Arithmetic='fixed'; The following
command generates VHDL code for Hd, using a partly serial architecture with the serial partition [7 4]. CoefficientSource specifies that a processor interface
is generated, with the default CoefficientStimulus.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
generatehdl(Hd,'SerialPartition',[7 4],'CoefficientSource', 'ProcessorInterface'); . ### Clock rate is 7 times the input sample rate for this architecture.
### HDL latency is 2 samples As reported by the coder, this partitioning results in a clock rate that is 7 times the input sample rate. The following timing
diagram illustrates the timing of coefficient loading relative to the timing of input data samples. While write_enable is asserted, 11 coefficient values are
loaded, via coeffs_in, to 11 sequential memory addresses. On the next clk cycle, write_enable is deasserted and write_done is asserted for one clock period.
The coefficient loading operation is completed within 2 cycles of data input, allowing 2 clk cycles to elapse before the arrival of the data value 07FFF.
Therefore the newly loaded coefficients are applied to that data sample. 3-75 3 Generating HDL Code for a Filter Design The following code generation
example defines a serial partition of [6 5] for the same filter. This results in a slower clock rate, 6 times the input sample rate.
generatehdl(Hd,'SerialPartition',[6 5],'CoefficientSource', 'ProcessorInterface'); . ### Clock rate is 6 times the input sample rate for this architecture.
### HDL latency is 2 samples The following timing diagram illustrates that write_done deasserts too late for the coefficients to be applied to the arriving data
value 278E. They are applied instead to the next sample, 7FFF. 3-76 Customizing the HDL Code Specifying Programmable Filter Coefficients for IIR Filters
By default, the coder obtains filter coefficients from a filter object and hard-codes them into the generated code. An HDL filter realization generated in this
way cannot be used with a different set of coefficients. For IIR filters, the coder provides GUI options and corresponding command-line properties that let
you: Generate an interface for loading coefficients from memory. Coefficients stored in memory are called programmable coefficients. Test the interface.
To use programmable coefficients, a port interface (referred to as a processor interface) is generated for the filter entity or module. Coefficient loading is
assumed to be under the control of a microprocessor that is external to the generated filter. The filter uses the loaded coefficients for processing input
samples.
For IIR filters, the current release supports programmable coefficients that are stored in a register file. 3-77 3 Generating HDL Code for a Filter Design Note
You can also generate a processor interface for loading FIR filter coefficients."Specifying Programmable Filter Coefficients for FIR Filters" on page 3-64 for
further information. Supported IIR Filter Types The following IIR filter types support programmable filter coefficients: Second-order section (SOS) infinite
impulse response (IIR) Direct Form I (dfilt.df1sos ) SOS IIR Direct Form I transposed (dfilt.df1tsos) SOS IIR Direct Form II (dfilt.df2sos) SOS IIR Direct
Form II transposed (dfilt.df2tsos) Generating a Port Interface for Programmable IIR Filter Coefficients This section describes how to use the
CoefficientSource property to specify that a processor interface for loading coefficients is generated. You can also use the Coefficient source menu on the
Generate HDL dialog box for this purpose. The valid value strings for the property are: 'Internal': (Default) Do not generate a processor interface.
Coefficients are obtained from the filter object and hard-coded. 'ProcessorInterface': Generate a processor interface for coefficients. When you specify
'ProcessorInterface', the generated entity or module definition for the filter includes the following port definitions: coeffs_in: Input port for coefficient data
write_address: Write address for coefficient memory (See also "Addressing Scheme for Loading IIR Coefficients" on page 3-81.) write_enable: Write enable
signal for coefficient memory 3-78 Customizing the HDL Code write_done: Signal to indicate completion of coefficient write operation Example.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
In the following command-line example, a processor interface is generated in VHDL code for an SOS IIR Direct Form II filter.
Fs = 48e3; Fc = 10.8e3; N = 5; % Sampling frequency % Cut-off frequency % Filter Order f_lp = fdesign.lowpass('n,f3db',N,Fc,Fs); Hd =
design(f_lp,'butter','FilterStructure','df2sos'); Hd.arithmetic = 'fixed'; generatehdl(Hd, 'CoefficientSource', 'ProcessorInterface') The following listing shows
the VHDL entity definition generated for the filter object Hd. ENTITY Hd IS PORT( clk clk_enable reset filter_in write_enable write_done write_address
coeffs_in filter_out ); : : : : : : : : : IN IN IN IN IN IN IN IN OUT std_logic; std_logic; std_logic; std_logic_vector(15 DOWNTO 0); -- sfix16_En15 std_logic;
std_logic; std_logic_vector(4 DOWNTO 0); -- ufix5 std_logic_vector(15 DOWNTO 0); -- sfix16 std_logic_vector(15 DOWNTO 0) -- sfix16_En12 END Hd;
Generating a Test Bench for Programmable IIR Coefficients This section describes how to use the TestbenchCoeffStimulus property to specify how the test
bench drives the coefficient ports.
You can also use the Coefficient stimulus option for this purpose. When a coefficient memory interface has been generated for a filter, all coefficient ports
have associated test vectors. The TestbenchCoeffStimulus property determines how the test bench drives the coefficient ports. 3-79 3 Generating HDL Code
for a Filter Design The TestBenchStimulus property determines the filter input stimuli, as with any filter. The TestbenchCoeffStimulus specified the source of
coefficients used for the test bench. The valid values for TestbenchCoeffStimulus are: [] : Empty vector. This is the default. When the value of
TestbenchCoeffStimulus is unspecified (or set to the default value of []) the test bench loads the coefficients from the filter object and then forces the input
stimuli. This shows the response to the input stimuli and verifies that the interface correctly writes one set of coefficients into the memory. A cell array
containing the following elements: - New_Hd.
ScaleValues: column vector of scale values for the IIR filter New_Hd.sosMatrix: second-order section (SOS) matrix for the IIR filter You can specify the
elements of the cell array in any of the following forms: {New_Hd.ScaleValues , New_Hd.sosMatrix} {New_Hd.ScaleValues ; New_Hd.sosMatrix}
{New_Hd.sosMatrix , New_Hd.ScaleValues} {New_Hd.sosMatrix ; New_Hd.ScaleValues} {New_Hd.
ScaleValues} {New_Hd.sosMatrix} In this case, the filter processes the input stimuli twice. First, the test bench loads the coefficients from the filter object and
forces the input stimuli to show the response. Then, the filter loads the set of coefficients specified in the TestbenchCoeffStimulus cell array, and shows the
response by processing the same input stimuli for a second time. In this case, the internal states of the filter, as set by the first run of the input stimulus, are
retained.
The test bench verifies that the interface writes two different sets of coefficients into the register file. The test bench also provides an example of how the
memory interface can be used to program the filter with different sets of coefficients. 3-80 Customizing the HDL Code If you omit New_Hd.ScaleValues, the
test bench uses the scale values loaded from the filter object twice. Likewise, if you omit New_Hd.
sosMatrix, the test bench uses the SOS matrix loaded from the filter object twice. Addressing Scheme for Loading IIR Coefficients The following table gives
the address generation scheme for the write_address port when loading IIR coefficients into memory. This addressing scheme allows all types of coefficients
(scale values, numerator coefficients, and denominator coefficients) to be loaded via a single port (coeffs_in). Note that all types of coefficients have the same
word length, but may have different fractional lengths. The address for each coefficient is divided into two fields: Section address: Width is ceil(log2N) bits,
where N is the number of sections.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Coefficient address : Width is 3 bits The total width of the write_address port is therefore ceil(log2N) + 3bits. 3-81 3 Generating HDL Code for a Filter
Design Section Address S S . S S . S S . S S .
S S . S S . S S . 0 0 . S S S S S S S 0 Coefficient Address 000 001 011 100 101 110 110 111 Description Section scale value Numerator coefficient: b1
Numerator coefficient: b2 Numerator coefficient: b3 Denominator coefficient: a2 Denominator coefficient: a3 (if order = 2; otherwise unused) Unused Last
scale value GUI Options for Programmable Coefficients The following GUI options let you specify programmable coefficients: The Coefficient source list on
the Generate HDL dialog box lets you select whether coefficients are obtained from the filter object and hard-coded (Internal), or from memory (Processor
interface). The default is Internal. The corresponding command-line property is CoefficientSource (see "Generating a Port Interface for Programmable IIR
Filter Coefficients" on page 3-78). 3-82 Customizing the HDL Code The Coefficient stimulus option on the Test Bench pane of the Generate HDL dialog box
lets you lets specify how the test bench tests the generated memory interface. The corresponding command-line property is TestbenchCoeffStimulus (see
"Generating a Test Bench for Programmable IIR Coefficients" on page 3-79). 3-83 3 Generating HDL Code for a Filter Design 3-84 Capturing Code
Generation Settings to a Script Capturing Code Generation Settings to a Script The Generate M-file option of the Generate HDL dialog box makes command-
line scripting of HDL filter code and test bench generation easier.
The option is located in the Target section of the Generate HDL dialog box, as shown in the following figure. By default, Generate M-file is cleared. When
you select Generate M-file and generate code, the coder captures all nondefault HDL code and test bench generation settings from the GUI and writes out a
script you can use to regenerate HDL code for the filter. The script contains: Header comments that document the design settings for the filter object from
which code was generated. A function that takes a filter object as its argument, and passes the filter object in to generatehdl and generatetb commands.
The property/value pairs passed to these commands correspond to the code generation settings in effect at the time the file was generated. The coder wites the
script to the target folder. The naming convention for the file is filter_generatehdl.m, where filter is the filter name defined in the Name option. When code
generation completes, the generated script opens automatically for inspection and editing.
In subsequent sessions, you can use the information in the script comments to construct a filter object that is compatible with the generatehdl and
generatehdltb commands in the script . Then you can execute the script as a function, passing in the filter object, to generate HDL code. 3-85 3 Generating
HDL Code for a Filter Design Generating Code for Multirate Filters In this section. "Supported Multirate Filter Types" on page 3-86 "Generating Multirate
Filter Code" on page 3-86 "Code Generation Options for Multirate Filters" on page 3-87 Supported Multirate Filter Types HDL code generation is supported
for the following types of multirate filters: Cascaded Integrator Comb (CIC) interpolation ( mfilt.cicdecim) Cascaded Integrator Comb (CIC) decimation (
mfilt.cicinterp) Direct-Form Transposed FIR Polyphase Decimator (mfilt.firtdecim) Direct-Form FIR Polyphase Interpolator (mfilt.firinterp) Direct-Form
FIR Polyphase Decimator (mfilt.firdecim) Direct-Form FIR Polyphase Sample Rate Converter (mfilt.firsrc) FIR Hold Interpolator (mfilt.
holdinterp) FIR Linear Interpolator (mfilt.linearinterp) Generating Multirate Filter Code To generate multirate filter code, you must first select and design
one of the supported filter types using FDATool, filterbuilder, or the MATLAB command line.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
After you have created the filter, open the Generate HDL dialog box, set the desired code generation properties, and generate code. GUI options that support
multirate filter code generation are described in "Code Generation Options for Multirate Filters" on page 3-87. If you prefer to generate code via the
generatehdlfunction, the coder also defines multirate filter code generation properties that are functionally equivalent to the GUI options. "generatehdl
Properties for Multirate Filters" on page 3-92 summarizes these properties. 3-86 Generating Code for Multirate Filters Code Generation Options for
Multirate Filters When a multirate filter of a supported type (see "Supported Multirate Filter Types" on page 3-86) is designed, the enabled/disabled state of
several options in the Generate HDL dialog box changes: The Clock inputs pull-down menu is enabled. This menu provides two alternatives for generating
clock inputs for multirate filters. Note For multirate filters with the Partly serial architecture option selected, the Clock inputs options is set to Single and
disabled. For CIC filters, the Coefficient multipliers option is disabled.
Coefficient multipliers are not used in CIC filters. However, the Coefficient multipliers option is enabled for Direct-Form Transposed FIR Polyphase
Decimator (mfilt.firtdecim) filters. For CIC filters, the FIR adder style option is disabled, since CIC filters do not require a final adder. 3-87 3 Generating
HDL Code for a Filter Design The following figure shows the default settings of the Generate HDL dialog box options for a supported CIC filter.
The Clock inputs options are: Single: When Single is selected, the ENTITY declaration for the filter defines a single clock input with an associated clock
enable input and clock enable output. The generated code maintains a counter that controls the timing of data transfers to the filter output (for decimation
filters) or input 3-88 Generating Code for Multirate Filters (for interpolation filters). The counter is, in effect, a secondary clock enable whose rate is
determined by the filter's decimation or interpolation factor. The Single option is primarily intended for FPGAs. It provides a self-contained solution for
multirate filters, and does not require you to provide any additional code.
A clock enable output is also generated when Single is selected. If you want to customize the name of this output in generated code, see "Setting the Clock
Enable Output Name" on page 3-91. The following code excerpts were generated from a CIC decimation filter having a decimation factor of 4, with Clock
inputs set to Single. The ENTITY declaration is as follows. ENTITY cic_decim_4_1_single IS PORT( clk clk_enable reset filter_in filter_out ce_out ); : : : : : :
IN IN IN IN OUT OUT std_logic; std_logic; std_logic; std_logic_vector(15 DOWNTO 0); -- sfix16_En15 std_logic_vector(15 DOWNTO 0); -- sfix16_En15
std_logic END cic_decim_4_1_single; The signal counter is maintained by the clock enable output process (ce_output). Every 4th clock cycle, counter is
toggled to 1. ce_output : PROCESS (clk, reset) BEGIN IF reset = '1' THEN cur_count [= to_unsigned(0, 4); ELSIF clk'event AND clk = '1' THEN IF
clk_enable = '1' THEN IF cur_count = 3 THEN cur_count [= to_unsigned(0, 4); ELSE cur_count [= cur_count + 1; END IF; END IF; END IF; 3-89 3
Generating HDL Code for a Filter Design END PROCESS ce_output; counter [= '1' WHEN cur_count = 1 AND clk_enable = '1' ELSE '0'; The following
code excerpt illustrates a typical use of the counter signal, in this case to time the filter output. output_reg_process : PROCESS (clk, reset) BEGIN IF reset =
'1' THEN output_register [= (OTHERS =] '0'); ELSIF clk'event AND clk = '1' THEN IF counter = '1' THEN output_register [= section_out4; END IF; END
IF; END PROCESS output_reg_process; Multiple: When Multiple is selected, the ENTITY declaration for the filter defines separate clock inputs (each with
an associated clock enable input) for each rate of a multirate filter.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
(For currently supported multirate filters, there are two such rates). The generated code assumes that the clocks are driven at the appropriate rates.
You are responsible for ensuring that the clocks run at the correct relative rates for the filter's decimation or interpolation factor. To see an example of such
code, generate test bench code for your multirate filter and examine the clk_gen processes for each clock. The Multiple option is intended for ASICs and
FPGAs. It provides more flexibility than the Single option, but assumes that you will provide higher-level code for driving your filter's clocks. Note that no
synchronizers between multiple clock domains are provided. When Multiple is selected, clock enable outputs are not generated; therefore the Clock enable
output port field of the Global Settings pane is disabled. The following ENTITY declaration was generated from a CIC decimation filter with Clock inputs set
to Multiple. ENTITY cic_decim_4_1_multi IS 3-90 Generating Code for Multirate Filters PORT( clk clk_enable reset filter_in clk1 clk_enable1 reset1
filter_out ); : : : : : : : : IN IN IN IN IN IN IN OUT std_logic; std_logic; std_logic; std_logic_vector(15 DOWNTO 0); -- sfix16_En15 std_logic; std_logic;
std_logic; std_logic_vector(15 DOWNTO 0) -- sfix16_En15 END cic_decim_4_1_multi; Setting the Clock Enable Output Name A clock enable output is
generated when Single is selected from the Clock inputs options in the Generate HDL dialog box. The default name for the clock enable output is ce_out. To
change the name of the clock enable output, enter the desired name into the Clock enable output port field of the Ports pane of the Generate HDL dialog box,
as shown in the following figure.
3-91 3 Generating HDL Code for a Filter Design Note that the coder enables the Clock enable output port field only when generating multiple clocks.
generatehdl Properties for Multirate Filters If you are using generatehdl to generate code for a multirate filter, you can set the following properties to specify
clock generation options: ClockInputs: Corresponds to the Clock inputs option; selects generation of single or multiple clock inputs for multirate filters.
ClockEnableOutputPort: Corresponds to the Clock enable output port field; specifies the name of the clock enable output port. 3-92 Generating Code for
Cascade Filters Generating Code for Cascade Filters In this section. "Supported Cascade Filter Types" on page 3-93 "Generating Cascade Filter Code" on
page 3-93 Supported Cascade Filter Types The coder supports code generation for the following types of cascade filters: Multirate cascade of filter objects (
mfilt.
cascade) Cascade of discrete-time filter objects ( dfilt.cascade) Generating Cascade Filter Code Generating Cascade Filter Code with FDATool To generate
cascade filter code with FDATool: 1 Instantiate the filter stages and cascade them in the MATLAB workspace (see the Filter Design Toolbox documentation
for the dfilt.cascade and mfilt.cascade filter objects). The coder currently imposes certain limitations on the filter types allowed in a cascade filter.
See "Rules and Limitations for Code Generation with Cascade Filters" on page 3-94 before creating your filter stages and cascade filter object. 2 Import the
cascade filter object into FDATool, as described in "Importing and Exporting Quantized Filters" in the Filter Design Toolbox documentation. 3 After you
have imported the filter, open the Generate HDL dialog box, set the desired code generation properties, and generate code. See "Rules and Limitations for
Code Generation with Cascade Filters" on page 3-94. 3-93 3 Generating HDL Code for a Filter Design Generating Cascade Filter Code with the fdhdltool
Function To generate cascade filter code from the command line using fdhdltool: 1 Instantiate the filter stages and cascade them in the MATLAB workspace
(see the Filter Design Toolbox documentation for the dfilt.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
cascade and mfilt.cascade filter objects). The coder currently imposes certain limitations on the filter types allowed in a cascade filter. See "Rules and
Limitations for Code Generation with Cascade Filters" on page 3-94 before creating your filter stages and cascade filter object. 2 Call fdhdltool to open the
Generate HDL dialog box, passing in the cascade filter object as in the following example: fdhdltool(my_cascade); 3 Set the desired code generation
properties, and generate code.
See "Rules and Limitations for Code Generation with Cascade Filters" on page 3-94. Rules and Limitations for Code Generation with Cascade Filters The
following rules and limitations apply to cascade filters when used for code generation: You can generate code for cascades that combine the following filter
types: - Decimators and/or single-rate filter structures Interpolators and/or single-rate filter structures Code generation for cascades that include both
decimators and interpolators is not currently supported, however. If unsupported filter structures or combinations of filter structures are included in the
cascade, code generation is disallowed. For code generation, only a flat (single-level) cascade structure is allowed. Nesting of cascade filters is disallowed.
By default, all input and output registers are removed from the stages of the cascade in generated code, except for the input of the first stage and the output of
the final stage. However, if the Add pipeline registers option in Generate HDL dialog box is selected, the output registers for each stage 3-94 Generating
Code for Cascade Filters are generated, and internal pipeline registers may be added, depending on the filter structures. Note Code generated for
interpolators within a cascade always includes input registers, regardless of the setting of the Add pipeline registers option. When a cascade filter is passed
in to the Generate HDL dialog box, the FIR adder style option is disabled. If you require tree adders for FIR filters in a cascade, select the Add pipeline
registers option (since pipelines require tree style FIR adders).
The coder generates separate HDL code files for each stage of the cascade, in addition to the top-level code for the cascade filter itself. The filter stage code
files are identified by appending the string _stage1, _stage2, . _stageN to the filter name. 3-95 3 Generating HDL Code for a Filter Design The following
figure shows the default settings of the Generate HDL dialog box options when a cascade filter has been designed 3-96 Generating Code for Polyphase
Sample Rate Converters Generating Code for Polyphase Sample Rate Converters In this section. "Overview" on page 3-97 "HDL Implementation for
Polyphase Sample Rate Converter" on page 3-97 Overview The coder supports code generation for direct-form FIR polyphase sample rate converters (mfilt.
firsrc). mfilt.firsrc is a multirate filter structure that combines an interpolation factor and a decimation factor, allowing you to perform fractional
interpolation or decimation on an input signal. The interpolation factor (l) and decimation factor (m) for a polyphase sample rate converter are specified as
integers in the RateChangeFactors property of an mfilt.firsrc object.
The following example code example constructs an mfilt.firsrc object with a resampling ratio of 5/3: frac_cvrter = mfilt.firsrc;
frac_cvrter.RateChangeFactors = [5 3]; Fractional rate resampling can be visualized as a two step process: an interpolation by the factor l , followed by a
decimation by the factorm. For example, given a resampling ratio of 5/3, a fractional sample rate converter raises the sample rate by a factor of 5, using a
standard five-path polyphase filter. A resampling switch then reduces the new rate by a factor of 3. This process extracts five output samples for every three
input samples. For general information on this filter structure, see the mfilt.firsrc reference page in the Filter Design Toolbox documentation.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
HDL Implementation for Polyphase Sample Rate Converter Signal Flow, Latency and Timing The signal flow for the mfilt.
firsrc filter is similar to the polyphase FIR interpolator ( mfilt.firinterp). The delay line is advanced such that the 3-97 3 Generating HDL Code for a Filter
Design inputs are delivered after the required set of polyphase coefficients are processed. The following diagram illustrates the timing of the HDL
implementation for mfilt.firsrc . A clock enable input (ce_in) enables the inputs into the filter. The outputs, and a clock enable output (ce_out) are produced
and delivered simultaneously, which results in a nonperiodic output. Clock Rate The clock rate required to process the hardware logic is related to the input
rate as: ceil(Hm.RateChangeFactors(1)/ Hm.RateChangeFactors(2)) For example, for a resampling ratio of 5/3, the clock rate is ceil(5/3) = 2, or twice the
input sample rate.
The inputs are delivered at every other clock cycle. The outputs are delivered as soon as they are produced and therefore are nonperiodic. Note When the
generated code or hardware logic is deployed, the outputs must be taken into an appropriately designed FIFO, with FIFO outputs occurring at the desired
sampling rate. 3-98 Generating Code for Polyphase Sample Rate Converters Clock Enable Ports The generated HDL entity or module the mfilt.firsrc filter
has two clock enable ports: Clock enable output: the default clock enable output port name is ce_out.
As with other multirate filters, you can use the Clock enable output port field of the Generate HDL dialog box to specify the port name. Alternatively, you can
use the ClockEnableOutputPort property to set the port name in the generatehdl command. Clock enable input: the default clock enable input port name is
ce_in. In the current release, there is no option to change the name of this port. Test Bench Generation Generated test benches use the input and output clock
enables to force in and verify the test vectors.
Generating Code for mfilt.firsrc filters at the Command Line The following example constructs a fixed-point mfilt.firsrc object with a resampling ratio of 5/3,
and generates VHDL filter code. frac_cvrter = mfilt.firsrc; frac_cvrter.arithmetic = 'fixed'; frac_cvrter.RateChangeFactors = [5 3];
generatehdl(frac_cvrter); ### Starting VHDL code generation process for filter: frac_cvrter ### Generating:
D:\Work\post_2006b_Adsp_sbox\hdlsrc\frac_cvrter.vhd ### Starting generation of frac_cvrter VHDL entity ### Starting generation of frac_cvrter VHDL
architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: frac_cvrter No special code generation
properties are required when generating code for mfilt.firsrc filters. However, the following code generation options are not supported for mfilt.
firsrc filters: Use of pipeline registers (AddPipelineRegisters) Distributed Arithmetic architecture 3-99 3 Generating HDL Code for a Filter Design Fully
or partially serial architectures Multiple clock inputs 3-100 Generating Code for Multirate Farrow Sample Rate Converters Generating Code for Multirate
Farrow Sample Rate Converters In this section. "Overview" on page 3-101 "Generating Code for mfilt.farrowsrc Filters at the Command Line" on page
3-101 "Generating Code for mfilt.farrowsrc Filters in the GUI" on page 3-103 Overview The coder supports code generation for multirate Farrow sample
rate converters (mfilt.farrowsrc). mfilt.farrowsrc is a multirate filter structure that implements a sample rate converter with an arbitrary conversion factor
determined by its interpolation and decimation factors. Unlike a single-rate Farrow filter (see "Generating Code for Single-Rate Farrow Filters" on page
3-105), a multirate Farrow sample rate converter does not have a fractional delay input. For general information on this filter structure, see the
mfilt.farrowsrc reference page in the Filter Design Toolbox documentation.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Generating Code for mfilt.farrowsrc Filters at the Command Line You can generate HDL code for either a standalone mfilt.farrowsrc object, or a cascade
that includes a mfilt.farrowsrc object. This section provides simple examples for each case.
The following example instantiates a standalone fixed-point Farrow sample rate converter. The converter performs a conversion between two standard audio
rates, from 44.1 kHz to 48 kHz. The example generates both VHDL code and a VHDL test bench. [L,M] = rat(48/44.
1); m = mfilt.farrowsrc(L,M); 3-101 3 Generating HDL Code for a Filter Design Hm.arithmetic = 'fixed'; ### Starting VHDL code generation process for
filter: Hm ### Starting VHDL code generation process for filter: Hm ### Generating: C:\Work\hdlsrc\Hm.vhd ### Starting generation of Hm VHDL entity
### Starting generation of Hm VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: Hm
generatetb(Hm, 'TestBenchStimulus','noise'); ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input
stimulus; length 1344 samples. ### Generating: C:\Work\hdlsrc\Hm_tb.vhd ### Please wait . ### Done generating VHDL test bench. The following example
illustrates code generation for a cascade that include a mfilt.farrowsrc filter. The coder requires that the mfilt.
farrowsrc filter is in the last position of the cascade. Astop = 50; % Minimum stopband attenuation % First interpolate the original 8 kHz signal by 4 using a
% cascade of FIR halfband filters. TW = .125; % Transition Width f2 = fdesign.interpolator(4,'Nyquist',4,'TW,Ast',TW,Astop); hfir =
design(f2,'multistage','HalfbandDesignMethod','equiripple'); % Then, interpolate the intermediate 8x4=32 kHz signal by 44.1/32 = % 1.378125 to get the
desired 44.1 kHz final sampling frequency. We use a % cubic Lagrange polynomial-based filter for this purpose. We first design % a single rate Farrow filter,
then convert it to a multirate Farrow filter.
N = 3; % Polynomial Order ffar = fdesign.fracdelay(0,'N',N); hfar = design(ffar,'lagrange'); [L,M]=rat(1.378125); % Interpolation and decimation factors
hfar = mfilt.farrowsrc(L,M,hfar.Coefficients); % The overall filter is obtained by cascading the two filters.
% For HDL code generation compatibility, the cascade of FIR filters is flattened. % Note that the mfilt.farrowsrc filter is at the end of the cascade. h2 =
cascade(hfir.Stage(1), hfir.
Stage(2),hfar); 3-102 Generating Code for Multirate Farrow Sample Rate Converters Generating Code for mfilt.farrowsrc Filters in the GUI FDATool and
filterbuilder do not currently support mfilt.farrowsrc filters. If you want to generate code an mfilt.farrowsrc filter in the HDL code generation GUI, you can
use the fdhdltool command, as in the following example: [L,M] = rat(48/44.1); m = mfilt.farrowsrc(L,M); fdhdltool(m); fdhdltool opens the Generate HDL
dialog box for the mfilt.farrowsrc filter, as shown in the following figure. 3-103 3 Generating HDL Code for a Filter Design The following code generation
options are not supported for mfilt.farrowsrc filters and are disabled in the GUI: Add pipeline registers Distributed Arithmetic architecture Fully or
partially serial architectures Multiple clock inputs 3-104 Generating Code for Single-Rate Farrow Filters Generating Code for Single-Rate Farrow Filters
In this section.
"Overview" on page 3-105 "Code Generation Properties for Farrow Filters" on page 3-105 "GUI Options for Farrow Filters" on page 3-107 "Farrow Filter
Code Generation Mechanics" on page 3-110 Overview The coder supports HDL code generation for the following single-rate Farrow filter structures:
dfilt.farrowlinearfd dfilt.farrowfd A Farrow filter differs from a conventional filter because it has a fractional delay input in addition to a signal input. The
fractional delay input enables the use of time-varying delays, as the filter operates. The fractional delay input receives a signal taking on values between 0
and 1.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
0. For general information how to construct and use Farrow filter objects, see the farrow function reference page of the Filter Design Toolbox
documentation. The coder provides generatetb and generatehdl properties and equivalent GUI options that let you: Define the fractional delay port name
used in generated code. Apply a variety of test bench stimulus signals to the fractional delay port, or define your own stimulus signal. Code Generation
Properties for Farrow Filters The following properties support Farrow filter code generation: FracDelayPort (string).
This property specifies the name of the fractional delay port in generated code. The default name is 'filter_fd'. In the 3-105 3 Generating HDL Code for a
Filter Design following example, the name 'FractionalDelay' is assigned to the fractional delay port. D = .3; hd = dfilt.
farrowfd(D); generatehdl(hd, 'FracDelayPort', 'FractionalDelay'); TestBenchFracDelayStimulus (string). This property specifies a stimulus signal applied
to the fractional delay port in test bench code. By default, a constant value is obtained from the FracDelay property of the Farrow filter object, and applied to
the fractional delay port. To use the default, leave the TestBenchFracDelayStimulus property unspecified, or pass in the empty string (''). In the following
example, the filter's FracDelay property is set to 0.
6, and this value is used (by default) as the fractional delay stimulus. D = .3; hd = dfilt.farrowfd(D); hd.Fracdelay = 0.6; generatetb(hd, 'VHDL');
Alternatively, you can specify generation of any of the following types of stimulus vectors: - 'RandSweep': A vector of random values within the range from 0
to 1. This stimulus signal has the same duration as the filter's input signal, but changes at a slower rate. Each fractional delay value obtained from the vector
is held for 10% of the total duration of the input signal before the next value is obtained. 'RampSweep' : A vector of values incrementally increasing over the -
range from 0 to 1. This stimulus signal has the same duration as the filter's input signal, but changes at a slower rate.
Each fractional delay value obtained from the vector is held for 10% of the total duration of the input signal before the next value is obtained. A user-defined
stimulus vector. You can pass in a call to any function that returns a vector. Alternatively, create the vector in the workspace and pass it in as shown in the
following code example: D = .3; hd = dfilt.farrowfd(D); - 3-106 Generating Code for Single-Rate Farrow Filters inputdata = generatetbstimulus(hd,
'TestBenchStimulus', {'ramp'}); mytestv = [0.5*ones(1, length(inputdata)/2), 0.2*ones(1, length(inputdata)/2)]; generatetb(hd, 'VHDL', 'TestBenchStimulus',
{'noise'},. 'TestbenchFracDelayStimulus',mytestv); Note A user-defined fractional delay stimulus signal must have the same length as the test bench input
signal. If the two signals do not have equal length, test bench generation terminates with an error message.
The error message displays the signal lengths, as shown in the following example: D = .3; hd = dfilt.farrowfd(D); inputdata = generatetbstimulus(hd,
'TestBenchStimulus', {'ramp'}); mytestv = [0.5*ones(1, length(inputdata)/2), 0.2*ones(1, length(inputdata)/2)]; generatetb(hd, 'VHDL', 'TestBenchStimulus',
{'noise' 'chirp'},.
'TestbenchFracDelayStimulus',mytestv); ??? Error using ==] generatevhdltb The lengths of specified vectors for FracDelay (1026) and Input (2052) do not
match. GUI Options for Farrow Filters This section describes Farrow filter code generation options that are available in the Filter Design HDL Coder GUI.
These options correspond to the properties described in "Code Generation Properties for Farrow Filters" on page 3-105. Note The Farrow filter options are
displayed only when the a Farrow filter is selected for HDL code generation. The Farrow filter options are: The Fractional delay port field in the Ports pane
of the Generate HDL dialog box (shown in the following figure) specifies the name of the fractional delay port in generated code.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The default name is filter_fd. 3-107 3 Generating HDL Code for a Filter Design The Fractional delay stimulus pop-up list in the Test Benchpane of the
Generate HDL dialog box (shown in the following figure) lets you select a stimulus signal applied to the fractional delay port in the generated test bench.
3-108 Generating Code for Single-Rate Farrow Filters The Fractional delay stimulus list lets you select generation of any of the following types of stimulus
signals: - Get value from filter: (default). A constant value is obtained from the FracDelay property of the Farrow filter object, and applied to the fractional
delay port. Ramp sweep. A vector of values incrementally increasing over the range from 0 to 1. This stimulus signal has the same duration as the filter's input
signal, but changes at a slower rate. Each fractional delay value obtained from the vector is held for 10% of the total duration of the input signal before the
next value is obtained. Random sweep. A vector of random values in the range from 0 to 1.
This stimulus signal has the same duration as the filter's input signal, but changes at a slower rate. Each fractional delay value obtained from the vector is
held for 10% of the total duration of the input signal before the next value is obtained. User defined. When you select this option, the User defined stimulus
field is enabled. You can enter a call to any function that returns a vector in the User defined stimulus field. Alternatively, create the - - 3-109 3 Generating
HDL Code for a Filter Design vector as a workspace variable and enter the variable name, as shown in the following figure. Farrow Filter Code Generation
Mechanics FDATool does not support design or import of Farrow filters. To generate HDL code for a Farrow filter, use one of the following methods: Use
the MATLAB command line to create a Farrow filter object and initiate code generation, and set Farrow-related properties, as in the examples shown in
"Code Generation Properties for Farrow Filters" on page 3-105. Use the MATLAB command line to create a Farrow filter object. Then use the fdhdltool
function to open the Generate HDL dialog box.
For example, the following commands create a Farrow linear fractional delay filter object Hd and pass it in to fdhdltool: D = .3; Hd =
dfilt.farrowlinearfd(D); Hd.arithmetic = 'fixed'; fdhdltool(Hd); 3-110 Generating Code for Single-Rate Farrow Filters Use filterbuilder to design a Farrow
(fractional delay) filter object. Then, select the Code Generation pane of the filterbuilder dialog box (shown in the following figure).
Click the Generate HDL button to open the Generate HDL dialog box, specify code generation options, and generate code. Options Disabled for Farrow
Filters The coder disables some options or sets them to fixed default value when the Generate HDL dialog box opens with a Farrow filter. The options
affected are: Architecture. The coder sets this option to its default (Fully parallel) and disables it. Clock inputs.
The coder sets this option to its default (Single) and disables it. 3-111 3 Generating HDL Code for a Filter Design Customizing the Test Bench In this section.
"Renaming the Test Bench" on page 3-112 "Specifying a Test Bench Type" on page 3-114 "Splitting Test Bench Code and Data into Separate Files" on page
3-115 "Configuring the Clock" on page 3-117 "Configuring Resets" on page 3-119 "Setting a Hold Time for Data Input Signals" on page 3-122 "Setting an
Error Margin for Optimized Filter Code" on page 3-125 "Setting an Initial Value for Test Bench Inputs" on page 3-126 "Setting Test Bench Stimuli" on page
3-127 "Setting a Postfix for Reference Signal Names" on page 3-129 "Generating HDL Cosimulation Blocks for Use with HDL Simulators" on page 3-130
"Generating a Simulink Model for Cosimulation with an HDL Simulator" on page 3-133 Renaming the Test Bench As discussed in "Customizing Reset
Specifications" on page 3-33, the coder derives the name of the test bench file from the name of the quantized filter for which the HDL code is being generated
and the postfix _tb.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The file type extension depends on the type of test bench that is being generated. If the Test Bench Is a. Verilog file The Extension Is. Defined by the Verilog
file extension field in the General subpane of the Global Settings pane of the Generate HDL dialog box Defined by the VHDL file extension field in the Global
Settings pane of the Generate HDL dialog box VHDL file 3-112 Customizing the Test Bench The file is placed in the folder defined by the Folder option in the
Target pane of the Generate HDL dialog box. To specify a test bench name, enter the name in the Name field of the Test bench settings pane, as shown in the
following figure. 3-113 3 Generating HDL Code for a Filter Design Note If you enter a string that is a VHDL or Verilog reserved word, the coder appends the
reserved word postfix to the string to form a valid identifier. Command Line Alternative: Use the generatetb function with the property TestBenchName to
specify a name for your filter's test bench.
Specifying a Test Bench Type The coder can generate two types of test benches: A VHDL file that you can simulate in a simulator of choice A Verilog file
that you can simulate in a simulator of choice By default, the coder generates a single test bench file, containing all test bench helper functions, data, and test
bench code. You can split these elements into separate files, as described in "Splitting Test Bench Code and Data into Separate Files" on page 3-115. Because
of differences in representation of double-precision data in VHDL and Verilog, restrictions apply to the types of test benches that are interoperable. The
following table shows valid and invalid test bench type and HDL combinations when code is generated for a double-precision filter. Test Bench Type Verilog
VHDL VHDL Invalid Valid Verilog Valid Invalid Note These restrictions do not apply for fixed-point filters. 3-114 Customizing the Test Bench By default, the
coder produces a VHDL or Verilog file, depending on your Language selection. Use the Test bench language pulldown menu in the Test bench generate
output panel of the Generate HDL dialog box. to select a test bench language that differs from the Language selection. In the following figure, the Language
is VHDL, while the Test bench language is Verilog. Command Line Alternative: Use the generatetb function's TbType parameter to specify the type of test
bench files to be generated.
Splitting Test Bench Code and Data into Separate Files By default, the coder generates a single test bench file, containing all test bench helper functions,
data, and test bench code. You can split these elements into separate files by selecting the Multi-file test bench option in 3-115 3 Generating HDL Code for a
Filter Design the Configuration subpane of the Test Bench pane of the Generate HDL dialog box, as shown below. When you select the Multi-file test bench
option, the Test bench data file name postfix option is enabled. The test bench file names are then derived from the name of the test bench, the Test bench
name option, and the Test bench data file name postfix option as follows: TestBenchName_TestBenchDataPostfix For example, if the test bench name is
my_fir_filt, and the target language is VHDL, the default test bench file names are: my_fir_filt_tb.vhd: test bench code my_fir_filt_tb_pkg.
vhd: helper functions package my_fir_filt_tb_data.vhd: data package 3-116 Customizing the Test Bench If the filter name is my_fir_filt and the target
language is Verilog, the default test bench file names are: my_fir_filt_tb.v: test bench code my_fir_filt_tb_pkg.v: helper functions package
my_fir_filt_tb_data.v: test bench data Command Line Alternative: Use the generatetb function with the properties MultifileTestBench, TestBenchDataPostFix,
and TestBenchName to generate and name separate test bench helper functions, data, and test bench code files.
Configuring the Clock Based on default settings, the coder configures the clock for a filter test bench such that it Forces clock enable input signals to active
high (1).
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Asserts the clock enable signal 1 clock cycle after deassertion of the reset signal. Forces clock input signals low (0) for a duration of 5 nanoseconds and
high (1) for a duration of 5 nanoseconds. To change these clock configuration settings: 1 Click Configuration in the Test bench pane of the Generate HDL
dialog box. 2 Within the Test Bench pane, select the Configuration subpane. 3 Make the following configuration changes as needed: If You Want to. Disable
the forcing of clock enable input signals Disable the forcing of clock input signals Then. Clear Force clock enable. Clear Force clock. 3-117 3 Generating
HDL Code for a Filter Design If You Want to.
Reset the number of nanoseconds during which clock input signals are to be driven low (0) Reset the number of nanoseconds during which clock input signals
are to be driven high (1) Change the delay time elapsed between the deassertion of the reset signal and the assertion of clock enable signal. Then. Specify a
positive integer or double (with a maximum of 6 significant digits after the decimal point) in the Clock low time field. Specify a positive integer or double
(with a maximum of 6 significant digits after the decimal point) in the Clock high time field. Specify a positive integer in the Clock enable delay field. The
following figure highlights the applicable options. 3-118 Customizing the Test Bench Command Line Alternative: Use the generatetb function with the
properties ForceClock, ClockHighTime, ClockLowTime, ForceClockEnable, and TestBenchClockEnableDelay to reconfigure the test bench clock.
Configuring Resets Based on default settings, the coder configures the reset for a filter test bench such that it Forces reset input signals to active high (1).
(Test bench reset input levels are set by the Reset asserted level option). Asserts reset input signals for a duration of 2 clock cycles.
Applies a hold time of 2 nanoseconds for reset input signals. The hold time is the amount of time (after some number of initial clock cycles defined by the
Reset length option) that reset input signals are to be held past the clock rising edge. The following figure shows the application of a hold time (thold) for
reset input signals when the signals are forced to active high and active low. The default Reset length of 2 clock cycles is shown. Clock Reset Input Active
High thold Reset Input Active Low thold Note The hold time applies to reset input signals only if the forcing of reset input signals is enabled.
3-119 3 Generating HDL Code for a Filter Design The following table summarizes the reset configuration settings, If You Want to. Disable the forcing of
reset input signals Change the length of time (in clock cycles) during which reset is asserted Change the reset value to active low (0) Then. Clear Force reset
in the Test Bench pane of the Generate HDL dialog box. Set Reset length (in clock cycles) to an integer greater than or equal to 0. This option is located in the
Test Bench pane of the Generate HDL dialog box.
Select Active-low from the Reset asserted level menu in the Global Settings pane of the Generate HDL dialog box (see "Setting the Asserted Level for the
Reset Input Signal" on page 3-34). Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing
nanoseconds, in the Hold time field. When the Hold time changes, the Setup time (ns) value (displayed below Hold time) is updated. The Setup time (ns) value
computed as (clock period - HoldTime) in nanoseconds. These options are in the Test Bench pane of the Generate HDL dialog box. Set the hold time The
following figures highlight the applicable options. 3-120 Customizing the Test Bench 3-121 3 Generating HDL Code for a Filter Design Note The hold time
and setup time settings also apply to data input signals. Command Line Alternative: Use the generatetb function with the properties ForceReset, ResetLength,
and HoldTime to reconfigure test bench resets.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Setting a Hold Time for Data Input Signals By default, the coder applies a hold time of 2 nanoseconds for filter data input signals. The hold time is the
amount of time that data input signals are to be held past the clock rising edge.
The following figure shows the application of a hold time (thold) for data input signals. 3-122 Customizing the Test Bench Clock Data Input thold To change
the hold time setting, 1 Click the Test Bench tab in the Generate HDL dialog box. 2 Within the Test Bench pane, select the Configuration subpane. 3-123 3
Generating HDL Code for a Filter Design 3 Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing
nanoseconds, in the Hold time field. In the following figure, the hold time is set to 2 nanoseconds. When the Hold time changes, the Setup time (ns) value
(displayed below Hold time) updates. The coder computes the Setup time (ns) value as (clock period - HoldTime) in nanoseconds. Setup time (ns) is a display-
only field. Note The hold time and setup time settings also apply to reset input signals, if the forcing of such signals is enabled. Command Line Alternative:
Use the generatetb function with the property HoldTime to adjust the hold time setting.
3-124 Customizing the Test Bench Setting an Error Margin for Optimized Filter Code Customizations that provide optimizations can generate test bench code
that produces numeric results that differ from results produced by the original filter object. These options include: Optimize for HDL FIR adder style set to
Tree Add pipeline registers for FIR, asymmetric FIR, and symmetric FIR filters If you choose to use any of these options, consider setting an error margin
for the generated test bench to account for differences in numeric results. The error margin is the number of least significant bits the test bench will ignore
when comparing the results. To set an error margin: 1 Select the Test Bench pane in the Generate HDL dialog box. 2 Within the Test Bench pane, select the
Configuration subpane.
3-125 3 Generating HDL Code for a Filter Design 3 For fixed-point filters, the initial Error margin (bits) field has a default value of 4. If you wish to change
the error margin, enter an integer in the Error margin (bits) field. In the following figure, the error margin is set to 3 bits. Setting an Initial Value for Test
Bench Inputs By default, the initial value driven on test bench inputs is 'X' (unknown). Alternatively, you can specify that the initial value driven on test bench
inputs is 0, as follows: 1 Select the Test Bench pane in the Generate HDL dialog box.
3-126 Customizing the Test Bench 2 Within the Test Bench pane, select the Configuration subpane. 3 To set an initial test bench input value of 0, select the
Initialize test bench inputs option. To set an initial test bench input value of 'X', clear the Initialize test bench inputs option. Command Line Alternative: Use
the generatetb function with the InitializeTestBenchInputs property to set the initial test bench input value. Setting Test Bench Stimuli By default, the coder
generates a filter test bench that includes stimuli appropriate for the given filter type. However, you can adjust the stimuli settings or specify user defined
stimuli, if necessary. 3-127 3 Generating HDL Code for a Filter Design To modify the stimuli that the coder is to include in a test bench, select one or more
response types listed in the Stimuli subpane of the Test bench settings pane of the Generate HDL dialog box. The following figure highlights this pane of the
dialog box. If you select User defined response, you must also specify an expression or function that returns a vector of values to be applied to the filter. The
values specified in the vector are quantized and scaled based on the filter's quantization settings.
Command Line Alternative: Use the generatetb function with the properties TestBenchStimulus and TestBenchUserStimulus to adjust stimuli settings.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
3-128 Customizing the Test Bench Setting a Postfix for Reference Signal Names Reference signal data is represented as arrays in the generated test bench
code. The string specified by Test bench reference postfix is appended to the generated signal names. The default string is _ref. You can set the postfix string
to a value other than _ref. To change the string: 1 Select the Test Bench pane in the Generate HDL dialog box. 2 Within the Test Bench pane, select the
Configuration subpane. 3 Enter a new string in the Test bench reference postfix field, as shown in the following figure. 3-129 3 Generating HDL Code for a
Filter Design Command Line Alternative: Use the generatehdl and generatetb functions with the property TestBenchReferencePostFix to change the postfix
string. Generating HDL Cosimulation Blocks for Use with HDL Simulators The coder supports generation of Simulink HDL Cosimulation block(s).
You can use the generated HDL Cosimulation blocks to cosimulate your filter design using Simulink and EDA Simulator LinkTM, in conjunction with an
3-130 Customizing the Test Bench HDL simulator. To use this feature, your installation must include one or more of the following: EDA Simulator Link for
use with Mentor GraphicsModelSim EDA Simulator Link for use with Cadence Incisive EDA Simulator Link for use with Synopsys DiscoveryTM
The generated HDL Cosimulation blocks are configured to conform to the port and data type interface of the filter selected for code generation. By
connecting an HDL Cosimulation block to a Simulink model in place of the filter, you can cosimulate your design with the desired HDL simulator. To
generate HDL Cosimulation blocks: 1 Select the Test Bench pane in the Generate HDL dialog box. 2 Select the Cosimulation blocks option.
When this option is selected, if your installation is licensed for one or more of the HDL simulation products listed previously, the coder generates and opens a
Simulink model that contains an HDL Cosimulation block for each licensed product. 3 If you want to generate HDL Cosimulation blocks only (without
generating HDL code), deselect HDL test bench. The following figure shows both HDL test bench and Cosimulation blocks selected. 3-131 3 Generating HDL
Code for a Filter Design 4 In the Generate HDL dialog box, click Generate to generate HDL and test bench code. 5 In addition to the usual code files, the
coder generates a Simulink model containing one or more HDL Cosimulation blocks.
The coder generates an HDL Cosimulation block for each EDA Simulator Link product that you have installed. The following figure shows a model
containing three HDL Cosimulation blocks, one for each of the supported EDA Simulator Link types. 3-132 Customizing the Test Bench 6 The generated
model is untitled and exists in memory only. Be sure to save it to an appropriate folder if you want to preserve the model and blocks for use in future sessions.
See the "Define the HDL Cosimulation Block Interface for Component Simulation" section of the EDA Simulator Link documentation for information on
timing, latency, data typing, frame-based processing, and other issues that may be of concern to you when setting up an HDL cosimulation. Command Line
Alternative: Use the generatetb function with the property GenerateCoSimBlock to generate HDL Cosimulation blocks. Generating a Simulink Model for
Cosimulation with an HDL Simulator Note To use this feature, your installation must include for one or both of the following: EDA Simulator Link for use
with Mentor GraphicsModelSim EDA Simulator Link for use with Cadence Incisive 3-133 3 Generating HDL Code for a Filter Design The coder supports
generation of a Simulink model, configured for both Simulink simulation of your filter design, and cosimulation of your design with an HDL simulator. The
generated model includes: A behavioral model of the filter design, realized in a Simulink subsystem.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The subsystem includes a Digital Filter block, generated by the realizemodel function of the Filter Design Toolbox. A corresponding HDL Cosimulation
block.
The coder configures this block to cosimulate the filter design using Simulink with either of the following: - EDA Simulator Link for use with Mentor
GraphicsModelSim EDA Simulator Link for use with Cadence Incisive Test input data, calculated from the test bench stimulus you specify. The coder stores
the test data in the model workspace variable inputdata. A From Workspace block routes test data to the filter subsystem and HDL Cosimulation blocks. A
Scope block that lets you observe and compare the test input signal, the outputs of the Filter block and the HDL cosimulation, and the difference (error)
between these two outputs. Generating the Model Generation of a cosimulation model requires registered inputs and/or outputs (see "Limitations" on page
3-141). Before generating the model, make sure your model meets this requirement, as follows: 1 Select the Global Settings pane the Generate HDL dialog
box. 2 In the Global Settings pane, click on the Ports tab. Port options appear. 3-134 Customizing the Test Bench 3 Select one or both of the following
options: Add input register Add output register The coder selects both options, as shown in the following figure. To generate the model: 1 In the Generate
HDL dialog box, configure other code generation and test bench parameters as required by your design.
2 Select the Test bench pane of the Generate HDL dialog box. 3 Select the Cosimulation model for use with: option. Selecting this option enables the adjacent
drop-down menu, as shown in the following figure. 3-135 3 Generating HDL Code for a Filter Design 4 The drop-down menu selects which type of HDL
Cosimulation block is to be used in the generated model. Select either Mentor Graphics ModelSim (the default) or Cadence Incisive.
In the following figure, the cosimulation model type is Mentor Graphics ModelSim, and the stimulus signal isWhite noise response . 3-136 Customizing the
Test Bench 5 In the Generate HDL dialog box, click Generate to generate HDL and test bench code. In addition to the usual code files, the coder generates
and opens a Simulink model. The following figure shows the model generated from the coder configuration shown in the previous step. 3-137 3 Generating
HDL Code for a Filter Design 6 The generated model is untitled and exists in memory only.
Be sure to save it to an appropriate folder if you want to preserve the model and blocks for use in future sessions. The documentation for EDA Simulator Link
contains information on timing, latency, data typing, frame-based processing, and other issues that may be of concern to you when setting up an HDL
cosimulation. You can access this information using one of the following links: EDA Simulator Linkfor use with Mentor Graphics ModelSim: EDA
Simulator Link for use with Cadence Incisive: Details of the Generated Model The generated model contains the following blocks: Test Stimulus: This From
Workspace block routes test data in the model workspace variable inputdata to the filter subsystem and HDL Cosimulation blocks. 3-138 Customizing the Test
Bench Filter: This subsystem realizes a behavioral model of the filter design. HDL Cosimulation: This block cosimulates the generated HDL code. The
table HDL Cosimulation Block Settings on page 3-139 describes how the block parameters are configured by Simulink HDL CoderTM. Reset Delay: The
Tcl commands specified in the HDL Cosimulation block apply the reset signal. Reset is high at 0 ns and low at 22 ns (before the third rising clock edge). The
Simulink simulation starts feeding the input at 0, 10, 20 ns. The Reset Delay block adds a delay such that the first sample is available to the RTL simulation
when it is ready after the reset is applied.
HDL Latency: This represents the difference between the latency of the RTL simulation and the Simulink behavioral block.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Error: Computes the difference between the outputs of the Filter block and the HDL Cosimulation block . Abs: Absolute value of the error computation.
Error margin:: Indicator comparing the Absolute value of the error with the test bench error margin value (see "Setting an Error Margin for Optimized Filter
Code" on page 3-125). Scope: Displays the input signal, outputs from the Filter block and the HDL Cosimulation blocks, and the difference (if any) between
the two. Start HDL Simulator button: Launches your HDL cosimulation software. HDL Cosimulation Block Settings Pane Ports Settings Port names: same
as those in the generated code for the filter. Input/Ouput data types: Inherit Input sample time: Inherit Output sample time: Same as Simulink fixed step size.
Clocks Clock port name: same as that in the generated code for the filter. 3-139 3 Generating HDL Code for a Filter Design HDL Cosimulation Block
Settings (Continued) Pane Settings Active clock edge: Rising Period: same as the Simulink sample time.
Timescales Connection 1 second in Simulink corresponds to 1 tick in the HDL simulator Connection Mode: Full Simulation Connection Method: Shared
memory Tcl (Pre-simulation commands) force /Hlp/clk_enable 1; force /Hlp/reset 1 0 ns, 0 22 ns; puts ----------------------------------------puts "Running
Simulink Cosimulation block."; puts [clock format [clock seconds]] force /Hlp/reset 1 puts [clock format [clock seconds]] Tcl (Post-simulation commands)
Generated Model Settings. The generated model has the following non-default settings: Solver: Discrete (no continuous states). Solver Type: Fixed-step.
Stop Time: Ts * StimLen, where Ts is the Simulink sample time and StimLen is the stimulus length.
Sample Time Colors: enabled Port Data Types: enabled Hardware Implementation: ASIC/FPGA 3-140 Customizing the Test Bench Limitations A
correct cosimulation requires that outputs from the generated HDL code are synchronous with the clock. Before generating code, make sure that one or both
of the following options are selected: - Add input register Add output register If you do not select either of these options, the coder terminates model
generation with an error. The process of code generation will complete, however. The coder does not support generation of a cosimulation model when the
target language is Verilog and data of type double is generated. Command Line Alternative Use the generatehdl function, passing in one of the following
values for the property GenerateCosimModel: generatehdl(filterObj, 'GenerateCosimModel', 'Incisive'); generatehdl(filterObj, 'GenerateCosimModel',
'ModelSim'); 3-141 3 Generating HDL Code for a Filter Design Generating the HDL Code To initiate HDL code generation for a filter and its test bench,
click Generate on the Generate HDL dialog box.
As code generation proceeds, a sequence of messages similar to the following appears in the MATLAB Command Window: ### Starting VHDL code
generation process for filter: iir ### Generating: D:\hdlfilter_tutorials\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir
VHDL architecture ### First-order section, # 1 ### Second-order section, # 2 ### Second-order section, # 3 ### HDL latency is 3 samples ### Successful
completion of VHDL code generation process for filter: iir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating
input stimulus; length 2172 samples. ### Generating: D:\hdlfilter_tutorials\hdlsrc\iir_tb.vhd ### Please wait . ### Done generating VHDL test bench. The
messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB
Editor. Note The message text varies based on your customization settings (file names and location, test bench type, and so on) and the length of the input
stimulus samples varies from filter to filter.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
For example, the value 2172 in the preceding message sequence is not fixed; the value is dependent on the filter under test. 3-142 Generating Scripts for EDA
Tools Generating Scripts for EDA Tools In this section.
"Overview" on page 3-143 "Defaults for Script Generation" on page 3-143 "Custom Script Generation" on page 3-144 "Properties for Controlling Script
Generation" on page 3-145 "Controlling Script Generation with the EDA Tool Scripts Dialog Box" on page 3-148 "Mixed-Language Scripts" on page 3-157
Overview The coder supports generation of script files for third-party Electronic Design Automation (EDA) tools. These scripts let you compile and simulate
generated HDL code and/or synthesize generated HDL code. Using the defaults, you can automatically generate scripts for the following tools: Mentor
Graphics ModelSim SE/PE HDL simulator The Synplify family of synthesis tools Defaults for Script Generation By default, script generation takes place
automatically, as part of the code and test bench generation process. All script files are generated in the target folder. When HDL code is generated for a
filter Hd, the coder writes the following script files: Hd_compile.do: Mentor Graphics ModelSim compilation script. This script contains commands to
compile the generated filter code, but not to simulate it. 3-143 3 Generating HDL Code for a Filter Design Hd_synplify.tcl: Synplify synthesis script When
test bench code is generated for a filter Hd, the coder writes the following script files: Hd_tb_compile.do: Mentor Graphics ModelSim compilation script.
This script contains commands to compile the generated filter and test bench code. Hd_tb_sim.do: Mentor Graphics ModelSim simulation script. This script
contains commands to run a simulation of the generated filter and test bench code. Custom Script Generation You can enable or disable script generation and
customize the names and content of generated script files using either of the following methods: Use the generatehdl or generatetb functions, and pass in the
appropriate property name/property value arguments, as described in "Properties for Controlling Script Generation" on page 3-145.
Set script generation options in the EDA Tool Scripts dialog box, as described in "Controlling Script Generation with the EDA Tool Scripts Dialog Box" on
page 3-148. Structure of Generated Script Files A generated EDA script consists of three sections, which are generated and executed in the following order: 1
An initialization (Init) phase. The Init phase performs any required setup actions, such as creating a design library or a project file. Some arguments to the
Init phase are implicit, for example, the top-level entity or module name. 2 A command-per-file phase (Cmd).
This phase of the script is called iteratively, once per generated HDL file or once per signal. On each call, a different file or signal name is passed in. 3-144
Generating Scripts for EDA Tools 3 A termination phase (Term). This is the final execution phase of the script. One application of this phase is to execute a
simulation of HDL code that was compiled in the Cmd phase. The Term phase takes no arguments. The coder generates scripts by passing format strings to
the fprintf function. Using the GUI options (or generatehdl and generatetb properties) summarized in the following sections, you can pass in customized
format strings to the script generator. Some of these format strings take arguments, such as the top-level entity or module name, or the names of the VHDL or
Verilog files in the design. You can use any legal fprintf formatting characters.
For example, '\n' inserts a newline into the script file. Properties for Controlling Script Generation This section describes how to set properties in the
generatehdl or generatetb functions to enable or disable script generation and customize the names and content of generated script files. Enabling and
Disabling Script Generation The EDAScriptGeneration property controls the generation of script files.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
By default, EDAScriptGeneration is set 'on'. To disable script generation, set EDAScriptGeneration to 'off', as in the following example.
generatehdl(Hd,'EDAScriptGeneration','off') Customizing Script Names When HDL code is generated, the code generator forms script names by appending a
postfix string to the filter name Hd. When test bench code is generated, the code generator forms script names by appending a postfix string to the test bench
name testbench_tb. The postfix string depends on the type of script (compilation, simulation, or synthesis) being generated. The default postfix strings are
shown in the following table. For each type of script, you can define your own postfix using the associated property.
3-145 3 Generating HDL Code for a Filter Design Script Type Compilation Simulation Synthesis Property 'HDLCompileFilePostfix' 'HDLSimFilePostfix'
'HDLSynthFilePostfix' Default Value '_compile.do' '_sim.do' '_synplify.tcl' The following command generates VHDL code for the filter object myfilt,
specifying a custom postfix string for the compilation script. The name of the generated compilation script will be myfilt_test_compilation.
do. generatehdl(myfilt, 'HDLCompileFilePostfix', '_test_compilation.do') Customizing Script Code Using the property name/property value pairs summarized
in the following table, you can pass in customized format strings to generatehdl or generatetb. The properties are named according to the following
conventions: Properties that apply to the initialization (Init) phase are identified by the substring Init in the property name. Properties that apply to the
command-per-file phase (Cmd) are identified by the substring Cmd in the property name.
Properties that apply to the termination (Term) phase are identified by the substring Term in the property name. Property Name and Default Name:
'HDLCompileInit' Default:'vlib work\n' Name: 'HDLCompileVHDLCmd' Default: 'vcom %s %s\n' Description Format string passed to fprintf to write the Init
section of the compilation script. Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the
contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). 3-146
Generating Scripts for EDA Tools Property Name and Default Name: 'HDLCompileVerilogCmd' Default: 'vlog %s %s\n' Description Format string passed to
fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the 'SimulatorFlags' property and the file
name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). Format string passed to fprintf to write the termination portion
of the compilation script. Format string passed to fprintf to write the initialization section of the simulation script.
Name:'HDLCompileTerm' Default:'' Name: 'HDLSimInit' Default: ['onbreak resume\n',. 'onerror resume\n'] Name: 'HDLSimCmd' Default: 'vsim -novopt
work.%s\n' Name: 'HDLSimViewWaveCmd' Default: 'add wave sim:%s\n' Name: 'HDLSimTerm' Default: 'run -all\n' Name: 'HDLSynthInit' Default: 'project
-new %s.prj\n' Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity name. Format string
passed to fprintf to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit arguments. Format string
passed to fprintf to write the Term portion of the simulation script. Format string passed to fprintf to write the Init section of the synthesis script. The default
string is a synthesis project creation command.
The implicit argument is the top-level module or entity name. 3-147 3 Generating HDL Code for a Filter Design Property Name and Default Name:
'HDLSynthCmd' Default: 'add_file %s\n' Name: 'HDLSynthTerm' Default: ['set_option -technology VIRTEX4\n',.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
'set_option -part XC4VSX35\n',. 'set_option -synthesis_onoff_pragma 0\n',. 'set_option -frequency auto\n',.
'project -run synthesis\n'] Description Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is the file name of the
entity or module. Format string passed to fprintf to write the Term section of the synthesis script. generatehdl Example The following example specifies a
Mentor Graphics ModelSim command for the Init phase of a compilation script for VHDL code generated from the filter myfilt. generatehdl(myfilt,
'HDLCompileInit', 'vlib mydesignlib\n') The following code shows the resultant script, myfilt_compile.
do. vlib mydesignlib vcom myfilt.vhd Controlling Script Generation with the EDA Tool Scripts Dialog Box The EDA Tool Scripts dialog box, a subdialog of
the Generate HDL dialog box, lets you set all options that control generation of script files. These options correspond to the properties described in
"Properties for Controlling Script Generation" on page 3-145. To view and set options in the EDA Tool Scripts dialog box: 1 Open the Generate HDL dialog
box. 2 Click the EDA Tool Scripts tab in the Generate HDL dialog box. 3-148 Generating Scripts for EDA Tools The EDA Tool scripts dialog box displays,
with the Compilation script options group selected, as shown in the following figure. 3 The Generate EDA scripts option controls the generation of script files.
By default, this option is selected. 3-149 3 Generating HDL Code for a Filter Design If you want to disable script generation, clear this option.
4 The list on the left of the dialog box lets you select from several categories of options. Select a category and set the options as desired. The categories are
Compilation script: options related to customizing scripts for compilation of generated VHDL or Verilog code. See "Compilation Script Options" on page
3-151 for further information. Simulation script: options related to customizing scripts for HDL simulators. See "Simulation Script Options" on page 3-153
for further information. Synthesis script: options related to customizing scripts for synthesis tools. See "Synthesis Script Options" on page 3-155 for further
information. 3-150 Generating Scripts for EDA Tools Compilation Script Options The following figure shows the Compilation script pane, with all options set
to their default values. The following table summarizes the Compilation script options.
3-151 3 Generating HDL Code for a Filter Design Option and Default Compile file postfix '_compile.do' Description Postfix string appended to the filter
name or test bench name to form the script file name. Format string passed to fprintf to write the Init section of the compilation script. Format string passed
to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the Simulator flags option and the file name
of the current entity or module.
To omit the flags, set Simulator flags to '' (the default). See also "Setting Simulator Flags for Compilation Scripts" on page 3-152. Format string passed to
fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the Simulator flags option and the file name
of the current entity or module. To omit the flags, set Simulator flags to '' (the default).
See also "Setting Simulator Flags for Compilation Scripts" on page 3-152. Format string passed to fprintf to write the termination portion of the compilation
script. Name: Compile initialization Default:'vlib work\n' Name: Compile command for VHDL Default: 'vcom %s %s\n' Name: Compile command for Verilog
Default: 'vlog %s %s\n' Name:Compile termination Default:'' Setting Simulator Flags for Compilation Scripts. You have the option of inserting simulator
flags into your generated compilation scripts. For example, you might need to specify a specific compiler version.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
To specify the flags: 1 Click Test Bench in the Generate HDL dialog box. 2 Type the flags of interest in the Simulator flags field. In the following figure, the
dialog box specifies that the Mentor Graphics ModelSim simulator use the -93 compiler option for compilation. 3-152 Generating Scripts for EDA Tools
Command Line Alternative: Use the generatetb function's SimulatorFlags property to specify the type of test bench files to be generated. Simulation Script
Options The following figure shows the Simulation script pane, with all options set to their default values.
3-153 3 Generating HDL Code for a Filter Design The following table summarizes the Simulation script options. 3-154 Generating Scripts for EDA Tools
Option and Default Simulation file postfix '_sim.do' Description Postfix string appended to the filter name or test bench name to form the script file name.
Format string passed to fprintf to write the initialization section of the simulation script. Simulation initialization Default: ['onbreak resume\n',. 'onerror
resume\n'] Simulation command Default: 'vsim -novopt work.%s\n' Simulation waveform viewing command Default: 'add wave sim:%s\n' Simulation
termination Default: 'run -all\n' Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity
name. Format string passed to fprintf to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit
arguments.
Format string passed to fprintf to write the Term portion of the simulation script. Synthesis Script Options The following figure shows the Synthesis script
pane, with all options set to their default values. 3-155 3 Generating HDL Code for a Filter Design The following table summarizes the Synthesis script
options. 3-156 Generating Scripts for EDA Tools Option Name and Default Name: Synthesis initialization Default: 'project -new %s.prj\n' Name: Synthesis
command Default: 'add_file %s\n' Name: Synthesis termination Default: ['set_option -technology VIRTEX4\n',.
'set_option -part XC4VSX35\n',. 'set_option -synthesis_onoff_pragma 0\n',. 'set_option -frequency auto\n',. 'project -run synthesis\n'] Description Format
string passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command.
The implicit argument is the top-level module or entity name. Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is
the file name of the entity or module. Format string passed to fprintf to write the Term section of the synthesis script. Mixed-Language Scripts The coder
allows most combinations of filter and test bench languages. For example, it is possible to generate VHDL filter code and a Verilog test bench file, as in the
following commands: generatehdl(myfilt, 'TargetLanguage', 'VHDL') generatetb(myfilt, 'Verilog') The following listing shows the generated test bench
compilation script for the above case (myfilt_tb_compile.do). The script contains the correct language-specific compile command for the generated filter and
test bench code. vlib work vcom myfilt.vhd vlog myfilt_tb.
v 3-157 3 Generating HDL Code for a Filter Design The two simulation compile Cmd properties ('HDLCompileVHDLCmd' and 'HDLCompileVerilogCmd')
allow you to customize the compilation command for each supported target language. You can specify generation of both VHDL and Verilog test bench code,
via the Generate HDL dialog box. In this case, the test bench compilation script defaults to the Verilog compilation command. 3-158 4 Optimizing Generated
HDL Code "Setting Optimizations" on page 4-2 "Optimizing Generated Code for HDL" on page 4-3 "Optimizing Coefficient Multipliers" on page 4-4
"Multiplier Input and Output Pipelining for FIR Filters" on page 4-6 "Optimizing Final Summation for FIR Filters" on page 4-8 "Speed vs.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Area Optimizations for FIR Filters" on page 4-10 "Distributed Arithmetic for FIR Filters" on page 4-27 "Optimizing the Clock Rate with Pipeline
Registers" on page 4-40 "Setting Optimizations for Synthesis" on page 4-42 4 Optimizing Generated HDL Code Setting Optimizations This chapter describes
options for optimizing generated filter HDL code. You can choose to apply a general code optimization, or select specific options for optimizing multipliers,
optimizing the final summation method used for FIR filters, choosing serial or distributed architectures for FIR filters, and use of pipeline registers. Code
optimization options appear in the Filter architecture tab of the Generate HDL dialog box, as shown below. Note Some of the optimization settings generate
HDL code that produces numeric results that differ from results produced by the original filter function. 4-2 Optimizing Generated Code for HDL Optimizing
Generated Code for HDL By default, generated HDL code is bit-compatibile with the numeric results produced by the original filter object. The Optimize for
HDL option generates HDL code that is slightly optimized for clock speed or space requirements.
However, note that this optimization causes the coder to Make tradeoffs concerning data types Avoid extra quantization Generate code that produces
numeric results that are different than the results produced by the original filter object To optimize generated code for clock speed or space requirements: 1
Select Optimize for HDL in the Filter architecture pane of the Generate HDL dialog box. 2 Consider setting an error margin for the generated test bench. The
error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin, a Select the Test Bench pane
in the Generate HDL dialog box. Then click on the Configuration tab.
b Specify an integer in the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the
coder issues a warning. 3 Continue setting other options or click Generate to initiate code generation. Command Line Alternative: Use the generatehdl and
generatetb functions with the property OptimizeForHDL to enable the optimizations described above. 4-3 4 Optimizing Generated HDL Code Optimizing
Coefficient Multipliers By default, the coder produces code that includes coefficient multiplier operations. If necessary, you can optimize these operations
such that they decrease the area used and maintain or increase clock speed.
You do this by instructing the coder to replace multiplier operations with additions of partial products produced by canonical signed digit (CSD) or factored
CSD techniques. These techniques minimize the number of addition operations required for constant multiplication by representing binary numbers with a
minimum count of nonzero digits. The amount of optimization you can achieve is dependent on the binary representation of the coefficients used. Note The
coder does not use coefficient multiplier operations for multirate filters. Therefore, the Coefficient multipliers options described below are disabled for
multirate filters. To optimize coefficient multipliers (for nonmultirate filter types), 1 Select CSD or Factored-CSD from the Coefficient multipliers menu in the
Filter architecture pane of the Generate HDL dialog box. 2 Consider setting an error margin for the generated test bench to account for numeric differences.
The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin, a Select the Test Bench
pane in the Generate HDL dialog box. Then click on the Configuration tab.
b Specify an integer in the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the
coder issues a warning. 3 Continue setting other options or click Generate to initiate code generation.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
If you are generating code for an FIR filter, see "Multiplier Input and Output Pipelining for FIR Filters" on page 4-6 for information on a related
optimization. 4-4 Optimizing Coefficient Multipliers Command Line Alternative: Use the generatehdl and generatetb functions with the property
CoeffMultipliers to optimize coefficient multipliers with CSD techniques. 4-5 4 Optimizing Generated HDL Code Multiplier Input and Output Pipelining for
FIR Filters If you choose to retain multiplier operations for a FIR filter, you can achieve significantly higher clock rates by adding pipeline stages at
multiplier inputs or outputs. The following figure shows the GUI options for multiplier pipelining options.To enable these options, Coefficient multipliers to
Multiplier. Multiplier input pipeline: To add pipeline stages before each multiplier, enter the desired number of stages as an integer greater than or equal to
0. Multiplier output pipeline: To add pipeline stages after each multiplier, enter the desired number of stages as an integer greater than or equal to 0. 4-6
Multiplier Input and Output Pipelining for FIR Filters Command Line Alternative: Use the generatehdl and generatetb functions with the
MultiplierInputPipeline and MultiplierOutputPipeline properties to specify multiplier pipelining for FIR filters.
4-7 4 Optimizing Generated HDL Code Optimizing Final Summation for FIR Filters If you are generating HDL code for an FIR filter, consider optimizing the
final summation technique to be applied to the filter. By default, the coder applies linear adder summation, which is the final summation technique discussed
in most DSP text books. Alternatively, you can instruct the coder to apply tree or pipeline final summation. When set to tree mode, the coder creates a final
adder that performs pair-wise addition on successive products that execute in parallel, rather than sequentially. Pipeline mode produces results similar to
tree mode with the addition of a stage of pipeline registers after processing each level of the tree.
In comparison, The number of adder operations for linear and tree mode are the same, but the timing for tree mode might be significantly better due to
summations occurring in parallel. Pipeline mode optimizes the clock rate, but increases the filter latency by the base 2 logarithm of the number of products
to be added, rounded up to the nearest integer. Linear mode ensures numeric accuracy in comparison to the original filter object. Tree and pipeline modes
can produce numeric results that differ from those produced by the filter object. To change the final summation to be applied to an FIR filter, 1 Select one of
the following options in the Filter architecture pane of the Generate HDL dialog box: For.
Linear mode (the default) Tree mode Pipeline mode Select. Linear from the FIR adder style menu Tree from the FIR adder style menu The Add pipeline
registers check box 2 If you specify tree or pipelined mode, consider setting an error margin for the generated test bench to account for numeric differences.
The error 4-8 Optimizing Final Summation for FIR Filters margin is the number of least significant bits the test bench will ignore when comparing the results.
To set an error margin, a Select the Test Bench pane in the Generate HDL dialog box. Then click on the Configuration tab. b Specify an integer in the Error
margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning. 3 Continue
setting other options or click Generate to initiate code generation. Command Line Alternative: Use the generatehdl and generatetb functions with the property
FIRAdderStyle or AddPipelineRegisters to optimize the final summation for FIR filters. 4-9 4 Optimizing Generated HDL Code Speed vs. Area Optimizations
for FIR Filters In this section.
"Overview of Speed vs. Area Optimizations" on page 4-10 "Parallel and Serial Architectures" on page 4-11 "Specifying Speed vs.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Area Tradeoffs via generatehdl Properties" on page 4-15 "Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box" on page 4-19
Overview of Speed vs. Area Optimizations The coder provides options that extend your control over speed vs. area tradeoffs in the realization of FIR filter
designs. To achieve the desired tradeoff, you can either specify a fully parallel architecture for generated HDL filter code, or choose one of several serial
architectures. Supported architectures are described in "Parallel and Serial Architectures" on page 4-11. The coder supports the full range of parallel and
serial architecture options via properties passed in to the generatehdl command, as described in "Specifying Speed vs. Area Tradeoffs via generatehdl
Properties" on page 4-15. Alternatively, you can use the Architecture pop-up menu on the Generate HDL dialog box to choose parallel and serial architecture
options, as described in "Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box" on page 4-19.
The following table summarizes the filter types that are available for parallel and serial architecture choices. 4-10 Speed vs. Area Optimizations for FIR
Filters Architecture Fully parallel (default) Fully serial Available for Filter Types. All filter types that are supported for HDL code generation dfilt.dffir
dfilt.
dfsymfir dfilt.dfasymfir mfilt.firdecim mfilt.firinterp dfilt.dffir dfilt.
dfsymfir dfilt.dfasymfir mfilt.firdecim dfilt.dffir dfilt.dfsymfir dfilt.dfasymfir Partly serial Cascade serial Note The coder also supports distributed
arithmetic (DA), another highly efficient architecture for realizing FIR filters. See "Distributed Arithmetic for FIR Filters" on page 4-27 for information about
how to use this architecture.) Parallel and Serial Architectures Fully Parallel Architecture This is the default option. A fully parallel architecture uses a
dedicated multiplier and adder for each filter tap; all taps execute in parallel. A fully parallel architecture is optimal for speed.
However, it requires more multipliers and adders than a serial architecture, and therefore consumes more chip area. 4-11 4 Optimizing Generated HDL Code
Serial Architectures Serial architectures reuse hardware resources in time, saving chip area. The coder provides a range of serial architecture options,
summarized below. All of these architectures have a latency of one clock period (see "Latency in Serial Architectures" on page 4-13). The available serial
architecture options are Fully serial: A fully serial architecture conserves area by reusing multiplier and adder resources sequentially. For example, a four-
tap filter design would use a single multiplier and adder, executing a multiply/accumulate operation once for each tap. The multiply/accumulate section of the
design runs at four times the filter's input/output sample rate. This saves area at the cost of some speed loss and higher power consumption. In a fully serial
architecture, the system clock runs at a much higher rate than the sample rate of the filter. Thus, for a given filter design, the maximum speed achievable by a
fully serial architecture will be less than that of a parallel architecture.
Partly serial: Partly serial architectures cover the full range of speed vs. area tradeoffs that lie between fully parallel and fully serial architectures. In a
partly serial architecture, the filter taps are grouped into a number of serial partitions. The taps within each partition execute serially, but the partitions
execute in parallel with respect to one another. The outputs of the partitions are summed at the final output.
When you select a partly serial architecture for a FIR filter, you can define the serial partitioning in any the following ways: - Define the serial partitions
directly, as a vector of integers. Each element of the vector specifies the length of the corresponding partition. Specify the desired hardware folding factor ff,
an integer greater than 1.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Given the folding factor, the coder computes the serial partition and the number of multipliers. Specify the desired number of multipliers nmults, an integer
greater than 1.
Given the number of multipliers, the coder computes the serial partition and the folding factor. The Generate HDL dialog box lets you specify a partly serial
architecture in terms of any of these three parameters, and view how a change in 4-12 Speed vs. Area Optimizations for FIR Filters one parameter interacts
with the other two. The coder also provides hdlgetserialpartition , an informational function that helps you define an optimal serial partition for an FIR filter.
Cascade-serial: A cascade-serial architecture closely resembles a partly serial architecture. As in a partly serial architecture, the filter taps are grouped
into a number of serial partitions that execute in parallel with respect to one another. However, the accumulated output of each partition is cascaded to the
accumulator of the previous partition. The output of all partitions is therefore computed at the accumulator of the first partition. This technique is termed
accumulator reuse. No final adder is required, which saves area.
The cascade-serial architecture requires an extra cycle of the system clock to complete the final summation to the output. Therefore, the frequency of the
system clock must be increased slightly with respect to the clock used in a noncascade partly serial architecture. To generate a cascade-serial architecture,
you specify a partly serial architecture with accumulator reuse enabled (see "Specifying Speed vs. Area Tradeoffs via generatehdl Properties" on page 4-15. If
you do not specify the serial partitions, the coder automatically selects an optimal partitioning. Latency in Serial Architectures Serialization of a filter
increases the total latency of the design by one clock cycle. The serial architectures use an accumulator (an adder with a register) to sequentially add the
products. An additional final register is used to store the summed result of all the serial partitions. The operation requires an extra clock cycle. Holding Input
Data in a Valid State In serial filters, data can be delivered to the outputs N cycles (N ]= 2) later than the inputs.
You can use the Hold input data between samples test bench option (or the HoldInputDataBetweenSamples CLI property) to determine how long (in terms of
clock cycles) input data values are held in a valid state, as follows: When Hold input data between samples is selected (the default), input data values are
held in a valid state across N clock cycles. 4-13 4 Optimizing Generated HDL Code When Hold input data between samples is cleared, data values are held
in a valid state for only one clock cycle. For the nextN-1 cycles, data is in an unknown state (expressed as 'X') until the next input sample is clocked in. The
following figure shows the Test Bench pane of the Generate HDL dialog box with Hold input data between samples set to its default setting. See also
HoldInputDataBetweenSamples.
4-14 Speed vs. Area Optimizations for FIR Filters Specifying Speed vs. Area Tradeoffs via generatehdl Properties By default, generatehdl generates filter
code using a fully parallel architecture. If you want to generate FIR filter code with a fully parallel architecture, you do not need to specify this explicitly.
Two properties are provided to specify serial architecture options when generating code via generatehdl: 'SerialPartition': This property specifies the serial
partitioning of the filter.
'ReuseAccum': This property enables or disables accumulator reuse. The table below summarizes how to set these properties to generate the desired
architecture. The table is followed by several examples. To Generate This Architecture. Fully parallel Fully serial Partly serial Set SerialPartition to. Set
ReuseAccum to. Omit this property N, where N is the length of the filter [p1 p2 p3.pN] : a vector of integers having N elements, where N is the number of
serial Omit this property Not specified, or 'off' 'off' partitions.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the filter.
When you define the partitioning for a partly serial architecture, consider the following: We recommend that the filter length should be divided as uniformly
as possible into a vector of length equal to the number of multipliers intended. For example, if your design requires a filter of length 9 with 2 multipliers, the
recommended partition is [5 4]. If your design requires 3 multipliers, the 4-15 4 Optimizing Generated HDL Code To Generate This Architecture. Set
SerialPartition to. Set ReuseAccum to. recommended partition is[3 3 3] rather than some less uniform division such as [1 4 4] or [3 4 2]. If your design is
constrained by the need to compute each output value (corresponding to each input value) in an exact number N of clock cycles, use N as the largest partition
size and partition the other elements as uniformly as possible. For example, if the filter length is 9 and your design requires exactly 4 cycles to compute the
output, define the partition as [4 3 2]. This partition executes in 4 clock cycles, at the cost of 3 multipliers. You can also specify a serial architecture in terms
of a desired hardware folding factor, or in terms of the optimal number of multiplers.
See hdlgetserialpartition for detailed information. 4-16 Speed vs. Area Optimizations for FIR Filters To Generate This Architecture. Cascade-serial with
explicitly specified partitioning Set SerialPartition to. Set ReuseAccum to.
[p1 p2 p3.pN]: a vector of integers having N elements, where N is the number of serial 'on' partitions. Each element of the vector specifies the length of the
corresponding partition. The sum of the vector elements must be equal to the length of the filter. The values of the vector elements must be in descending
order, except that the last two elements must be equal.
For example, for a filter of length 9, partitions such as[5 4] or [4 3 2] would be legal, but the partitions [3 3 3] or [3 2 4] would raise an error at code
generation time. Omit this property 'on' Cascade-serial with automatically optimized partitioning Specifying Parallel and Serial FIR Architectures in
generatehdl The following examples show the use of the 'SerialPartition' and 'ResuseAccum' properties in generating code with the generatehdl function. All
examples assume that a direct-form FIR filter has been created in the workspace as follows: Hd = design(fdesign.lowpass('N,Fc',8,.4)); Hd.arithmetic =
'fixed'; In this example, a fully parallel architecture is generated (by default). generatehdl(Hd, 'Name','FullyParallel'); ### Starting VHDL code generation
process for filter: FullyParallel ### Generating: D:\Work\test\hdlsrc\FullyParallel.vhd ### Starting generation of FullyParallel VHDL entity ### Starting
generation of FullyParallel VHDL architecture ### HDL latency is 2 samples 4-17 4 Optimizing Generated HDL Code ### Successful completion of VHDL
code generation process for filter: FullyParallel In this example, a fully serial architecture is generated. Notice that the system clock rate is nine times the
filter's sample rate. Also, the HDL latency reported is one sample greater than in the previous (parallel) example.
generatehdl(Hd,'SerialPartition',9, 'Name','FullySerial') ### Starting VHDL code generation process for filter: FullySerial ### Generating:
D:\Work\test\hdlsrc\FullySerial.vhd ### Starting generation of FullySerial VHDL entity ### Starting generation of FullySerial VHDL architecture ### Clock
rate is 9 times the input sample rate for this architecture. ### HDL latency is 3 samples ### Successful completion of VHDL code generation process for
filter: FullySerial In this example, a partly serial architecture with three equal partitions is generated. generatehdl(Hd,'SerialPartition',[3 3 3], 'Name',
'PartlySerial') ### Starting VHDL code generation process for filter: PartlySerial ### Generating: D:\Work\test\hdlsrc\PartlySerial.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
vhd ### Starting generation of PartlySerial VHDL entity ### Starting generation of PartlySerial VHDL architecture ### Clock rate is 3 times the input
sample rate for this architecture. ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: PartlySerial In this
example, a cascade-serial architecture with three partitions is generated. The partitions are entered in descending order of size. Note that the clock rate is
higher than that in the previous (partly serial without accumulator reuse) example. generatehdl(Hd,'SerialPartition',[4 3 2], 'ReuseAccum',
'on','Name','CascadeSerial') ### Starting VHDL code generation process for filter: CascadeSerial ### Generating: D:\Work\test\hdlsrc\CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity ### Starting generation of CascadeSerial VHDL architecture ### Clock rate is 5 times the input
sample rate for this architecture.
### HDL latency is 3 samples ### Successful completion of VHDL code generation process for filter: CascadeSerial 4-18 Speed vs. Area Optimizations for
FIR Filters In this example, a cascade-serial architecture is generated, with the partitioning automatically determined by the coder .
generatehdl(Hd,'ReuseAccum','on', 'Name','CascadeSerial') ### Starting VHDL code generation process for filter: CascadeSerial ### Generating:
D:\Work\test\hdlsrc\CascadeSerial.vhd ### Starting generation of CascadeSerial VHDL entity ### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture. ### Serial partition # 1 has 4 inputs.
### Serial partition # 2 has 3 inputs. ### Serial partition # 3 has 2 inputs. ### HDL latency is 3 samples ### Successful completion of VHDL code generation
process for filter: CascadeSerial Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box The Architecture pop-up menu, located on the
Generate HDL dialog box, lets you select parallel and serial architecture options corresponding to those described in "Parallel and Serial Architectures" on
page 4-11. The following sections describe the GUI options you need to set for each Architecture choice. Specifying a Fully Parallel Architecture The default
Architecture setting is Fully parallel, as shown in the following figure.
4-19 4 Optimizing Generated HDL Code Specifying a Fully Serial Architecture When you select the Fully serial, Architecture options, the Generate HDL
dialog box displays additional information about the filters's folding factor, number of multipliers, and serial partitioning. Since these parameters are
determined by the length of the filter, they display in a read-only format, as shown in the following figure. 4-20 Speed vs. Area Optimizations for FIR Filters
Specifying Partitions for a Partly Serial Architecture When you select the Partly serial Architecture option, the Generate HDL dialog box displays additional
information and data entry fields related to serial partitioning, as shown in the following figure. 4-21 4 Optimizing Generated HDL Code The Specified by
pulldown menu lets you decide how you define the partly serial architecture. Select one of the following options: Folding factor: The pulldown menu to the
right of Folding factor contains an exhaustive list of possible folding factors for the filter. When you select a value, the display of the current folding factor,
multiplier, and serial partition settings updates. 4-22 Speed vs. Area Optimizations for FIR Filters Multipliers: The pulldown menu to the right of Multipliers
contains an exhaustive list of possible values for the number of multipliers for the filter. When you select a value, the display of the current folding factor,
multiplier, and serial partition settings updates.
Serial partition: The pulldown menu to the right of Serial partition contains an exhaustive list of possible serial partitions for the filter. When you select a
value, the display of the current folding factor, multiplier, and serial partition settings updates.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
4-23 4 Optimizing Generated HDL Code Specifying a Cascade Serial Architecture When you select the Cascade serial Architecture option, the Generate
HDL dialog box displays the Serial partition field, as shown in the following figure. 4-24 Speed vs. Area Optimizations for FIR Filters The Specified by menu
lets you define the number and size of the serial partitions according to different criteria, as described in "Specifying Speed vs. Area Tradeoffs via generatehdl
Properties" on page 4-15. Specifying a Distributed Arithmetic Architecture The Architecture pop-up menu also includes the Distributed arithmetic (DA)
option. See "Distributed Arithmetic for FIR Filters" on page 4-27) for information about this architecture. 4-25 4 Optimizing Generated HDL Code
Interactions Between Architecture Options and Other HDL Options Selection of some Architecture menu options may change or disable other options, as
described below. When the Fully serial option is selected, the following options are set to their default values and disabled: - Coefficient multipliers Add
pipeline registers FIR adder style The Coefficient multipliers option is set to its default value and disabled.
If the filter is multirate, the Clock inputs options is set to Single and disabled. When the Partly serial option is selected: When the Cascade serial option is
selected, the following options are set to their default values and disabled: - Coefficient multipliers Add pipeline registers FIR adder style 4-26 Distributed
Arithmetic for FIR Filters Distributed Arithmetic for FIR Filters In this section. "Distributed Arithmetic Overview" on page 4-27 "Requirements and
Considerations for Generating Distributed Arithmetic Code" on page 4-29 "DALUTPartition Property" on page 4-30 "DARadix Property" on page 4-34
"Special Cases" on page 4-34 "Distributed Arithmetic Options in the Generate HDL Dialog Box" on page 4-35 Distributed Arithmetic Overview Distributed
Arithmetic (DA) is a widely-used technique for implementing sum-of-products computations without the use of multipliers. Designers frequently use DA to
build efficient Multiply-Accumulate Circuitry (MAC) for filters and other DSP applications. The main advantage of DA is its high computational efficiency.
DA distributes multiply and accumulate operations across shifters, lookup tables (LUTs) and adders in such a way that conventional multipliers are not
required. The coder supports DA in HDL code generated for several single-rate and multirate FIR filter structures (see "Requirements and Considerations for
Generating Distributed Arithmetic Code" on page 4-29 ). Only fixed-point filter designs are supported. This section briefly summarizes of the operation of
DA. Detailed discussions of the theoretical foundations of DA appear in the following publications: Meyer-Baese, U.
, Digital Signal Processing with Field Programmable Gate Arrays, Second Edition, Springer, pp 8894, 128143 White, S.A., Applications of Distributed
Arithmetic to Digital Signal Processing: A Tutorial Review. IEEE ASSP Magazine, Vol. 6, No. 3 4-27 4 Optimizing Generated HDL Code In a DA realization
of a FIR filter structure, a sequence of input data words of width W is fed through a parallel to serial shift register, producing a serialized stream of bits. The
serialized data is then fed to a bit-wide shift register. This shift register serves as a delay line, storing the bit serial data samples. The delay line is tapped
(based on the input word size W), to form a W-bit address that indexes into a lookup table (LUT). The LUT stores all possible sums of partial products over
the filter coefficients space.
The LUT is followed by a shift and adder (scaling accumulator) that adds the values obtained from the LUT sequentially. A table lookup is performed
sequentially for each bit (in order of significance starting from the LSB). On each clock cycle, the LUT result is added to the accumulated and shifted result
from the previous cycle.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
For the last bit (MSB), the table lookup result is subtracted, accounting for the sign of the operand. This basic form of DA is fully serial, operating on one bit
at a time. If the input data sequence is W bits wide, then a FIR structure takes W clock cycles to compute the output. Symmetric and asymmetric FIR structures
are an exception, requiring W+1 cycles, because one additional clock cycle is needed to process the carry bit of the pre-adders. Improving Performance with
Parallelism The inherently bit serial nature of DA can limit throughput. To improve throughput, the basic DA algorithm can be modified to compute more
than one bit sum at a time. The number of simultaneously computed bit sums is expressed as a power of two called the DA radix.
For example, a DA radix of 2 (2^1) indicates that one bit sum is computed at a time; a DA radix of 4 (2^2) indicates that two bit sums are computed at a time,
and so on. To compute more than one bit sum at a time, the LUT is replicated. For example, to perform DA on 2 bits at a time (radix 4), the odd bits are fed to
one LUT and the even bits are simultaneously fed to an identical LUT. The LUT results corresponding to odd bits are left-shifted before they are added to the
LUT results corresponding to even bits. This result is then fed into a scaling accumulator that shifts its feedback value by 2 places.
Processing more than one bit at a time introduces a degree of parallelism into the operation, improving performance at the expense of area. The DARadix
4-28 Distributed Arithmetic for FIR Filters property lets you specify the number of bits processed simultaneously in DA (see "DARadix Property" on page
4-34). Reducing LUT Size The size of the LUT grows exponentially with the order of the filter. For a filter with N coefficients, the LUT must have 2^N values.
For higher order filters, LUT size must be reduced to reasonable levels.
To reduce the size, you can subdivide the LUT into a number of LUTs, called LUT partitions. Each LUT partition operates on a different set of taps. The
results obtained from the partitions are summed. For example, for a 160 tap filter, the LUT size is (2^160)*W bits, where W is the word size of the LUT data.
Dividing this into 16 LUT partitions, each taking 10 inputs (taps), the total LUT size is reduced to 16*(2^10)*W bits, a significant reduction. Although LUT
partitioning reduces LUT size, more adders are required to sum the LUT data. The DALUTPartition property lets you specify how the LUT is partitioned in
DA (see "DALUTPartition Property" on page 4-30 ). Requirements and Considerations for Generating Distributed Arithmetic Code The coder lets you
control how DA code is generated using the DALUTPartition and DARadix properties (or equivalent Generate HDL dialog box options). Before using these
properties, review the following general requirements, restrictions, and other considerations for generation of DA code. Supported Filter Types The coder
supports DA in HDL code generated for the following single-rate and multirate FIR filter structures: dfilt.
dffir dfilt.dfsymfir dfilt.dfasymfir 4-29 4 Optimizing Generated HDL Code mfilt.firdecim mfilt.firinterp Requirements Specific to Filter Type The
DALUTPartition and DARadix properties have certain requirements and restrictions that are specific to different filter types. These requirements are included
in the discussions of each property: "DALUTPartition Property" on page 4-30 "DARadix Property" on page 4-34 Fixed Point Quantization Required
Generation of DA code is supported only for fixed-point filter designs. Specifying Filter Precision The data path in HDL code generated for the DA
architecture is carefully optimized for full precision computations. The filter result is cast to the output data size only at the final stage when it is presented to
the output. If the FilterInternals property is set to the default (FullPrecision), numeric results obtained from simulation of the generated HDL code are bit-
true to filter results produced by the original filter object.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
If the FilterInternals property is set to SpecifyPrecision and you change filter word or fraction lengths, generated DA code may produce numeric results that
are different than the filter results produced by the original filter object.
DALUTPartition Property Syntax: 'DALUTPartition', [p1 p2. pN] DALUTPartition enables DA code generation and specifies the number and size of LUT
partitions used for DA. Specify LUT partitions as a vector of integers [p1 p2.pN] where N is the number of partitions. 4-30 Distributed Arithmetic for FIR
Filters Each vector element specifies the size of a partition.
The maximum size for an individual partition is 12. The sum of all vector elements equals the filter length FL. FL is calculated differently depending on the
filter type (see "Specifying DALUTPartition for Single-Rate Filters" on page 4-31 and "Specifying DALUTPartition for Multirate Filters" on page 4-32). To
enable generation of DA code for your filter design without LUT partitioning, specify a vector of one element, whose value is equal to the filter length, as in
the following example: filtdes = fdesign.lowpass('N,Fc,Ap,Ast',4,0.
4,0.05,0.03,'linear'); Hd = design(filtdes); Hd.arithmetic = 'fixed'; generatehdl (Hd, 'DALUTPartition', 5); Specifying DALUTPartition for Single-Rate Filters
To determine the LUT partition for one of the supported single-rate filter types, calculate FL as shown in the following table. Then, specify the partition as a
vector whose elements sum to FL. Filter Type dfilt.dffir FL = length(find(Hd.numerator~= 0)) dfilt.dfsymfir dfilt.dfasymfir Filter Length (FL) Calculation FL
= ceil(length(find(Hd.
numerator~= 0))/2) The following example shows the FL calculation and one possible partitioning for a direct form FIR filter: filtdes =
fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear'); Hd = design(filtdes,'filterstructure','dffir'); Hd.arithmetic = 'fixed'; FL =
length(find(Hd.numerator~= 0)) 4-31 4 Optimizing Generated HDL Code FL = 31 generatehdl(Hd, 'DALUTPartition',[8 8 8 7]); The following example
shows the FL calculation and one possible partitioning for a direct-form symmetric FIR filter: filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.
03,'linear'); Hd = design(filtdes,'filterstructure','dfsymfir'); Hd.arithmetic = 'fixed'; FL = ceil(length(find(Hd.numerator~= 0))/2) FL = 16 generatehdl(Hd,
'DALUTPartition',[8 8]); Specifying DALUTPartition for Multirate Filters For supported multirate filters (mfilt.firdecim and mfilt.firinterp) , you can specify
the LUT partition as A vector defining a partition for LUTs for all polyphase subfilters.
A matrix of LUT partitions, where each row vector specifies a LUT partition for a corresponding polyphase subfilter. In this case, the FL is uniform for all
subfilters. This approach provides a fine control for partitioning each subfilter. The following table shows the FL calculations for each type of LUT partition.
4-32 Distributed Arithmetic for FIR Filters LUT Partition Specified As.
Vector: determine FL as shown in the Filter Length (FL) Calculation column to the right. Specify the LUT partition as a vector of integers whose elements
sum to FL. Filter Length (FL) Calculation FL = size(polyphase(Hm), 2) Matrix: determine the subfilter length FLi based on the polyphase decomposition of
the filter, as shown in the Filter Length (FL) Calculation column to the right. Specify the LUT partition for each subfilter as a row vector whose elements sum
to FLi. p = polyphase(Hm); FLi = length(find(p(i,:))); where i is the index to the ith row of the polyphase matrix of the multirate filter. The ith row of the
matrix p represents theith subfilter. The following example shows the FL calculation for a direct-form FIR polyphase decimator, with the LUT partition
specified as a vector: d = fdesign.decimator(4); Hm = design(d); Hm.arithmetic = 'fixed'; FL = size(polyphase(Hm),2) FL = 27 generatehdl(Hm,
'DALUTPartition',[8 8 8 3]); The following example shows the LUT partition specified as a matrix for the same direct-form FIR polyphase decimator.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The length of the first subfilter is 1, and all other subfilters have length 26.
d = fdesign.decimator(4); Hm = design(d); Hm.arithmetic = 'fixed'; generatehdl(Hm, 'DALUTPartition',[1 0 0 0; 8 8 8 2; 8 8 6 4; 8 8 8 2]); 4-33 4
Optimizing Generated HDL Code DARadix Property Syntax: 'DARadix', N DARadix specifies the number of bits processed simultaneously in DA. The number
of bits is expressed as N, which must be A nonzero positive integer that is a power of two Such that mod(W, log2(N)) = 0 where W is the input word size of
the filter. The default value for N is 2, specifying processing of one bit at a time, or fully serial DA, which is slow but low in area. The maximum value for N is
2^W, where W is the input word size of the filter. This maximum specifies fully parallel DA, which is fast but high in area. Values of N between these extrema
specify partly serial DA. Note When setting a DARadix value for symmetrical (dfilt.dfsymfir) and asymmetrical (dfilt.
dfasymfir) filters, see "Considerations for Symmetrical and Asymmetrical Filters" on page 4-34. Special Cases Coefficients with Zero Values DA ignores taps
that have zero-valued coefficients and reduces the size of the DA LUT accordingly. Considerations for Symmetrical and Asymmetrical Filters For symmetrical
(dfilt.dfsymfir) and asymmetrical (dfilt.dfasymfir) filters: A bit-level preadder or presubtractor is required to add tap data values that have coefficients of
equal value and/or opposite sign.
One extra clock cycle is required to compute the result because of the additional carry bit. The coder takes advantage of filter symmetry where possible. This
reduces the DA LUT size substantially , because the effective filter length for these filter types is halved. 4-34 Distributed Arithmetic for FIR Filters Holding
Input Data in a Valid State In filters with a DA architecture, data can be delivered to the outputs N cycles (N ]= 2) later than the inputs. You can use the
HoldInputDataBetweenSamples property to determine how long (in terms of clock cycles) input data values are held in a valid state, as follows: When
HoldInputDataBetweenSamples is set 'on' (the default), input data values are held in a valid state across N clock cycles.
When HoldInputDataBetweenSamples is set 'off' , data values are held in a valid state for only one clock cycle. For the nextN-1 cycles, data is in an unknown
state (expressed as 'X') until the next input sample is clocked in. Distributed Arithmetic Options in the Generate HDL Dialog Box This section describes
Generate HDL dialog box options related to DA code generation. The following figure shows these options. 4-35 4 Optimizing Generated HDL Code The DA
related options are: The Architecture pop-up menu, which lets you enable DA code generation and displays related options The LUT Partition field, which
displays and lets you change the value of the DALUTPartition property The DA Radix field, which displays and lets you change the value of the DARadix
property 4-36 Distributed Arithmetic for FIR Filters The Generate HDL dialog box initially displays default DA related option values that are appropriate for
the current filter design. In other respects, the requirements for setting these options are identical to those described in "DALUTPartition Property" on page
4-30 and "DARadix Property" on page 4-34. To specify DA code generation using the Generate HDL dialog box, follow these steps: 1 Design a FIR filter
(using FDATool, filterbuilder, or MATLAB commands) that meets the requirements described in "Requirements and Considerations for Generating
Distributed Arithmetic Code" on page 4-29. 2 Open the Generate HDL dialog box. 3 Select Distributed Arithmetic (DA) from the Architecture pop-up menu.
When you select this option, the related LUT Partition and DA Radix options are displayed to the right of the Architecture menu.
The following figure shows the default DA options for a Direct Form FIR filter.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
4-37 4 Optimizing Generated HDL Code The default value for LUT Partition is a vector of integers such that each partition has a maximum of 8 inputs. The
figure illustrates a 51-tap filter, with 7 partitions. All partitions have 8 inputs except for the last, which has 3 inputs. 4 If desired, set the LUT Partition field to
a nondefault value. See "DALUTPartition Property" on page 4-30 for detailed information. 4-38 Distributed Arithmetic for FIR Filters 5 The default DA
Radix value is 2, specifying processing of one bit at a time, or fully serial DA. If desired, set the DA Radix field to a nondefault value. See "DARadix
Property" on page 4-34 for detailed information. If you are setting the DA Radix value for a dfilt.
dfsymfir and dfilt.dfasymfir filter, see "Considerations for Symmetrical and Asymmetrical Filters" on page 4-34. 6 Set other HDL options as required, and
generate code. Incorrect or illegal values for LUT Partition or DA Radix are reported at code generation time. DA Interactions with Other HDL Options
When Distributed Arithmetic (DA) is selected in the Architecture menu, some other HDL options change automatically to settings that are appropriate for DA
code generation: Coefficient multipliers is set to Multiplier and disabled.
FIR adder style is set to Tree and disabled. Add input register in the Ports pane of the Generate HDL dialog box is selected and disabled. (An input
register, used as part of a shift register, is always used in DA code.) Add output register in the Ports pane of the Generate HDL dialog box is selected and
disabled. 4-39 4 Optimizing Generated HDL Code Optimizing the Clock Rate with Pipeline Registers You can optimize the clock rate used by filter code by
applying pipeline registers.
Although the registers increase the overall filter latency and space used, they provide significant improvements to the clock rate. These registers are disabled
by default. When you enable them, the coder adds registers between stages of computation in a filter. For. FIR, antisymmetric FIR, and symmetric FIR filters
Transposed FIR filters IIR filters Pipeline Registers Are Added Between. Each level of the final summation tree Coefficient multipliers and adders Sections
For example, for a sixth order IIR filter, the coder adds two pipeline registers, one between the first and second section and one between the second and third
section. For FIR filters, the use of pipeline registers optimizes filter final summation. For details, see "Optimizing Final Summation for FIR Filters" on page
4-8 Note The use of pipeline registers in FIR, antisymmetric FIR, and symmetric FIR filters can produce numeric results that differ from those produced by
the original filter object because they force the tree mode of final summation. To use pipeline registers, 1 Select the Add pipeline registers option in the Filter
architecture pane of the Generate HDL dialog box. 2 For FIR, antisymmetric FIR, and symmetric FIR filters, consider setting an error margin for the
generated test bench to account for numeric differences.
The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin: 4-40 Optimizing the
Clock Rate with Pipeline Registers a Select the Test Bench pane in the Generate HDL dialog box. Then click on the Configuration tab. b Specify an integer in
the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numerical results can differ before the coder issues a warning.
3 Continue setting other options or click Generate to initiate code generation. Command Line Alternative: Use the generatehdl and generatetb functions with
the property AddPipelineRegisters to optimize the filters with pipeline registers. 4-41 4 Optimizing Generated HDL Code Setting Optimizations for Synthesis
The following table maps various synthesis goals with optimization settings that can help you achieve those goals.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Use the table as a guide, while understanding that your results may vary depending on your synthesis target. For example, if you target FPGAs with built-in
multipliers, the benefit of using CSD or factored CSD can be quite small until you utilize all the built-in multipliers. In an ASIC application, where the ability
to route the design largely controls the speed, the difference in speed between a linear and tree FIR adder style can be negligible.
It may be necessary for you to combine various option settings to achieve your synthesis goals. To. Slightly increase the clock speed and slightly decrease the
area used Increase the clock speed while maintaining the area used Select. Optimize for HDL Which. Removes extra quantization operations Computes final
summation for FIR, asymmetric FIR, and symmetric FIR pair-wise in parallel At the Cost of.
Not remaining bit-true to the original filter object. Tree for FIR adder style Not remaining bit-true to the original filter object. If no rounding or saturation
occurs during final summation, results are bit-true to original filter object. Not remaining bit-true to the original filter object when the FIR adder style is
forced to Tree. Significantly increase the clock speed while increasing overall latency and the area used Add pipeline registers Adds pipeline registers and
forces use of the Tree FIR adder style, as necessary 4-42 Setting Optimizations for Synthesis To.
Decrease the area used while maintaining or increasing clock speed (depends on binary representation of coefficients) Decrease the area used (lower than
what is achieved with CSD) while decreasing the clock speed Select. CSD for Coefficient multipliers Which. Uses shift and add techniques instead of
multipliers At the Cost of. Factored CSD for Coefficient multipliers Uses shift and add techniques on the prime factors of coefficients instead of multipliers
4-43 4 Optimizing Generated HDL Code 4-44 5 Testing a Filter Design 5 Testing a Filter Design Testing with an HDL Test Bench In this section. "Overview"
on page 5-2 "Generating the Filter and Test Bench HDL Code" on page 5-3 "Starting the Simulator" on page 5-6 "Compiling the Generated Filter and Test
Bench Files" on page 5-7 "Running the Test Bench Simulation" on page 5-8 Overview If you generate VHDL or Verilog test bench code, you can use a
simulator of your choice to verify your filter design. For example purposes, the following sections explain how to apply generated HDL test bench code by
using the Mentor Graphics ModelSim simulator, in the following steps: 1 Generate the filter and test bench HDL code. 2 Start the simulator. 3 Compile the
generated filter and test bench files. 4 Run the test bench simulation. Note Due to differences in representation of double-precision data in VHDL and Verilog,
restrictions apply to the types of test benches that are interoperable.
The following table shows valid and invalid test bench type and HDL combinations when code is generated for a double-precision filter. Test Bench Type
VHDL Verilog VHDL Valid Invalid Verilog Invalid Valid These restrictions do not apply for fixed-point filters. 5-2 Testing with an HDL Test Bench
Generating the Filter and Test Bench HDL Code Use the Filter Design HDL Coder GUI or command line interface to generate the HDL code for your filter
design and test bench. As explained in "Specifying a Test Bench Type" on page 3-114, the GUI generates a VHDL or Verilog test bench file by default,
depending on your language selection. To specify a language-specific test bench type explicitly, select the Test bench language option in the Test Bench pane
of the Generate HDL dialog box. You can specify a number of other test bench customizations, as described in "Customizing the Test Bench" on page 3-112.
The following figure shows settings for generating the filter (VHDL) and test bench (Verilog) files MyFilter.vhd, and MyFilter_tb.v. The dialog box also
specifies that the generated files are to be placed in the default target folder hdlsrc under the current working folder.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
5-3 5 Testing a Filter Design After you click Generate, the coder displays progress information similar to the following in the MATLAB Command Window:
### Starting VHDL code generation process for filter: MyFilter ### Generating: C:\Work\sl_hdlcoder_work\hdlsrc\MyFilter.vhd ### Starting generation of
MyFilter VHDL entity ### Starting generation of MyFilter VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code
generation process for filter: MyFilter 5-4 Testing with an HDL Test Bench ### Starting generation of VERILOG Test Bench ### Generating input stimulus
### Done generating input stimulus; length 3429 samples. ### Generating Test bench: C:\Work\sl_hdlcoder_work\hdlsrc\MyFilter_tb.v ### Please wait . ###
Done generating VERILOG Test Bench Note The length of the input stimulus samples varies from filter to filter.
For example, the value 3429 in the preceding message sequence is not fixed; the value is dependent on the filter under test. If you use the command line
interface, you must Invoke the functions generatehdl and generatetb, in that order. The order is important because generatetb takes into account additional
latency or numeric differences introduced into the filter's HDL code that results from the following property settings. Property. 'AddInputRegister' Set to.
'on' Can Affect. Latency or 'AddOutputRegister' 'FIRAdderStyle' 'pipeline' Numeric computations and latency Numeric computations Numeric computations
Numeric computations Numeric computations 'FIRAdderStyle' 'OptimizeForHDL' 'CastBeforeSum' 'CoeffMultipliers' 'tree' 'off' 'on' 'csd' or 'factored-csd' 5-5
5 Testing a Filter Design Specify 'VHDL' or 'Verilog' for the TbType parameter. For double-precision filters, you must specify the type that matches the
target language specified for your filter code. Make sure the property settings specified in the invocation of generatetb match those of the corresponding
invocation of generatehdl. You can do this in one of two ways: - Omit explicit property settings from the generatetb invocation. This function automatically
inherits the property settings established in the generatehdl invocation. Take care to specify the same property settings specified in the generatehdl
invocation. You might also want to consider using the function generatetbstimulus to return the test bench stimulus to the MATLAB Command Window. For
details on the property name and property value pairs that you can specify with the generatehdl and generatetb functions for customizing the output, see
Chapter 6, "Property Reference". Starting the Simulator After you generate your filter and test bench HDL files, start your simulator.
When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears: 5-6 Testing with an HDL Test Bench After
starting the simulator, set the current folder to the folder that contains your generated HDL files. Compiling the Generated Filter and Test Bench Files Using
your choice HDL compiler, compile the generated filter and test bench HDL files. Depending on the language of the generated test bench and the simulator
you are using, you might need to complete some precompilation setup. For example, in the Mentor Graphics ModelSim simulator, you might choose to create
a design library to store compiled VHDL entities, packages, architectures, and configurations. The following Mentor Graphics ModelSim command sequence
changes the current folder to hdlsrc, creates the design library work, and compiles VHDL filter and filter test bench code. The vlib command creates the
design library work and the vcom commands initiate the compilations. cd hdlsrc vlib work vcom MyFilter.vhd vcom MyFilter_tb.vhd 5-7 5 Testing a Filter
Design Note For VHDL test bench code that has floating-point (double) realizations, use a compiler that supports VHDL-93 or VHDL-02 (for example, in the
Mentor Graphics ModelSim simulator, specify the vcom command with the -93 option).
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Do not compile the generated test bench code with a VHDL-87 compiler.
VHDL test benches using double- precision data types do not support VHDL-87, because test bench code uses the image attribute, which is available only in
VHDL-93 or higher. The following screen display shows this command sequence and informational messages displayed during compilation. Running the Test
Bench Simulation Once your generated HDL files are compiled, load and run the test bench. The procedure for doing this varies depending on the simulator
you are using. 5-8 Testing with an HDL Test Bench In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim
command.
For example: vsim work.MyFilter_tb The following display shows the results of loading work.MyFilter_tb with the vsim command. Once the design is loaded
into the simulator, consider opening a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim
simulator, you might use the add wave * command to open a wave window to view the results of the simulation as HDL waveforms.
To start running the simulation, issue the appropriate simulator command. For example, in the Mentor Graphics ModelSim simulator, you can start a
simulation with the run -all command. 5-9 5 Testing a Filter Design The following display shows the add wave * command being used to open a wave window
and the -run all command being used to start a simulation. As your test bench simulation runs, watch for error messages. If any error messages appear, you
must interpret them as they pertain to your filter design and the code generation options you applied. For example, a number of HDL customization options
allow you to specify settings that can produce numeric results that differ from those produced by the original filter object. For HDL test benches, expected
and actual results are compared. If they differ (excluding the specified error margin), an error message similar to the following is returned: Error in filter
test: Expected xxxxxxxx Actual xxxxxxxx You must determine whether the actual results are expected based on the customizations you specified when
generating the filter HDL code. 5-10 Testing with an HDL Test Bench Note The failure message that appears in the preceding display is not flagging an error.
If the message includes the string Test Complete, the test bench has successfully run to completion.
The Failure part of the message is tied to the mechanism the coder uses to end the simulation. The following wave window shows the simulation results as
HDL waveforms. 5-11 5 Testing a Filter Design 5-12 6 Property Reference Language Selection Properties (p. 6-2) File Naming and Location Properties (p.
6-2) Reset Properties (p. 6-2) Header Comment and General Naming Properties (p. 6-3) Port Properties (p. 6-4) Advanced Coding Properties (p. 6-5)
Optimization Properties (p. 6-6) Test Bench Properties (p.
6-7) Script Generation Properties (p. 6-9) Lists properties for selecting language of generated HDL code Lists properties that name and specify location of
generated files Lists reset properties Lists header comment and general naming properties Lists port properties Lists advanced HDL coding properties Lists
optimization properties Lists test bench properties Lists properties for customizing generated scripts for EDA tools 6 Property Reference Language Selection
Properties TargetLanguage Specify HDL language to use for generated filter code File Naming and Location Properties Name Specify file name for
generated HDL code and name for filter's VHDL entity or Verilog module Identify folder into which generated output files are written Specify file type
extension for generated Verilog files Specify file type extension for generated VHDL files TargetDirectory VerilogFileExtension VHDLFileExtension Reset
Properties RemoveResetFrom ResetAssertedLevel ResetLength ResetType Suppress generation of resets from shift registers Specify asserted (active) level of
reset input signal Define length of time (in clock cycles) during which reset is asserted Specify whether to use asynchronous or synchronous reset style when
generating HDL code for registers 6-2 Header Comment and General Naming Properties Header Comment and General Naming Properties
ClockProcessPostfix CoeffPrefix ComplexImagPostfix ComplexRealPostfix EntityConflictPostfix Specify string to append to HDL clock process names
Specify prefix (string) for filter coefficient names Specify string to append to imaginary part of complex signal names Specify string to append to real part of
complex signal names Specify string to append to duplicate VHDL entity or Verilog module names Specify string prefixed to generated component instance
names Specify string to append to specified filter name to form name of VHDL package file Specify string to append to value names, postfix values, or labels
that are VHDL or Verilog reserved words Specify string to append to specified name to form name of file containing filter's VHDL architecture Specify
whether generated VHDL entity and architecture code is written to single VHDL file or to separate files Specify string to append to specified filter name to
form name of file that contains filter's VHDL entity Specify string prefixed to vector names in generated VHDL code InstancePrefix PackagePostfix
ReservedWordPostfix SplitArchFilePostfix SplitEntityArch SplitEntityFilePostfix VectorPrefix 6-3 6 Property Reference VHDLArchitectureName
VHDLLibraryName Specify architecture name for generated VHDL code Specify target library name used in initialization section of compilation script Port
Properties AddInputRegister AddOutputRegister ClockEnableInputPort ClockEnableOutputPort Generate extra register in HDL code for filter input
Generate extra register in HDL code for filter output Name HDL port for filter's clock enable input signals For multirate filters (with single clock), specify
name of clock enable output port Name HDL port for filter's clock input signals For multirate filters, specify generation of single or multiple clock inputs
Name port for Farrow filter's fractional delay input signal Enable generation ports and signal paths appropriate for filter with complex input data Name HDL
port for filter's input signals Specify HDL data type for filter's input port ClockInputPort ClockInputs FracDelayPort InputComplex InputPort InputType 6-4
Advanced Coding Properties OutputPort OutputType ResetInputPort Name HDL port for filter's output signals Specify HDL data type for filter's output port
Name HDL port for filter's reset input signals Advanced Coding Properties BlockGenerateLabel Specify string to append to block labels used for HDL
GENERATE statements Enable or disable type casting of input values for addition and subtraction operations Specify type of memory for storage of
programmable coefficients for serial FIR filters Specify source for FIR or IIR filter coefficients Specify whether generated VHDL code includes inline
configurations Specify string to append to instance section labels in VHDL GENERATE statements Specify whether VHDL FOR and GENERATE loops are
unrolled and omitted from generated VHDL cod Specify string that labels output assignment block for VHDL GENERATE statements CastBeforeSum
CoefficientMemory CoefficientSource InlineConfigurations InstanceGenerateLabel LoopUnrolling OutputGenerateLabel 6-5 6 Property Reference
SafeZeroConcat UseAggregatesForConst Specify syntax used in generated VHDL code for concatenated zeros Specify whether all constants are represented
by aggregates, including constants that are less than 32 bits wide Specify comment line in header of generated filter and test bench files Specify VHDL coding
style used to check for rising edges when operating on registers Allow or exclude use of compiler `timescale directives in generated Verilog code
UserComment UseRisingEdge UseVerilogTimescale Optimization Properties AddPipelineRegisters CoeffMultipliers DALUTPartition Optimize clock rate
used by filter code by adding pipeline registers Specify technique used for processing coefficient multiplier operations Specify number and size of LUT
partitions for distributed arithmetic architecture Specify number of bits processed simultaneously in distributed arithmetic architecture Specify final
summation technique used for FIR filters Specify number of pipeline stages at multiplier inputs for FIR filters DARadix FIRAdderStyle
MultiplierInputPipeline 6-6 Test Bench Properties MultiplierOutputPipeline OptimizeForHDL Specify number of pipeline stages at multiplier outputs for FIR
filters Specify whether generated HDL code is optimized for specific performance or space requirements Enable accumulator reuse, generating cascade-
serial architecture for FIR filters Specify number and size of partitions generated for serial FIR filter architectures ReuseAccum SerialPartition Test Bench
Properties ClockHighTime Specify period, in nanoseconds, during which test bench drives clock input signals high (1) Specify period, in nanoseconds, during
which test bench drives clock input signals low (0) Specify error margin for HDL language-based test benches Specify whether test bench forces clock input
signals Specify whether test bench forces clock enable input signals Specify whether test bench forces reset input signals Generate model containing HDL
Cosimulation block(s) for simulation of filter in Simulink ClockLowTime ErrorMargin ForceClock ForceClockEnable ForceReset GenerateCoSimBlock 6-7 6
Property Reference GenerateCosimModel Generate model containing realized filter and HDL Cosimulation block for simulation of filter in Simulink Specify
how long input data values are held in valid state Specify hold time for filter data input signals and forced reset input signals Specify initial value driven on
test bench inputs before data is asserted to filter Divide generated test bench into helper functions, data, and HDL test bench code files Specify simulator flags
applied to generated test bench Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable Specify testing options for
coefficient memory interface for FIR or IIR filters Specify suffix added to test bench data file name when generating multi-file test bench Specify input
stimulus that test bench applies to Farrow filter fractional delay port Name VHDL test bench entity or Verilog module and file that contains test bench code
Specify string appended to names of reference signals generated in test bench code HoldInputDataBetweenSamples HoldTime InitializeTestBenchInputs
MultifileTestBench SimulatorFlags TestBenchClockEnableDelay TestbenchCoeffStimulus TestBenchDataPostFix TestBenchFracDelayStimulus
TestBenchName TestBenchReferencePostFix 6-8 Script Generation Properties TestBenchStimulus TestBenchUserStimulus Specify input stimuli that test
bench applies to filter Specify user-defined function that returns vector of values that test bench applies to filter Script Generation Properties
EDAScriptGeneration HDLCompileFilePostfix Enable or disable generation of script files for third-party tools Specify postfix string appended to file name
for generated Mentor Graphics ModelSim compilation scripts Specify string written to initialization section of compilation script Specify string written to
termination section of compilation script Specify command string written to compilation script for Verilog files Specify command string written to compilation
script for VHDL files Specify simulation command written to simulation script Specify postfix string appended to file name for generated Mentor Graphics
ModelSim simulation scripts Specify string written to initialization section of simulation script HDLCompileInit HDLCompileTerm HDLCompileVerilogCmd
HDLCompileVHDLCmd HDLSimCmd HDLSimFilePostfix HDLSimInit 6-9 6 Property Reference HDLSimTerm HDLSimViewWaveCmd HDLSynthCmd
HDLSynthFilePostfix Specify string written to termination section of simulation script Specify waveform viewing command written to simulation script Specify
command written to synthesis script Specify postfix string appended to file name for generated Synplify synthesis scripts Specify string written to initialization
section of synthesis script Specify string written to termination section of synthesis script HDLSynthInit HDLSynthTerm 6-10 7 Properties -- Alphabetical List
AddInputRegister Purpose Settings Generate extra register in HDL code for filter input 'on' (default) Add an extra input register to the filter's generated HDL
code.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The code declares a signal named input_register and includes a PROCESS block similar to the block below. Names and meanings of the timing parameters
(clock, clock enable, and reset) and the coding style that checks for clock events may vary depending on other property settings. Input_Register_Process :
PROCESS (clk, reset) BEGIN IF reset = '1' THEN input_register [= (OTHERS =] '0'); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN
input_register [= input_typeconvert; END IF; END IF; END PROCESS Input_Register_Process ; 'off' Omit the extra input register from the filter's generated
HDL code.
Consider omitting the extra register if you are incorporating the filter into HDL code that already has a source for driving the filter. You might also consider
omitting the extra register if the latency it introduces to the filter is not tolerable. See Also AddOutputRegister 7-2 AddOutputRegister Purpose Settings
Generate extra register in HDL code for filter output 'on' (default) Add an extra output register to the filter's generated HDL code. The code declares a signal
named output_register and includes a PROCESS block similar to the block below. Names and meanings of the timing parameters (clock, clock enable, and
reset) and the coding style that checks for clock events may vary depending on other property settings.
Output_Register_Process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN output_register [= (OTHERS =] '0'); ELSIF clk'event AND clk = '1' THEN IF
clk_enable = '1' THEN output_register [= output_typeconvert; END IF; END IF; END PROCESS Output_Register_Process ; 'off' Omit the extra output
register from the filter's generated HDL code. Consider omitting the extra register if you are incorporating the filter into HDL code that has its own input
register. You might also consider omitting the extra register if the latency it introduces to the filter is not tolerable. See Also AddInputRegister 7-3
AddPipelineRegisters Purpose Settings Optimize clock rate used by filter code by adding pipeline registers 'on' Add a pipeline register between stages of
computation in a filter. For example, for a sixth-order IIR filter, the coder adds two pipeline registers, one between the first and second sections and one
between the second and third sections. Although the registers add to the overall filter latency, they provide significant improvements to the clock rate. For.
FIR Transposed filters FIR, Asymmetric FIR, and Symmetric FIR filters IIR filters 'off' (default) A Pipeline Register Is Added Between. Coefficient multipliers
and adders Levels of a tree-based final adder Sections Suppress the use of pipeline registers. Usage Notes For FIR filters, the use of pipeline registers
optimizes filter final summation.
For details, see "Optimizing Final Summation for FIR Filters" on page 4-8. Note The use of pipeline registers in FIR, antisymmetric FIR, and symmetric FIR
filters can produce numeric results that differ from those produced by the original filter object because they force the tree mode of final summation. In such
cases, consider adjusting the test bench error margin. See Also CoeffMultipliers, FIRAdderStyle, OptimizeForHDL 7-4 BlockGenerateLabel Purpose Settings
Specify string to append to block labels used for HDL GENERATE statements 'string' Specify a postfix string to append to block labels used for HDL
GENERATE statements. The default string is _gen. See Also InstanceGenerateLabel, OutputGenerateLabel 7-5 CastBeforeSum Purpose Settings Enable or
disable type casting of input values for addition and subtraction operations 'off' (default) Preserve the types of input values during addition and subtraction
operations and then convert the result to the result type. 'on' Type cast input values in addition and subtraction operations to the result type before operating
on the values. This setting produces numeric results that are typical of DSP processors.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The CastBeforeSum property is related to the FDATool setting for the quantization property Cast signals before accum. as follows: Some filter object types
do not have theCast signals before accum.
property. For such filter objects, CastBeforeSum is effectively off when HDL code is generated; it is not relevant to the filter. Where the filter object. does
have the Cast signals before accum. property, the coder by default sets CastBeforeSum following the setting of Cast signals before accum.
in the filter object. This is visible in the GUI. If the you change the setting of Cast signals before accum., the coder updates the setting of Cast before sum.
However, by explicitly setting the CastBeforeSum property, you can override the Cast signals before accum.
setting passed in from FDATool. See Also "Specifying Input Type Treatment for Addition and Subtraction Operations" on page 3-60, InlineConfigurations,
LoopUnrolling, SafeZeroConcat, UseAggregatesForConst, UseRisingEdge, UseVerilogTimescale 7-6 ClockEnableInputPort Purpose Settings Name HDL
port for filter's clock enable input signals 'string' The default name for the filter's clock enable input port is clk_enable. For example, if you specify the string
'filter_clock_enable' for filter entity Hd, the generated entity declaration might look as follows: ENTITY Hd IS PORT( clk : IN IN IN IN std_logic; std_logic;
std_logic; std_logic_vector (15 DOWNTO 0); filter_clock_enable : reset filter_in filter_out ); END Hd; : : : OUT std_logic_vector (15 DOWNTO 0); If you
specify a string that is a VHDL or Verilog reserved word, a reserved word postfix string is appended to form a valid VHDL or Verilog identifier. For example,
if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information. Usage Notes See Also
The clock enable signal is asserted active high (1). Thus, the input value must be high for the filter entity's registers to be updated. ClockInputPort, InputPort,
InputType, OutputPort, OutputType, ResetInputPort 7-7 ClockEnableOutputPort Purpose Settings For multirate filters (with single clock), specify name of
clock enable output port 'string' The default name for the generated clock enable output port is ce_out. Usage Notes See Also For multirate filters, a clock
enable output is generated when Single is selected from the Clock inputs menu in the Generate HDL dialog box. In this case only, the Clock enable output
port option is enabled.
ClockInputs 7-8 ClockHighTime Purpose Settings Specify period, in nanoseconds, during which test bench drives clock input signals high (1) ns The default is
5. The clock high time is expressed as a positive integer or double (with a maximum of 6 significant digits after the decimal point). Usage Notes See Also The
coder ignores this property if ForceClock is set to 'off'. ClockLowTime, ForceClock, ForceClockEnable, ForceReset, HoldTime 7-9 ClockInputPort Purpose
Settings Name HDL port for filter's clock input signals 'string' The default clock input port name is clk. For example, if you specify the string 'filter_clock' for
filter entity Hd, the generated entity declaration might look as follows: ENTITY Hd IS PORT( filter_clock clk_enable reset filter_in filter_out ); ENDHd; : : : :
: IN IN IN IN std_logic; std_logic; std_logic; std_logic_vector (15 DOWNTO 0); -- sfix16_En15 OUT std_logic_vector (15 DOWNTO 0); -- sfix16_En15 If
you specify a string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the
reserved word signal, the resulting name string would be signal_rsvd. See for more information. See Also ClockEnableInputPort, InputPort, InputType,
OutputPort, OutputType, ResetInputPort 7-10 ClockInputs Purpose Settings For multirate filters, specify generation of single or multiple clock inputs 'Single'
(default) Generate a single clock input for a multirate filter.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
When this option is selected, the ENTITY declaration for the filter defines a single clock input with an associated clock enable input and clock enable output.
The generated code maintains a counter that controls the timing of data transfers to the filter output (for decimation filters) or input (for interpolation filters).
The counter is, in effect, a secondary clock whose rate is determined by the filter's decimation or interpolation factor. 'Multiple' Generate multiple clock
inputs for a multirate filter. When this option is selected, the ENTITY declaration for the filter defines separate clock inputs (each with an associated clock
enable input) for each rate of a multirate filter. (For currently supported multirate filters, there are two such rates.) Usage Notes The Clock inputs menu is
enabled only when a multirate filter (of one of the types supported for code generation) has been designed in fdatool.
The generated code assumes that the clocks are driven at the appropriate rates. You are responsible for ensuring that the clocks run at the correct relative
rates for the filter's decimation or interpolation factor. To see an example, generate test bench code for your multirate filter and examine the clk_gen
processes for each clock. See Also ClockEnableOutputPort 7-11 ClockLowTime Purpose Settings Specify period, in nanoseconds, during which test bench
drives clock input signals low (0) ns The default is 5. The clock low time is expressed as a positive integer or double (with a maximum of 6 significant digits
after the decimal point).
Usage Notes See Also The coder ignores this property if ForceClock is set to 'off'. ClockHighTime, ForceClock, ForceClockEnable, ForceReset, HoldTime
7-12 ClockProcessPostfix Purpose Settings Specify string to append to HDL clock process names 'string' The default postfix is _process. The coder uses
process blocks to modify the content of a filter's registers. The label for each of these blocks is derived from a register name and the postfix _process. For
example, the coder derives the label delay_pipeline_process in the following block declaration from the register name delay_pipeline and the default postfix
string _process: delay_pipeline_process : PROCESS (clk, reset) BEGIN . See Also PackagePostfix, ReservedWordPostfix 7-13 CoefficientMemory Purpose
Settings Specify type of memory for storage of programmable coefficients for serial FIR filters 'Registers' (default) Store programmable coefficients in a
register file. 'DualPortRAMs' Store programmable coefficients in dual-port RAM. 'SinglePortRAMs' Usage Notes This property applies only to FIR filters that
have one of the following serial architectures: Fully serial Partly serial Cascade serial When you use this property, be sure to set CoefficientSource to
'ProcessorInterface'. The coder ignores CoefficientMemory unless it is generating an interface for programmable coefficients. See Also "Specifying
Programmable Filter Coefficients for FIR Filters" on page 3-64, , CoefficientSource, TestbenchCoeffStimulus 7-14 CoefficientSource Purpose Settings
Specify source for FIR or IIR filter coefficients 'Internal' (default) Coefficients are obtained from the filter object and hard coded.
ProcessorInterface Generate a memory interface, which can be driven by an external microprocessor, for coefficients. When you specify 'ProcessorInterface',
the generated entity or module definition for the filter includes the following port definitions: coeffs_in: Input port for coefficient data write_address: Write
address for coefficient memory write_enable: Write enable signal for coefficient memory write_done: Signal to indicate completion of coefficient write
operation See Also "Specifying Programmable Filter Coefficients for FIR Filters" on page 3-64, "Specifying Programmable Filter Coefficients for IIR Filters"
on page 3-77, TestbenchCoeffStimulus 7-15 CoeffMultipliers Purpose Settings Specify technique used for processing coefficient multiplier operations
'multiplier' (default) Retain multiplier operations in the generated HDL code.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
'csd' This option uses canonic signed digit (CSD) techniques, which replace multiplier operations with shift and add operations. CSD techniques minimize the
number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits. This decreases
the area used by the filter while maintaining or increasing clock speed. 'factored-csd' This option uses factored CSD techniques, which replace multiplier
operations with shift and add operations on prime factors of the coefficients. This option lets you achieve a greater filter area reduction than CSD, at the cost
of decreasing clock speed. See Also AddPipelineRegisters, FIRAdderStyle, OptimizeForHDL 7-16 CoeffPrefix Purpose Settings Specify prefix (string) for
filter coefficient names 'string' The default prefix for filter coefficient names is coeff. For. FIR filters The Prefix Is Concatenated with.
Each coefficient number, starting with 1. For example, the default for the first coefficient would be coeff1. An underscore (_) and an a or b coefficient name
(for example, _a2, _b1, or _b2) followed by the string _sectionn, where n is the section number. For example, the default for the first numerator coefficient of
the third section is coeff_b1_section3. IIR filters For example: ARCHITECTURE rtl OF Hd IS -- Type Definitions TYPE delay_pipeline_type IS ARRAY
(NATURAL range []) OF signed(15 DOWNTO 0); -- sfix16_En15 CONSTANT coeff1 : signed(15 DOWNTO 0) := to_signed(-30, 16); -- sfix16_En15
CONSTANT coeff2 : signed(15 DOWNTO 0) := to_signed(-89, 16); -- sfix16_En15 CONSTANT coeff3 : signed(15 DOWNTO 0) := to_signed(-81, 16); --
sfix16_En15 CONSTANT coeff4 : signed(15 DOWNTO 0) := to_signed(120, 16); -- sfix16_En15 .
If you specify a string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify
the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information. 7-17 CoeffPrefix See Also
ClockProcessPostfix, EntityConflictPostfix, PackagePostfix 7-18 ComplexImagPostfix Purpose Settings Specify string to append to imaginary part of complex
signal names 'string' Default: '_im' See Also ComplexRealPostfix, InputComplex "Using Complex Data and Coefficients" on page 3-62 7-19
ComplexRealPostfix Purpose Settings See Also Specify string to append to real part of complex signal names 'string' Default: 're' ComplexImagPostfix,
InputComplex "Using Complex Data and Coefficients" on page 3-62 7-20 DALUTPartition Purpose Settings Specify number and size of LUT partitions for
distributed arithmetic architecture [p1 p2.pN] Where [p1 p2 p3.
pN] is a vector of N integers, divides the LUT used in distributed arithmetic (DA) into N partitions. Each vector element specifies the size of a partition. The
maximum size for an individual partition is 12. The sum of all vector elements must be equal to the filter length. The filter length is calculated differently
depending on the filter type (see "Distributed Arithmetic for FIR Filters" on page 4-27). Usage Notes To enable generation of DA code for your filter design
without LUT partitioning, specify a vector of one element, whose value is equal to the filter length, as in the following example: fdes =
fdesign.lowpass('N,Fc,Ap,Ast',4,0.4,0.05,0.03,'linear'); Hd = design(fdse); Hd.
arithmetic = 'fixed'; generatehdl (Hd, 'DALUTPartition', 5); See Also DARadix 7-21 DARadix Purpose Settings Specify number of bits processed
simultaneously in distributed arithmetic architecture N N specifies the number of bits processed simultaneously in a distributed arithmetic (DA) architecture.
N must be A nonzero positive integer that is a power of two Such that mod(W, log2(N)) = 0, where W is the input word size of the filter. The default value
for N is 2, specifying processing of one bit at a time, or fully serial DA.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The maximum value for N is 2^W, where W is the input word size of the filter. This maximum specifies fully parallel DA. Values of N between these extrema
specify partly serial DA. Usage Notes The DARadix property lets you introduce a degree of parallelism into the operation of DA, improving performance at
the expense of area. See "Distributed Arithmetic for FIR Filters" on page 4-27 for a complete description of DA. DALUTPartition See Also 7-22
EDAScriptGeneration Purpose Settings Enable or disable generation of script files for third-party tools 'on' (default) Enable generation of script files. 'off'
Disable generation of script files.
See Also "Generating Scripts for EDA Tools" on page 3-143 7-23 EntityConflictPostfix Purpose Settings Specify string to append to duplicate VHDL entity or
Verilog module names 'string' The specified postfix resolves duplicate VHDL entity or Verilog module names. The default string is _block. For example, if the
coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_block. See Also ClockProcessPostfix,
CoeffPrefix, PackagePostfix, ReservedWordPostfix 7-24 ErrorMargin Purpose Settings Specify error margin for HDL language-based test benches n Some
HDL optimizations can generate test bench code that produces numeric results that differ from those produced by the original filter function. By specifying an
error margin, you can specify an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning.
Specify the error margin as an integer number of bits. Usage Notes Optimizations that can generate test bench code that produces numeric results that differ
from those produced by the original filter function include CastBeforeSum (qfilts only) OptimizeForHDL FIRAdderStyle ('Tree') AddPipelineRegisters
(for FIR, Asymmetric FIR, and Symmetric FIR filters) The error margin is the number of least significant bits a Verilog or VHDL language-based test bench
can ignore when comparing the numeric results before generating a warning. For fixed-point filters, the Error margin (bits) value is initialized to a default
value of 4. See Also AddPipelineRegisters, CastBeforeSum, CoeffMultipliers, FIRAdderStyle, OptimizeForHDL 7-25 FIRAdderStyle Purpose Settings Specify
final summation technique used for FIR filters 'linear' (default) Apply linear adder summation. This technique is discussed in most DSP text books.
'tree' Increase clock speed while maintaining the area used. This option creates a final adder that performs pair-wise addition on successive products that
execute in parallel, rather than sequentially. Usage Notes If you are generating HDL code for a FIR filter, consider optimizing the final summation technique
by applying tree or pipeline final summation techniques. Pipeline mode produces results similar to tree mode with the addition of a stage of pipeline registers
after processing each level of the tree. For information on applying pipeline mode, see AddPipelineRegisters. Consider the following tradeoffs when selecting
the final summation technique for your filter: The number of adder operations for linear and tree mode are the same, but the timing for tree mode might be
significantly better due to summations occurring in parallel. Pipeline mode optimizes the clock rate, but increases the filter latency by the base 2 logarithm
of the number of products to be added, rounded up to the nearest integer. Linear mode ensures numeric accuracy in comparison to the original filter
function. Tree and pipeline modes can produce numeric results that differ from those produced by the original filter function. See Also AddPipelineRegisters,
CoeffMultipliers, OptimizeForHDL 7-26 ForceClock Purpose Settings Specify whether test bench forces clock input signals 'on' (default) Specify that the test
bench forces the clock input signals.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
When this option is set, the clock high and low time settings control the clock waveform. 'off' Specify that a user-defined external source forces the clock input
signals. See Also ClockHighTime, ClockLowTime, ForceClockEnable, ForceReset, HoldTime 7-27 ForceClockEnable Purpose Settings Specify whether test
bench forces clock enable input signals 'on' (default) Specify that the test bench forces the clock enable input signals to active high (1) or active low (0),
depending on the setting of the clock enable input value. 'off' Specify that a user-defined external source forces the clock enable input signals. See Also
ClockHighTime, ClockLowTime, ForceClock, ForceReset, HoldTime 7-28 ForceReset Purpose Settings Specify whether test bench forces reset input signals
'on' (default) Specify that the test bench forces the reset input signals. If you enable this option, you can also specify a hold time to control the timing of a
reset. 'off' Specify that a user-defined external source forces the reset input signals. See Also ClockHighTime, ClockLowTime, ForceClock,
ForceClockEnable,HoldTime 7-29 FracDelayPort Purpose Settings Name port for Farrow filter's fractional delay input signal 'string' The default string is
filter_fd. For example, if you specify the string FractionalDelay for filter entity Hd, the generated entity declaration might look as follows: ENTITY Hd IS
PORT( clk clk_enable reset filter__in FractionalDelay filter_out ); END Hd; : : : : : : IN IN IN IN IN std_logic; std_logic; std_logic; std_logic_vector (15
DOWNTO 0); std_logic_vector (5 DOWNTO 0); OUT std_logic_vector (15 DOWNTO 0); If you specify a string that is a VHDL reserved word, a reserved
word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved word signal, the resulting name string would be
signal_rsvd.
See ReservedWordPostfix for more information. See Also "Generating Code for Single-Rate Farrow Filters" on page 3-105, TestBenchFracDelayStimulus
7-30 GenerateCoSimBlock Purpose Settings Generate model containing HDL Cosimulation block(s) for simulation of filter in Simulink 'off' (default) Do not
generate HDL Cosimulation blocks. 'on' If your installation is licensed for one or more of the following HDL simulation products, the coder generates and
opens a Simulink model that contains an HDL Cosimulation block for each licensed product: EDA Simulator Link for use with Mentor GraphicsModelSim
EDA Simulator Link for use with Cadence Incisive EDA Simulator Link for use with Synopsys Discovery The coder configures the generated HDL
Cosimulation blocks to conform to the port and data type interface of the filter selected for code generation. By connecting an HDL Cosimulation block to a
Simulink model in place of the filter, you can cosimulate your design with the desired HDL simulator. The coder appends the string (if any) specified by the
CosimLibPostfix property to the names of the generated HDL Cosimulation blocks.
7-31 GenerateCosimModel Purpose Settings Generate model containing realized filter and HDL Cosimulation block for simulation of filter in Simulink 'none'
(default) Do not generate a cosimulation model. 'ModelSim If your installation includes EDA Simulator Link for use with Mentor GraphicsModelSim, the
coder generates and opens a Simulink model that contains an HDL Cosimulation block for that simulator. 'Incisive' If your installation is licensed for EDA
Simulator Link for use with Cadence Incisive, the coder generates and opens a Simulink model that contains an HDL Cosimulation block for that simulator.
See Also "Generating a Simulink Model for Cosimulation with an HDL Simulator" on page 3-133 7-32 HDLCompileFilePostfix Purpose Settings Specify
postfix string appended to file name for generated Mentor Graphics ModelSim compilation scripts The default postfix is _compile.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
do.
For example, if the name of the filter or test bench is my_design, the coder adds the postfix _compile.do to form the name my_design_compile.do. See Also
"Generating Scripts for EDA Tools" on page 3-143 7-33 HDLCompileInit Purpose Settings Specify string written to initialization section of compilation script
'string' The default string is 'vlib %s\n'. At script generation time, the string you specify as VHDLLibraryName substitutes into the HDLCompileInit string
value. By default, this generates the library specification'vlib work/n' You can use VHDLLibraryName to avoid library name conflicts. See Also
VHDLLibraryName "Generating Scripts for EDA Tools" on page 3-143 7-34 HDLCompileTerm Purpose Settings Specify string written to termination section
of compilation script 'string' The default is the null string (''). See Also "Generating Scripts for EDA Tools" on page 3-143 7-35 HDLCompileVerilogCmd
Purpose Settings Specify command string written to compilation script for Verilog files 'string' The default string is 'vlog %s %s\n'. The two arguments are the
contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default).
See Also "Generating Scripts for EDA Tools" on page 3-143 7-36 HDLCompileVHDLCmd Purpose Settings Specify command string written to compilation
script for VHDL files 'string' The default string is 'vcom %s %s\n'. The two arguments are the contents of the 'SimulatorFlags' property and the file name of
the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). See Also "Generating Scripts for EDA Tools" on page 3-143 7-37
HDLSimCmd Purpose Settings Specify simulation command written to simulation script 'string' The default string is'vsim -novopt work.%s\n'. The implicit
argument is the top-level module or entity name. See Also "Generating Scripts for EDA Tools" on page 3-143 7-38 HDLSimFilePostfix Purpose Settings
Specify postfix string appended to file name for generated Mentor Graphics ModelSim simulation scripts 'string' The default postfix is _sim.do. For example,
if the name of your test bench file is my_design, the coder adds the postfix _sim.do to form the name my_design_tb_sim.
do. 7-39 HDLSimInit Purpose Settings Specify string written to initialization section of simulation script 'string' The default string is ['onbreak resume\n',.
'onerror resume\n'] See Also "Generating Scripts for EDA Tools" on page 3-143 7-40 HDLSimTerm Purpose Settings Specify string written to termination
section of simulation script 'string' The default string is 'run -all\n'. See Also "Generating Scripts for EDA Tools" on page 3-143 7-41 HDLSynthCmd Purpose
Settings Specify command written to synthesis script 'string' The default string is 'add_file %s\n'. The implicit argument is the file name of the entity or
module.
See Also "Generating Scripts for EDA Tools" on page 3-143 7-42 HDLSynthFilePostfix Purpose Settings Specify postfix string appended to file name for
generated Synplify synthesis scripts 'string' The default postfix is _synplify.tcl. For example, if the name of the filter is my_design, the coder adds the postfix
_synplify.tcl to form the name my_design_synplify.tcl.
7-43 HDLSynthInit Purpose Settings Specify string written to initialization section of synthesis script 'string' The default string is 'project -new %s.prj\n',
which is a synthesis project creation command. The implicit argument is the top-level module or entity name. See Also "Generating Scripts for EDA Tools" on
page 3-143 7-44 HDLSynthTerm Purpose Settings Specify string written to termination section of synthesis script 'string' The default string is ['set_option
-technology VIRTEX4\n',. 'set_option -part XC4VSX35\n',.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
'set_option -synthesis_onoff_pragma 0\n',. 'set_option -frequency auto\n',. 'project -run synthesis\n'] See Also "Generating Scripts for EDA Tools" on page
3-143 7-45 HDLSimViewWaveCmd Purpose Settings Specify waveform viewing command written to simulation script 'string' The default string is 'add wave
sim:%s\n'. The implicit argument is the top-level module or entity name. See Also "Generating Scripts for EDA Tools" on page 3-143 7-46
HoldInputDataBetweenSamples Purpose Settings Specify how long input data values are held in valid state This property can be applied to filters that do not
have fully parallel implementations.
(See "Parallel and Serial Architectures" on page 4-11 and "Distributed Arithmetic for FIR Filters" on page 4-27.) In such filter implementations, data can be
delivered to the outputs N cycles (N ]= 2) later than the inputs. The HoldInputDataBetweenSamples property determines how long (in terms of clock cycles)
input data values for these signals are held in a valid state, as follows: When HoldInputDataBetweenSamples is set to 'on' (the default), input data values are
held in a valid state across N clock cycles. When HoldInputDataBetweenSamples is set to 'off' , data values are held in a valid state for only one clock cycle.
For the next N-1 cycles, data is in an unknown state (expressed as 'X') until the next input sample is clocked in. See Also HoldTime 7-47 HoldTime Purpose
Settings Specify hold time for filter data input signals and forced reset input signals ns Specify the number of nanoseconds during which filter data input
signals and forced reset input signals are held past the clock rising edge. The default is 2. The hold time is expressed as a positive integer or double (with a
maximum of 6 significant digits after the decimal point). This option applies to reset input signals only if forced resets are enabled. Usage Notes The hold time
is the amount of time that reset input signals and input data are held past the clock rising edge.
The following figures show the application of a hold time (thold) for reset and data input signals when the signals are forced to active high and active low.
The ResetLength property is set to its default of 2 cycles, and the reset signal is asserted for a total of two cycles plus thold. Clock Reset Input Active High
thold Reset Input Active Low thold Hold Time for Reset Input Signals 7-48 HoldTime Clock Data Input thold Hold Time for Data Input Signals See Also
ClockHighTime, ClockLowTime, ForceClock, ForceClockEnable, ForceReset, HoldInputDataBetweenSamples 7-49 InitializeTestBenchInputs Purpose
Settings Specify initial value driven on test bench inputs before data is asserted to filter 'on' Initial value driven on test bench inputs is'0'. 'off' (default) Initial
value driven on test bench inputs is 'X' (unknown). 7-50 InlineConfigurations Purpose Settings Specify whether generated VHDL code includes inline
configurations 'on' (default) Include VHDL configurations in any file that instantiates a component.
'off' Suppress the generation of configurations and require user-supplied external configurations. Use this setting if you are creating your own VHDL
configuration files. Usage Notes VHDL configurations can be either inline with the rest of the VHDL code for an entity or external in separate VHDL source
files. By default,the coder includes configurations for a filter within the generated VHDL code. If you are creating your own VHDL configuration files, you
should suppress the generation of inline configurations.
CastBeforeSum, LoopUnrolling, SafeZeroConcat, UseAggregatesForConst, UseRisingEdge See Also 7-51 InputComplex Purpose Settings Enable generation
ports and signal paths appropriate for filter with complex input data 'on' Use this option when your filter design requires complex input data. To enable
generation of ports and signal paths for the real and imaginary components of a complex signal, set InputComplex to 'on', as in the following code example.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Hd = design(fdesign.lowpass,'equiripple','Filterstructure','dffir'); generatehdl(Hd, 'InputComplex', 'on'); 'off' (default) Do not generate ports for complex
input data See Also ComplexImagPostfix ComplexRealPostfix "Using Complex Data and Coefficients" on page 3-62 7-52 InputPort Purpose Settings Name
HDL port for filter's input signals 'string' The default string is filter_in. For example, if you specify the string 'filter_data_in' for filter entity Hd, the generated
entity declaration might look as follows: ENTITY Hd IS PORT( clk clk_enable reset filter_data_in filter_out ); END Hd; : : : : : IN IN IN IN std_logic;
std_logic; std_logic; std_logic_vector (15 DOWNTO 0); OUT std_logic_vector (15 DOWNTO 0); If you specify a string that is a VHDL reserved word, a
reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved word signal, the resulting name string
would be signal_rsvd. See ReservedWordPostfix for more information. See Also ClockEnableInputPort, ClockInputPort, OutputPort, OutputType,
ResetInputPort 7-53 InputType Purpose Settings Specify HDL data type for filter's input port 'std_logic_vector' Specifies VHDL type STD_LOGIC_VECTOR
for the filter input port. 'signed/unsigned' Specifies VHDL type SIGNED or UNSIGNED for the filter input port. 'wire' (Verilog) If the target language is
Verilog, the data type for all ports is wire.
This property is not modifiable in this case. See Also ClockEnableInputPort, ClockInputPort, InputPort, OutputPort, OutputType, ResetInputPort 7-54
InstanceGenerateLabel Purpose Settings Specify string to append to instance section labels in VHDL GENERATE statements 'string' Specify a postfix string
to append to instance section labels in VHDL GENERATE statements. The default string is _gen. See Also BlockGenerateLabel, OutputGenerateLabel 7-55
InstancePrefix Purpose Settings Specify string prefixed to generated component instance names 'string' Specify a string to be prefixed to component instance
names in generated code. The default string is u_. 7-56 LoopUnrolling Purpose Settings Specify whether VHDL FOR and GENERATE loops are unrolled and
omitted from generated VHDL cod 'on' Unroll and omit FOR and GENERATE loops from the generated VHDL code. Verilog is always unrolled. This option
takes into account that some EDA tools do not support GENERATE loops. If you are using such a tool, enable this option to omit loops from your generated
VHDL code. 'off' (default) Include FOR and GENERATE loops in the generated VHDL code.
Usage Notes See Also The setting of this option does not affect generated VHDL code during simulation or synthesis. CastBeforeSum, InlineConfigurations,
LoopUnrolling, SafeZeroConcat, UseAggregatesForConst, UseRisingEdge 7-57 MultifileTestBench Purpose Settings Divide generated test bench into helper
functions, data, and HDL test bench code files 'on' Write separate files for test bench code, helper functions, and test bench data. The file names are derived
from the test bench name and the TestBenchDataPostfix property as follows: TestBenchName_TestBenchDataPostfix For example, if the test bench name is
my_fir_filt, and the target language is VHDL, the default test bench file names are: my_fir_filt_tb.vhd: test bench code my_fir_filt_tb_pkg.vhd: helper
functions package my_fir_filt_tb_data.
vhd: test vector data package If the test bench name is my_fir_filt and the target language is Verilog, the default test bench file names are: my_fir_filt_tb.v:
test bench code my_fir_filt_tb_pkg.v: helper functions package my_fir_filt_tb_data.v: test bench data 'off' (default) Write a single test bench file containing
all HDL test bench code and helper functions and test bench data. See Also TestBenchName, TestBenchDataPostFix 7-58 MultiplierInputPipeline Purpose
Settings Specify number of pipeline stages at multiplier inputs for FIR filters nStages Default: 0.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
nStages must be an integer greater than or equal to 0. MultiplierInputPipeline lets you specify generation of pipeline stages at multiplier inputs for all FIR
filter structures. Multiplier pipelining can help you achieve significantly higher clock rates. Usage Notes See Also The coder ignores this property if
CoeffMultipliers is not set to 'multipliers'. CoeffMultipliers 7-59 MultiplierOutputPipeline Purpose Settings Specify number of pipeline stages at multiplier
outputs for FIR filters nStages Default: 0. nStages must be an integer greater than or equal to 0. MultiplierOutputPipeline lets you specify generation of
pipeline stages at multiplier outputs for all FIR filter structures. Multiplier pipelining can help you achieve significantly higher clock rates. Usage Notes See
Also The coder ignores this property if CoeffMultipliers is not set to 'multipliers'. CoeffMultipliers 7-60 Name Purpose Settings Specify file name for
generated HDL code and name for filter's VHDL entity or Verilog module 'string' The defaults take the name of the filter as defined in the FDATool.
The file type extension for the generated file is the string specified for the file type extension option for the selected language. The generated file is placed in
the folder or path specified by TargetDirectory. If you specify a string that is a reserved word in the selected language, the coder appends the string specified
by ReservedWordPostfix. For a list of reserved words, see "Setting the Postfix String for Resolving HDL Reserved Word Conflicts" on page 3-42. See Also
TargetDirectory, VerilogFileExtension, VHDLFileExtension 7-61 OptimizeForHDL Purpose Settings Specify whether generated HDL code is optimized for
specific performance or space requirements 'on' Generate HDL code that is optimized for specific performance or space requirements. As a result of these
optimizations, the coder may Make tradeoffs concerning data types Avoid excessive quantization Generate code that produces numeric results that differ
from results produced by the original filter function 'off' (default) Generate HDL code that maintains bit compatibility with the numeric results produced by
the original filter function. See Also AddPipelineRegisters, CoeffMultipliers, FIRAdderStyle 7-62 OutputGenerateLabel Purpose Settings Specify string that
labels output assignment block for VHDL GENERATE statements 'string' Specify a postfix string to append to output assignment block labels in VHDL
GENERATE statements. The default string is outputgen. See Also BlockGenerateLabel, InstanceGenerateLabel 7-63 OutputPort Purpose Settings Name HDL
port for filter's output signals 'string' The default is filter_out. For example, if you specify 'filter_data_out' for filter entity Hd, the generated entity declaration
might look as follows: ENTITY Hd IS PORT( clk clk_enable reset filter_in filter_data_out ); ENDHd; : : : : : IN IN IN IN std_logic; std_logic; std_logic;
std_logic_vector (15 DOWNTO 0); OUT std_logic_vector (15 DOWNTO 0); If you specify a string that is a VHDL reserved word, a reserved word postfix
string is appended to form a valid VHDL identifier.
For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information. See
Also ClockEnableInputPort, ClockInputPort, InputPort, InputType, OutputType, ResetInputPort 7-64 OutputType Purpose Settings Specify HDL data type for
filter's output port 'Same as input data type' (VHDL default) The filter's output port has the same type as the specified input port type. 'std_logic_vector' The
filter's output port has VHDL type STD_LOGIC_VECTOR. 'signed/unsigned' The filter's input port has type SIGNED or UNSIGNED.
'wire' (Verilog) If the target language is Verilog, the data type for all ports is wire. This property is not modifiable in this case.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
See Also ClockEnableInputPort, ClockInputPort, InputPort, InputType, OutputPort, ResetInputPort 7-65 PackagePostfix Purpose Settings Specify string to
append to specified filter name to form name of VHDL package file 'string' The coder applies this option only if a package file is required for the design. The
default string is _pkg. See Also ClockProcessPostfix, CoeffPrefix, EntityConflictPostfix, ReservedWordPostfix 7-66 RemoveResetFrom Purpose Settings
Suppress generation of resets from shift registers 'none' (default) Do not suppress generation of resets from shift registers.
'ShiftRegister' Suppress generation of resets from shift registers. See Also "Suppressing Generation of Reset Logic" on page 3-35 7-67 ReservedWordPostfix
Purpose Settings Specify string to append to value names, postfix values, or labels that are VHDL or Verilog reserved words 'string' The default postfix is
_rsvd. For example, if you name your filter mod, the coder adds the postfix _rsvd to form the name mod_rsvd. See Also ClockProcessPostfix, CoeffPrefix,
EntityConflictPostfix, PackagePostfix 7-68 ResetAssertedLevel Purpose Settings Specify asserted (active) level of reset input signal 'active-high' (default)
Specify that the reset input signal must be driven high (1) to reset registers in the filter design. For example, the following code fragment checks whether reset
is active high before populating the delay_pipeline register: Delay_Pipeline_Process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0
TO 50) [= (OTHERS =] (OTHERS =] '0')); . 'active-low' Specify that the reset input signal must be driven low (0) to reset registers in the filter design. For
example, the following code fragment checks whether reset is active low before populating the delay_pipeline register: Delay_Pipeline_Process : PROCESS
(clk, reset) BEGIN IF reset = '0' THEN delay_pipeline(0 TO 50) [= (OTHERS =] (OTHERS =] '0')); . See Also ResetType 7-69 ResetInputPort Purpose
Settings Name HDL port for filter's reset input signals 'string' The default name for the filter's reset input port is reset. For example, if you specify the string
'filter_reset' for filter entity Hd, the generated entity declaration might look as follows: ENTITY Hd IS PORT( clk clk_enable filter_reset filter_in filter_out );
END Hd; : : : : : IN IN IN IN std_logic; std_logic; std_logic; std_logic_vector (15 DOWNTO 0); OUT std_logic_vector (15 DOWNTO 0); If you specify a
string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved
word signal, the resulting name string would be signal_rsvd.
See ReservedWordPostfix for more information. Usage Notes If the reset asserted level is set to active high, the reset input signal is asserted active high (1)
and the input value must be high (1) for the entity's registers to be reset. If the reset asserted level is set to active low, the reset input signal is asserted active
low (0) and the input value must be low (0) for the entity's registers to be reset. ClockEnableInputPort, ClockInputPort, InputPort, InputType, OutputPort,
OutputType See Also 7-70 ResetLength Purpose Settings Define length of time (in clock cycles) during which reset is asserted N Default: 2. N must be an
integer greater than or equal to 0. Resetlength defines N, the number of clock cycles during which reset is asserted. The following figure illustrates the default
case, in which the reset signal (active-high) is asserted for 2 clock cycles. 7-71 ResetType Purpose Settings Specify whether to use asynchronous or
synchronous reset style when generating HDL code for registers 'async' (default) Use an asynchronous reset style. The following generated code fragment
illustrates the use of asynchronous resets. Note that the process block does not check for an active clock before performing a reset.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
delay_pipeline_process : PROCESS (clk, reset) BEGIN IF Reset_Port = 1 THEN delay_pipeline (0 To 50) [= (OTHERS =](OTHERS =] '0')); ELSIF
Clock_Port event AND Clock_Port = IF ClockEnable_Port = 1 THEN 1 THEN delay_pipeline(0) [= signed(Fin_Port) delay_pipeline(1 TO 50) [=
delay_pipeline(0 TO 49); END IF; END IF; END PROCESS delay_pipeline_process; 'sync' Use a synchronous reset style. Code for a synchronous reset
follows. This process block checks for a clock event, the rising edge, before performing a reset. delay_pipeline_process : PROCESS (clk, reset) BEGIN IF
rising_edge(Clock_Port) THEN IF Reset_Port = 0 THEN delay_pipeline(0 To 50) [= (OTHERS =](OTHERS =] '0')); ELSIF ClockEnable_Port = 1 THEN
delay_pipeline(0) [= signed(Fin_Port) delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49); END IF; END IF; END PROCESS delay_pipeline_process;
7-72 ResetType See Also ResetAssertedLevel 7-73 ReuseAccum Purpose Settings Enable accumulator reuse, generating cascade-serial architecture for FIR
filters 'off' (default) Disable accumulator reuse. 'on' Enable accumulator reuse when generating a partly serial architecture.
(i.e., a cascade-serial architecture). If the number and size of serial partitions is not specified (see SerialPartition), the coder generates an optimal partition.
Usage Notes In a cascade-serial architecture, filter taps are grouped into a number of serial partitions, and the accumulated output of each partition is
cascaded to the accumulator of the previous partition.
The output of all partitions is therefore computed at the accumulator of the first partition. This technique, termed accumulator reuse, saves chip area. See
"Speed vs. Area Optimizations for FIR Filters" on page 4-10 for a complete description of parallel and serial architectures and a list of filter types supported
for each architecture. See Also SerialPartition 7-74 SafeZeroConcat Purpose Settings Specify syntax used in generated VHDL code for concatenated zeros
'on' (default) Use the type-safe syntax, '0' & '0', for concatenated zeros. Typically, this syntax is preferred. 'off' Use the syntax "000000." for concatenated
zeros. This syntax can be easier to read and is more compact, but can lead to ambiguous types. See Also CastBeforeSum, InlineConfigurations,
LoopUnrolling, UseAggregatesForConst, UseRisingEdge 7-75 SerialPartition Purpose Settings Specify number and size of partitions generated for serial FIR
filter architectures N Generate a fully serial architecture for a filter of length N.
[p1 p2 p3.pN] Where [p1 p2 p3.pN] is a vector of N integers, generate a partly serial architecture with N partitions. Each element of the vector specifies the
length of the corresponding partition. The sum of the vector elements must be equal to the length of the filter. Usage Notes To save chip area in a partly serial
architecture, you can enable the ReuseAccum property. See "Speed vs. Area Optimizations for FIR Filters" on page 4-10 for a complete description of
parallel and serial architectures and a list of filter types supported for each architecture. See Also ReuseAccum 7-76 SimulatorFlags Purpose Settings Specify
simulator flags applied to generated test bench 'string' Specify options that are specific to your application and the simulator you are using. For example, if
you must use the 10761993 VHDL compiler, specify the flag -93.
Usage Notes The flags you specify with this option are added to the compilation command in generated EDA tool scripts. The compilation command string is
specified by the HDLCompileVHDLCmd or HDLCompileVerilogCmd properties. HDLCompileVerilogCmd, HDLCompileVHDLCmd See Also 7-77
SplitArchFilePostfix Purpose Settings Specify string to append to specified name to form name of file containing filter's VHDL architecture 'string' The default
is _arch. This option applies only if you direct the coder to place the filter's entity and architecture in separate files.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Usage Notes See Also The option applies only if you direct the coder to place the filter's entity and architecture in separate files.
SplitEntityArch, SplitEntityFilePostfix 7-78 SplitEntityArch Purpose Settings Specify whether generated VHDL entity and architecture code is written to
single VHDL file or to separate files 'on' Write the code for the filter VHDL entity and architecture to separate files. The names of the entity and architecture
files derive from the base file name (as specified by the filter name). By default, postfix strings identifying the file as an entity (_entity) or architecture (_arch)
are appended to the base file name. You can override the default and specify your own postfix string. The file type extension is specified by the VHDL file
extension option.
For example, instead of all generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd. 'off'
(default) Write the generated filter VHDL code to a single file. See Also SplitArchFilePostfix, SplitEntityFilePostfix 7-79 SplitEntityFilePostfix Purpose
Settings Specify string to append to specified filter name to form name of file that contains filter's VHDL entity 'string' The default is _entity. This option
applies only if you direct the coder to place the filter's entity and architecture in separate files. Usage Notes See Also This option applies only if you direct the
coder to place the filter's entity and architecture in separate files. SplitArchFilePostfix, SplitEntityArch 7-80 TargetDirectory Purpose Settings Identify folder
into which generated output files are written Specify the subfolder under the current working folder into which generated files are written. The string can
specify a complete pathname.
The default string is hdlsrc. Name, VerilogFileExtension, VHDLFileExtension See Also 7-81 TargetLanguage Purpose Settings Specify HDL language to use
for generated filter code 'VHDL' (default) Generate VHDL filter code. 'verilog' Generate Verilog filter code. 7-82 TestBenchClockEnableDelay Purpose
Settings Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable N (integer number of clock cycles) Default: 1 The
TestBenchClockEnableDelay property specifies a delay time N, expressed in clock cycles (the default value is 1) elapsed between the time the reset signal is
deasserted and the time the clock enable signal is first asserted. TestBenchClockEnableDelay works in conjunction with the HoldTime property. After
deassertion of reset, the clock enable goes high after a delay of N clock cycles plus the delay specified by HoldTime. In the figure below, the reset signal
(active-high) deasserts after the interval labeled Hold Time. The clock enable asserts after a further interval labeled Clock enable delay. See Also HoldTime,
ResetLength 7-83 TestbenchCoeffStimulus Purpose Settings Specify testing options for coefficient memory interface for FIR or IIR filters [] : Empty vector
(default) When the value of TestbenchCoeffStimulus is unspecified (or set to the default value of []). the test bench loads the coefficients from the filter object
and then forces the input stimuli.
This shows the response to the input stimuli and verifies that the interface correctly writes one set of coefficients into the RAM. (For FIR filters): vector of
coefficient values . In this case, the filter processes the input stimuli twice. First, the test bench loads the coefficients from the filter object and forces the input
stimuli to show the response. Then, the filter loads the set of coefficients specified in the TestbenchCoeffStimulus vector, and shows the response by processing
the same input stimuli for a second time.
In this case, the internal states of the filter, as set by the first run of the input stimulus, are retained. The testbench verifies that the interface writes two
different sets of coefficients into the RAM.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
See "Specifying Programmable Filter Coefficients for FIR Filters" on page 3-64 for further information. (for IIR filters): Cell array containing a column
vector of scale values, and a second-order section (SOS) matrix for the filter. See "Specifying Programmable Filter Coefficients for IIR Filters" on page 3-77
for further information.
See Also CoefficientSource 7-84 TestBenchDataPostFix Purpose Settings Specify suffix added to test bench data file name when generating multi-file test
bench 'string' The default postfix is '_data'. The coder applies TestBenchDataPostFix only when generating a multi-file test bench (i.e., when
MultifileTestBench is set 'on'). For example, if the name of your test bench is test_fir_tb, the coder adds the postfix _data to form the test bench data file name
test_fir_tb_data. See Also MultifileTestBench 7-85 TestBenchFracDelayStimulus Purpose Settings Specify input stimulus that test bench applies to Farrow
filter fractional delay port Note This option applies only to Farrow filters. Default: A constant value is obtained from the FracDelay property of the Farrow
filter object, and applied to the fractional delay port. 'RandSweep' A vector of values incrementally increasing over the range from 0 to 1. This stimulus signal
has the same duration as the filter's input signal, but changes at a slower rate. Each fractional delay value obtained from the vector is held for 10% of the
total duration of the input signal before the next value is obtained.
'RampSweep' A vector of random values in the range from 0 to 1. This stimulus signal has the same duration as the filter's input signal, but changes at a
slower rate. Each fractional delay value obtained from the vector is held for 10% of the total duration of the input signal before the next value is obtained.
Vector or function returning a vector Define a vector as a workspace variable, store the stimulus signal in the vector, and pass in the vector name.
Alternatively, pass in a call to any function that returns a vector. See Also FracDelayPort, "Generating Code for Single-Rate Farrow Filters" on page 3-105
7-86 TestBenchName Purpose Settings Name VHDL test bench entity or Verilog module and file that contains test bench code 'string' The file type extension
depends on the type of test bench that is being generated. If the Test Bench Is a. Verilog file VHDL file The Extension Is. Defined by the Verilog file extension
option Defined by the VHDL file extension option The file is placed in the target folder. If you specify a string that is a VHDL or Verilog reserved word, a
reserved word postfix string is appended to form a valid HDL identifier.
For example, if you specify the reserved word entity, the resulting name string would be entity_rsvd. To set the reserved word postfix string, see
ReservedWordPostfix. See Also ClockHighTime, ClockLowTime, ForceClock, ForceClockEnable, ForceReset, HoldTime 7-87 TestBenchReferencePostFix
Purpose Settings Specify string appended to names of reference signals generated in test bench code 'string' The default postfix is '_ref'. Reference signal data
is represented as arrays in the generated test bench code. The string specified by TestBenchReferencePostFix is appended to the generated signal names.
7-88 TestBenchStimulus Purpose Settings Specify input stimuli that test bench applies to filter 'impulse' Specify that the test bench acquire an impulse stimulus
response. The impulse response is output arising from the unit impulse input sequence defined such that the value of x(n) is 1 when n equals 1 and x(n) equals
0 when n does not equal 1. 'step' Specify that the test bench acquire a step stimulus response. 'ramp' Specify that the test bench acquire a ramp stimulus
response, which is a constantly increasing or constantly decreasing signal. 'chirp' Specify that the test bench acquire a chirp stimulus response, which is a
linear swept-frequency cosine signal.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
'noise' Specify that the test bench acquire a white noise stimulus response. The coder assigns default stimuli based on the filter type. Usage Notes You can
specify any combination of stimuli in any order. If you specify multiple stimuli, specify the appropriate strings in a cell array. For example: {'impulse', 'ramp',
'noise'} See Also TestBenchUserStimulus 7-89 TestBenchUserStimulus Purpose Settings Specify user-defined function that returns vector of values that test
bench applies to filter function call For example, the following function call generates a square wave with a sample frequency of 8 bits per second (Fs/8):
repmat([1 1 1 1 0 0 0 0], 1, 10) See Also TestBenchStimulus 7-90 UseAggregatesForConst Purpose Settings Specify whether all constants are represented by
aggregates, including constants that are less than 32 bits wide 'on' Specify that all constants, including constants that are less than 32 bits, be represented by
aggregates. The following VHDL constant declarations show scalars less than 32 bits being declared as aggregates: CONSTANT c1: signed(15 DOWNTO
0):= (5 DOWNTO 3 =]'0',1 DOWNTO 0 =] '0',OTHERS =]'1'); CONSTANT c2: signed(15 DOWNTO 0):= (7 =] '0',5 DOWNTO 4 =]'0',0 =] '0',OTHERS
=]'1'); 'off' (default) Specify that the coder represent constants less than 32 bits as scalars and constants greater than or equal to 32 bits as aggregates. This
is the default. The following VHDL constant declarations are examples of declarations generated by default for values less than 32 bits: CONSTANT coeff1:
signed(15 DOWNTO 0) := to_signed(-60, 16); -- sfix16_En16 CONSTANT coeff2: signed(15 DOWNTO 0) := to_signed(-178, 16); -- sfix16_En16 See Also
CastBeforeSum, InlineConfigurations, , LoopUnrolling, SafeZeroConcat, UseRisingEdge, UseVerilogTimescale 7-91 UserComment Purpose Settings Specify
comment line in header of generated filter and test bench files 'string' The comment is generated in each of the generated code and test bench files. The code
generator adds leading comment characters as appropriate for the target language. When newlines or line feeds are included in the string, the code generator
emits single-line comments for each newline.
For example, the following generatehdl command adds two comment lines to the header in a generated VHDL file. generatehdl(Hlp,'UserComment','This is a
comment line.\nThis is a second line.') The resulting header comment block for filter Hlp would appear as follows: --
--------------------------------------------------------------- Module: Hlp --- Generated by MATLAB(R) 7.4 and --- Generated on: 2006-11-20 16:27:42 --- This is a
comment line. -- This is a second line. --- ------------------------------------------------------------Filter Design HDL Coder 2.0. 7-92 UseRisingEdge Purpose
Settings Specify VHDL coding style used to check for rising edges when operating on registers 'on' Use the VHDL rising_edge function to check for rising
edges when operating on registers. The generated code applies rising_edge as shown in the following PROCESS block: Delay_Pipeline_Process : PROCESS
(clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 50) [= (OTHERS =] (OTHERS =] '0')); ELSIF rising_edge(clk) THEN IF clk_enable = '1'
THEN delay_pipeline(0) [= signed(filter_in); delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49); END IF; END IF; END PROCESS
Delay_Pipeline_Process ; 'off' (default) Check for clock events when operating on registers.
The generated code checks for a clock event as shown in the ELSIF statement of the following PROCESS block: Delay_Pipeline_Process : PROCESS (clk,
reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 50) [= (OTHERS =] (OTHERS =] '0')); ELSIF clk event AND clk = 1 THEN IF clk_enable = '1'
THEN delay_pipeline(0) [= signed(filter_in); delay_pipeline(1 TO 50) [= delay_pipeline(0 TO 49); END IF; 7-93 UseRisingEdge END IF; END PROCESS
Delay_Pipeline_Process ; Usage Notes See Also The two coding styles have different simulation behavior when the clock transitions from 'X' to '1'.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
CastBeforeSum, InlineConfigurations, LoopUnrolling, SafeZeroConcat, UseAggregatesForConst 7-94 UseVerilogTimescale Purpose Settings Allow or
exclude use of compiler `timescale directives in generated Verilog code 'on' (default) Use compiler `timescale directives in generated Verilog code. 'off'
Suppress the use of compiler `timescale directives in generated Verilog code. Usage Notes See Also The `timescale directive provides a way of specifying
different delay values for multiple modules in a Verilog file. CastBeforeSum, InlineConfigurations, LoopUnrolling, SafeZeroConcat, UseAggregatesForConst,
UseRisingEdge 7-95 VectorPrefix Purpose Settings Specify string prefixed to vector names in generated VHDL code 'string' Specify a string to be prefixed to
vector names in generated VHDL code.
The default string is vector_of_. 7-96 VerilogFileExtension Purpose Settings Specify file type extension for generated Verilog files 'string' The default file type
extension for generated Verilog files is .v. See Also Name, TargetDirectory 7-97 VHDLArchitectureName Purpose Settings Specify architecture name for
generated VHDL code 'string' The default string is rtl. 7-98 VHDLFileExtension Purpose Settings Specify file type extension for generated VHDL files 'string'
The default file type extension for generated VHDL files is .
vhd. See Also Name, TargetDirectory 7-99 VHDLLibraryName Purpose Settings Specify target library name used in initialization section of compilation
script 'string' The default string is 'work'. At script generation time, the string you specify as VHDLLibraryName substitutes into the HDLCompileInit string
value. By default, this generates the library specification'vlib work/n' You can use VHDLLibraryName to avoid library name conflicts. See Also
HDLCompileInit "Generating Scripts for EDA Tools" on page 3-143 7-100 8 Function Reference fdhdltool Purpose Syntax Description Open Generate HDL
dialog box fdhdltool(Hd) fdhdltool(Hd) is a convenience function that lets you open the Generate HDL dialog box from the command line, passing in the filter
object handle Hd. When the Generate HDL dialog box opens, it displays default values for code generation options applicable to the filter object. You can
then use the Generate HDL dialog box and its subordinate dialog boxes to specify code generation options and initiate generation of HDL and test bench
code and scripts for third-party EDA tools. fdhdltool operates on a copy of the filter object, rather than the original object in the workspace. Any changes
made to the original filter object after fdhdltool is invoked will not affect the copy and will not update the Generate HDL dialog box. The naming convention
for the copied object is filt_copy, where filt is the name of the original filter object.
Example The following code example designs a lowpass filter, constructs a direct-form FIR filter object, Hd, and then opens the Generate HDL dialog box.
filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear'); Hd = design(filtdes,'filterstructure','dffir'); Hd.arithmetic = 'fixed'; fdhdltool(Hd); % open
Generate HDL dialog box See Also "Opening the Generate HDL Dialog Box" on page 3-4 8-2 generatehdl Purpose Syntax Description Generate HDL code
for quantized filter generatehdl(Hd) generatehdl(Hd 'PropertyName', 'PropertyValue',.) generatehdl(Hd) generates HDL code for a quantized filter. The
argument Hd must be a handle to a filter object. The function uses default settings for properties that determine file and HDL element naming, whether
optimizations are applied, HDL coding styles, and test bench characteristics.
The defaults are summarized below. Defaults for Naming, Location and Packaging of Generated Files Places generated files in the target folder hdlsrc and
names the files as follows: File Verilog source VHDL source VHDL package Name Hd.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
v, where Hd is the name of the specified filter object Hd.vhd, where Hd is the name of the specified filter object Hd_pkg.vhd, where Hd is the name of the
specified filter object Places generated files in a subfolder name hdlsrc, under your current working folder.
Includes the VHDL entity and architecture code in a single source file. Generates script files for third-party EDA tools. Where Hd is the name of the
specified filter object, the following script files are generated: -- Hd_compile.do :Mentor Graphics ModelSim compilation script. This script contains
commands to compile the generated filter code, but not to simulate it.
8-3 generatehdl -- Hd_synplify.tcl : Synplify synthesis script Default Settings for Register Resets Uses an asynchronous reset when generating HDL code for
registers. Uses an active-high (1) signal for register resets. Default Settings for General HDL Code Names the generated VHDL entity or Verilog module
with the name of the quantized filter. Names a filter's HDL ports as follows: HDL Port Input Output Clock input Clock enable input Reset input Name
filter_in filter_out clk clk_enable reset Sets the data type for clock input, clock enable input, and reset ports to STD_LOGIC and data input and output ports
to VHDL type STD_LOGIC_VECTOR or Verilog type wire. Names coefficients as follows: For. FIR filters IIR filters Names Coefficients. coeffn, where n is
the coefficient number, starting with 1 coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number 8-4 generatehdl When
declaring signals of type REAL, initializes the signal with a value of 0.0. Places VHDL configurations in any file that instantiates a component.
Appends _rsvd to names that are VHDL or Verilog reserved words. Uses a type safe representation when concatenating zeros: '0' & '0'. Applies the
statement IF clock'event AND clock='1' THEN to check for clock events. Adds an extra input register and an extra output register to the filter. Appends
_process to process names. When creating labels for VHDL GENERATE statements: -- Appends _gen to section and block names. -- Names output
assignment blocks with the string outputgen. Default Settings for Code Optimizations Generates HDL code that is bit-true to the original filter function and
is not optimized for performance or space requirements. Applies a linear final summation to FIR filters. This is the form of summation explained in most
DSP text books.
Enables multiplier operations for a filter, as opposed to replacing them with additions of partial products. generatehdl(Hd 'PropertyName',
'PropertyValue',.) generates HDL code for the filter identified by Hd, using the specified property name and property value pair settings. You can specify the
function with one or more of the property name and property value pairs 8-5 generatehdl described in Chapter 6, "Property Reference", and Chapter 7,
"Properties -- Alphabetical List". Example 1 Design a filter.
The call to fdesign in the following command line sequence designs a minimum order lowpass filter with a normalized passband frequency of 0.2, a stopband
frequency of 0.22, a passband ripple of 1 dB, and a stopband attenuation of 60 dB. 2 Construct a filter object. The call to design constructs the FIR equiripple
filter object Hd.
3 Set the filter arithmetic. The arithmetic assignment statement sets the filter arithmetic to fixed-point arithmetic. 4 Generate VHDL code for the filter. The
call to generatehdl generates VHDL code for the FIR equiripple filter Hd. The function names the file MyFilter.vhd and places it in the default target folder
hdlsrc. d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2, 0.22, 1, 60); Hd = design(d, 'equiripple'); Hd.
arithmetic='fixed'; generatehdl(Hd, 'Name', 'MyFilter'); %Generate VHDL code % Create filter See Also generatetb, generatetbstimulus 8-6 generatetb
Purpose Syntax Generate HDL test bench for quantized filter generatetb(Hd, 'TbType') generatetb(Hd 'TbType', 'PropertyName', 'PropertyValue',.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
) generatetb(Hd) generatetb(Hd, 'PropertyName', 'PropertyValue',.) generatetb(Hd, 'TbType') generates a HDL test bench of a specified type to verify the
HDL code generated for the quantized filter identified by Hd. The argument Hd must be a handle to a filter object. The value that you specify for 'TbType'
identifies the type of test bench to be generated and can be one of the values shown in the following table (or a cell array that contains one or more of these
values). Description If you do not specify the 'TbType' argument, the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or
'Verilog'). Specify. 'Verilog' 'VHDL' To Generate a Test Bench Consisting of. Verilog code VHDL code The generated test bench applies input stimuli based
on the setting of the properties TestBenchStimulus and TestBenchUserStimulus. The coder assigns default stimuli based on the filter type.
The following choices of stimuli are available: 'impulse' 'step' 'ramp' 'chirp' 'noise' 8-7 generatetb The function uses default settings for other properties
that determine test bench characteristics. By default the function does the following. Default Settings for the Test Bench Places the generated test bench file
in the target folder hdlsrc under your current working folder with the name Hd_tb and a file type extension that is based on the type of test bench you are
generating. If the Test Bench Is a. Verilog file VHDL file The Extension Is.
Defined by the property VerilogFileExtension Defined by the property VHDLFileExtension Generates script files for third-party EDA tools. Where Hd is the
name of the specified filter object, the following script files are generated: -- Hd_tb_compile.do :Mentor Graphics ModelSim compilation script. This script
contains commands to compile the generated filter and test bench code. -- Hd_tb_sim.
do: Mentor Graphics ModelSim simulation script. This script contains commands to run a simulation of the generated filter and test bench code. Forces
clock, clock enable, and reset input signals. Forces clock enable and reset input to active high. Drives the clock input signal high (1) for 5 nanoseconds and
low (0) for 5 nanoseconds. Forces reset signals. Applies a hold time of 2 nanoseconds to filter reset and data input signals. 8-8 generatetb For HDL test
benches, applies an error margin of 4 bits. Default Settings for Files Places generated files in the target folder hdlsrc and names the files as follows: File
Verilog source VHDL source VHDL package Name Hd.v, where Hd is the name of the specified filter object Hd.
vhd, where Hd is the name of the specified filter object Hd_pkg.vhd, where Hd is the name of the specified filter object Places generated files in a subfolder
name hdlsrc, under your current working folder. Includes VHDL entity and architecture code in a single source file. Default Settings for Register Resets
Uses an asynchronous reset when generating HDL code for registers. Asserts the reset input signal high (1) to reset registers in the design. Default Settings
for General HDL Code Names the generated VHDL entity or Verilog module with the name of the filter. Names the filter's HDL ports as follows: HDL Port
Input Output Name filter_in filter_out 8-9 generatetb HDL Port Clock input Clock enable input Reset input Name clk clk_enable reset Sets the data type for
clock input, clock enable input, and reset ports to STD_LOGIC and data input and output ports to VHDL type STD_LOGIC_VECTOR or Verilog type wire.
Names coefficients as follows: For. FIR filters IIR filters Names Coefficients. coeffn, where n is the coefficient number, starting with 1 coeff_xm_sectionn,
where x is a or b, m is the coefficient number, and n is the section number When declaring signals of type REAL, initializes the signal with a value of 0.
0. Places VHDL configurations in any file that instantiates a component.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Appends _rsvd to names that are VHDL or Verilog reserved words. Uses a type safe representation when concatenating zeros: '0' & '0'. Applies the
statement IF clock'event AND clock='1' THEN to check for clock events.
Allows scale values to be up to 3 bits smaller than filter input values. 8-10 generatetb Adds an extra input register and an extra output register to the filter.
Appends _process to process names. When creating labels for VHDL GENERATE statements: -- Appends _gen to section and block names. -- Names output
assignment blocks with the string outputgen Default Settings for Code Optimizations Generates HDL code that is bit-true to the original filter function and is
not optimized for performance or space requirements.
Applies a linear final summation to FIR filters. This is the form of summation explained in most DSP text books. Enables multiplier operations for a filter,
as opposed to replacing them with additions of partial products. generatetb(Hd 'TbType', 'PropertyName', 'PropertyValue',.) generates an HDL test bench of
a specified type to verify the HDL code generated for the quantized filter identified by Hd, using the specified property name and property value pair settings.
You can specify the function with one or more of the property name and property value pairs described in Chapter 6, "Property Reference", and Chapter 7,
"Properties -- Alphabetical List". generatetb(Hd) generates an HDL test bench to verify the HDL code generated for the quantized filter identified by Hd The
'TbType' argument is omitted, and the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or 'Verilog'). generatetb(Hd,
'PropertyName', 'PropertyValue',.) generates an HDL test bench to verify the HDL code generated for the quantized filter identified by Hd, using the specified
property name and property value pair settings. The 'TbType' argument is omitted, and the test bench type defaults to the current setting of the
TargetLanguage property ('VHDL' or 'Verilog').
8-11 generatetb You can specify the function with one or more of the property name and property value pairs described in Chapter 6, "Property Reference",
and Chapter 7, "Properties -- Alphabetical List". Example 1 Design a filter. The call to fdesign in the following command line sequence designs a minimum
order lowpass filter with a normalized passband frequency of 0.2, a stopband frequency of 0.22, a passband ripple of 1 dB, and a stopband attenuation of 60
dB. 2 Construct a filter object. The call to design constructs the FIR equiripple filter object Hd. 3 Set the filter arithmetic. The arithmetic assignment
statement sets the filter arithmetic to fixed-point arithmetic. 4 Generate VHDL code for the filter.
The call to generatehdl generates VHDL code for the filter Hd. The function names the file MyFilter.vhd and places it in the default target folder hdlsrc. 5
Generate a test bench for the filter. The call to generatetb generates a VHDL test bench for the filter Hd named MyFilterTB.
vhd and places the generated test bench file in the default target folder hdlsrc. d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2, 0.22, 1, 60); Hd = design(d,
'equiripple'); % Create FIR equiripple filter Hd.
arithmetic='fixed'; %Quantized filter with default settings generatehdl(Hd, 'Name', 'MyFilter'); %Generate filter's VHDL code generatetb(Hd, 'VHDL',
'TestBenchName', 'MyFilterTB'); See Also generatetbstimulus, generatehdl 8-12 generatetbstimulus Purpose Syntax Generate and return HDL test bench
stimulus generatetbstimulus(Hd) generatetbstimulus(Hd, 'PropertyName', 'PropertyValue'.) x = generatetbstimulus(Hd, 'PropertyName', 'PropertyValue'.)
generatetbstimulus(Hd) generates and returns filter input stimulus for the filter Hd, where Hd is a handle to a filter object. The stimulus is generated based on
the setting of the properties TestBenchStimulus and TestBenchUserStimulus. Description The generated test bench applies input stimuli based on the setting of
the properties TestBenchStimulus and TestBenchUserStimulus.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
The coder assigns default stimuli based on the filter type. The following choices of stimuli are available: 'impulse' 'step' 'ramp' 'chirp' 'noise' Note The
function quantizes the results by applying the reference coefficients of the specified quantized filter. generatetbstimulus(Hd, 'PropertyName', 'PropertyValue'.)
generates and returns filter input stimuli for the filter Hd based on specified settings for TestBenchStimulus and TestBenchUserStimulus. x =
generatetbstimulus(Hd, 'PropertyName', 'PropertyValue'.
) generates and returns filter input stimuli for the filter Hd based on specified settings for TestBenchStimulus and 8-13 generatetbstimulus
TestBenchUserStimulus and writes the output to x for future use or reference. Example 1 Generate and return test bench stimuli. The call to
generatetbstimulus in the following command line sequence generates ramp and chirp stimuli and returns the results to y. 2 Apply a quantized filter to the
data and plot the results. The call to the filter function applies the quantized filter Hd to the data that was returned to y and gains access to state and filtering
information. The plot function then plots the resulting data. y = generatetbstimulus(Hd, 'TestBenchStimulus', {'ramp', 'chirp'}); %Generate and return test
bench stimuli plot(filter(Hd,y)); %Apply a quantized filter to the data and plot the results See Also generatetb 8-14 hdlgetserialpartition Purpose Syntax Serial
partition information for filter object hdlgetserialpartition (Hd) hdlgetserialpartition (Hd,'FoldingFactor, ff) hdlgetserialpartition (Hd,'Multipliers, nmults)
hdlgetserialpartition (Hd,'SerialPartition', [p1 p2.pN]) [sp,fold,nm] = hdlgetserialpartition(Hd) [sp,fold,nm] = hdlgetserialpartition(Hd,'FoldingFactor, ff)
[sp,fold,nm] = hdlgetserialpartition(Hd,'Multipliers, nmults) [sp,fold,nm] = hdlgetserialpartition(Hd,'SerialPartition', [p1 p2.pN]) hdlgetserialpartition is an
informational function that Description helps you define an optimal serial partition for an FIR filter. hdlgetserialpartition provides answers to design
questions such as: What is the folding factor and associated number of multipliers that results from a particular choice of serial partition? What are all
valid serial partitions for a given filter? When you specify a serial architecture for a FIR filter, you can define the serial partitioning in any the following
ways: Directly specify a vector of integers having N elements, where N is the number of serial partitions.
Each element of the vector specifies the length of the corresponding partition. Specify the desired hardware folding factor ff, an integer greater than 1. Given
the folding factor, the coder computes the serial partition and the number of multipliers. Specify the desired number of multipliers nmults, an integer greater
than 1. Given the number of multipliers, the coder computes the serial partition and the folding factor.
8-15 hdlgetserialpartition By default, hdlgetserialpartition displays a table of possible serial partition vectors for a filter object Hd, with corresponding
values of folding factor and number of multipliers. Optionally, you can pass in a parameter/value pair specifying a serial partition vector, a folding factor, or
number of multipliers. In this case, hdlgetserialpartition displays the corresponding values for the other parameters. Optionally, you can also specify that
hdlgetserialpartition returns serial partition values and corresponding values of folding factor and number of multipliers to a cell array. hdlgetserialpartition
(Hd): for the filter object Hd, displays an exhaustive table of serial partition values with corresponding values of folding factor and number of multipliers.
hdlgetserialpartition (Hd,'FoldingFactor, ff): for the filter object Hd, displays the serial partition values and number of multipliers corresponding the folding
factor ff. hdlgetserialpartition (Hd,'Multipliers, nmults): for the filter object Hd, displays the serial partition values and folding factor corresponding to the
number of multipliers nmults.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
hdlgetserialpartition (Hd,'SerialPartition', [p1 p2.pN]): for the filter object Hd, displays the folding factor and number of multipliers corresponding to the
serial partition vector [p1p2.pN]. [sp,fold,nm] = hdlgetserialpartition(Hd): for the filter object Hd, returns an exhaustive table of serial partition values with
corresponding values of folding factor and number of multipliers to a cell array. [sp,fold,nm] = hdlgetserialpartition(Hd,'FoldingFactor, ff): for the filter
object Hd, returns the serial partition values and number of multipliers corresponding to the folding factor ff to a cell array. [sp,fold,nm] =
hdlgetserialpartition(Hd,'Multipliers, nmults): for the filter object Hd, displays the serial partition values and folding factor corresponding to the number of
multipliers nmults to a cell array. 8-16 hdlgetserialpartition [sp,fold,nm] = hdlgetserialpartition(Hd,'SerialPartition',[p1 p2.pN]): for the filter object Hd,
returns the folding factor and number of multipliers corresponding to the serial partition vector [p1p2.
pN] to a cell array. Input Arguments Hd A FIR filter object. See "Speed vs. Area Optimizations for FIR Filters" on page 4-10 for a summary of filter types that
support serial architectures. Parameter Name/Value Pairs The following parameter name/value inputs are optional. None of these parameters has a default
value; you must supply a valid value. FoldingFactor Hardware folding factor, an integer greater than 1 (or inf). If the folding factor is inf, the coder uses the
maximum folding factor. Given the folding factor, the coder computes the serial partition and the number of multipliers. Default: None Multipliers Desired
number of multipliers, an integer greater than 1 (or inf).
If the number of multipliers is inf, the coder uses the maximum number of multipliers. Given the number of multipliers, the coder computes the serial partition
and the folding factor. Default: None SerialPartition A vector of integers having N elements, where N is the number of serial partitions. Each element of the
vector specifies the length of the corresponding partition. 8-17 hdlgetserialpartition Default: None Output Arguments Examples [sp,fold,nm] Cell array.
hdlgetserialpartition returns, in order, the serial partition sp, folding factor fold and number of multipliers nm. Each of the following examples constructs a
direct-form FIR filter object, passes it to hdlgetserialpartition, and shows the results as displayed at the MATLAB command line. Pass only the filter object to
hdlgetserialpartition to display all valid serial partitions: Hd = design(fdesign.lowpass('N,Fc',8,.4)); Hd.
Arithmetic = 'fixed'; hdlgetserialpartition(Hd) Table of 'SerialPartition' values with corresponding values of folding factor and number of multipliers for the
given filter. | Folding Factor | Multipliers | SerialPartition | -----------------------------------------------------| | | | | | | | | 1 2 3 4 5 6 7 8 9 | | | | | | | | | 9 5 3 3 2 2 2
2 1 |[1 1 1 1 1 1 1 1 1] |[2 2 2 2 1] |[3 3 3] |[4 4 1] |[5 4] |[6 3] |[7 2] |[8 1] |[9] | | | | | | | | | Pass the filter object to hdlgetserialpartition, specifying the
desired number of multipliers as 3: Hd = design(fdesign.lowpass('N,Fc',8,.4)); Hd.Arithmetic = 'fixed'; 8-18 hdlgetserialpartition hdlgetserialpartition(Hd,
'Multipliers', 3) SerialPartition: [3 3 3], Folding Factor: 3, Multipliers: 3 Pass the filter object to hdlgetserialpartition, specifying the desired folding factor
as 4: Hd = design(fdesign.lowpass('N,Fc',8,.4)); Hd.Arithmetic = 'fixed'; hdlgetserialpartition(Hd, 'FoldingFactor', 4) SerialPartition: [4 4 1], Folding
Factor: 4, Multipliers: 3 Pass only the filter object to hdlgetserialpartition, returning the results to a cell array: Hd = design(fdesign.lowpass('N,Fc',8,.4));
Hd.
Arithmetic = 'fixed'; [sp,ff,nm] = hdlgetserialpartition(Hd) sp = '[1 1 1 1 1 1 1 1 1]' '[2 2 2 2 1]' '[3 3 3]' '[4 4 1]' '[5 4]' '[6 3]' '[7 2]' '[8 1]' '[9]' ff = '1' '2' '3'
'4' '5' '6' '7' 8-19 hdlgetserialpartition '8' '9' nm = '1' '2' '3' '5' '9' Pass the filter object to hdlgetserialpartition, specifying the desired folding factor as 4,
returning the results to a cell array: Hd = design(fdesign.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
lowpass('N,Fc',8,.4)); Hd.Arithmetic = 'fixed'; [sp,ff,nm] = hdlgetserialpartition(Hd, 'FoldingFactor', 4) sp = 4 4 1 ff = 4 nm = 3 See Also "Speed vs. Area
Optimizations for FIR Filters" on page 4-10 8-20 A Examples Use this list to find examples in the documentation. A Examples Tutorials "Basic FIR Filter
Tutorial" on page 2-3 "Optimized FIR Filter Tutorial" on page 2-24 "IIR Filter Tutorial" on page 2-48 Basic FIR Filter Tutorial "Designing a Basic FIR
Filter in FDATool" on page 2-3 "Quantizing the Basic FIR Filter" on page 2-5 "Configuring and Generating the Basic FIR Filter's VHDL Code" on page 2-8
"Getting Familiar with the Basic FIR Filter's Generated VHDL Code" on page 2-16 "Verifying the Basic FIR Filter's Generated VHDL Code" on page 2-18
Optimized FIR Filter Tutorial "Designing the FIR Filter in FDATool" on page 2-24 "Quantizing the FIR Filter" on page 2-26 "Configuring and Generating
the FIR Filter's Optimized Verilog Code" on page 2-29 "Getting Familiar with the FIR Filter's Optimized Generated Verilog Code" on page 2-39 "Verifying
the FIR Filter's Optimized Generated Verilog Code" on page 2-41 IIR Filter Tutorial "Designing an IIR Filter in FDATool" on page 2-48 "Quantizing the IIR
Filter" on page 2-50 "Configuring and Generating the IIR Filter's VHDL Code" on page 2-54 "Getting Familiar with the IIR Filter's Generated VHDL Code"
on page 2-60 A-2 Speed vs. Area Optimizations for FIR Filters "Verifying the IIR Filter's Generated VHDL Code" on page 2-62 Speed vs. Area Optimizations
for FIR Filters "Specifying Parallel and Serial FIR Architectures in generatehdl" on page 4-17 A-3 A Examples A-4 Index A Index Add input register option
3-52 Add output register option 3-52 AddInputRegister property 7-2 addition operations specifying input type treatment for 3-60 type casting 7-6
AddOutputRegister property 7-3 AddPipelineRegisters property 7-4 advanced coding properties 6-5 antisymmetric FIR filters 1-7 application-specific
integrated circuits (ASICs) 1-2 Architecture options for FIR filters 4-10 cascade serial 4-10 Distributed arithmetic (DA) 4-27 fully parallel 4-10 fully serial
4-10 partly serial 4-10 architectures setting postfix from command line 7-78 setting postfix from GUI 3-31 asserted level, reset 3-34 setting 7-69
asynchronous resets setting from command line 7-72 setting from GUI 3-33 B block labels for GENERATE statements 7-5 for output assignment blocks 7-63
specifying postfix for 7-5 BlockGenerateLabel property 7-5 C canonical signed digit (CSD) technique 4-4 cascade filters 3-93 Cascaded Integrator Comb
(CIC) filters 3-86 Cast before sum option 3-60 CastBeforeSum property 7-6 checklist requirements 3-19 clock configuring for test benches 3-117 specifying
high time for 7-9 specifying low time for 7-12 clock enable input port naming 3-49 specifying forced signals for 7-28 Clock enable port options 3-49 Clock
high time option 3-117 clock input port 7-10 forcing 7-27 naming 3-49 Clock low time 3-117 Clock port options 3-49 clock process names specifying postfix
for 7-13 clock time configuring 3-117 high 7-9 low 7-12 clocked process block labels 3-45 Clocked process postfix option 3-45 ClockEnableInputPort
property 7-7 ClockEnableOutputPort property 7-8 ClockHighTime property 7-9 ClockInputPort property 7-10 ClockInputs property 7-11 ClockLowTime
property 7-12 ClockProcessPostfix property 7-13 code, generated 3-142 advanced properties for customizing 6-5 configuring for basic FIR filter tutorial 2-8
configuring for IIR filter tutorial 2-54 Index-1 Index configuring for optimized FIR filter tutorial 2-29 customizing 3-37 defaults 3-14 for filter and test bench
5-3 general HDL defaults 3-15 optimizing 4-3 reviewing for basic FIR filter tutorial 2-16 reviewing for IIR filter tutorial 2-60 reviewing for optimized FIR
filter tutorial 2-39 verifying for basic FIR filter tutorial 2-18 verifying for IIR filter tutorial 2-62 verifying for optimized FIR filter tutorial 2-41 coefficient
multipliers 4-4 Coefficient prefix option 3-39 CoefficientMemory property 7-14 coefficients complex 3-62 for FIR filters 3-64 for IIR filters 3-77 naming 7-17
specifying a prefix for 3-39 CoefficientSource property 7-15 CoeffMultipliers property 7-16 CoeffPrefix property 7-17 command line interface generating
filter and test bench code with 5-3 command-line interface 1-6 Comment in header option 3-38 comments, header as property value 7-92 specifying 3-38
complex input data 3-62 generating ports for 3-62 ComplexImagPostfix property 7-19 ComplexRealPostfix property 7-20 Concatenate type safe zeros 3-58
configurations, inline suppressing from command line 7-51 suppressing from GUI 3-57 constants setting representation from command line 7-91 setting
representation from GUI 3-53 context-sensitive help 1-13 Cosimulation model 3-133 D DALUTPartition property 7-21 DARadix property 7-22 data input
port naming from command line 7-53 naming from GUI 3-49 specifying hold time for from GUI 3-122 specifying hold time for with command line 7-48 data
output port specifying name from command line 7-64 specifying name from GUI 3-49 defaults for general HDL code 3-15 for generated EDA tool scripts 3-15
for generated files 3-14 for optimizations 3-17 for resets 3-15 for test benches 3-17 demos 1-14 dialog box Generate HDL description 1-5 opening 3-4 setting
cascade filter options with 3-93 setting Farrow filter options with 3-105 setting multirate filter options with 3-86 setting test bench options with 3-112
specifying test bench type with 3-114 More Test Bench Settings 3-112 Index-2 Index dialogs Generate HDL setting optimizations with 4-2 Direct Form I
filters 1-7 Direct Form II filters 1-7 E EDAScriptGeneration property 7-23 Electronic Design Automation (EDA) tool scripts defaults for generation of 3-15
Electronic Design Automation (EDA) tools generation of scripts for 3-143 entities name conflicts of 3-41 naming 7-61 setting names of 3-27 setting postfix
from command line 7-80 setting postfix from GUI 3-31 Entity conflict postfix option 3-41 entity name conflicts 7-24 EntityConflictPostfix property 7-24 error
margin specifying from command line 7-25 specifying from GUI 3-125 Error margin (bits) option 3-125 ErrorMargin property 7-25 F factored CSD
technique 4-4 Farrow filters code generation for 3-105 fractional delay port for 7-30 types supported for code generation 3-105 FDATool 1-5 fdatool
command 3-4 fdhdltool function 8-2 field programmable gate arrays (FPGAs) 1-2 file extensions setting 3-27 Verilog 7-97 VHDL 7-99 file location properties
6-2 file names defaults 3-14 for architectures 7-78 for entities 7-80 for generated output 1-10 file naming properties 6-2 files, generated default names 3-14
defaults 3-14 HDL output 1-10 setting architecture postfix for 3-31 setting entity postfix for 3-31 setting location of 3-29 setting names of 3-27 setting options
for 3-26 setting package postfix for 3-30 splitting 7-79 test bench 7-87 filter arithmetic 3-4 filter structures 1-7 filterbuilder function 3-4 filters designing in
basic FIR tutorial 2-3 designing in IIR filter tutorial 2-48 designing in optimized FIR filter tutorial 2-24 generated HDL output for 1-10 naming generated file
for 7-61 properties of 1-9 quantized 1-7 quantizing 3-4 realizations of 1-7 finite impulse response (FIR) filters 1-7 FIR adder style option 4-8 FIR filter
architectures serial 7-74 Index-3 Index serial-cascade 7-74 FIR filter architectures property partly serial 7-76 serial 7-76 FIR filter coefficients processor
interface for 3-64 programmable vs.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
hard-coded 3-64 FIR filter tutorial basic 2-3 optimized 2-24 FIR filters 1-7 optimizing clock rate for 4-40 optimizing final summation for 4-8 specifying
summation technique for 7-26 FIRAdderStyle property 7-26 Folder option redirecting output with 3-29 folder, target 7-81 Force clock enable option 3-117
Force clock option 3-117 force reset hold time 7-48 Force reset option 3-119 ForceClock property 7-27 ForceClockEnable property 7-28 ForceReset
property 7-29 FPGAs (field programmable gate arrays) 1-2 FracDelayPort property 7-30 fractional delay input port naming from command line 7-30
functions fdhdltool 8-2 generatehdl 8-3 generatetb 8-7 generatetbstimulus 8-13 hdlgetserialpartition 8-15 input parameters for 1-9 Generate cosimulation
blocks 3-130 Generate HDL dialog box defaults 3-14 description 1-5 opening 3-4 opening with fdhdltool 3-11 opening with fdhdltool function 8-2 setting
optimizations with 4-2 specifying test bench type with 3-114 GenerateCoSimBlock property 7-31 GenerateCosimModel property 7-32 generatehdl function
8-3 generatetb function 8-7 generatetbstimulus function 8-13 Generating cosimulation models 3-133 graphical user interface (GUI) 1-5 H hardware
description languages (HDLs) 1-2 See also Verilog; VHDL hardware design process HDL code generation in 1-15 HDL code 2-8 See also code, generated
HDL files 1-10 HDL language 3-25 HDL test benches 5-2 HDLCompileFilePostfix property 7-33 HDLCompileInit property 7-34 HDLCompileTerm property
7-35 HDLCompileVerilogCmd property 7-36 HDLCompileVHDLCmd property 7-37 hdlgetserialpartition function 8-15 HDLs (hardware description
languages) 1-2 See also Verilog; VHDL HDLSimCmd property 7-38 HDLSimFilePostfix property 7-39 HDLSimInit property 7-40 HDLSimTerm property
7-41 G General tab 3-39 Index-4 Index HDLSimViewWaveCmd property 7-46 HDLSynthCmd property 7-42 HDLSynthFilePostfix property 7-43
HDLSynthInit property 7-44 HDLSynthTerm property 7-45 header comment properties 6-3 header comments 3-38 help context-sensitive 1-13 getting 1-12
Help browser 1-13 hold time 7-48 for data input signals 3-122 for resets 3-119 HoldInputDataBetweenSamples time 7-47 HoldTime property 7-48 adding
code for 7-2 suppressing generation of extra 3-52 InputComplex property 7-52 InputPort property 7-53 InputType property 7-54 installation 1-11 Instance
prefix option 3-47 instance sections 7-55 InstanceGenerateLabel property 7-55 InstancePrefix property 7-56 K key product features summary of 1-3 L I IIR
filter coefficients processor interface for 3-77 programmable vs. hard-coded 3-77 IIR filter tutorial 2-48 IIR filters 1-7 optimizing clock rate for 4-40 infinite
impulse response (IIR) filters 1-7 Initialize test bench inputs option 3-126 InitializeTestBenchInputs property 7-50 inline configurations specifying 7-51
suppressing the generation of 3-57 Inline VHDL configurations option 3-57 InlineConfigurations property 7-51 Input data type option 3-50 input parameters
1-9 Input port option 3-49 input ports naming 3-49 specifying data type for 7-54 input registers labels block 7-63 process block 3-45 language setting target
3-25 target 7-82 Language option 3-25 language selection properties 6-2 linear FIR final summation 4-8 Loop unrolling option 3-54 loops unrolling 7-57
unrolling and removing 3-54 LoopUnrolling property 7-57 M modules name conflicts for 3-41 naming 7-61 setting names of 3-27 Multi-file test bench option
3-115 MultifileTestBench property 7-58 Index-5 Index MultiplierInputPipeline property 7-59 MultiplierOutputPipeline property 7-60 multipliers optimizing
coefficient 4-4 multirate Farrow sample rate converters code generation for 3-101 multirate filters Cascaded Integrator Comb (CIC) 3-86 clock enable output
for 7-8 clock inputs for 7-11 code generation for 3-86 decimating 3-86 Direct-Form Transposed FIR Polyphase Decimator 3-86 interpolating 3-86 types
supported for code generation 3-86 N name conflicts 7-24 Name option 3-27 Name property 7-61 names clock process 7-13 coefficient 3-39 package file 7-66
naming properties 6-3 O optimization properties 6-6 optimizations defaults for 3-17 for synthesis 4-42 HDL code 4-3 setting 4-2 Optimize for HDL option 4-3
optimized FIR filter tutorial 2-24 OptimizeForHDL property 7-62 options Add input register 3-52 Add output register 3-52 Add pipeline registers 4-40
Architecture 4-10 Cast before sum 3-60 Clock enable input port 3-49 Clock high time 3-117 Clock low time 3-117 Clock port 3-49 Clocked process postfix
3-45 Coefficient multipliers 4-4 Coefficient prefix 3-39 Comment in header 3-38 Concatenate type safe zeros 3-58 Cosimulation model 3-133 DA radix 4-27
Entity conflict postfix 3-41 Error margin (bits) 3-125 FIR adder style 4-8 Folder for test bench output 3-112 redirecting output with 3-29 Force clock 3-117
Force clock enable 3-117 Force reset 3-119 Generate cosimulation blocks 3-130 Hold time 3-122 Initialize test bench inputs option 3-126 Inline VHDL
configurations 3-57 Input data type 3-50 Input port 3-49 Instance prefix 3-47 Language 3-25 Loop unrolling 3-54 LUT partition 4-27 Optimize for HDL 4-3
Output data type 3-50 Output port 3-49 Package postfix 3-30 Remove reset from 3-35 Index-6 Index Represent constant values by aggregates 3-53 Reserved
word postfix 3-42 Reset asserted level 3-34 Reset port 3-49 Reset type 3-33 Serial Partition 4-10 Split arch.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
file postfix 3-31 Split entity and architecture 3-31 Split entity file postfix 3-31 Test bench reference postfix 3-129 Use 'rising_edge' for registers 3-55 Use
Verilog `timescale directives 3-59 User defined response 3-127 Vector prefix 3-48 Verilog file extension setting file extension with 3-27 Verilog file extension
option renaming test bench file with 3-112 VHDL file extension renaming test bench file with 3-112 setting file extension with 3-27 output generated HDL
1-10 redirecting 3-29 Output data type option 3-50 Output port option 3-49 output ports naming 3-49 specifying data type for 7-65 output registers adding
code for 7-3 suppressing generation of extra 3-52 OutputGenerateLabel property 7-63 OutputPort property 7-64 OutputType property 7-65 P package files
default name for 3-14 specifying postfix for 7-66 Package postfix option 3-30 PackagePostfix property 7-66 packages setting names of 3-27 setting postfix
3-30 parameters 1-9 pipeline registers using from command line 7-4 using from GUI 4-40 pipelined FIR final summation 4-8 polyphase sample rate
converters code generation for 3-97 port data types 3-50 port properties 6-4 ports clock enable input 7-7 clock input 7-10 data input 7-53 data output 7-64
fractional delay input 7-30 input 7-54 naming 3-49 output 7-65 reset input 7-70 Ports tab 3-49 Prerequisite knowledge for using code generation software 1-3
process block labels 3-45 properties AddInputRegister 7-2 AddOutputRegister 7-3 AddPipelineRegisters 7-4 advanced coding 6-5 as input parameters 1-9
BlockGenerateLabel 7-5 CastBeforeSum 7-6 ClockEnableInputPort 7-7 ClockEnableOutputPort 7-8 Index-7 Index ClockHighTime 7-9 ClockInputPort 7-10
ClockInputs 7-11 ClockLowTime 7-12 ClockProcessPostfix 7-13 header comment 6-3 HoldInputDataBetweenSamples 7-47 HoldTime 7-48
InitializeTestBenchInputs 7-50 InlineConfigurations 7-51 InputComplex 7-52 InputPort 7-53 InputType 7-54 InstanceGenerateLabel 7-55 InstancePrefix 7-56
coding 6-5 CoefficientMemory 7-14 CoefficientSource 7-15 CoeffMultipliers 7-16 CoeffPrefix 7-17 ComplexImagPostfix 7-19 ComplexRealPostfix 7-20
DALUTPartition 7-21 DARadix 7-22 EDAScriptGeneration 7-23 EntityConflictPostfix 7-24 ErrorMargin 7-25 language selection 6-2 LoopUnrolling 7-57
MultifileTestBench 7-58 MultiplierInputPipeline 7-59 MultiplierOutputPipeline 7-60 Name 7-61 file location 6-2 file naming 6-2 FIRAdderStyle 7-26
ForceClock 7-27 ForceClockEnable 7-28 ForceReset 7-29 FracDelayPort 7-30 GenerateCoSimBlock 7-31 GenerateCosimModel 7-32
HDLCompileFilePostfix 7-33 HDLCompileInit 7-34 HDLCompileTerm 7-35 HDLCompileVerilogCmd 7-36 HDLCompileVHDLCmd 7-37 HDLSimCmd 7-38
HDLSimFilePostfix 7-39 HDLSimInit 7-40 HDLSimTerm 7-41 HDLSimViewWaveCmd 7-46 HDLSynthCmd 7-42 HDLSynthFilePostfix 7-43 HDLSynthInit
7-44 HDLSynthTerm 7-45 naming 6-3 optimization 6-6 OptimizeForHDL 7-62 OutputGenerateLabel 7-63 OutputPort 7-64 OutputType 7-65 PackagePostfix
7-66 port 6-4 RemoveResetFrom 7-67 ReservedWordPostfix 7-68 reset 6-2 ResetAssertedLevel 7-69 ResetInputPort 7-70 ResetLength 7-71 ResetType 7-72
ReuseAccum 7-74 SafeZeroConcat 7-75 script generation 6-9 SerialPartition 7-76 SimulatorFlags 7-77 SplitArchFilePostfix 7-78 SplitEntityArch 7-79
SplitEntityFilePostfix 7-80 TargetDirectory 7-81 Index-8 Index TargetLanguage 7-82 test bench 6-7 TestBenchClockEnableDelay 7-83
TestbenchCoeffStimulus 7-84 TestBenchDataPostFix 7-85 TestBenchFracDelayStimulus 7-86 TestBenchName 7-87 TestBenchReferencePostFix 7-88
TestBenchStimulus 7-89 TestBenchUserStimulus 7-90 UseAggregatesForConst 7-91 UserComment 7-92 UseRisingEdge 7-93 UseVerilogTimescale 7-95
VectorPrefix 7-96 VerilogFileExtension 7-97 VHDLArchitectureName 7-98 VHDLFileExtension 7-99 VHDLLibraryName 7-100 Q quantized filters 1-7 R
registers adding code for input 7-2 adding code for output 7-3 adding for optimization 7-4 pipeline 4-40 RemoveResetFrom property 7-67 Represent constant
values by aggregates option 3-53 requirements identifying for HDL code and test benches 3-19 product 1-11 Reserved word postfix option 3-42 reserved
words setting postfix for resolution of 3-42 specifying postfix for 7-68 ReservedWordPostfix property 7-68 Reset asserted level option 3-34 reset input port
7-70 naming 3-49 Reset length option 3-119 Reset port options 3-49 reset properties 6-2 Reset type option 3-33 ResetAssertedLevel property 7-69
ResetInputPort property 7-70 ResetLength property 7-71 resets configuring for test benches 3-119 customizing 3-33 defaults for 3-15 setting asserted level for
from command line 7-69 setting asserted level for from GUI 3-34 setting style of 3-33 specifying forced 7-29 suppressing generation of 3-35 types of 7-72
ResetType property 7-72 ReuseAccum property 7-74 rising_edge function 3-55 S SafeZeroConcat property 7-75 script generation properties 6-9 second-order
section (SOS) filters 1-7 sections instance 7-55 SerialPartition property 7-76 setup time for data input signals 3-122 for resets 3-119 simulator 5-6 Index-9
Index SimulatorFlags property 7-77 SOS filters 1-7 Split arch.
You're reading an excerpt. Click here to read official MATLAB
FILTER DESIGN HDL CODER 2 user guide
http://somemanuals.com/dref/2875609
Powered by TCPDF (www.tcpdf.org)