POWER DIODES

Power diodes are made of silicon p-n junction with two terminals, anode and
cathode. P-N junction is formed by alloying, diffusion and epitaxial growth. Modern
techniques in diffusion and epitaxial processes permit desired device characteristics.
he diodes have the following advantages
!igh mechanical and thermal reliability
!igh pea" inverse voltage
#ow reverse current
#ow forward voltage drop
!igh efficiency
$ompactness.
%iode is forward biased when anode is made positive with respect to the cathode. %iode
conducts fully when the diode voltage is more than the cut-in voltage &'.( ) for *i+.
$onducting diode will have a small voltage drop across it.
%iode is reverse biased when cathode is made positive with respect to anode. ,hen
reverse biased, a small reverse current "nown as lea"age current flows. his lea"age
current increases with increase in magnitude of reverse voltage until avalanche voltage is
reached &brea"down voltage+.
DYNAMIC CHARACTERISTICS OF POWER
SWITCHING DIODES
-t low frequency and low current, the diode may be assumed to act as a perfect switch
and the dynamic characteristics &turn on . turn off characteristics+ are not very
important. /ut at high frequency and high current, the dynamic characteristics plays an
important role because it increases power loss and gives rise to large voltage spi"es
which may damage the device if proper protection is not given to the device.
- 0
1
)
2
1 e v e r s e
# e a " a g e $ u r r e n t
3

4
)
V
+ -
+
-
V
i
R
L
I
V
i
V
F
0 t
t
1
- V
R
( b )
( C )
t
0
p - p
a t
j u n c t i o n
n n 0
I
0
t
( d )
t
( e )
- V
R
0
V
I
0
t
2
t
1
F o r w a r d
b i a s
M i n o r i t y
c a r r i e r
s t o r a g e t
s
" r a n s i t i o n
i n t e r # a $ t
t
I
F
V
F
R
L

I
R
V
R
R
L
6ig7 *torage . ransition imes during the %iode *witching
REVERSE RECOVERY CHARACTERISTIC
1everse recovery characteristic is much more important than forward recovery
characteristics because it adds recovery losses to the forward loss. $urrent when diode is
forward biased is due to net effect of majority and minority carriers. ,hen diode is in
forward conduction mode and then its forward current is reduced to 8ero &by applying
reverse voltage+ the diode continues to conduct due to minority carriers which remains
stored in the p-n junction and in the bul" of semi-conductor material. he minority
carriers ta"e some time to recombine with opposite charges and to be neutrali8ed. his
time is called the reverse recovery time. he reverse recovery time &t
rr
+ is measured from
the initial 8ero crossing of the diode current to 49: of maximum reverse current 3
rr
. t
rr
has 4 components, t
5
and t
4
. t
5
is as a result of charge storage in the depletion region of
he waveform in
&a+ *imple diode circuit.
&b+3nput waveform
applied to the diode
circuit in &a+;
&c+ he excess-carrier
density at the junction; &d+
the diode current; &e+ the
diode voltage.
the junction i.e., it is the time between the 8ero crossing and the pea" reverse current 3
rr
.
t
4
is as a result of charge storage in the bul" semi-conductor material.
( )
5 4
5
rr
RR
t t t
di
I t
dt
+

The reverse recovery time depends on the junction temperature, rate of fall of
forward current and the magnitude of forward current prior to commutation &turning off+.
,hen diode is in reverse biased condition the flow of lea"age current is due to minority
carriers. hen application of forward voltage would force the diode to carry current in the
forward direction. /ut a certain time "nown as forward recovery time &turn-<N time+ is
required before all the majority carriers over the whole junction can contribute to current
flow. Normally forward recovery time is less than the reverse recovery time. he forward
recovery time limits the rate of rise of forward current and the switching speed.
Reverse recovery charge
RR
Q
, is the amount of charge carriers that flow across
the diode in the reverse direction due to the change of state from forward conduction to
reverse bloc"ing condition. he value of reverse recovery charge
RR
Q
is determined form
the area enclosed by the path of the reverse recovery current.
5 4
5 5 5
4 4 4
RR RR RR RR RR
Q I t I t I t
_
+

,

5
4
RR RR RR
Q I t
POWER DIODES TYPES
Power diodes can be classified as
t
5
t
4
t
r r
' . 4 9 3
1 1
t
3
1 1
3
6
=eneral purpose diodes.
!igh speed &fast recovery+ diodes.
*chott"y diode.
GENERAL PURPOSE DIODES
he diodes have high reverse recovery time of about 49 microsecs &sec+. hey are used
in low speed &frequency+ applications. e.g., line commutated converters, diode rectifiers
and converters for a low input frequency upto 5 0!8. %iode ratings cover a very wide
range with current ratings less than 5 - to several thousand amps &4''' -+ and with
voltage ratings from 9' ) to 9 0). hese diodes are generally manufactured by diffusion
process. -lloyed type rectifier diodes are used in welding power supplies. hey are most
cost effective and rugged and their ratings can go upto >''- and 50).
FAST RECOVERY DIODES
he diodes have low recovery time, generally less than 9 s. he major field of
applications is in electrical power conversion i.e., in free-wheeling ac-dc and dc-ac
converter circuits. heir current ratings is from less than 5 - to hundreds of amperes with
voltage ratings from 9' ) to about > 0). ?se of fast recovery diodes are preferable for
free-wheeling in *$1 circuits because of low recovery loss, lower junction temperature
and reduced di dt . 6or high voltage ratings greater than @'' ) they are manufactured by
diffusion process and the recovery time is controlled by platinum or gold diffusion. 6or
less than @'' ) rating epitaxial diodes provide faster switching speeds than diffused
diodes. Apitaxial diodes have a very narrow base width resulting in a fast recovery time
of about 9' ns.
SCHOTTKY DIODES
- *chott"y diode has metal &aluminium+ and semi-conductor junction. - layer of metal is
deposited on a thin epitaxial layer of the n-type silicon. 3n *chott"y diode there is a larger
barrier for electron flow from metal to semi-conductor.
,hen *chott"y diode is forward biased free electrons on n-side gain enough energy to
flow into the metal causing forward current. *ince the metal does not have any holes
there is no charge storage, decreasing the recovery time. herefore a *chott"y diode can
switch-off faster than an ordinary p-n junction diode. - *chott"y diode has a relatively
low forward voltage drop and reverse recovery losses. he lea"age current is higher than
a p-n junction diode. he maximum allowable voltage is about 5'' ). $urrent ratings
vary from about 5 to >'' -. hey are mostly used in low voltage and high current dc
power supplies. he operating frequency may be as high 5''->'' "!8 as the device is
suitable for high frequency application. *chott"y diode is also "nown as hot carrier diode.
=eneral Purpose %iodes are available upto 9'''), >9''-. he rating of fast-recovery
diodes can go upto >'''), 5'''-. he reverse recovery time varies between '.5 and
9sec. he fast recovery diodes are essential for high frequency switching of power
converters. *chott"y diodes have low-on-state voltage drop and very small recovery time,
typically a few nanoseconds. !ence turn-off time is very low for schott"y diodes. he
lea"age current increases with the voltage rating and their ratings are limited to 5''),
>''-. he diode turns on and begins to conduct when it is forward biased. ,hen the
anode voltage is greater than the cathode voltage diode conducts.
he forward voltage drop of a power diode is low typically '.9) to 5.4). 3f the cathode
voltage is higher than its anode voltage then the diode is said to be reverse biased.
Power diodes of high current rating are available in
*tud or stud-mounted type.
%is" or press pac" or !oc"ey-pac" type.
3n a stud mounted type, either the anode or the cathode could be the stud.
COMPARISON BETWEEN DIFFERENT TYPES OF
DIODES
General Purpose Diodes Fast Recovery Diodes Schottky Diodes
?pto 9''') . >9''- ?pto >''') and 5'''- ?pto 5'') and >''-
1everse recovery time B
!igh
1everse recovery time B
#ow
1everse recovery time B
Axtremely low.
49
rr
t s '.5 s to 9 s
rr
t
rr
t
C a few nanoseconds
urn off time - !igh urn off time - #ow urn off time B Axtremely
low
*witching frequency B
#ow
*witching frequency B
!igh
*witching frequency B
)ery high.
F
V
C '.() to 5.4)
F
V
C '.D) to 5.9)
F
V
'.@) to '.E)
P<,A1 M<*6A
!istorically, bipolar semiconductor devices &i.e, diode, transistor, thyristor, thyristor,
=< etc+ have been the front runners in the quest for an ideal power electronic switch.
Aver since the invention of the transistor, the development of solid-state switches with
increased power handling capability has been of interest for expending the application of
these devices. he /F and the =< thyristor have been developed over the past >' years
to serve the need of the power electronic industry. heir primary advantage over the
thyristors have been the superior switching speed and the ability to interrupt the current
without reversal of the device voltage. -ll bipolar devices, however, suffer from a
common set of disadvantages, namely, &i+ limited switching speed due to considerable
redistribution of minority charge carriers associated with every switching operation; &ii+
relatively large control power requirement which complicates the control circuit design.
/esides, bipolar devices can not be paralleled easily.
Introduction of a new MOS gate controlled power device technology in
the 1980s. The power MOS feld eect transistor !MOS"#T$ evolved
fro% the MOS integrated circuit technology. The new device pro%ised
e&tre%ely low input power levels and no inherent li%itation to the
switching speed. Thus' it opened up the possi(ility of increasing the
operating fre)uency in power electronic syste%s resulting in reduction
in si*e and weight. The initial clai%s of infnite current gain for the
power MOS"#T were' however' diluted (y the need to design the gate
drive circuit to account for the pulse currents re)uired to charge and
discharge the high input capacitance of these devices. +t high
fre)uency of operation the re)uired gate drive power (eco%es
su(stantial. MOS"#Ts also have co%paratively higher on state
resistance per unit area of the device cross section which increases
with the (loc,ing voltage rating of the device. -onse)uently' the use of
MOS"#T has (een restricted to low voltage !less than a(out .00 volts$
applications where the O/ state resistance reaches accepta(le values.
Inherently fast switching speed of these devices can (e eectively
utili*ed to increase the switching fre)uency (eyond several hundred
,0*.
"ro% the point of view of the operating principle a MOS"#T is a
voltage controlled %a1ority carrier device. +s the na%e suggests'
%ove%ent of %a1ority carriers in a MOS"#T is controlled (y the voltage
applied on the control electrode !called gate$ which is insulated (y a
thin %etal o&ide layer fro% the (ul, se%iconductor (ody. The electric
feld produced (y the gate voltage %odulate the conductivity of the
se%iconductor %aterial in the region (etween the %ain current
carrying ter%inals called the 2rain !2$ and the Source !S$. 3ower
MOS"#Ts' 1ust li,e their integrated circuit counterpart' can (e of two
types !i$ depletion type and !ii$ enhance%ent type. 4oth of these can
(e either n5 channel type or p5channel type depending on the nature of
the (ul, se%iconductor. "ig 6.1 !a$ shows the circuit sy%(ol of these
four types of MOS"#Ts along with their drain current vs gate5source
voltage characteristics !transfer characteristics$.
Fig.1: Different types of power MSF!". #a$ %ircuit sy&'ols and transfer
characteristics
"ro% "ig.1 !a$ it can (e concluded that depletion type MOS"#Ts are
nor%ally O/ type switches i.e' with the gate ter%inal open a non*ero
drain current can 7ow in these devices. This is not convenient in %any
power electronic applications. Therefore' the enhance%ent type
MOS"#Ts !particularly of the n5channel variety$ is %ore popular for
power electronics applications.
1Constructional Features of a Power MOSFET
-s mentioned in the introduction section, Power M<*6A is a device that evolved from
M<* integrated circuit technology. he first attempts to develop high voltage M<*6As
were by redesigning lateral M<*6A to increase their voltage bloc"ing capacity. he
resulting technology was called lateral double diffused M<* &%M<*+. !owever it was
!owever it was soon reali8ed that
much larger brea"down voltage and current ratings could be achieved by resorting to a
vertically oriented structure. *ince then, vertical %M<* &)%M<*+ structure has been
adapted by virtually all manufacturers of Power M<*6A. - power M<*6A using
)%M<* technology has vertically oriented three layer structure of alternating p type and
n type semiconductors as shown in 6ig E.4 &a+ which is the schematic representation of a
single M<*6A cell structure. - large number of such cells are connected in parallel n in
to form a complete device.
Fig.(. Structure of a MSF!"
he two n
)
end layers labeled G*ourceH and G%rainH are heavily doped to
approximately the same level. he p type middle layer is termed the body &or substrate+
and has moderate doping level &4 to > orders of magnitude lower than n
)
regions on both
sides+. he n
*
drain drift region has the lowest doping density. hic"ness of this region
determines the brea"down voltage of the device. he gate terminal is placed over the n
*
and p type regions of the cell structure and is insulated from the semiconductor body be a
thin layer of silicon dioxide &also called the gate oxide+. he source and the drain region
of all cells on a wafer are connected to the same metallic contacts to form the *ource and
the %rain terminals of the complete device. *imilarly all gate terminals are also
connected together. he source is constructed of many &thousands+ small polygon shaped
areas that are surrounded by the gate regions. he geometric shape of the source regions,
to same extent, influences the <N state resistance of the M<*6A.
Fig.+: Parasitic ,-" in a MSF!" cell.
One interesting feature of the MOS"#T cell is that the alternating n) n* p
n) structure e%(eds a parasitic 48T !with its (ase and e%itter shorted
(y the source %etalli*ation$ into each MOS"#T cell as shown in "ig .9.
The non*ero resistance (etween the (ase and the e%itter of the
parasitic npn 48T arises due to the (ody spreading resistance of the p
type su(strate. In the design of the MOS"#T cells special care is ta,en
so that this resistance is %ini%i*ed and switching operation of the
parasitic 48T is suppressed. :ith an eective short circuit (etween the
(ody and the source the 48T always re%ain in cut o and its collector5
(ase 1unction is represented as an anti parallel diode !called the (ody
diode$ in the circuit sy%(ol of a 3ower MOS"#T.

Operating principle of a MOSFET
+t frst glance it would appear that there is no path for any current to
7ow (etween the source and the drain ter%inals since at least one of
the p n 1unctions !source ; (ody and (ody52rain$ will (e reverse (iased
for either polarity of the applied voltage (etween the source and the
drain. There is no possi(ility of current in1ection fro% the gate ter%inal
either since the gate o&ide is a very good insulator. 0owever'
application of a positive voltage at the gate ter%inal with respect to
the source will covert the silicon surface (eneath the gate o&ide into an
n type layer or <channel=' thus connecting the Source to the 2rain as
e&plained ne&t.he gate region of a M<*6A which is composed of the gate
metalli8ation, the gate &silicon+ oxide layer and the p-body silicon forms a high quality
capacitor. ,hen a small voltage is application to this capacitor structure with gate
terminal positive with respect to the source &note that body and source are shorted+ a
depletion region forms at the interface between the *i<4 and the silicon as shown in 6ig.@
a.
6ig. .@7 =ate control of M<*6A conduction. &a+ %epletion layer formation; &b+ 6ree
electron accumulation; &c+ 6ormation of inversion layer.
The positive charge induced on the gate %etalli*ation repels the
%a1ority hole carriers fro% the interface region (etween the gate o&ide
and the p type (ody. This e&poses the negatively charged acceptors
and a depletion region is created. "urther increase in >?S causes the
depletion layer to grow in thic,ness. +t the sa%e ti%e the electric feld
at the o&ide5silicon interface gets larger and (egins to attract free
electrons as shown in "ig .@ !($. The i%%ediate source of electron is
electron5hole generation (y ther%al ioni*ation. The holes are repelled
into the se%iconductor (ul, ahead of the depletion region. The e&tra
holes are neutrali*ed (y electrons fro% the source.
+s >?S increases further the density of free electrons at the
interface (eco%es e)ual to the free hole density in the (ul, of the
(ody region (eyond the depletion layer. The layer of free electrons at
the interface is called the inversion layer and is shown in "ig .@ !c$. The
inversion layer has all the properties of an n type se%iconductor and is
a conductive path or <channel= (etween the drain and the source
which per%its 7ow of current (etween the drain and the source. Since
current conduction in this device ta,es place through an n5 type
<channel= created (y the electric feld due to gate source voltage it is
called <#nhance%ent type n5channel MOS"#T=. The value of >?S at
which the inversion layer is considered to have for%ed is called the
<?ate ; Source threshold voltage >?S !th$=. +s >?S is increased (eyond
>?S!th$ the inversion layer gets so%e what thic,er and %ore
conductive' since the density of free electrons increases further with
increase in >?S. The inversion layer screens the depletion layer
ad1acent to it fro% increasing >?S. The depletion layer thic,ness now
re%ains constant.
Steady state output i-v characteristics of a MOSFET
The MOS"#T' li,e the 48T is a three ter%inal device where the voltage
on the gate ter%inal controls the 7ow of current (etween the output
ter%inals' Source and 2rain. The source ter%inal is co%%on (etween
the input and the output of a MOS"#T. The output characteristics of a
MOS"#T is then a plot of drain current !i2$ as a function of the 2rain ;
Source voltage !v2S$ with gate source voltage !v?S$ as a para%eter.
"ig .. !a$ shows such a characteristics.
6ig. .97 <utput i-v characteristics of a Power M<*6A &a+ i-v characteristics; &b+
$omponents of <N-state resistance; &c+ Alectron drift velocity vs Alectric field; &d+
ransfer
:ith gate5source voltage !>?S$ (elow the threshold voltage
!v?S !th$$ the MOS"#T operates in the cut5o %ode. /o drain
current 7ows in this %ode and the applied drain;source voltage
!v2S$ is supported (y the (ody5collector p-n 1unction. Therefore' the
%a&i%u% applied voltage should (e (elow the avalanche (rea,
down voltage of this 1unction !>2SS$ to avoid destruction of the
device. :hen >?S is increased (eyond v?S!th$ drain current starts
7owing. "or s%all values of v2S !v2S A !v?S ; v?S!th$$ i2 is al%ost
proportional to v2S. -onse)uently this %ode of operation is called
<oh%ic %ode= of operation. In power electronic applications a
MOS"#T is operated either in the cut o or in the oh%ic %ode. The
slope of the v2S ; i2 characteristics in this %ode is called the O/
state resistance of the MOS"#T !r2S !O/$$. Several physical
resistances as shown in "ig .. !($ contri(ute to r2S !O/$. /ote that
r2S !O/$ reduces with increase in v?S. This is %ainly due to
reduction of the channel resistance at higher value of v=*. !ence, it is
desirable in power electronic applications, to use as large a gate-source voltage as
possible subject to the dielectric brea" down limit of the gate-oxide layer.
-t still higher value of v%* &v%* I &v=* B v=* &th++ the i% B v%* characteristics deviates
from the linear relationship of the ohmic region and for a given v=*, i% tends to
saturate with increase in v%*. he exact mechanism behind this is rather complex. 3t
will suffice to state that, at higher drain current the voltage drop across the channel
resistance tends to decrease the channel width at the drain drift layer end. 3n
addition, at large value of the electric field, produced by the large %rain B *ource
voltage, the drift velocity of free electrons in the channel tends to saturate as shown
in 6ig .9 &c+. -s a result the drain current becomes independent of )%* and
determined solely by the gate B source voltage v=*. his is the active mode of
operation of a M<*6A.
he similarity of the output characteristics of a M<*6A with that of a /F
should be apparent. /oth of them have three distinct modes of operation, namely,
&i+cut off, &ii+ active and &iii+ ohmic &saturation for /F+ modes. !owever, there are
some important differences as well.
5J ?nli"e /F a power M<*6A does not undergo second brea" down.
5J he primary brea" down voltage of a M<*6A remains same in the cut off
and in the active modes. his should be contrasted with three different brea"
down voltages &)*?*, )$A< . )$/<+ of a /F.
5J he <N state resistance of a M<*6A in the ohmic region has positive
temperature coefficient which allows paralleling of M<*6A without any
special arrangement for current sharing. <n the other hand, v$A &sat+ of a
/F has negative temperature coefficient ma"ing parallel connection of
/Fs more complicated.
he *<- of a M<*6A is plotted on a log-log graph. <n the top, the *<- is
restricted by the absolute maximum permissible value of the drain current &3%M+
which should not be exceeded even under pulsed operating condition. o the left,
operating restriction arise due to the non 8ero value of r%*&<N+ corresponding to v=*
C v=*&Max+. o the right, the first operating restriction is due to the limit on the
maximum permissible junction temperature rise which depends on the power
dissipation inside the M<*6A. his limit is different for %$ &continuous+ and
pulsed operation of different pulse widths. -s in the case of a /F the pulsed safe
operating areas are useful for shaping the switching trajectory of a M<*6A. -
M<*6A does not undergo Gsecond brea" downH and no corresponding operating
limit appears on the *<-. he final operation limit to the extreme right of the *<-
arises due to the maximum permissible drain source voltage &)%**+ which is decided
by the avalanche brea" down voltage of the drain -body p*n junction. his is an
instantaneous limit. here is no distinction between the forward biased and the
reverse biased *<-s for the M<*6A. hey are identical.
%ue to the presence of the anti parallel Gbody diodeH, a M<*6A can not bloc"
any reverse voltage. he body diode, however, can carry an 1M* current equal to
3%M. 3t also has a substantial surge current carrying capacity. ,hen reverse biased it
can bloc" a voltage equal to )%**.

6or safe operation of a M<*6A, the maximum limit on the gate source voltage
&)=* &Max++ must be observed. Axceeding this voltage limit will cause dielectric
brea" down of the thin gate oxide layer and permanent failure of the device. 3t
should be noted that even static charge inadvertently put on the gate oxide by
careless handling may destroy it. he device user should ground himself before
handling any M<*6A to avoid any static charge related problem.
*<- 6<1 P<,A1 M<*6A.
M<*6A is a voltage controlled majority carrier device. J - Power M<*6A has a
vertical structure of alternating p and n layers. J he main current carrying terminals of an
n channel enhancement mode M<*6A are called the %rain and the *ource and are made
up of n2 type semiconductor. J he control terminal is called the =ate and is isolated
form the bul" semiconductor by a thin layer of *i<4. J p type semiconductor body
separates n2 type source and drain regions. J - conducting n type channel is produced in
the p type body region when a positive voltage greater than a threshold voltage is applied
at the gate. J $urrent conduction in a M<*6A occurs by flow of electron from the
source to the drain through this channel. J ,hen the gate source voltage is below
threshold level a M<*6A remains in the G$ut <ffH region and does not conduct any
current. J ,ith v=* I v=* &th+ and v%* K &v=* B v=* &th++ the drain current in a
M<*6A is proportional to v%*. his is the G<hmic regionH of the M<*6A output
characteristics. J 6or larger values of v%* the drain current is a function of v=* alone and
does not depend on v%s. his is called the Gactive regionH of the M<*6A. J 3n power
electronic applications a M<*6A is operated in the G$ut <ffH and <hmic regions only. J
he on state resistance of a M<*6A &)%* &<N++ has a positive temperature coefficient.
herefore, M<*6As can be easily paralleled. J - M<*6A does not undergo second
brea" down. J he safe operating area &*<-+ of a M<*6A is similar to that of a /F
except that it does not have a second brea" down limit. J ?nli"e /F the maximum
forward voltage withstanding capability of a M<*6A does not depend on the drain
current. J he safe operating area of a M<*6A does not change under 6orward and
1everse bias conditions. J he drain B body junction in a M<*6A structure constitute an
anti parallel diode connected between the source and the drain. his is called the
M<*6A Gbody B diode.H J he body diode of a M<*6A has the same brea" down
voltage and forward current rating as the main M<*6A.he switching delays in a
M<*6A are due to finite charging and discharging time of the input and output
capacitors. J *witching times of a M<*6A can be controlled completely by external
gate drive design. he input capacitor along with the gate drive resistance determine the
current rise and fall time of a M<*6A during switching. J he transfer capacitor &$gd+
determines the drain voltage rise and fall times. J r%* &<N+ of a M<*6A determines the
conduction loss during <N period. J r%* &<N+ reduces with higher vgs. herefore, to
minimi8e conduction power loss maximum permissible vgs should be used subject to
dielectric brea" down of the gate oxide layer. J he gate oxide layer can be damaged by
static charge. herefore M<*6As should be handled only after discharging one self
through proper grounding. J 6or similar voltage rating, a M<*6A has a relatively higher
conduction loss and lower switching loss compared to a /F. herefore, M<*6As are
more popular for high frequency &I9' "!8+ low voltage &K5'' )+ circuits.
P.!R ,-"
Power /ipolar Function ransistor &/F+ is the first semiconductor device to allow full
control over its urn on and urn off operations. 3t simplified the design of a large
number of Power Alectronic circuits that used forced commutated thyristors at that time
and also helped reali8e a number of new circuits. *ubsequently, many other devices that
can broadly be classified as GransistorsH have been developed. Many of them have
superior performance compared to the /F in some respects. hey have, by now, almost
completely replaced /Fs. !owever, it should be emphasi8ed that the /F was the first
semiconductor device to closely approximate an ideal fully controlled Power switch.
<ther GtransistorsH have characteristics that are qualitatively similar to those of the /F
&although the physics of operation may differ+. !ence, it will be worthwhile studying the
characteristics and operation a /F in some depth. 6rom the point of view of construction
and operation /F is a bipolar &i.e. minority carrier+ current controlled device. 3t has been
used at signal level power for a long time.
Basic Operating Principle of a Bipolar Junction Transistor
+ 1unction transistor consists of a se%iconductor crystal in which a p
type region is sandwiched (etween two n type regions. This is called
an n-p-n transistor. +lternatively an n type region %ay (e placed in
(etween two p type regions to give a p-n-p transistor. "ig shows the
circuit sy%(ols and sche%atic representations of an n-p-n and a p-n-p
transistor. The ter%inals of a transistor are called #%itter !#$' 4ase !4$
B -ollector !-$ as shown in the fgure.
1Constructional Features of a Power BJT
Power transistors face the same conflicting design requirements &i.e. large off state
bloc"ing voltage and large on state current density+ as that of a power diode. herefore, it
is only natural to extend some of the constructional features of power diodes to power
/F. 6ollowing *ection summari8es some of the constructional features of a Power /F.
*ince Power ransistors are predominantly of the n-p-n type, in this section and
subsequently only this type of transistor will be discussed.
5J - power /F has a vertically oriented alternating layers of n type and p type
semiconductor materials as shown in 6ig >.>&a+. he vertical structure is preferred
for power transistors because it maximi8es the cross sectional area through which
the on state current flows. hus, on state resistance and power lass is minimi8ed.
5J 3n order to maintain a large current gain / L 0 &and hence reduce base drive
current+ the emitter doping density is made several orders of magnitude higher
than the base region. he thic"ness of the base region is also made as small as
possible.
5J 3n order to bloc" large voltage during G<66H state a lightly doped Gcollector drift
regionH is introduced between the moderately doped base region and the heavily
doped collector region. he function of this drift region is similar to that in a
Power %iode. !owever, the doping density donation of the base region being
GmoderateH the depletion region does penetrate considerably into the base.
herefore, the width of the base region in a power transistor can not be made as
small as that in a signal level transistor. his comparatively larger base width has
adverse effect on the current gain &L+ of a Power transistor which
5 typically varies within 9-4'. -s will be discusses later the collector drift region
has significant effect on the out put characteristics of a Power /F.
5J Practical Power transistors have their emitters and bases interleaved as narrow
fingers. his is necessary to prevent /current crowding0 and consequent
/second 'reak down0. 3n addition multiple emitter structure also reduces
parasitic ohmic resistance in the base current path.
%onstructional Features of a Power ,ipolar -unction "ransistor
Output i-v characteristics of a Power Transistor
- typical output &i$ vs )$A+ characteristics of an n*p*n type power transistor is shown in
6ig .- power transistor exhibits G$ut offH, G-ctiveH and G*aturation regionsH of operation
in its output characteristics similar to a signal level transistor. 3n fact output
characteristics of a Power ransistor in the G$ut offH and G-ctiveH regions are
qualitatively identical to a signal level transistor.
)3 $haracteristics of P<,A1 /F.
In the cut o region !i4 C 0$ the collector current is al%ost *ero. The
%a&i%u% voltage (etween collector and e%itter under this condition is
ter%ed <Ma&i%u% forward (loc,ing voltage with (ase ter%inal open
!i4 D 0$= and is denoted (y >-#O. "or all practical purpose this is the
%a&i%u% voltage that can (e applied in the forward direction !-
positive with respect to #$ across a power transistor since a power
transistor is e&pected to see any signifcant forward voltage only with
i4 D 0. This (loc,ing voltage can however (e increased to a value >-4O
(y ,eeping the e%itter ter%inal open. In this case i4 A o. +ctually >-4O
is the (rea,down voltage of the collector (ase 1unction. 0owever' since
the open (ase confguration is %ore co%%on the value of >-#O is used
(y the %anufacturers as the %a&i%u% voltage rating of a power
transistor. 3ower transistors have poor reverse voltage withstanding
capa(ility due to low (rea, down voltage of the (ase5e%itter 1unction.
Therefore' reverse voltage !- negative with respect to #$ should not
appear across a power transistor. In the active region the ratio of
collector current to (ase current !2- current ?ain !E$$ re%ains fairly
constant upto certain value of the collector current after which it falls
o rapidly. Manufacturers usually provide a graph showing the
variation of E as a function of the collector current for dierent 1unction
te%peratures and collector e%itter voltages. This graph is useful for
designing the (ase drive of a 3ower transistor. Typically' the value of
the dc current gain of a 3ower transistor is %uch s%aller co%pared to
their signal level counterpart.
he maximum collector-emitter voltage that a power transistor can withstand in active
region is determined by the /ase collector avalanche brea" down voltage. his voltage,
denoted by )*?* in 6ig, >.@ is usually smaller than )$A<. he voltage )*?* can be attained
only for relatively lower values of collector current. -t higher collector current the limit
on the Gtotal power dissipationH defines the boundary of the allowable active region as
shown in 6ig . -t still higher levels of collector currents the allowable active region is
further restricted by a potential failure mode called /the Second ,reak down0. 3t
appears on the output characteristics of the /F as a precipitous drop in the collector-
emitter voltage at large collector currents. he collector voltage drop is often
accompanied by significant rise in the collector current and a substantial increase in the
power dissipation. Most importantly this dissipation is not uniformly spread over the
entire volume of the device but is concentrated in highly locali8ed regions. his locali8ed
heating is a combined effect of the intrinsic non uniformity of the collector current
density distribution across the cross section of the device and the negative temperature
coefficient of resistively of minority carrier devices which leads to the formation of
Gcurrent filamementsH &locali8ed areas of very high current density+ by a positive feed-
bac" mechanism. <nce current filaments are formed locali8ed Gthermal runawayH quic"ly
ta"es the junction temperature beyond the safe limit and the device is destroyed.
It is in the saturation region that the output characteristics of a 3ower
transistor diers signifcantly fro% its signal level counterpart. In fact
the saturation region of a 3ower transistor can (e further su(divided
into a quasi saturation region and a hard saturation region.
+ppearance of the )uasi saturation region in the output characteristics
of a power transistor is a direct conse)uence of introducing the drift
region into the structure of a power transistor. In the )uasi saturation
region the (ase5collector 1unction is forward (iased (ut the lightly
doped drift region is not co%pletely shorted out (y e&cess %inority
carrier in1ection fro% the (ase. The resistivity of this region depends to
so%e e&tent on the (ase current. Therefore' in the )uasi saturation
region' the (ase current still retains so%e control over the collector
current although the value of E decreases signifcantly. +lso' since the
resistivity of the drift region is still signifcant the total voltage drop
across the device in this %ode of operation is higher for a given
collector current co%pared to what it will (e in the hard saturation
region.
In the hard saturation region (ase current looses control over the
collector current which is deter%ined entirely (y the collector load and
the (iasing voltage >--. This (ehavior is si%ilar to what happens in a
signal transistor e&cept that the drift region of a power transistor
continues to oer a s%all resistance even when it is co%pletely
shorted out !(y e&cess carrier in1ection fro% the (ase$. Therefore' for
larger collector currents the collector5e%itter voltage drop is al%ost
proportional to the collector current. Manufacturers usually provide the
plots of the variation of >-# !sat$ vs. i- for dierent values of (ase
current and 1unction te%perature. -urves showing the variation of >-#
!sat$ with i4 for dierent values of i- and 1unction te%perature are also
provided (y certain %anufacturers.
Safe operating +rea !SO+$ for 3ower 48T
+pplica(le operating li%its on a power transistors are co%pactly
represented in two diagra%s called the "orward 4ias Safe Operating
+rea !"4SO+$ and the Feverse 4ias Safe Operating +rea. !F4SO+$
applica(le to i4 G 0 and i4 C 0 conditions respectively.
Safe operating areas of a Power "ransistor. #a$ F,S12 #'$ R,S1.
he hori8ontal upper limit of the 6/*<- is determined by the maximum allowable
collector current &3$M+ that should not be exceeded even as a pulse. Axceeding this current
limit may cause bonding wire or metalli8ation of the wafer to vapori8e or otherwise fail.
*ince a power transistor does not have any appreciable reverse voltage bloc"ing capacity
they are usually not used in ac circuits. !owever, if the collector current, for some reason
is not dc or a pulse, the rms value of the collector current waveform should not exceed
this limit. he next applicable limit in the 6/*<- &green lines+ corresponds to the
restriction on the maximum allowable power dissipation and maximum junction
temperature. *ince 6/*<- is shown on a log-log scale constant Power dissipation &Pd C
)$A i$+ limits appear as straight lines. his limit is different for dc and pulsed operation
due to the thermal time constant of the device. he G%$H limit is applicable to the
average power loss if the transistor remains continuously in the conduction state &active,
quasi saturation or saturation+. he third limit of the 6/*<- &red line+ arises due to the
/second 'reak down0 failure mode of a Power transistor. 3t shows the limiting
combinations of collector voltage and current so that second brea" down does not occur.
<n the log Blog scale of the 6/*<- this limit also appears as a straight limit. #i"e the
maximum power dissipation limit, the second brea" down limit is also different for G%$H
and GPulsedH operation of different pulse durations. he interpretation of the pulse
duration &mar"ed on the right side of 6ig >.9 &a++ corresponding to a particular limit is
also same.he final limit of the 6/*<- corresponds to the forward biased avalanche
brea" down voltage &)*?*+ of the transistor and appear as a vertical line in the 6/*<- at
)$A C )*u*..
1/*<- is a switching *<- since a transistor can not conduct current for any
appreciable duration under reverse biased condition. 3t essentially shows the limiting
permissible combinations of )$A . i$ with base emitter junction reverse biased. he
upper hori8ontal limit corresponds to the maximum allowable collector current &3$M+
and is same as that in the 6/*<-. he right hand side vertical limit corresponds the
avalanche brea" down voltage of the transistor with reverse bias. 3f the base terminal is
open &i,e, i/ C '+ then this voltage is )$A<. 3f a negative voltage is applied across the
/A junction the right hand side limit of the 1/*<- increases somewhat to the value
)$/< at low value of the collector current.
Switching characteristics of a Power Transistor
In a power electronic circuit the power transistor is usuall e!ploe" as a switch
i#e# it operates in either $cut off% &switch OFF' or saturation &switch O(' regions#
)owever* the operating characteristics of a power transistor differs significantly from
an ideal controlled switch in the following respects.
5J 3t can conduct only finite amount of current in one direction when G<NH
4J 3t can bloc" only a finite voltage in one direction.
>J 3t has a voltage drop during G<NH condition
@J 3t carries a small lea"age current during <66 condition
9J *witching operation is not instantaneous
EJ 3t requires non 8ero control power for switching
To turn the transistor O( at t + ,* the -ase -iasing voltage .
BB
changes to a
suita-le positive value# This starts the process of charge re"istri-ution at the
-ase-e!itter /unction# The process is a0in to charging of a capacitor# In"ee"* the
reverse -iase" -ase e!itter /unction is often represente" - a voltage "epen"ent
capacitor* the value of which is given - the !anufacturer as a function of the
-ase-e!itter reverse -ias voltage# The rising -ase current that flows "uring this
perio" can -e thought of as this capacitor charging current# Finall at t + t
"
the BE
/unction is forwar" -iase"# The /unction voltage an" the -ase current settles
"own to their stea" state values#1uring this perio"* calle" the $Turn O( "ela
ti!e% no apprecia-le collector current flows# The values of i
O
an" .
CE
re!ains
essentiall at their OFF state levels# -t the end of the delay time &td <N+ the minority
carrier density at the base region quic"ly approaches its steady state distribution and the
collector current starts rising while the diode current &id+ starts falling. -t t C td<N 2 tri the
collector current becomes equal to the load current &and id becomes 8ero+ 3#. -t this point
% starts bloc"ing reverse voltage and )$A becomes unclamped. tri is called the current rise
time of the transistor.
?1N B<N $!-1-$A13*3$*
he urn <N delay time can however be reduced by boosting the base current at the
beginning of the urn <N process. his can be achieved by connecting a small
capacitance across 1/.
T23( 4OFF C)535CTE3ISTICS
he Gurn <66H process starts with the base drive voltage going negative to a value -)//.
he base-emitter voltage however does not change from its forward bias value of )/A&sat+
immediately, due to the excess, minority carriers stored in the base region. - negative
base current starts removing this excess carrier at a rate determined by the negative base
drive voltage and the base drive resistance. -fter a time GtsH called the storage time of the
transistor, the remaining stored charge in the base becomes insufficient to support the
transistor in the hard saturation region. -t this point the transistor enters quasi saturation
region and the collector voltage starts rising with a small slope. -fter a further time
interval Gtrv5H the transistor completes traversing through the quasi saturation region and
enters the active region. he stored charge in the base region at this point is insufficient to
support the full negative base current. )/A starts falling forward B)// and the negative
base current starts reducing. 3n the active region, )$A increases rapidly towards )$$ and at
the end of the time interval Gtrv4H exceeds it to turn on %. )$A remains clamped at )$$,
thereafter by the conducting diode %. -t the end of trv4 the stored base charge can no
longer support the full load current through the collector and the collector current starts
falling. -t the end of the current fall time tfi the collector current becomes 8ero and the
load current freewheels through the diode %. urn <66 process of the transistor ends at
this point. he total urn <66 time is given by s &<66+ C ts 2 trv5 2 trv4 2 tfi .
3G,"
The I6T "evice has un"ergone !an i!prove!ent ccles to result in the !o"ern
Insulate" 6ate Bipolar Transistor &I6BT'# These "evices have near i"eal
characteristics for high voltage &7 1,,.' !e"iu! fre8uenc &9 :, 0);'
applications# This "evice along with the MOSFET &at low voltage high fre8uenc
applications' have the potential to replace the BJT co!pletel# he major
difference with the corresponding M<*6A cell structure lies in the addition of a p)
injecting layer. his layer forms a pn junction with the drain layer and injects minority
carriers into it. he n type drain layer itself may have two different doping levels. he
lightly doped n* region is called the drain drift region. %oping level and width of this
layer sets the forward bloc"ing voltage &determined by the reverse brea" down voltage of
F4+ of the device. !owever, it does not affect the on state voltage drop of the device due to
conductivity modulation as discussed in connection with the power diode. his
construction of the device is called GPunch roughH &P+ design. he Non-Punch
hrough &NP+ construction does not have this added n) buffer layer. he P
construction does offer lower on state voltage drop compared to the NP construction
particularly for lower voltage rated devices. !owever, it does so at the cost of lower
reverse brea" down voltage for the device, since the reverse brea" down voltage of the
junction F5 is small. he rest of the construction of the device is very similar to that of a
vertical MSF!" including the insulated gate structure and the shorted body &p type+ B
emitter &n) type+ structure. he doping level and physical geometry of the p type body
region however, is considerably different from that of a M<*6A in order to defeat the
latch up action of a parasitic thyristor embedded in the 3=/ structure. - large number of
basic cells as shown in 6ig are grown on a single silicon wafer and connected in parallel
to form a complete 3=/ device. The I6BT cell has a parasitic p-n-p-n thristor
structure e!-e""e" into it as shown in Fig# The constituent p-n-p transistor* n-p-
n transistor an" the "river MOSFET are shown - "otte" lines in this figure#
I!portant resistances in the current flow path are also in"icate"#
4ertical cross section of an 3G," cell.
6ig shows the exact static equivalent circuit of the 3=/ cell structure. he top p*n*p
transistor is formed by the p) injecting layer as the emitter, the n type drain layer as the
base and the p type body layer as the collector. he lower n*p*n transistor has the n) type
source, the p type body and the n type drain as the emitter, base and collector
respectively. he base of the lower n*p*n transistor is shorted to the emitter by the emitter
metalli8ation. !owever, due to imperfect shorting, the exact equivalent circuit of the
3=/ includes the body spreading resistance between the base and the emitter of the
lower n*p*n transistor. 3f the output current is large enough, the voltage drop across this
resistance may forward bias the lower n*p*n transistor and initiate the latch up process of
the p*n*p*n thyristor structure. <nce this structure latches up the gate control of 3=/ is
lost and the device is destroyed due to excessive power loss. - major effort in the
development of 3=/ has been towards prevention of latch up of the parasitic thyristor.
his has been achieved by modifying the doping level and physical geometry of the body
region. he modern 3=/ is latch-up proof for all practical purpose.
Operating principle of an I6BT
<perating principle of an 3=/ can be explained in terms of the schematic cell structure
and equivalent circuit of 6ig &a+ and &c+. 6rom the input side the 3=/ behaves
essentially as a M<*6A. herefore, when the gate emitter voltage is less then the
threshold voltage no inversion layer is formed in the p type body region and the device is
in the off state. he forward voltage applied between the collector and the emitter drops
almost entirely across the junction F4. )ery small lea"age current flows through the device
under this condition. 3n terms of the equivalent current of 6ig &c+, when the gate emitter
voltage is lower than the threshold voltage the driving M<*6A of the %arlington
configuration remains off and hence the output p*n*p transistor also remains off.
,hen the gate emitter voltage exceeds the threshold, an inversion layer forms in
the p type body region under the gate. his inversion layer &channel+ shorts the emitter
and the drain drift layer and an electron current flows from the emitter through this
channel to the drain drift region. his in turn causes substantial hole injection from the p)
type collector to the drain drift region. - portion of these holes recombine with the
electrons arriving at the drain drift region through the channel. he rest of the holes cross
the drift region to reach the p type body where they are collected by the source
metalli8ation. 6rom the above discussion it is clear that the n type drain drift region acts
as the base of the output p*n*p transistor. he doping level and the thic"ness of this layer
determines the current gain G H of the p*n*p transistor. his is intentionally "ept low so
that most of the device current flows through the M<*6A and not the output p*n*p
transistor collector. his helps to reduced the voltage drop across the GbodyH spreading
resistance shown in 6ig &b+ and eliminate the possibility of static latch up of the 3=/.
he total on state voltage drop across a conducting 3=/ has three components.
he voltage drop across F5 follows the usual exponential law of a pn junction. he next
component of the voltage drop is due to the drain drift region resistance. his component
in an 3=/ is considerably lower compared to a M<*6A due to strong conductivity
modulation by the injected minority carriers from the collector. his is the main reason
for reduced voltage drop across an 3=/ compared to an equivalent M<*6A. he last
component of the voltage drop across an 3=/ is due to the channel resistance and its
magnitude is equal to that of a comparable M<*6A
.
Stea" state characteristics of an I6BT
The i5v characteristics of an n channel I?4T is shown in "ig. They
appear )ualitatively si%ilar to those of a logic level 48T e&cept that the
controlling para%eter is not a (ase current (ut the gate5e%itter
voltage.,hen the gate emitter voltage is below the threshold voltage only a very small
lea"age current flows though the device while the collector B emitter voltage almost
equals the supply voltage &point $ in 6ig &a+. he device, under this condition is said to
be operating in the cut off region. he maximum forward voltage the device can
withstand in this mode &mar"ed )$A* in 6ig &a++ is determined by the avalanche brea"
down voltage of the body B drain p*n junction. ?nli"e a /F, however, this brea" down
voltage is independent of the collector current as shown in 6ig &a+. 3=/s of Non-punch
through design can bloc" a maximum reverse voltage &)1M+ equal to )$A* in the cut off
mode. !owever, for Punch hrough 3=/s )1M is negligible &only a few tens of volts+
due the presence of the heavily doped n) drain buffer layer.
-s the gate emitter voltage increases beyond the threshold voltage the 3=/
enters into the active region of operation. 3n this mode, the collector current ic is
determined by the transfer characteristics of the device as shown in 6ig &b+. his
characteristic is qualitatively similar to that of a power M<*6A and is reasonably linear
over most of the collector current range. he ratio of ic to &)gA B vgA&th++ is called the
forward transconductance &gfs+ of the device and is an important parameter in the gate
drive circuit design. he collector emitter voltage, on the other hand, is determined by the
external load line -/$ as shown in 6ig.
$!-1-$A13*3$* <6 3=/
-s the gate emitter voltage is increased further ic also increases and for a given
load resistance &1#+ v$A decreases. -t one point v$A becomes less than vgA B vgA&th+.
?nder this condition the driving M<*6A part of the 3=/ enters into the ohmic region
and drives the output p*n*p transistor to saturation. ?nder this condition the device is
said to be in the saturation mode. 3n the saturation mode the voltage drop across the
3=/ remains almost constant reducing only slightly with increasing vgA.
In power electronic applications an I6BT is operate" either in the cut off or in the
saturation region of the output characteristics# Since v
CE
"ecreases with
increasing v
gE*
it is "esira-le to use the !a<i!u! per!issi-le value of v
gE
in the
O( state of the "evice# v
gE
&Ma<' is li!ite" - the !a<i!u! collector current that
shoul" -e per!itte" to flow in the I6BT as "ictate" - the $latch-up% con"ition
"iscusse" earlier# =i!iting .
gE
also helps to li!it the fault current through the
device. 3f a short circuit fault occurs in the load resistance 1#, the fault load line is given
by $6. #imiting vgA to vgAE restricts the fault current corresponding to the operating point
6. Most 3=/s are designed to with stand this fault current for a few microseconds within
which the device must be turned off to prevent destruction of the device. It is interesting
to note that an I6BT "oes not e<i-it a BJT-li0e secon" -rea0 "own failure# Since*
in an I6BT !ost of the collector current flows through the "rive MOSFET with
positive te!perature coefficient the effective te!perature coefficient of v
CE
in an
I6BT is slightl positive# This helps to prevent secon" -rea0 "own failure of the
"evice an" also facilitates paralleling of I6BTs#
Switching characteristics of I6BT

*witching characteristics of the 3=/ will be analy8ed with respect to the clamped
inductive switching circuit shown in 6ig. he equivalent circuit of the 3=/ shown in 6ig
&b+ will be used to explain the switching waveforms.
*,3$!3N= -N% AM?3)-#AN $31$?3 <6 3=/
he switching waveforms of an 3=/ is, in many respects, similar to that of a Power
M<*6A. his is expected, since the input stage of an 3=/ is a M<*6A as shown in
6ig &b+. -lso in a modern 3=/ a major portion of the total device current flows through
the M<*6A. herefore, the switching voltage and current waveforms exhibit a strong
similarity with those of a M<*6A. !owever, the output p*n*p transistor does have a
significant effect on the switching characteristics of the device, particularly during turn
off. -nother important difference is in the gate drive requirement. o avoid dynamic latch
up, &to be discussed later+ the gate emitter voltage of an 3=/ is maintained at a negative
value when the device is off.
*,3$!3N= ,-)A6<1M* <6 3=/
he switching waveforms of an 3=/ is shown in 6ig. *imilarity of these waveforms
with those of a M<*6A is obvious. o turn on the 3=/ the gate drive voltage changes
from B)gg to 2)gg. he gate emitter voltage vgA follows )gg with a time constant N5. *ince
the drain source voltage of the drive M<*6A is large the gate drain capacitor assumes
the lower value $=%5. he collector current ic does not start increasing till vgA reaches the
threshold voltage vgA&th+. hereafter, ic increases following the transfer characteristics of
the device till vgA reaches a value vgA3# corresponding to ic C i#. his period is called the
current rise time tri. he free wheeling diode current falls from 3# to 8ero during this
period. -fter ic reaches 3#, vgA becomes clamped at vgA 3# similar to a M<*6A. v$A also
starts falling during this period. 6irst v$A falls rapidly &tfv5+ and afterwards the fall of v$A
slows down considerably. wo factors contribute to the slowing down of voltage fall.
6irst the gate-drain capacitance $gd will increase in the M<*6A portion of the 3=/ at
low drain-source voltages. *econd, the pnp transistor portion of the 3=/ traverses the
active region to its on state more slowly than the M<*6A portion of the 3=/. <nce the
pnp transistor is fully on after tfv4, the on state voltage of the device settles down to
v$A&sat+. he turn <N process ends here.
The turn off process of an I6BT follows the inverse se8uence of turn O(
with one !a/or "ifference# Once v
gE
goes -elow v
gE
&th' the "rive MOSFET of the
I6BT e8uivalent circuit turns off# 1uring this perio" &t
fi1
' the "evice current falls
rapi"l# )owever* when the "rive MOSFET turns off* so!e a!ount of current
continues of flow through the output p*n*p transistor due to stored charge in its base.
*ince there is no reverse voltage applied to the 3=/ terminals that could generate a
negative drain current, there is no possibility for removing the stored charge by carrier
sweep-out. he only way these excess carriers can be removed is by recombination
within the 3=/. %uring this recombination period &tfi4+ the remaining current in the
3=/ decays relatively slowly forming a current fail. - long tfi4 is undesirable, because
the power dissipation in this interval will be large due to full collector-emitter voltage. tfi4
can be reduced by decreasing the excess carrier life time in the p*n*p transistor base.
!owever, in the process, on state losses will increase. herefore, judicious design trade
offs are made in a practical 3=/ to give minimum total loss.
he gate drive circuit of an 3=/ should ensure fast and reliable switching of the
device. 3n particular, it should.
5J -pply maximum permissible )gA during <N period.
4J -pply a negative voltage during off period.
>J $ontrol during turn <N and turn off to avoid excessive Alectro magnetic
interference &AM3+.
@J $ontrol during switching to avoid 3=/ latch up.
9J Minimi8e switching loss.
>? Provi"e protection against short circuit fault.
he 3=/ has robust *<- both during turn on and turn off. 6ig shows the
6/*<-. <n the left side it is restricted by the forward voltage drop characteristics. ?p to
maximum continuous collector current this voltage remains reasonably constant at a low
value. !owever, at 3$M this voltage starts increasing as the 3=/ starts entering active
region. <n the top the 6/*<- is restricted by 3$M.
he other two limits are formed by the maximum power dissipation limit and the
maximum forward voltage limit. #i"e other devices the maximum power dissipation limit
increases with reduction in the on pulse width. he 1/*<- for low values of is
rectangular. !owever, for increased the upper-right hand corner is progressively cut out.
he reason for this restriction on the 1/*<- is to avoid dynamic latch up. he device
user can easily control by proper choice of )gg and the gate drive resistance.
"R31%
he riac is a member of the thyristor family. /ut unli"e a thyristor which conducts only
in one direction &from anode to cathode+ a triac can conduct in both directions. hus a
triac is similar to two bac" to bac" &anti parallel+ connected thyristosr but with only three
terminals. -s in the case of a thyristor, the conduction of a triac is initiated by injecting a
current pulse into the gate terminal. he gate looses control over conduction once the
triac is turned on. he triac turns off only when the current through the main terminals
become 8ero. herefore, a triac can be categori8ed as a minority carrier, a bidirectional
semi-controlled device. hey are extensively used in residential lamp dimmers, heater
control and for speed control of small single phase series and induction motors.
1 Construction an" operating principle
-s the riac can conduct in both the directions the terms GanodeH and GcathodeH are not
used for riacs. he three terminals are mar"ed as M5 &Main erminal 5+, M4 &Main
erminal 4+ and the gate by =. -s shown in 6ig the gate terminal is near M5 and is
connected to both N> and P4 regions by metallic contact. *imilarly M5 is connected to N4
and P4 regions while M4 is connected to N@ and P5 regions.
$31$?3 *OM/<# -N% $<N*1?$3<N <6 13-$
Since a Triac is a (idirectional device and can have its ter%inals at
various co%(inations of positive and negative voltages' there are four
possi(le electrode potential co%(inations as given (elow 1. MTH
positive with respect to MT1' ? positive with respect to MT1 H. MTH
positive with respect to MT1' ? negative with respect to MT1 9. MTH
negative with respect to MT1' ? negative with respect to MT1 @. MTH
negative with respect to MT1' ? positive with respect to MT1 The
triggering sensitivity is highest with the co%(inations 1 and 9 and are
generally used. 0owever' for (idirectional control and unifor%s gate
trigger %ode so%eti%es trigger %odes H and 9 are used. Trigger %ode
@ is usually averded.
Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode
1 , (b) Mode 3.
In trigger %ode51 the gate current 7ows %ainly through the 3H /H
1unction li,e an ordinary thyristor. :hen the gate current has in1ected
suIcient charge into 3H layer the triac starts conducting through the 31
/1 3H /H layers li,e an ordinary thyristor. In the trigger %ode59 the gate
current Ig forward (iases the 3H 39 1unction and a large nu%(er of
electrons are introduced in the 3H region (y /9. "inally the structure 3H
/1 31 /@ turns on co%pletely.
Stea" State Output Characteristics an" 3atings of a Triac
6rom a functional point of view a triac is similar to two thyristors connected in anti
parallel. herefore, it is expected that the )-3 characteristics of riac in the 5
st
and >
rd
quadrant of the )-3 plane will be similar to the forward characteristics of a thyristors. -s
shown in 6ig., with no signal to the gate the triac will bloc" both half cycle of the applied
ac voltage provided its pea" value is lower than the brea" over voltage &)/<+ of the
device. !owever, the turning on of the triac can be controlled by applying the gate trigger
pulse at the desired instance. Mode-5 triggering is used in the first quadrant where as
Mode-> triggering is used in the third quadrant. -s such, most of the thyristor
characteristics apply to the triac &ie, latching and holding current+. !owever, in a triac the
two conducting paths &from M5 to M4 or from M5 to M5+ interact with each other in
the structure of the triac. herefore, the voltage, current and frequency ratings of triacs
are considerably lower than thyristors. -t present triacs with voltage and current ratings
of 54'') and >''- &rms+ are available. riacs also have a larger on state voltage drop
compared to a thyristor. Manufacturers usually specify characteristics curves relating rms
device current and maximum allowable case temperature as shown in 6ig. $urves
relating the device dissipation and 1M* on state current are also provided for different
conduction angles.
RMS ! state current "s ma#imum case temperature.
COMPARISON OF MOSFET WITH BJT
Power M<*6A* have lower switching losses but its on-resistance and
conduction losses are more. - /F has higher switching loss bit lower conduction
loss. *o at high frequency applications power M<*6A is the obvious choice. /ut
at lower operating frequencies /F is superior.
M<*6A has positive temperature coefficient for resistance. his ma"es parallel
operation of M<*6APs easy. 3f a M<*6A shares increased current initially, it
heats up faster, its resistance increases and this increased resistance causes this
current to shift to other devices in parallel. - /F is a negative temperature
coefficient, so current shaving resistors are necessary during parallel operation of
/FPs.
3n M<*6A secondary brea"down does not occur because it have positive
temperature coefficient. /ut /F exhibits negative temperature coefficient which
results in secondary brea"down.
Power M<*6APs in higher voltage ratings have more conduction losses.
Power M<*6APs have lower ratings compared to /FPs . Power M<*6APs
9'') to 5@'-, /F 54''), D''-.
T)@3ISTO3S
- thyristor is the most important type of power semiconductor devices. hey are
extensively used in power electronic circuits. hey are operated as bi-stable switches
from non-conducting to conducting state.
- thyristor is a four layer, semiconductor of p-n-p-n structure with three p-n junctions. 3t
has three terminals, the anode, cathode and the gate.
he word thyristor is coined from thyratron and transistor. 3t was invented in the year
5Q9( at /ell #abs. he %ifferent types of hyristors are
*ilicon $ontrolled 1ectifier &*$1+.
13-$
%3-$
=ate urn <ff hyristor &=<+
S353%6 %6"R55!D R!%"3F3!R #S%R$
6ig.7 *ymbol
he *$1 is a four layer three terminal device with junctions
5 4 >
, , J J J
as shown. he construction of *$1 shows that the
gate terminal is "ept nearer the cathode. he approximate
thic"ness of each layer and doping densities are as indicated in
the figure. 3n terms of their lateral dimensions hyristors are
the largest semiconductor devices made. - complete silicon
wafer as large as ten centimeter in diameter may be used to
ma"e a single high power thyristor.
6ig.7 *tructure of a generic thyristor
QUALITATIVE ANALYSIS
,hen the anode is made positive with respect the cathode junctions
5 >
. J J
are forward
biased and junction
4
J
is reverse biased. ,ith anode to cathode voltage
AK
V
being small,
only lea"age current flows through the device. he *$1 is then said to be in the forward
bloc"ing state. 3f
AK
V
is further increased to a large value, the reverse biased junction
4
J
will brea"down due to avalanche effect resulting in a large current through the device.
he voltage at which this phenomenon occurs is called the forward brea"down voltage
BO
V
. *ince the other junctions
5 >
. J J
are already forward biased, there will be free
movement of carriers across all three junctions resulting in a large forward anode current.
<nce the *$1 is switched on, the voltage drop across it is very small, typically 5 to 5.9).
he anode current is limited only by the external
impedance present in the circuit.
}
}
}
}
G a t e C a t h o d e
J

J
!
J
"
A # o d e
" $ % &
" ' (
" $ ( ) * " $ % &
" " + (
" $ % &
" ' (
" $ % &
" , (
" $ % &
" , (
" $ % &
" , (
#
-
#
-
.
(
#
/
.
.
-
" $ &
$ ( " $ $ &
) $ ( " $ $ $ &
$ ( ) $ &
6ig.7 *implified model of a thyristor
-lthough an *$1 can be turned on by increasing the forward voltage beyond
BO
V
, in
practice, the forward voltage is maintained well below
BO
V
and the *$1 is turned on by
applying a positive voltage between gate and cathode. ,ith the application of positive
gate voltage, the lea"age current through the junction
4
J
is increased. his is because the
resulting gate current consists mainly of electron flow from cathode to gate. *ince the
bottom end layer is heavily doped as compared to the p-layer, due to the applied voltage,
some of these electrons reach junction
4
J
and add to the minority carrier concentration in
the p-layer. his raises the reverse lea"age current and results in brea"down of junction
4
J
even though the applied forward voltage is less than the brea"down voltage
BO
V
. ,ith
increase in gate current brea"down occurs earlier.
4*3 %71R1%"!R3S"3%S
6ig. $ircuit
6ig7 )-3 $haracteristics
- typical )-3 characteristics of a thyristor is shown above. 3n the reverse direction the
thyristor appears similar to a reverse biased diode which conducts very little current until
avalanche brea"down occurs. 3n the forward direction the thyristor has two stable states
or modes of operation that are connected together by an unstable mode that appears as a
negative resistance on the )-3 characteristics. he low current high voltage region is the
forward bloc"ing state or the off state and the low voltage high current mode is the on
V
A A
V
G G
R
L
A
K
state. 6or the forward bloc"ing state the quantity of interest is the forward bloc"ing
voltage
BO
V
which is defined for 8ero gate current. 3f a positive gate current is applied to
a thyristor then the transition or brea" over to the on state will occur at smaller values of
anode to cathode voltage as shown. -lthough not indicated the gate current does not have
to be a dc current but instead can be a pulse of current having some minimum time
duration. his ability to switch the thyristor by means of a current pulse is the reason for
wide spread applications of the device.
!owever once the thyristor is in the on state the gate cannot be used to turn the device
off. he only way to turn off the thyristor is for the external circuit to force the current
through the device to be less than the holding current for a minimum specified time
period.
6ig.7 Affects on gate current on forward bloc"ing voltage
HOLDING CURRENT H
I
-fter an *$1 has been switched to the on state a certain minimum value of anode current
is required to maintain the thyristor in this low impedance state. 3f the anode current is
reduced below the critical holding current value, the thyristor cannot maintain the current
through it and reverts to its off state usually
I

is associated with turn off the device.

LATCHING CURRENT L
I
-fter the *$1 has switched on, there is a minimum current required to sustain
conduction. his current is called the latching current.
L
I
associated with turn on and is
usually greater than holding current.
QUANTITATIVE ANALYSIS
". "R16S3S"R MD!5
he general transistor equations are,
( )
( )
5
5
C B CBO
C E CBO
E C B
B E CBO
I I I
I I I
I I I
I I I

+ +
+
+

he *$1 can be considered to be made up of two transistors as shown in above figure.
$onsidering PNP transistor of the equivalent circuit,
( ) ( )
5 5 5 5
5 5
5
5
, , , ,
5 5
E A C C CBO CBO B B
B A CBO
I I I I I I I I
I I I

$onsidering NPN transistor of the equivalent circuit,
( ) ( )
4 4 4
4 4
4 4
4
4
, ,
4
C C B B E K A G
C k CBO
C A G CBO
I I I I I I I I
I I I
I I I I

+
+
+ +
6rom the equivalent circuit, we see that
( )
4 5
4 5 4
5 4
5
C B
g CBO CBO
A
I I
I I I
I



+ +

+
wo transistors analog is valid only till *$1 reaches <N state
%ase 1: ,hen
'
g
I
,
( )
5 4
5 4
5
CBO CBO
A
I I
I

+

+
he gain
5

of transistor
5
T
varies with its emitter current
E A
I I
. *imilarly varies with
E A g K
I I I I +
. 3n this case, with
'
g
I
,
4

varies only with

A
I
. 3nitially when the
applied forward voltage is small, ( )
5 4
5 + <
.
3f however the reverse lea"age current is increased by increasing the applied forward
voltage, the gains of the transistor increase, resulting in ( )
5 4
5 +
.
6rom the equation, it is seen that when ( )
5 4
5 +
, the anode current
A
I
tends towards

. his explains the increase in anode current for the brea" over voltage
' B
V
.
%ase (: ,ith gate current
g
I
applied.
,hen sufficient gate drive is applied, we see that
4
B g
I I
is established. his in turn
results in a current through transistor
4
T
, this increases
4

of
4
T
. /ut with the existence of
4 4
4 4 C g
I I I

, a current through , is established. herefore,
5 5 4
5 5 4 5 4 C B B g
I I I I
. his current in turn is connected to the base of
4
T
. hus
the base drive of
4
T
is increased which in turn increases the base drive of
5
T
, therefore
regenerative feedbac" or positive feedbac" is established between the two transistors.
his causes ( )
5 4
+
to tend to unity therefore the anode current begins to grow towards
a large value. his regeneration continues even if
g
I
is removed this characteristic of *$1
ma"es it suitable for pulse triggering; *$1 is also called a #athing %evice.
SWITCHING CHARACTERISTICS 0DYNAMIC
CHARACTERISTICS1
"78R3S"R "9R6*6 %71R1%"!R3S"3%S

6ig.7 urn-on characteristics
,hen the *$1 is turned on with the application of the gate signal, the *$1 does not
conduct fully at the instant of application of the gate trigger pulse. 3n the beginning, there
is no appreciable increase in the *$1 anode current, which is because, only a small
portion of the silicon pellet in the immediate vicinity of the gate electrode starts
conducting. he duration between Q': of the pea" gate trigger pulse and the instant the
forward voltage has fallen to Q': of its initial value is called the gate controlled R trigger
delay time
gd
t
. 3t is also defined as the duration between Q': of the gate trigger pulse
and the instant at which the anode current rises to 5': of its pea" value.
gd
t
is usually in
the range of 5sec.
<nce
gd
t
has lapsed, the current starts rising towards the pea" value. he period during
which the anode current rises from 5': to Q': of its pea" value is called the rise time. 3t
is also defined as the time for which the anode voltage falls from Q': to 5': of its pea"
value. he summation of
gd
t
and
r
t
gives the turn on time
on
t
of the thyristor.
THYRISTOR TURN OFF CHARACTERISTICS
A # o d e % 2 3 3 e # t
4 e 5 6 # 7 t o
d e % 3 e a 7 e
t
C
t
8
t
t
C o & & 2 t a t 6 o #
d 6
d t
R e % o 9 e 3 : R e % o & 4 6 # a t 6 o #
t
"
t
!
t

t
+
t
)
t
3 3
t
5 3
t
8
t
%
V
A K
I
A
t
8
; d e 9 6 % e o < < t 6 & e
t
%
; % 6 3 % 2 6 t o < < t 6 & e
,hen an *$1 is turned on by the gate signal, the gate loses control over the device and
the device can be brought bac" to the bloc"ing state only by reducing the forward current
to a level below that of the holding current. 3n -$ circuits, however, the current goes
through a natural 8ero value and the device will automatically switch off. /ut in %$
circuits, where no neutral 8ero value of current exists, the forward current is reduced by
applying a reverse voltage across anode and cathode and thus forcing the current through
the *$1 to 8ero.
-s in the case of diodes, the *$1 has a reverse recovery time
rr
t
which is due to charge
storage in the junctions of the *$1. hese excess carriers ta"e some time for
recombination resulting in the gate recovery time or reverse recombination time
gr
t
.
hus, the turn-off time
q
t
is the sum of the durations for which reverse recovery current
flows after the application of reverse voltage and the time required for the recombination
of all excess carriers present. -t the end of the turn off time, a depletion layer develops
across
4
J
and the junction can now withstand the forward voltage. he turn off time is
dependent on the anode current, the magnitude of reverse
g
V
applied ad the magnitude
and rate of application of the forward voltage. he turn off time for converte grade *$1Ps
is 9' to 5''sec and that for inverter grade *$1Ps is 5' to 4'sec.
o ensure that *$1 has successfully turned off , it is required that the circuit off time
c
t
be greater than *$1 turn off time
q
t
.
THYRISTOR TURN ON
"her&al "urn on: 3f the temperature of the thyristor is high, there will be an
increase in charge carriers which would increase the lea"age current. his would
cause an increase in
5

.
4

and the thyristor may turn on. his type of turn on

many cause thermal run away and is usually avoided.
5ight7 3f light be allowed to fall on the junctions of a thyristor, charge carrier
concentration would increase which may turn on the *$1.
51S%R: #ight activated *$1s are turned on by allowing light to stri"e the
silicon wafer.
7igh 4oltage "riggering: his is triggering without application of gate voltage
with only application of a large voltage across the anode-cathode such that it is
greater than the forward brea"down voltage
BO
V
. his type of turn on is
destructive and should be avoided.
Gate "riggering: =ate triggering is the method practically employed to turn-on
the thyristor. =ate triggering will be discussed in detail later.

dv
dt
"riggering: ?nder transient conditions, the capacitances of the p-n junction
will influence the characteristics of a thyristor. 3f the thyristor is in the bloc"ing
state, a rapidly rising voltage applied across the device would cause a high current
to flow through the device resulting in turn-on. 3f
4
j
i
is the current throught the
junction
4
j
and
4
j
C
is the junction capacitance and
4
j
V
is the voltage across
4
j
,
then
( )
4 4
4 4
4 4
4
4
j J j
j j j j
C dV dC
dq d
i C V V
dt dt dt dt
+
6rom the above equation, we see that if
dv
dt
is large,
4
5
j
will be large. - high value
of charging current may damage the thyristor and the device must be protected against
high
dv
dt
. he manufacturers specify the allowable
dv
dt
.
THYRISTOR RATINGS
First Su'script Second Su'script "hird Su'script
% off state , wor"ing M Pea" )alue
<N state 1 1epetitive
6 6orward * *urge or non-repetitive
1 1everse
45"1G! R1"36GS
DW
V
7 his specifies the pea" off state wor"ing forward voltage of the device. his
specifies the maximum forward off state voltage which the thyristor can withstand during
its wor"ing.
DR
V
7 his is the pea" repetitive off state forward voltage that the thyristor can bloc"
repeatedly in the forward direction &transient+.
D!
V
7 his is the pea" off state surge R non-repetitive forward voltage that will occur
across the thyristor.
RW
V
7 his the pea" reverse wor"ing voltage that the thyristor can withstand in the
reverse direction.
RR
V
7 3t is the pea" repetitive reverse voltage. 3t is defined as the maximum permissible
instantaneous value of repetitive applied reverse voltage that the thyristor can bloc" in
reverse direction.
R!
V
7 Pea" surge reverse voltage. his rating occurs for transient conditions for a
specified time duration.
T
V
7 <n state voltage drop and is dependent on junction temperature.
T
V
7 Pea" on state voltage. his is specified for a particular anode current and junction
temperature.
dv
dt
rating7 his is the maximum rate of rise of anode voltage that the *$1 has to
withstand and which will not trigger the device without gate signal &refer
dv
dt
triggering+.
%9RR!6" R1"36G
T"v#r"g#
I
7 his is the on state average current which is specified at a particular temperature.
TR!
I
7 his is the on-state 1M* current.
#atching current,
L
I
7 -fter the *$1 has switched on, there is a minimum current required
to sustain conduction. his current is called the latching current.
L
I
associated with turn
on and is usually greater than holding current
!olding current,
H
I
7 -fter an *$1 has been switched to the on state a certain minimum
value of anode current is required to maintain the thyristor in this low impedance state. 3f
the anode current is reduced below the critical holding current value, the thyristor cannot
maintain the current through it and reverts to its off state usually
I

is associated with
turn off the device.
di
dt
rating7 his is a non repetitive rate of rise of on-state current. his maximum value of
rate of rise of current is which the thyristor can withstand without destruction. ,hen
thyristor is switched on, conduction starts at a place near the gate. his small area of
conduction spreads rapidly and if rate of rise of anode current
di
dt
is large compared to
the spreading velocity of carriers, local hotspots will be formed near the gate due to high
current density. his causes the junction temperature to rise above the safe limit and the
*$1 may be damaged permanently. he
di
dt
rating is specified in sec A .
G1"! SP!%3F3%1"36S
GT
I
7 his is the required gate current to trigger the *$1. his is usually specified as a %$
value.
GT
V
7 his is the specified value of gate voltage to turn on the *$1 &dc value+.
GD
V
7 his is the value of gate voltage, to switch from off state to on state. - value below
this will "eep the *$1 in off state.
RR
Q
7 -mount of charge carriers which have to be recovered during the turn off process.
t$jc
R
7 hermal resistance between junction and outer case of the device.
G1"! "R3GG!R36G M!"7DS
ypes
he different methods of gate triggering are the following
1-triggering.
1$ triggering.
?F triggering.
RESISTANCE TRIGGERING
- simple resistance triggering circuit is as shown. he resistor
5
R
limits the current
through the gate of the *$1.
4
R
is the variable resistance added to the circuit to achieve
control over the triggering angle of *$1. 1esistor S1P is a stabili8ing resistor. he diode
% is required to ensure that no negative voltage reaches the gate of the *$1.
6ig.7 1esistance firing circuit
6ig.7 1esistance firing of an *$1 in half wave circuit with dc load
#a$ 6o triggering of S%R #'$ : ;<
<
#c$ = ;<
<
L O A D
9
O
a
4
6 R
"
R
!
D
R V
5
V
T
9 ; V 7 6 # t
S &

V
S
!
+
t
V 7 6 # t
&

V
5 V
5 t
t
t
t
t
V
o
6
o
V
T
V
5 .
V
5 t V
5 .
0 a 1
t
t
t
t
t
t
t
t
t
t
!
+
!
+
V
S
V
5
V
o
6
o
V
T
V
S
V
5
V
o
6
o
V
T
V ; V
5 . 5 t

! ' $
$
!
+

, $
$
; , $
$
0 % 1 0 4 1
= , $
$
V > V
5 . 5 t
De765#
,ith
4
' R
, we need to ensure that
5
%
g%
V
I
R
<
, where
g%
I
is the maximum or pea" gate
current of the *$1. herefore 5
%
g%
V
R
I

.
-lso with
4
' R
, we need to ensure that the voltage drop across resistor S1P does not
exceed
g%
V
, the maximum gate voltage
( )
5
5
5
5
%
g%
g% g% %
g% % g%
g%
% g%
V R
V
R R
V R V R V R
V R R V V
V R
R
V V

+
+

OPERATION
%ase 1:
g& gt
V V <
g&
V
, the pea" gate voltage is less then
gt
V
since
4
R
is very large. herefore, current S3P
flowing through the gate is very small. *$1 will not turn on and therefore the load
voltage is 8ero and
scr
v
is equal to
s
V
. his is because we are using only a resistive
networ". herefore, output will be in phase with input.
%ase (:
g& gt
V V
,
4
R
optimum value.
,hen
4
R
is set to an optimum value such that
g& gt
V V
, we see that the *$1 is triggered
at
'
Q' &since
g&
V
reaches its pea" at
'
Q' only+. he waveforms shows that the load voltage
is 8ero till
'
Q' and the voltage across the *$1 is the same as input voltage till it is
triggered at
'
Q' .
%ase +:
g& gt
V V >
,
4
R
small value.
he triggering value
gt
V
is reached much earlier than
'
Q' . !ence the *$1 turns on
earlier than
!
V
reaches its pea" value. he waveforms as shown with respect to
sin
s %
V V t
.
-t ( )
, , sin
! gt % g& gt g&
t V V V V V V J
herefore
5
sin
gt
g&
V
V

,
/ut
5 4
%
g&
V R
V
R R R

+ +
herefore
( )
5 4 5
sin
gt
%
V R R R
V R

+ + 1

1
]
*ince
5
, ,
gt
V R R
are constants
4
R
RESISTANCE CAPACITANCE TRIGGERING
R% 715F .14!
$apacitor S$P in the circuit is connected to shift the phase of the gate voltage.
5
D
is used
to prevent negative voltage from reaching the gate cathode of *$1.
3n the negative half cycle, the capacitor charges to the pea" negative voltage of the
supply ( )
%
V
through the diode
4
D
. he capacitor maintains this voltage across it, till the
supply voltage crosses 8ero. -s the supply becomes positive, the capacitor charges
through resistor S1P from initial voltage of
%
V
, to a positive value.
,hen the capacitor voltage is equal to the gate trigger voltage of the *$1, the *$1 is
fired and the capacitor voltage is clamped to a small positive value.
6ig.7 1$ half-wave trigger circuit
L O A D
9
O
R
C
V
T
9 ; V 7 6 # t
S &

D
!
V
C
-
(
D
"
9
7
$
V 7 6 # t
&

$
t
t
t
a
9
%
( ? !
a
9
%
V
5 t
9
o
9
T

2 3

V
&
( V
&
9
7
$
V 7 6 # t
&

$
t
a
9
%
( ? !
a
9
%
V
5 t
$
$
9
o
9
T
V
&
V
&

2 3
( V
&
0 ! - 1
0 a 1
0 4 1
t t
6ig.7 ,aveforms for 1$ half-wave trigger circuit
#a$ 7igh value of R #'$ 5ow value of R
%ase 1: 1 #arge.
,hen the resistor S1P is large, the time ta"en for the capacitance to charge from
%
V
to
gt
V
is large, resulting in larger firing angle and lower load voltage.
%ase (: 1 *mall
,hen S1P is set to a smaller value, the capacitor charges at a faster rate towards
gt
V
resulting in early triggering of *$1 and hence
L
V
is more. ,hen the *$1 triggers, the
voltage drop across it falls to 5 B 5.9). his in turn lowers, the voltage across 1 . $.
#ow voltage across the *$1 during conduction period "eeps the capacitor discharge
during the positive half cycle.
DESIGN EQUATION
6rom the circuit
5 C gt d
V V V +
. $onsidering the source voltage and the gate circuit, we
can write
s gt C
v I R V +
. *$1 fires when
s gt C
v I R V +
that is
5 ! g gt d
v I R V V + +
.
herefore
5 s gt d
gt
v V V
R
I

. he 1$ time constant for 8ero output voltage that is

maximum firing angle for power frequencies is empirically gives as
5.>
4
T
RC
_

,
.
RC FULL WAVE
- simple circuit giving full wave output is shown in figure below. 3n this circuit the initial
voltage from which the capacitor S$P charges is essentially 8ero. he capacitor S$P is reset
to this voltage by the clamping action of the thyristor gate. 6or this reason the charging
time constant 1$ must be chosen longer than for half wave 1$ circuit in order to delay
the triggering. he 1$ value is empirically chosen as
9'
4
T
RC . -lso
s gt
gt
v V
R
I

.
9
O
R
C
V
T
9 ; V 7 6 # t
S &

-
(
L O A D
-
(
D " D
D + D !
9
d
6ig7 1$ full-wave trigger circuit
6ig7 ,ave-forms for 1$ full-wave trigger circuit
#a$ 7igh value of R #'$ 5ow value of R
PR,5!M
5. %esign a suitable 1$ triggering circuit for a thyristorised networ" operation on a
44'), 9'!8 supply. he specifications of *$1 are
min
9
gt
V V
,
max
>'
gt
I %A
.
(5@>.>
s gt D
g
v V V
R
I


herefore '.'5> RC
(.5@> R k

5.D5QQ C F
9
7
9
d
9
o
9
T
t
t
t
t
V 7 6 # t
&

9
d
9
%
9
%
9
% 9
5 t

V 7 6 # t
&

9
7
9
d
9
o
9
T
t
t
t
9
5 t

0 a 1 0 4 1
963*-96%"36 "R16S3S"R #9-"$
6ig.7 &a+ /asic structure of ?F &b+ *ymbolic representation
#c$ !>uivalent circuit
?F is an n-type silicon bar in which p-type emitter is embedded. 3t has three terminals
base5, base4 and emitter SAP. /etween
5
B
and
4
B
?F behaves li"e ordinary resistor and
the internal resistances are given as
5 B
R
and
4 B
R
with emitter open
5 4 BB B B
R R R +
.
?sually the p-region is heavily doped and n-region is lightly doped. he equivalent
circuit of ?F is as shown. ,hen
BB
V
is applied across
5
B
and
4
B
, we find that potential
at - is
5 5
5
5 4 5 4
BB B B
AB BB
B B B B
V R R
V V
R R R R

1

1
+ +
]

is intrinsic stand off ratio of ?F and ranges between '.95 and '.D4. 1esistor
4 B
R
is
between 9 to 5'0.
P!R1"36
,hen voltage
BB
V
is applied between emitter SAP with base 5
5
B
as reference and the
emitter voltage
E
V
is less than ( )
D BE
V V +
the ?F does not conduct. ( )
D BB
V V +
is
designated as
'
V
which is the value of voltage required to turn on the ?F. <nce
E
V
is
equal to
' BE D
V V V +
, then ?F is forward biased and it conducts.
he pea" point is the point at which pea" current
'
I
flows and the pea" voltage
'
V
is
across the ?F. -fter pea" point the current increases but voltage across device drops,
this is due to the fact that emitter starts to inject holes into the lower doped n-region.
*ince p-region is heavily doped compared to n-region. -lso holes have a longer life time,
therefore number of carriers in the base region increases rapidly. hus potential at S-P
falls but current
E
I
increases rapidly.
5 B
R
acts as a decreasing resistance.
R
B !
V
B B
-
(
E
B
"
R
B "
V
B B
A
-
(
V
e
I
e
B
!
E
B
!
B
"
B
"
A
B
!
E
R
B !
R
B "
# ( t : . e
. ( t : . e
E t a ( . o 6 # t
E t a ( . o 6 # t
0 a 1 0 4 1
0 % 1
he negative resistance region of ?F is between pea" point and valley point. -fter
valley point, the device acts as a normal diode since the base region is saturated and
5 B
R
does not decrease again.
V
e
V
B B
R @ o a d @ 6 # e
V
.
V
9
I
e
I
9
I
.
$
P e a A P o 6 # t
C 2 t o < <
3 e 5 6 o #
N e 5 a t 6 9 e R e 7 6 7 t a # % e
R e 5 6 o #
S a t 2 3 a t 6 o #
3 e 5 6 o #
V a @ @ e : P o 6 # t
6ig.7 )-3 $haracteristics of ?F
9-" R!51?1"36 S%3551"R
?F is highly efficient switch. he switching times is in the range of nanoseconds. *ince
?F exhibits negative resistance characteristics it can be used as relaxation oscillator. he
circuit diagram is as shown with
5
R
and
4
R
being small compared to
5 B
R
and
4 B
R
of
?F.
6ig.7 ?F oscillator &a+ $onnection diagram and &b+ )oltage waveforms
R
R
!
V
B B
R
"
C
E
B
!
B
"
V
e
9
o
V
e
V
.
V
V
V
o
t
t
C a . a % 6 t o 3
% h a 3 5 6 # 5
T ; R C
"
"

T
V - V
B B
V
P
T ; R C
! "
C a . a % 6 t o 3
d 6 7 % h a 3 5 6 # 5
V
9
0 a 1 0 4 1
P!R1"36
,hen
BB
V
is applied, capacitor S$P begins to charge through resistor S1P exponentially
towards
BB
V
. %uring this charging emitter circuit of ?F is an open circuit. he rate of
charging is
5
RC
. ,hen this capacitor voltage which is nothing but emitter voltage
E
V
reaches the pea" point
' BB D
V V V +
, the emitter base junction is forward biased and
?F turns on. $apacitor S$P rapidly discharges through load resistance
5
R
with time
constant ( )
4 5 4 5
RC D
. ,hen emitter voltage decreases to valley point
v
V
, ?F turns
off. <nce again the capacitor will charge towards
BB
V
and the cycle continues. he rate
of charging of the capacitor will be determined by the resistor 1 in the circuit. 3f 1 is
small the capacitor charges faster towards
BB
V
and thus reaches
'
V
faster and the *$1 is
triggered at a smaller firing angle. 3f 1 is large the capacitor ta"es a longer time to charge
towards
'
V
the firing angle is delayed. he waveform for both cases is as shown below.
EBPRESSION FOR PERIOD OF OSCILLATION CTD
he period of oscillation of the ?F can be derived based on the voltage across the
capacitor. !ere we assume that the period of charging of the capacitor is lot larger than
than the discharging time.
?sing initial and final value theorem for voltage across a capacitor, we get
( )
t
RC
C (in") initi") (in")
V V V V #

+
, , ,
C ' initi") V (in") BB
t T V V V V V V
herefore ( )
R T RC
' BB V BB
V V V V #

+
log
BB V
#
BB '
V V
T RC
V V
_

,
3f

,
ln
5
ln
5
V BB
BB
BB '
'
BB
V V
V
T RC
V V
RC
V
V
<
_

,
1
1
1
1

1
]
/ut
' BB D
V V V +
3f
D BB ' BB
V V V V D
herefore
5
ln
5
T RC

]
DESIGN OF UJT OSCILLATOR
1esistor S1P is limited to a value between > "ilo ohms and > mega ohms. he upper limit
on S1P is set by the requirement that the load line formed by S1P and
BB
V
intersects the
device characteristics to the right of the pea" point but to the left of valley point. 3f the
load line fails to pass to the right of the pea" point the ?F will not turn on, this condition
will be satisfied if
BB ' '
V I R V >
, therefore
BB '
'
V V
R
I

<
.
-t the valley point
E V
I I
and
E V
V V
, so the condition for the lower limit on S1P to
ensure turn-off is
BB V V
V I R V <
, therefore
BB V
V
V V
R
I

>
.
he recommended range of supply voltage is from 5' to >9). the width of the triggering
pulse
5 g B
t R C
.
3n general
5 B
R
is limited to a value of 5'' ohm and
4 B
R
has a value of 5'' ohm or greater
and can be approximately determined as
@
4
5'
B
BB
R
V