Enclosure

Door
Power Supply
Load
Line
Neutral
Earth
Timer Thermostat
Frost Detector
Heater
Supply
Return
Logic
Unit
Supply
Return
Heater
Thermostat
Timer
Frost Detector
The AND Gate
Truth Table
A B X = A B
0 0 0
0 1 0
1 0 0
1 1 1
A
B
X
The OR Gate
Truth Table
A B X = A + B
0 0 0
0 1 1
1 0 1
1 1 1
A
B
X
The NOT Gate
Truth Table
A X = A
0 1
1 0
A X
The small
circle indicates
inversion
T
M
F
H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Quad Gate in 14 pin TSSOP
Package 33.66mm
2
Board
Area
TSSOP - Thin Shrink Small-Outline
Package
Dual Gate in 8 pin DCU
Package 11.8mm
2
Board
Area (0.01g)
Note: DCU also known as US8
2.0mm
Single Gate in
5 pin YEA
Package
1.26mm
2
Board Area
(0.001g)
1.4mm
0.9mm 3.1mm
5.1
mm
6.4mm
A
B
C
A
B
A
C
D
A
B
C
A
B
C
A
B
C
D
B
D
A
C
A
D
B
C
A
X Y X Y
X Y X Y
Z
Y
X
X
Y
X
Z
D
D
Z
A
B
C
Z
A
B
C
Z
A
B
C
A 1' or high state is shown by:
A 0' or low state is shown by:
A dont care state is shown by:
1
0
X
X
X
X
X
X
X
X
X
X
X
Z = X Z = X
X
X
X
X
Z = 1 Z = 0
0
1
1
0
1
1
0
0
00 01 11 10
CD
AB
00
01
11
10
A
A
C C
D D D
B
B
B
1
1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1 1 1
1 1 1 1
1
1
1
1
1
1
1
1
1 1 1 1
1 1 1 1
1
1
1
1
1 1 1 1
1 1


1 1
1 1
1
1
00 01 11 10
CD
AB
00
01
11
10
CD
AB
00
01
11
10
00 01 11 10
CD
AB
CD
AB
E
F
0
0
1
1
1
1
1 1
1
ABCD
ABCDEF
The NAND Gate
Truth Table
A B X = A B
0 0 1
0 1 1
1 0 1
1 1 0
A
B
X
A
B
X
The NOR Gate
Truth Table
A B X = A + B
0 0 1
0 1 0
1 0 0
1 1 0
A
B
X
A
B
X
X + Y = X Y
X Y X
Y
X
Y
X
Y
X + Y = X Y
X Y X Y
X + Y
X Y = X + Y
X
Y
X Y = X + Y
X
Y
X
Y
X Y X Y
X =A A =A
X =A B =A B
X =A B =A +B
A
A
A
B
B
X =A +A =A
X =A +B =A +B
X =A +B =A B
A
A
B
A
B
A
W
X
Y
Z
WX+YZ
W
X
Y
Z
OR
WX+YZ
Y
Z
WX+YZ
W
X
A
B
AND
A
B
OR
NAND
NOR
A
B
A
B
NOT
A
A B = A+B
A B = A+B
A+B = A B
A+B = A B
A
A
B
A
B
A
B
A
B
X
X
X
X
X
A
A
B
A
B
A
B
A
B
X
X
X
X
X
1
&
1
&
1
NOT
AND
OR
NAND
NOR
The XOR Gate
Truth Table
A B X = A B
0 0 0
0 1 1
1 0 1
1 1 0
A
B
X
=1
X AB AB
The XNOR Gate
Truth Table
A B X = A B
0 0 1
0 1 0
1 0 0
1 1 1
A
B
X
=1
X AB AB
driver_present
belted_in
ignition_on
warning
Warning ON Warning OFF Warning OFF
Jump to Repeat
Is driver
present?
Is seatbelt
fastened?
Warning OFF
No
No
Is ignition
on?
No
Yes
Yes
Yes
O1
O2
O3
O4
O5
Om-1
I1
I2
I3
In-1
Decoder
A
B
0
1
2
3
A
B
C
0
1
2
3
4
5
6
7
A
B
C
7
6
5
4
3
2
1
0
E3
E2
E1
74LS138
A B C E1 E2 E3
O7 O6 O5 O4 O3 O2 O1 O0
A
B
C
D
E
O0
O31
1
0 0 0
74LS138 74LS138 74LS138 74LS138
A
B
X
Y
m
n
A
B
X
Y
m
n
A
B
X
Y
m
n
A
B
X
Y
m
n
A
B
Set
Reset
Q
Q
Set
Reset
Q
Q
S
R
Q
Q
S
R
Q
Q
Q
(a) (b)
S
R
Q
Q
S-R Bistable
S
R
Q
Q
Alarm
R1
IC1
SW1 SW2
SW3
V
CC
0V
R2
Set
Reset
Q
Q
Gate
S
G
R
Q
Q
S
R
Q
Q
D
G
G
D
Q
Q
Follow Latch Latch Follow Follow
Clock
CK
CK
P
CK
CK
P
Clock
D Q
Q
CLR
RST
Clock
Preset
Clear
D
Q
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
Q
T
CLK1 Q1
CLR
CLK2 Q2
CLR
CLK1
Q1
Q2
Passive Components
Resistor
eg:12K 2% 0.25W
Capacitor
eg: 470pF 5% 100V
Inductor
eg: 100mH
10% 50
5mA
Also: or:
Active Components
Diode Bipolar Transistor Field Effect Transistor
Logic Product Life Cycle
TTL
S
LS
AS
F
ALS
Bipolar
4000
HC
HCT
CMOS
BiCMOS
BCT
Decline
Maturity
Growth Introduction
FCT
ABT
CBT
LVC
LVT
LV
AHC
ALVT
Little Logic
ULP
VME
AUP
AVC
0V
+5V
+Vcc
0 V
Output
Logic
Function
I
V
+Vcc
0 V
Output
Logic
Function
Ib
I
OL
V
OL
On
+Vcc
0 V
Output
Logic
Function
I
OH
V
OH
Off
+Vcc
0 V
Output
Logic
Function
I
OH
V
OH
Off
4K
I
IH
V
IH
Logic 1
INPUT
+Vcc
0V (Gnd)
Logic
Device
I
IL
V
IL
Logic 0
INPUT
+Vcc
0V (Gnd)
Logic
Device
V
IL
+Vcc
0V (Gnd)
Logic
Device
V
OL
Logic
Device
Driver
Receiver
+Vcc
0V (Gnd)
Logic
Device
Logic
Device
Driver
Receiver
V
OH
V
IH
V Current I
D
Voltage V
D
Current Limiting Resistance
V
cc
0V
V
in1
V
in2
V
in3
V
out
R
V
cc
0V
V
in1
V
in2
V
in3
V
out
R
npn Transistors:
n
p
n
Base
Emitter
Collector
Collector
Base
Emitter
I
c
I
b
Collector
Base
Emitter
I
e
=I
b
+I
c
I
c
=gain I
b
Collector
Base
Emitter
Collector
Base
Emitter
V
cc
0V
V
in
V
out
R
1
R
2
V
cc
0V
V
in
V
out
R
1
R
2
V
cc
0V
V
in
V
out
R
1
R
2
V
cc
0V
V
in
V
out
R
1
R
2
V
cc
0V
V
in
V
out
R
1
R
2
Y = A
V
cc
0V
V
in
V
out
R
1
R
2
Base
Collector
Emitters
Equivalent Circuit
V
cc
0V
V
out
R
L
R
B
R
C
R
E
Q
1
Q
2
Q
3
A
B
C
V
cc
0V
V
out
R
L
R
B
R
C
R
E
Q
1
Q
2
Q
3
A
B
C
V
cc
0V
V
out
R
L
R
B
R
C
R
E
Q
1
Q
2
Q
3
A
B
C
V
cc
0V
V
in
V
out
R
1
R
2
C
S
V
cc
0V
V
1
V
out
C
S
V
2
Q
A
Q
B
V
cc
0V
V
1
V
out
C
S
Q
A
Q
B
Q
C
R
C
R
E
R
L
V
cc
0V
V
out
Q
A
Q
B
Q
C
R
C
R
E
R
L
R
B
A
B
C
Q
D
V
cc
0V
V
be
V
out
R
Schottky-barrier diode
Q
V
cc
0V
V
out
Drive from logic function
Q
V
CC1
0V
V
CC2
74LS05
R
IC1
IC2
P Type Substrate
Drain (D)
Source S
Substrate
Gate G
N Type Substrate
Substrate
Source S
Drain (D)
n-type well
p-type well
Metal layer
Silicon dioxide layer
(Insulator)
Gate G
P Type Substrate
Drain (D)
Source S
Substrate
Gate G
V
DS
V
GS
Induced n channel
a
G
S
D
SS
b
G
S
D
SS
c
G
S
D
d
G
S
D
N Channel MOSFET
S
D
Circuit Model
V
DD
0V
G
G
G
G
G
D D
D D
S
S S
S
0V
On
Off
+5V
I
DS
I
DS
10
10

10
3

Low
High
V
GS
= +5V
P Channel MOSFET
S
D
Circuit Model
V
G
G
G
G
G
G
D
D
D
D
S
S S
S
0V
On
Off
+5V
I
DS
I
DS
10
10

10
3

Low
High
+V
V
GS
= -5V
Q1 Q2
Q3
Q4
A
B
Output
V
DD
0V
D1 D2
Q1 Q2
Q3
Q4
A
B
Output
V
DD
0V
D1 D2
Q1
Q2
Q3
Q4
A
B
Output
V
DD
0V
D1 D2
Q1 Q2
Q3
Q4
A
B
Out
V
DD
0V
D1 D2
Q5
Q6
Q7
Q8
Q1
Q2
A
B
Output
V
DD
0V
A Y
Enable
Y =A (When enable is high)
A Y
Enable A
B
Enable B
Address
Data
A0
A1
Control
Read
Write
Output Enable
D0
D1
D2
D3 INPUTS
INPUT
&
OUTPUT
A0
A1
A2
A3
Processor
D0
D1
D2
D3
Read
Write
Memory
En
+V
A0
A1
A2
A3
Processor
D0
D1
D2
D3
Read
Write
Memory
En
Memory
En
1 2
Decode
g
i
v
m
d
gs

g
i
v
m
c
be

V+
0V
V
out
V
i
Q
4
Q
3
Q
1
Q
2
V+
0V
V
out
V
i
Q
4
Q
3
Q
1
Q
2
R
1
R
2
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
Alternative Symbols for NMOS FETs
Alternative Symbols for PMOS FETs
(i) (ii) (iii)
(iv) (v) (vi)
/OE1 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 Vcc
19 /OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
Pinout
74ABT540 Octal Buffer/Driver with 3-state Outputs.
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
&
EN
1
/OE1 1
/OE2 19
IEC Logic Symbol Logic Diagram
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
/OE1 1
/OE2 19
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A
B
Y
A 1
B 2
GND 3
5 Vcc

4 Y
3mm
1.6mm
2.8mm
1.45mm
DBV Pack
5 Vcc

4 Y
A 1
B 2
GND 3
0.5mm
0.9mm
1.4mm
YZP Pack
1
2
3
4
5
6
Voltage
Tolerance
Optimized
Voltage
Normal
Operating
Limits
(Specification)
Typically
Functional
LVC Logic AUP Logic AUC Logic
B 1
GND 2
A 3
6 C
5 Vcc
4 Y
DBV Pack
6 C
5 Vcc
4 Y
B 1
GND 2
A 3
YZP Pack
B
A
C
Y
A
Y
C
A
0V
Vcc C
Y
B
Y
C
0V
Vcc C
Y
B
1 6
2 5
3 4
1 6
2 5
3 4
0V
Vcc
Y
B
1 6
2 5
3 4
B Y
A
0V
Vcc C
Y
1 6
2 5
3 4
B
B
Y
A
C
NAND
NOR
INVERT
/DataSelect
1 0 1 0
1 1 0 1
0 0 1 1
1 0 0 1
D 4 A 7
LSB
MSB
Parallel data
Serial data
INPUT
Combinational
Logic
OUTPUT
Combinational
Logic
MEMORY
Clock (if present)
State Variables
Inputs
Outputs
INPUT
Combinational
Logic
OUTPUT
Combinational
Logic
MEMORY
Clock
State Variables
Inputs
Outputs
INPUT
Combinational
Logic
OUTPUT
Combinational
Logic
MEMORY
Clock
State Variables
Inputs
Outputs
(g) (S) (f)
X
S
Z
Z = f(S)
S g(S,X)
INPUT
Combinational
Logic
OUTPUT
Combinational
Logic
MEMORY
Clock
State Variables
Inputs
Outputs
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
S
R Q
Q
a
b
K
J
Clock
10,11
01,11
00,01 00,10
A
0
B
1
10/1,11/1
01/0,11/0
00/0,01/0 00/1,10/1
A B
11
00
00, 01, 10 01, 11, 10
A
0
B
1
x
y
Z
NAND
Clock
D Q
X
Y
1
0
0
1
A
0
C
1
B
0
0
1
Clock
X
Z
D P D Q
Q P
Infant Mortality Constant Failure Rate Wearout
Log Time
B1
B2
R1 R2 R3
LED1 - LED3 Light Emitting Diodes
D1 D2
S1 S2
LED1 LED2 LED3
S1 - S2 Switches
D1 - D2 Diodes
R1 - R3 Resistors
B1 - B2 Batteries
R L
C