Dr. Ahmed H.

Madian-VLSI 1
Very Large Scale Integration
(VLSI)
Dr. Ahmed H. Madian
[email protected]
Lecture 2
2
Acknowledgement
This lecture note has been summarized from
lecture note on Introduction to VLSI Design, VLSI
Circuit Design all over the world. I cant remember
where those slide come from. However, Id like to
thank all professors who create such a good work
on those lecture notes. Without those lectures, this
slide cant be finished.
Dr. Ahmed H. Madian-VLSI
3
Circuit simulation
Circuit simulators like Spice numerically
solve device models and Kirchoffs laws
to determine time-domain circuit
behavior.
Numerical solution allows more
sophisticated models, non-functional
(table-driven) models, etc.
Dr. Ahmed H. Madian-VLSI
4
Spice MOSFET models
Level 1: basic transistor equations of Section 2.2; not
very accurate.
Level 2: more accurate model (effective channel
length, etc.).
Level 3: empirical model.
Level 4 (BSIM): efficient empirical model.
New models: level 28 (BSIM2), level 47 (BSIM3).
Dr. Ahmed H. Madian-VLSI
5
Some (by no means all) Spice
model parameters
L, W: transistor length width.
KP: transconductance.
GAMMA: body bias factor.
AS, AD: source/drain areas.
CJSW: zero-bias sidewall capacitance.
CGBO: zero-bias gate/bulk overlap
capacitance.
Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI 6
Contents
Design Rules
Wiring tracks
Latch-up
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Inductance estimation
Delay estimation
Simple RC model
Penfield-Rubenstein Model
Delay minimization techniques
Transistor sizing
Distributed drivers
Large driver
Wiring techniques
Dr. Ahmed H. Madian-VLSI 7
Design Rules
Why we need design rules?
We can specify the design rules using some
convenient units, e.g., microns but what happens if
we want to manufacture the chip using different
manufacturers?
use an abstract unit, the lambda (), and scale the design
to the appropriate actual dimensions when the chip is to be
manufactured.
Each piece of fabrication equipment used in the IC
manufacturing process has limited accuracy.
So, we need rules to ensure that the inaccuracy in
the fabrication will not result in malfunction IC.
Dr. Ahmed H. Madian-VLSI 8
Lambda-based Rules
One lambda ()= one half of
the minimum mask
dimension, typically the length
of a transistor channel. This
can be used to derive design
rules and to estimate minimum
dimensions of a junction area
and perimeter before a
transistor has to be laid out.
Lambda Rule (cont.)
Design rules based on single parameter,
Simple for the designer
Wide acceptance
Provide feature size independent way of setting out mask
If design rules are obeyed, masks will produce working
circuits
Minimum feature size is defined as 2
Used to preserve topological features on a chip
Prevents shorting, opens, contacts from slipping out of area
to be contacted
Dr. Ahmed H. Madian-VLSI 9
Dr. Ahmed H. Madian-VLSI 11
Design Rules
A set of geometrical specifications that dictate the design of
the layout masks.
It provides numerical values for minimum dimensions, line
spacing, and other geometrical quantities that are derived
from the limits of a specific processing line.
This rules must be followed to ensure functional structures
on the fabricated chip.
Poly (gate)
Poly (gate)
S
p-p
w
p
w
p
W
p
= min. width of a polysilicon
line
S
p-p
= min. poly-to-poly spacing
Dr. Ahmed H. Madian-VLSI 12
Design Rules
Classified into four main
types
Min. width to avoid breaks
Min. spacing to avoid
shorts
Min. surround
Min. extension
N+
oxide oxide
Active
contact
cut
P-substrate
S
a-ac
Poly (gate)
Poly (gate)
S
p-p
w
p
w
p
N+
oxide oxide
P-substrate
Dr. Ahmed H. Madian-VLSI 13
Design Rules
Min. extension to ensure
complete overlaps
d
po
Drain-source
short
Dr. Ahmed H. Madian-VLSI 14
Design Rules (cont.)
Most foundry allows submission of designs using
simpler set of design rules that can be easily scaled to
different processes.
These are called lambda design rules that has units
of m.
All distance and widths and spacing are written as
value = m, where m is scaling multiplier.
for ex.: w =3 , s = 4
If the factory will use technology =0.15 m
w =0.45 m, s = 0.6 m
Dr. Ahmed H. Madian-VLSI 15
Design Rules
The masking sequence was established as:
P-type substrate
nWell
Active
Poly
pSelect
nSelect
Active contact
Poly contact
Metal1
Via
Metal2
Overglass
Dr. Ahmed H. Madian-VLSI 16
DR for N-Wells
Required for pFET
S
nw-nw
W
nw-nw
P-substrate
N-Well N-Well
S
nw-nw
w
nw-nw
w
nw-nw
Dr. Ahmed H. Madian-VLSI 17
DR for Active Areas
Silicon devices are built on active areas of the
substrate
W
a
= min width of active feature
S
a-a
= min. edge-to-edge spacing of active mask polygon
Silicon substrate
FOX
Active
Active
S
a-a
W
a
Dr. Ahmed H. Madian-VLSI 18
DR for Doped silicon (n+)
W
a
= min width of an active area
s
a-n
= min. active-to-nSelect spacing
Silicon substrate
FOX
Active Active
N+ N+
w
a
S
a-n
S
a-n
Dr. Ahmed H. Madian-VLSI 19
Silicon substrate
N-well
DR for Doped silicon (P+)
W
a
= min width of an active area
s
a-p
= min. active-to-nSelect spacing
S
a-nw
= min. p+ to nWell spacing
FOX
Active
w
a
S
a-n
S
a-n
P+
P Select
S
p-nw
S
p-nw
Active
P Select
Dr. Ahmed H. Madian-VLSI 20
MOSFETs
MOSFET structure exists every time a poly gate line completely
crosses an n+ or p+ region
DRs for poly features are
W
p
= min. poly width of a poly line
d
po
= min. extension of poly beyond Active
P substrate
N+ N+
Poly L
N+ N+
w
p
N+
S
p-p
d
po
Dr. Ahmed H. Madian-VLSI 21
DR for Active contact
Active contact is a cut in the oxide that allows the first layer of
metal to contact as active n+ or p+ region.
S
a-ac
= min. spacing between active and active contact
d
ac,v
= vertical size of the contact
d
ac,h
= horizontal size of the contact
P-substrate
N+
N-well
P+
Active contact
d
ac,h
d
ac,v
S
a-ac
Dr. Ahmed H. Madian-VLSI 22
DR for Metal1
Metal1 is applied to the wafer after oxide. It is used as interconnect
for signals and also for power supply distribution.
W
m1
= min. width of Metal1 line
S
m1-ac
= min. spacing from Metal1 to Active Contact
P-substrate
N+
Metal 1
S
m1-ac
w
m1
Dr. Ahmed H. Madian-VLSI 23
DR Vias and higher level Metals
Vias is a cut in the oxide layers to contact between two
metals.
P-substrate
N+
Metal 1
Via
Metal2
Via
metal1
metal2
d
v
S
v-m2
S
v-m1
S
m2-m2
w
m2
Layout Design Rules summary
Dr. Ahmed H. Madian-VLSI 24
Layout Design Rules (cont.)
Transistor dimensions are in W/L ratio
NFETs are usually twice the width
PFETs are usually twice the width of NFETs
Holes move more slowly than electrons (must be wider to deliver same
current)
Dr. Ahmed H. Madian-VLSI
25
Layout example
Dr. Ahmed H. Madian-VLSI 26
3-input NAND
VLSI layout library
Dr. Ahmed H. Madian-VLSI
27
Layout
28
Types of Design Rules
Scalable Design Rules (e.g. SCMOS)
Based on scalable coarse grid - (lambda)
Idea: reduce value for each new process, but keep rules
the same
Key advantage: portable layout
Key disadvantage: not everything scales the same
Not used in real life
Absolute Design Rules
Based on absolute distances (e.g. 0.75m)
Tuned to a specific process (details usually proprietary)
Complex, especially for deep submicron
Layouts not portable
Dr. Ahmed H. Madian-VLSI
29
SCMOS Design Rules
Intended to be Scalable
Original rules: SCMOS
Submicron: SCMOS-SUBM
Deep Submicron: SCMOS-DEEP
Authoritative Reference: www.mosis.org
Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI 30
Contents
Wiring tracks
Latch-up
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Inductance estimation
Delay estimation
Simple RC model
Penfield-Rubenstein Model
Delay minimization techniques
Transistor sizing
Distributed drivers
Large driver
Wiring techniques
Dr. Ahmed H. Madian-VLSI 31
Wiring Tracks
A wiring track space required for a wire
4 width, 4 spacing from the neighbor=8
Transistor consumes one wiring track
4
4
4
4
Dr. Ahmed H. Madian-VLSI 32
Area Estimation
Estimate Area by Counting wiring tracks
Multiply by 8 (4Width + 4Spacing) to express in
40
32
Dr. Ahmed H. Madian-VLSI 33
Latch up
Latch up is a condition that can occur in a circuit
fabricated in a bulk CMOS technology.
N+ N+ P+ P+
V
DD
GND
N-well
P
N
P
N
V
DD
Dr. Ahmed H. Madian-VLSI 34
P-substrate
Latch up Prevention
This could be corrected by:
Include an N-well contact every time a pFET is connected to V
DD
Include an p-substrate contact every time a NFET is connected to
GND
N+ N+ P+ P+
V
DD
GND
N-well
V
DD GND
Dr. Ahmed H. Madian-VLSI 35
Its required to draw the layout of:
Inverter
4 input NAND gate
4 input NOR gate
3 input XOR gate
MUX 2X1 using pass transistor logic
according to the Design rules given in the lecture due date next
Saturday.
(use any layout tool (Microwind)submission will be soft copy and hard
copy)
Late submissions with reduction 10%.
1
st
assignment