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    S/No - Year Title Journal JSSC Data Rate Power Technolgy Architecture CDR Equalizer ADC Conclusion

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    Ashfaq Ahmed
    1. The document lists 5 research papers on high-speed serial data links from 2010 back to 2006. It provides brief summaries of the key aspects of each paper including data rates, technologies, power consumption, architectures and conclusions. 2. The papers describe demonstrations of serial links from 5Gb/s to 40Gb/s using 90nm and 65nm CMOS processes. Architectures include transmitters with FFE equalization, receivers with DFE, CDR and ADC-based designs. 3. Power consumption ranges from 98mW to 300mW. Link distances demonstrated range from 6 feet to 20 feet of cable. Error rates below 10^-12 were achieved on several links. Advanced equalization techniques were

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    S/No - Year Title Journal JSSC Data Rate Power Technolgy Architecture CDR Equalizer ADC Conclusion

    Uploaded by

    Ashfaq Ahmed
    39 views1 page
    1. The document lists 5 research papers on high-speed serial data links from 2010 back to 2006. It provides brief summaries of the key aspects of each paper including data rates, technologies, power consumption, architectures and conclusions. 2. The papers describe demonstrations of serial links from 5Gb/s to 40Gb/s using 90nm and 65nm CMOS processes. Architectures include transmitters with FFE equalization, receivers with DFE, CDR and ADC-based designs. 3. Power consumption ranges from 98mW to 300mW. Link distances demonstrated range from 6 feet to 20 feet of cable. Error rates below 10^-12 were achieved on several links. Advanced equalization techniques were

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    summary of some research papers on Tx/RX

    Original Title

    Summary 1

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    1. The document lists 5 research papers on high-speed serial data links from 2010 back to 2006. It provides brief summaries of the key aspects of each paper including data rates, technologies, power consumption, architectures and conclusions. 2. The papers describe demonstrations of serial links from 5Gb/s to 40Gb/s using 90nm and 65nm CMOS processes. Architectures include transmitters with FFE equalization, receivers with DFE, CDR and ADC-based designs. 3. Power consumption ranges from 98mW to 300mW. Link distances demonstrated range from 6 feet to 20 feet of cable. Error rates below 10^-12 were achieved on several links. Advanced equalization techniques were

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
    39 views1 page

    S/No - Year Title Journal JSSC Data Rate Power Technolgy Architecture CDR Equalizer ADC Conclusion

    Uploaded by

    Ashfaq Ahmed
    1. The document lists 5 research papers on high-speed serial data links from 2010 back to 2006. It provides brief summaries of the key aspects of each paper including data rates, technologies, power consumption, architectures and conclusions. 2. The papers describe demonstrations of serial links from 5Gb/s to 40Gb/s using 90nm and 65nm CMOS processes. Architectures include transmitters with FFE equalization, receivers with DFE, CDR and ADC-based designs. 3. Power consumption ranges from 98mW to 300mW. Link distances demonstrated range from 6 feet to 20 feet of cable. Error rates below 10^-12 were achieved on several links. Advanced equalization techniques were

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
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    Year Title Journal


    1 ##### 10+ Gb/s 90-nmCMOS Serial JSSC Data Rate Power Technolgy Architecture CDR Equalizer ADC Conclusion
    Link Demo in CBGA Package 11.7Gb/s for Tx Chip uses 1.0V and Tx,Rx 90nmCMOS using 8-tap FFE (TX), full-rate 4:1 MUX Rx clock signals are supplied externally FFE is used in Tx and Programmable Not used Link was operated with extenal clocking at 11.4 Gb/s over 6 ft
    13.3 Gb/s for Rx 1.40V Consumption is 280 NRZ signaling, consists of half rate 1:4 DEMUX with four single peaking amp is used in Rx high-bandwidth cable (20 GHz) with BER 10^-13 . At 10 ^10-13
    Tx+Tx is 11.4Gb/s mW. 2.5V EPP I/O chip area 5x5mm^2 ended o/p drivers Rx with programmable peaking PPA, consists of two buffers, peaking 10Gb/S on 20 ft lossy cable the same link works at with BER <
    Tx=182mW 550x450m^2 Rx amplifier and parallel port interface Tx,Rx and EPP and non peaking.
    Rx=98mW
    2 2006 A 10-Gb/s 5-Tap DFE/4-Tap FFE
    Transceiver in 90-nmCMOS JSSC 10 Gb/s. 300 mW 90-nmCMOS 4-tap 5-tap DFE which equalizes digital CDR loop generates the DFE summing stages, a variable gain Not used The performance of the tranciever is analysed
    Technology The power dissipation of FFE and 5-tap in-phase ( I) and quadrature ( Q) clocks used to sample the amplifier (VGA) regulates the data The links with bad reflections are more
    the receiver, including the DFE enables error are shipped fromthe PLL.T-coil is centers and edges of the data bits. swing at the slicer input difficult to equalize than those with more loss. The requirement
    DFE and CDR logic is 130 mW
    at nominal PVT
    free NRZ signaling used for compensation of the electrostatic discharge
    (ESD)diode capacitance to improve i/p return loss
    CDR logic which keeps the data and edge
    sampling clocks properly aligned to the
    incoming data bits. The CDR is able to track
    most of the reference jitter not filtered by the
    PLL
    DFE block monitors the amplitude (Amp) of
    the equalized eye by comparing it with an
    expected target.
    is to use advanced board technologies to solve the problem
    3 2008 A 40 Gb/s CMOS Serial-Link Receiver
    With Adaptive Equalization and
    Clock/Data Recovery
    JSSC 40 Gb/s, a 4 m
    cable with 10 dB
    loss at 20 GHz
    Rx: 115mW, 58 mWis
    dissipated in the equalizer
    and 57 mWin the
    CDR. Supply 1.8/1.5V
    90 nmCMOS, Area 0.54 RC-degenerated equalizing filter is used for equilization.
    CDR citcuits and Phase detectors are used in conjunction
    with Power detector circuits.
    CDR circuit consists of 5 latches and
    dissipates 57mWof Power. CDR output
    serves as the reference for the equalizer. If
    nonlinearity is caused due to extra jitter on
    the equalized data, the CDR circuit can still
    lock and provides retiming if the amount of
    jitter is within the tolerance of the CDR
    circuit.
    Not used Adaptive equalization and clock and data recovery to achieve 40 Gb/s data suffering
    from10 dB loss at 20 GHz. CDR circuits consists of 5-latchs and Phase detector.
    Power consumption and area is reduced. The receiver reproduces the data with 500
    mV output swing and 9.6 ps jitter with
    BER
    4 2009 A 4.8 GS/s 5-bit ADC-Based Receiver
    With Embedded DFE for Signal
    Equalization
    JSSC 4.8 GS/s 300 mW 0.13 mCMOS technology 1.2-
    V supply, 5-bit 4.8 GS/s SNDR
    30, Resolution bit 5
    4 time-interleaved ADCs multi-level DFE Not used 4X 4 Mux is used in multi-level DFE DFE
    relates the same reference valus as ADC so
    it shares the same digital adjustment bit
    4 slices targets 1.2 GS/s for a total
    sampling rate of 4.8 GS/s. ADC employs
    look ahead pipeline architecture
    4x time-interleaved ADC, running at 1.2 GS/s are used as a look-ahead pipeline
    architecture. A capacitor is used for pre-charging to reduces the memory effect
    errors. A stage by stage mixed signal DFE can be used to reduce to ISI. I/P capcitance
    104,FOM2.3 Effective Resolution BW 4GHz
    5 2010 A 5-Gb/s ADC-Based Feed-Forward
    CDR in 65 nmCMOS
    JSSC 5Gb/s 178.4 mW 65 nmCMOS
    Blind-sampling feed-forward CDR is
    Digital CDR consists of 2-tap FFE. FFE o/p is
    fed to Slicer and PD. Slicer represents
    2-tap FFE is used to compesate channel
    loss. ADC represents every sample A ADC base CDR architecture has been proposed to to recover data
    proposed in the work. ADC gets the Rx alongwith blind
    sampling clock. The o/p of ADC is fed to Phase detector
    and Data decision.Phase detector o/p is fed to Filter and
    data decision block. The error signal generated by
    summing phase in loop.
    signal in 1 bit. Data decision picks 1 sliced
    sample by comparing the instantaeous phase
    and average phase.
    with 5 bits.The received signal is
    sampled blindly with an ADC at twice
    the baud-ratewhich allows removing the
    phase-tracking feedback loop fromthe
    CDR to make its architecture simple.
    at Gb/s with 10db attenuation at 2.5GHz for high speed serial link.
    Summary
    Data has been taken randomly fromdifferent research papers listed serial vise
    ^2
    <10^(12)
    10^(13)

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