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Risc Reduced Instruction Set Computer

RISC processors have a reduced instruction set with simple instructions that can each complete in one clock cycle when pipelined. Key features include many general purpose registers, limited addressing modes, and an emphasis on optimizing the instruction pipeline. Advantages include uniform instruction encoding, a homogeneous register set, and support for optimizing the interaction between software and hardware. Disadvantages include potentially slower performance for complex instructions. Debate continues on whether RISC or CISC designs best support high-level languages and software optimization. Techniques like register windows and delayed branches help optimize register usage and instruction pipelining in RISC processors.

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189 views33 pages

Risc Reduced Instruction Set Computer

RISC processors have a reduced instruction set with simple instructions that can each complete in one clock cycle when pipelined. Key features include many general purpose registers, limited addressing modes, and an emphasis on optimizing the instruction pipeline. Advantages include uniform instruction encoding, a homogeneous register set, and support for optimizing the interaction between software and hardware. Disadvantages include potentially slower performance for complex instructions. Debate continues on whether RISC or CISC designs best support high-level languages and software optimization. Techniques like register windows and delayed branches help optimize register usage and instruction pipelining in RISC processors.

Uploaded by

api-26594847
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© Attribution Non-Commercial (BY-NC)
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RISC

Reduced Instruction Set Computer

Key features
Large number of general purpose registers
or use of compiler technology to optimize
register use
Limited and simple instruction set
Emphasis on optimising the instruction
pipeline
Advantages

Uniform instruction encoding


e.g. opcode always in the same bit position
Operands and result are typically held in register
Homogenous register set
Any register can be used for any operation
Simple addressing
Few data types
Can manage the synergy between software and hardware
Memory model
Disadvantages

Speed
Proprietary applications
Good for simple ones – too complex for complex
instructions
Comparison of processors
Driving force for CISC

Software costs far exceed hardware costs


Increasingly complex high level
languages
Semantic gap
Leads to:
Large instruction sets
More addressing modes
Hardware implementations of HLL statements
e.g. CASE (switch) on VAX
Intention of CISC

Ease compiler writing


Improve execution efficiency
Complex operations in microcode
Support more complex HLLs
Execution Characteristics

Operations performed
Operands used
Execution sequencing
Studies have been done based on
programs written in HLLs
Operations

Assignments
Movement of data
Conditional statements (IF, LOOP)
Sequence control
Procedure call-return is very time
consuming
Some HLL instruction lead to many
machine code operations
Operands

Mainly local scalar variables


Optimisation should concentrate on
accessing local variables
Procedure Calls

Very time consuming


Depends on number of parameters
passed
Depends on level of nesting
Most programs do not do a lot of calls
followed by lots of returns
Most variables are local
(c.f. locality of reference)
Implications

Best support is given by optimising most


used and most time consuming features
Large number of registers
Operand referencing
Careful design of pipelines
Branch prediction etc.
Simplified (reduced) instruction set
Large Register File

Software solution
Require compiler to allocate registers
Allocate based on most used variables in a
given time
Requires sophisticated program analysis
Hardware solution
Have more registers
Thus more variables will be in registers
Registers for Local Variables

Store local scalar variables in registers


Reduces memory access
Every procedure (function) call changes
locality
Parameters must be passed
Results must be returned
Variables from calling programs must be
restored
Register Windows

Only few parameters


Limited range of depth of call
Use multiple small sets of registers
Calls switch to a different set of registers
Returns switch back to a previously used
set of registers
Register Windows cont.

Three areas within a register set


Parameter registers
Local registers
Temporary registers
Temporary registers from one set overlap
parameter registers from the next
This allows parameter passing without
moving data
Overlapping Register Windows
Circular Buffer diagram
Operation of Circular Buffer

When a call is made, a current window


pointer is moved to show the currently
active register window
If all windows are in use, an interrupt is
generated and the oldest window (the
one furthest back in the call nesting) is
saved to memory
A saved window pointer indicates where
the next saved windows should restore to
Global Variables

Allocated by the compiler to memory


Inefficient for frequently accessed variables
Have a set of registers for global
variables
Compiler Based Register Optimization

Assume small number of registers (16-


32)
Optimizing use is up to compiler
HLL programs have no explicit references
to registers
usually - think about C - register int
Assign symbolic or virtual register to each
candidate variable
Map (unlimited) symbolic registers to real
registers
Symbolic registers that do not overlap
can share real registers
Graph Coloring

Given a graph of nodes and edges


Assign a color to each node
Adjacent nodes have different colors
Use minimum number of colors
Nodes are symbolic registers
Two registers that are live in the same
program fragment are joined by an edge
Try to color the graph with n colors,
where n is the number of real registers
Nodes that can not be colored are placed
in memory
Graph Coloring Approach
Why CISC (1)?

Compiler simplification?
Disputed…
Complex machine instructions harder to
exploit
Optimization more difficult
Smaller programs?
Program takes up less memory but…
Memory is now cheap
May not occupy less bits, just look shorter in
symbolic form
More instructions require longer op-codes
Register references require fewer bits
Why CISC (2)?

Faster programs?
Bias towards use of simpler instructions
More complex control unit
Microprogram control store larger
thus simple instructions take longer to
execute

It is far from clear that CISC is the


appropriate solution
RISC Characteristics

One instruction per cycle


Register to register operations
Few, simple addressing modes
Few, simple instruction formats
Hardwired design (no microcode)
Fixed instruction format
More compile time/effort
RISC v CISC

Not clear cut


Many designs borrow from both
philosophies
e.g. PowerPC and Pentium II
RISC Pipelining

Most instructions are register to register


Two phases of execution
I: Instruction fetch
E: Execute
ALU operation with register input and output
For load and store
I: Instruction fetch
E: Execute
Calculate memory address
D: Memory
Register to memory or memory to register
operation
Effects of Pipelining
Optimization of Pipelining

Delayed branch
Does not take effect until after execution of
following instruction
This following instruction is the delay slot
Normal and Delayed Branch

Address Normal Branch Delayed Branch Optimized


Delayed Branch

100 LOAD X, rA LOAD X, rA LOAD X, rA

101 ADD 1, rA ADD 1, rA JUMP 105

102 JUMP 105 JUMP 106 ADD 1, rA

103 ADD rA, rB NOOP ADD rA, rB

104 SUB rC, rB ADD rA, rB SUB rC, rB

105 STORE rA, Z SUB rC, rB STORE rA, Z

106 STORE rA, Z


Use of Delayed
Branch
Controversy

Quantitative
compare program sizes and execution speeds
Qualitative
examine issues of high level language
support and use of VLSI real estate
Problems
No pair of RISC and CISC that are directly
comparable
No definitive set of test programs
Difficult to separate hardware effects from
complier effects
Most comparisons done on “toy” rather than
production machines
Required Reading

MIPS Architecture
PA-RISC
SPARC
Power PC

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