TINA

PCB Design Manual

DesignSoft DesignSoft DesignSoft DesignSoft
www.designsoftware.com
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CREATING A PRINTED
CIRCUIT BOARD (PCB)
Once you have designed your circuit diagram you can go on and design a printed circuit
board too, for manufacturing the circuit. This very easy in TINA 7 and its later versions
since PCB design is an integral part of the program now.
Lets see the PCB design process through a few examples.
Note, the different phases of the presented design examples have been saved into the
TINAs Examples/PCB directory using the following naming conventions:
* origin.tsc original schematic file
*.tsc schematic file backannotated (after pin/gate swapping and renumbering)
* placed.tpc design parameters set, components placed pcb file
* routed.tpc net properties set and routed pcb file
* finished.tpc optionally pin/gate swapped and renumbered, routed, silkscreen adjusted,
documentation layers finalized pcb file
If you do save your results of these demo examples, be cautious not to overwrite the
install files.
1.1 Setting and checking footprint names
As a first example open the opamp2.tsc project from TINAs Examples/PCB folder.
The following schematic will appear:
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The most important thing for PCB design that every part in your schematic must have
a physical representative with exact physical size. This is realized through so called
footprints: drawings showing the outline and the pins of the parts.
The TINA Pro footprint naming uses as startpoint the IPC-SM-782A (Surface Mount
Design and Land Pattern Standard) and the JEDEC standard JESD30C (Descriptive
Designation System for Semiconductor-Device Packages, see
http://www.jedec.org/download/search/jesd30c.pdf.). However, the libraries do not
conform any given set of industry or manufacturer standards, because standards have
difficulty keeping up to date, as technology grow up faster than the standards.
Generally, standards mirror a fixed set of data at a point in time, while the new
manufacturing capabilities yield new footprints.
In TINA default footprint names are already assigned to all parts, which represent real
components.
Note that some parts used for theoretical investigations, for example controlled sources
do not represent real physical parts so you cannot place them on a PCB. If your design
contains such components you should substitute them with real physical parts.
Of course there is no guarantee that the default physical representatives of the parts are
the same as needed by your design.
There are two ways to check this.
1) You can use TINAs Footprint name editor which you can invoke from the
Tools menu of TINA. In this dialog you see all TINA components and the
corresponding footprint names.
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Clicking on the footprint name fields you can select from the available footprint names.
In the dialog the components without a footprint name association will be denoted by
red characters and also a ??? in the footprint name field.
2) Alternatively you can double-click on each part and check the Footprint Name of
the appearing component property dialog.
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You can also click the button in the Footprint Name line and see the PCB
information dialog where you can select from the available footprint names on the
Footprint list and also see the 3D view of the different parts on the 3D package view
field of the dialog.
If you find the footprint name you want on the list, click on it and press OK, you will
return to the component property dialog with the selected footprint name in the
Footprint name line. To confirm the change press OK on the component property
dialog again.
If you do not find footprint name you want you can also add a new footprint using the
Add buttons of the PCB information dialog. Note that in such a case it is not enough
to add a footprint name in this dialog, you should also add the corresponding footprint
to TINAs catalog. The details of this are described in chapter 6 - Making your own
schematic symbols and footprints - of the Quick Start Manual.
When everything looks good you can make a final check by clicking 2D/3D view
button or simply pressing F6. The 3D view of those components will appear
which have already a physical representative.
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1.2 Invoking TINA PCB
Now if you find the physical part association satisfactory we can go ahead to the PCB
layout design. To do this simply press the button on TINAs toolbar (the last on
the right) or select the PCB Design command on the Tools menu. Do the following
setting.
Select Start New Project, Autoplacement and Use board template. With the
Browse button find and select the 2layer_A.tpt template files from the Template folder
of TINA. Using this file will make sure of the proper setting for a double-sided PCB.
If you use template, you set the level of manufacturing complexity. The following three
levels of manufacturing technology are defined by the IPC-2221 generic standard.
Level A : General Design Complexity
Level B : Moderate Design Complexity
Level C : High Design Complexity
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The template file specifies the number of layers, including their properties, system grid
size, autorouter settings, spacing and track width. The following templates are included
with PCB Designer:
Level Routing
Layers
Plane
Layers
Routing Spacing
1layer_A.tpt A 1 - 25 12 1/2
2layer_A.tpt A 2 - 25 12
Allows one track between
standard DIP IC pin
2layer_B.tpt B 2 - 8 1/3 8 1/3
2layer_B_mm.tpt B 2 - 0.1 0.2
Use for SMT or mixed-technoly
board
4layer_C_mm.tpt C 2 2 0.1 0.15 For moderate and high density
SMT boards
You can choose PCB template based on technology, density and package pitch.
Finally you can set the size of the PCB board in inches or mm depending on the
measurement unit settings in the View/Options dialog of TINA.
When everything is set properly press the OK button and the PCB layout design will
appear with all the components automatically placed on the PCB board.
Now click a drag the parts to the position as shown on the figure below. (Find
opamp2 placed.tpc to check your results.)
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Press F4 for Net Editor to set nets routing width. First, click on Modify all and enter
12.5 into Track width field. Then select power nets (Ground, VCC, -VCC) and set
their width to 25mil.
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To automatically route the components press the F5 button or select Autoroute
board command from the Tools menu. The following screen will appear:
To see of everything is route correctly press F7 or select DRC (Design Rule Check)
from the Tools menu. The following message will appear:
To finish our first simple design lets add a text onto the silkscreen/assembly layer. To
do this click the T button on the toolbar. The following message will appear:
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Enter the text into the empty upper field and press the OK button. The text will be
attached to the cursor. Move it to the place shown on the picture below and press the
left mouse button to place.
Finally you can also check your design in full 3D. To do this press F3 or select 3D View
from the View menu. After some calculation the following window will appear.
You can rotate this 3D model into any direction by clicking with the mouse at any
point and then hold down the left button and move the mouse. You can also move
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the camera forward or backward and so see the whole design or just a part of it but
in more details, by holding down the right mouse button.
After this you can either print your design or create a Gerber file for a manufacturer.
To print use Print from File menu.
To obtain Gerber files to direct a photoplotter, choose Export Gerber file from File
menu. (Gerber option can be changed through Gerber output setting under Options
menu.)
1.3 Advanced editing functions of TINA PCBs Layout editor
In practice you may need more editing which you can do with TINA PCBs advanced
editing features. This is described through examples in the next section.
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CREATING TWO-LAYER,
DOUBLE-SIDED, SURFACE-
MOUNT TECHNOLOGY
BOARD
To go into the further details, as a second example open the PIC flasher origin.TSC
project from TINAs Examples/PCB folder. The following schematic will appear if you
press down 2D/3D View button in the toolbar:
The schematic is PCB-ready, - as you can easily check by pressing the 2D/3D button, -
every part has physical representation from the surface mount devices (SMD). Now,
before we start the PCB wizard, click Tools/Footprint Name Editor to check the
footprints list.
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Since all the components have their footprint name, we can go on with the Tools/PCB
Wizard menu point. Set the Start new project, check Autoplacement and the
Use board template browsing 2layer_B_mm.tpt. Enter 40mm length and 30mm
width. The values should be estimated by the size of the used components. Moreover,
it is important to provide enough space between the components allowing for the
placement of vias and tracks during routing.
Press the OK button, ignore the Electric Rule Check warning and finally save board as
PIC flasher.tpc.
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The components are placed in the closest distance to minimize the connections lengths
following similar topology to that of the schematic, while not to violate the design rule
settings. However, the result is convenient for autorouting, it often occurs that designer
has to change the component layout to satisfy electrical, mechanical and other
characteristics. Lets consider the mechanical effect of a power or a signal input/output
connector, or the length of a track from the signal source to the load in high-speed
digital system to avoid reflection, or in analog case to reduce noise level and so on.
These cases influence the components position and could be critical not in the complex
designs, but even in the simplest ones. Moreover, the component layout has other
practical viewpoints as to the assembly process and an esthetical also to improve
maintainability, servicing.
Because of the above, to find the final position of the components needs manual
placing in many cases in general, even though the autoplacement could be effective.
Our circuit, although it is small and low in density, has such requirements, namely to
put the crystal closer to the microcontroller, position the power supply connector and
adjust the LEDs along the board.
If you want to change the board size, click Draw/modify shapes button . Now,
lets try it and make the board now smaller. You can double click on the middle of the
board and enter the following values into the fields:
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When you press OK, the board outline is shrinking.
Now, before we start the routing, lets set the position of the components; place the
power connector, DIP switch on the left hand side and the LED bar onto the right
hand side. Place the capacitors and resistor networks on the bottom side by double
clicking on the components and choose Bottom Placement side on the dialog.
Compare your result to the file \Examples\PCB\PIC flasher placed.tpc.
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In order to decrease route length, swap R1 pins connected to SW1. Pin swapping is
allowable if identically functioning pins are to be exchanged, such as pins of resistors,
capacitors, etc. Click on Pinswap button on the toolbar to pick up tool, then pad 1
of R1 (the upper right), finally pad 4 of that. The following window should come up:
Press the Yes button, then do the same with R1 pad 2,3 and R2 pad 3,4.
Note, pinswap changes the original connections, that is why we have to and we will
update the original schematic later in order that corresponds to the board with any
changes we made to the board while it was in PCB Designer. This process, the
backannotation, has to be always accomplished when pin/gate swap and/or component
renaming have been performed before.
To which direction tracks should travel during the autorouting can be determined by
the user through the Autorouter settings. Now, click Options/Autorouter settings, to
set our preferred direction by choosing an integer number from 1 to 9. Choosing 1
forces the router very much to use horizontal lines on that layer, while 9 forces it to use
vertical lines. 5 means no horizontal and no vertical preference on the given layer.
Choosing the extreme values (1 and 9 for a pair) is usually too strict, so we now enter 3
for the top layer and 7 for the bottom.
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Also on this panel, check Force router to use short side SMD pad entry with pad
number 9 constraining the router to connect SMD pads on their short side if the
component has at least 9 pins. This option could be very useful to preserve the gaps
between SMD pads for tracks routing. Now as a result, the R1, R2 and SW1 are allowed
to route freely, as half of the pins connected together, while U1 pads connects on short
side.
After these moves, press Ctrl+F5 to route PCB automatically. You can follow how the
autorouter forms the electrical connection between the components at the whole area;
first, the power and ground nets are to be connected, then signal routing comes. If
necessary, the program rip-up and reroute the unconnected nets. The following result
will appear:
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You can notice that there is a net left unconnected. (Here, we note that you might use a
more recent version of PCB Designer. Your program could have improvements since
this documentation was issued and thus, you may not encounter unconnected wires in
this and further examples.) To examining the exact state of the design, run DRC by
pressing F7 to test the integrity of your board. The DRC Results window will come up
highlighting the corresponding nets.
Now, violations should be browsed and corrected. If we double click on the text
Unrouted net N00013 then the program magnifies and highlights the selected net
maintaining the position of the objects in the center point.
In order to have the board fully routed we either use the manual route modes of the
program to make space for the unconnected tracks or do similar, delete crossing tracks
then reroute them in another order.
In manual route feature allows you to direct routing wherever necessary. You can move
existing segments of tracks, remove segments, or create new segments. Let's use
autorouting to get the new track in. Lets proceed step by step.
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First, press the XXX, the select button on the toolbar then hold down Shift key and
click the track connects U1 pad 9 to D5 (see picture below), then press Delete key to
remove the track. This makes room for the unconneted net.
Now, press F4 for the net editor and disable N00012, the previously removed
connection. This will prevent the autorouter from reconnecting the net. Leave N00013
routing enabled.
Click OK and press F5 for autorouting and the autorouter connects all the enabled
nets. Now, enable N00012 too, by pressing F4, checking RE, then click OK and
autoroute (F5).
Now, press F7 to perform DRC to check if no errors left.
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Now, lets synchronize the PCB and schematic files. First, choose Export Tina
backannotation file from the File menu to save the changes into PIC flasher origin.ban.
Then, start TINA Pro and click Backannotate under the Tools menu and select the
same file you have just saved. Click OK, the TINA reads and update the original
schematic.
Take a close look at the resistor networks; the pin order reflects the result of the
pinswap.
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You can double click R1 and press in the Footprint Name field to reach PCB
information dialog. On the right side, the swapped nodes will be emerged. Save this file
as PIC flasher.TSC.
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CREATING PCB
COMPONENTS
Now, lets see how to create additional PCB component for our own use. We place an
LM78L05ACM (plastic SO-8 package) voltage regulator on the schematic to make the
circuit +12V powerable. If we do not want to simulate the circuit, TINA gives specific
tool to create PCB symbol. So, click PCB Component Wizard in the Tools menu and
enter the name of the component in the Name field.
Click the button to choose the component Shape from the library. Enter a few
letters from macro shape name: <VoltageReg>, then click OK.
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If you do not find appropriate macro shape for the new components use the Design
Suite Schematic Symbol Editor.
Now, choose the REG icon from the Icon drop down list.
To access a new PCB component in TINA, we should add it to one of component
groups. This time, for the clarity you can define a new group for our component, called
PIC flasher, then press the OK button.
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Finally, you may save the new PCB component macro into the Macrolib folder.
Replace the short circuit between Vcc and +5V with the new component on the
schematic diagram and double-click on the schematic symbol of the regulator. Give the
PCB information:
1. click in the Footprint Name edit line on the button
2. click the Add button on the Component list area and type LM78L05ACM and then
press OK
3. click the Add button on the Footprint list area and choose SO8 from the SMDIC
category
4. build the node list with the help of the component data sheet
(http://www.national.com/ds.cgi/LM/LM78L05.pdf) : click Add, then select OUT
from the Change Node List and press OK. Repeat these steps until all of the pins
are covered and finally click OK.
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Now, we fulfilled every condition to have a PCB-ready component. After all, if you
demand to know whether modifications are done well, you can open PIC flasher
reg.TSC and check it.
As the electric type of U3 pin OUT is defined out and connected to power of U1 and
U2, you will run ERC error when you call PCB Wizard or perform ERC. But this time,
knowing our case we can freely ignore it.
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CREATING 4 LAYER PCB
LAYOUT
This chapter will give you an introduction in designing an entire 4 layers circuit board
from the start to the end with a medium size circuit card. It will demonstrate the major
concepts and introduce the settings, technics and tools behind completing a PCB
design emphasizing the main movements which differs from the previous, single and
double layers designs. Many phases of the example can be found in the
\Examples\PCB directory, such as
Schematic files
FPGA origin.tsc original schematic file
FPGA.tsc schematic file (backannotated, after renumbering)
PCB files
FPGA placed.tpc design parameters set, components placed
FPGA placed split.tpc as above with power plane splitting
FPGA Spartan power routed.tpc net properties set and Spartan FPGA chip power routed
FPGA Spartan power routed split.tpc as above with power plane splitting
FPGA all power routed.tpc power routed
FPGA all power routed split.tpc as above with power plane splitting
FPGA routed.tpc all connections routed
FPGA finished.tpc optionally pin/gate swapped and renumbered, routed,
silkscreen adjusted, documentation layers finalized pcb
file
The block diagram of the circuit we will design is shown in the figure below. The main
component is a field programmable gate array (FPGA) from Xilinx, Inc. In this circuit,
we will use the FPGA with few pushbuttons/switches as inputs and LEDs as outputs.
A lot of the FPGA IO pin can be used freely for general purposes on the J1 connector.
Additionaly, the board contains a power connector for an external 5-volt suply, a
programming interface for the FPGA, and some miscellaneous resistors and capacitors.
Xilinx
XC2S50
Spartan-2
FPGA
XCF01S 1Mbit
Configuration PROM
JTAG Header
Slide switches
Power on LED
8 LEDs
DONE LED
Exapansion headers
DIP switches
Mode select jumpers
2 pushbuttons
50MHz oscillator
2.5V regulator
3.3V regulator
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For the complete circuit digram, open FPGA origin.TSC. (The backannoteted version
saved as FPGA.tsc.) All the footprints are named, the schematic is ready-to-use for
layout design. Just click on the PCB Wizard set Start new project, check
Autoplacement, use board template 4layer_C_mm.tpt, because the used components
physical dimensions are defined in metric system. For the best performance, taking the
smallest pitch size (0.5mm) as reference, we set the Grid size parameter to 0.1mm
which will be applied as a visible, placing and routing grid.
Finally enter width 110mm and height 60mm, then click OK.
After exporting the netlist from TINA, you can check few parameters in PCB editor.
First, select Option/System setting. Make sure that PACKAGE.FPL is checked.
5.1 Placing parts
Just to make the screen a little easier to look at, let us turn off a few layers at this point.
Select Option/Layer Settings and press Uncheck All and check Assembly Drawing Top
and Bottom layers.
You are now ready to place parts on your design. To get into parts placement mode,
make sure that the Select/Move components/tracks tool is selected. A good start to
place the non-electrical components on our board, the mounting holes in each corner
of the board.
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Note, every non-electrical component (mounting hole, rubber foot, enclosure, )
symbol has to be placed onto the TINA schematic before making netlist. In the case
when no footprint should be placed on the board (e.g. rubber foot) then the componet
has NOPCB footprint name in TINA schematic.
Now, place the mounting holes at every corner of the board.
Since we dont want to accidentally move the part, so right click, select Component
Properties and check the box labeled Lock component.
Now, you can begin to place the rest of your components. You will probably want to
print out your schematics so that you can see where the components are supposed to
go in relation to each other. When you pick up a component, the airwire for that
component will appear to show you the connections to other parts.
When placing components, you may want to work on coarser grid. Right now, the grid
is set at 0.1 mm. You can change this by selecting Options/System Settings and then
changing the Grid setting.
Start placing the remaining components on your board. Start with placing the power
connector and voltage regulators on the right side of the board, provide enough room
for the power dissipating copper area. Place the FPGA in the left center with the 40
pins connector above, and LEDs, switches on the below. Try to keep components that
belong together near each other.
Put the buffer and filter capacitors of the FPGA and flash memory on the bottom side
of the board as close as possible to power pins of the chip; the smaller ones right under
the leads, the bigger ones around the middle of the package.
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To place them to the opposite, just do a right click on the components, choose
Component properties and select bottom placement side.
When you are done, your board should look something like this.
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The silkscreen is a bit messy, but we will deal with that later. In fact, during routing, the
silkscreen can get in the way, so you may turn off the silkscreen and assembly layers
now using the same method you used before for the other layers.
Now, you may save your design as FPGA placed.tpc.
5.2 Draw copper areas for voltage regulators
(Go on with your own created file or open FPGA placed.tpc in the
\EXAMPLES\PCB directory.)
Copper areas can be used for noise suppression, shielding, to draw heat away from
components that tend to get hot, to isolate signals, or to provide small voltage planes.
Now, to enhance the maximum power dissipation of the voltage regulator circuits
(U4,5), we draw a 15 by 15mm area of copper on the top to widen the regulator
heatsink surface.
Choose Add Cooper pour icon from the toolbar then click on the left up corner,
drag the mouse towards the right down corner and finally make a left button click.
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When you double click the area, you can enter the parameters exactly. Do not forget to
check the shape type and select Assigned net 2.5V. Normally, copper pour voids where
there are tracks or pads except for the Assigned net. (See Options/Design Parameters.)
The other shape type is the copper fill area which is solid.
At last, click on the copper pour, hold down the left mouse button and position the
rectangular to overlap the heatsink expanding leftward.
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Finally, repeat these operations for the other voltage regulator and save your design.
Note, you can find this state of the design if you open \Examples\PCB\FPGA
placed.TSC.
5.3 Assign and routing Ground and Power
In any design, it is usually wise to route all power and ground connections before doing
anything else. On a thru-hole technology board, this is very easy because connections
can be made to the solid plane as the pins pass through the board. On a SMT board,
for power and ground pads need to be routed by via to the plane using thermal releif.
Usual procedure, that the designer enables the power and ground nets for routing,
while disabling all the other signals for routing. After routing power and ground nets,
he/she must disable them and enable all other signals for routing. Then he/she can
route the remaining signals.
But first of all, we need to set up our design so that PCB editor knows that the two
planes are associated with nets. (Plane layers are typically used for power and ground.)
To achive this, the most convenient way is to label a wire of the net (as we did) in
TINA schematic editor which should be assigned to the plane layers. We have already
placed such labels in FPGA.TSC at the output of the power regulators. (See FPGA
origin.TSC at X:485, Y:880; X:440, Y:930) The GND label will inform TINA PCB that
the solid plane on layer 2 (Ground) is designated to the net, while PWR tag designates
layer 3 (Power).
You can see and you can do the same thing for other nets by double clicking on the
wire and modify the ID in TINA schematic.
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Note, only GND and PWR IDs have special effect on the plane layer allocation; other
net names are just for clearity to help you with recognizing the giving nets in the PCB
editor, eg. 2.5V in this design. It is always advisable to name the significant nets for
referencing to the later operation in PCB editor.
Now, open the Net Editor and check the result.
You can attach any nets to any plane layer in PCB editor also, but it is easier to do this
in TINA schematic as described.
To view plane layers, click Cancel to Net Editor and choose Option/Layer settings,
press Uncheck All and check Ground. The thru-holes are already connected by thermal
reliefs.
You can now see all of the connections to the ground plane. You can do the same thing
for the power plane: Option/Layer settings, uncheck Ground and check Power.
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But so far, we have only just the trou-holes power and ground connections routed. On
surface mount technology board, we should fanout
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the board with only the
power/ground net enabled. In the Net Editor (F4) press Modify All button to
uncheck Enable autorouting.
Then select the ground and power nets to create group POWER, simply type in the
Group field. Enter 0.4mm to Track width and check Enable autorouting with via type
PWRVIA.
At last, Net Editor should look like as follows.
As we have two plane layers and still have one more voltage net to route, - that is the
2.5V voltage goes from the U4 to the FPGA core, - we need dedicate trace. This net
touches only a few pins, so we could just put a trace to connect all the components. So,
click Draw tracks tool to route 2.5V under the Xilinx chip package onto the bottom
side.

1
Fanout is the process of routing a SMD pad to a via so that the pad can be routed on other layers. For power and ground pads, the fanout is
attached to a power or ground plane using a thermal relief.
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Connect all the power pins of FPGA then those of filter ands buffer capacitors set
track width 0.4mm, then make the power track 2mm width as shown below by double
click onto the track.
Now, route all the nets from the POWER net group. When you are manually routing
you can begin/end a new track on another track of the same net, which is know as T-
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routing. After all that press F7 to run DRC. You cannot see any unrouted net belongs
to the group. (See FPGA power routed.tpc as reference.)
5.4 Finishing the routing and post processing
At the start, disable the route of the POWER net group and enable the other signals.
Set the autorouter in the Options/Autorouter settings as follows.
Check the settings under Options/Design Parameters.
Press F5 to autoroute the whole board, then renumber components (Tools/Renumber
components, F10). Renumbering begins at the upper left of the board, renames
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components in a sweep from left to right, then moves down and renames in successive
sweeps.
After renumbering, backannotate design as much as chapter 4.8. You may save the new
schematic, as a result see FPGA.TSC as reference.
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CREATING SPLIT PLANE
LAYERS
Power layers are especially used to provide electrical power reference and stable ground
throughout the board. In multi power supplied system, the power planes, which are
tipically solid copper internal layers, are used to split. When you split the plane, you
assign a part of a plane layer to a second net (e.g.: processor core voltage) by placing a
copper pour onto a plane layer. You assign a primary net to the whole plane layer as we
did by the GND and PWR IDs in TINA Pro, and a secondary net to the copper pour.
Now, lets see how it works within TINA PCB. Open the FPGA placed.tpc as a
startpoint to our work. Remember that the PWR net the 3.3V primary supply voltage,
- has already been assigned to the plane layer Power. Now, you split a portion of that
plane for the FPGA core voltage (2.5V) instead of routing a net from U4.
First, it is important to select the power layer, then click the Draw/modify shapes
and Add copper pour area buttons. The cursor turns into cross shape. You can
begin to draw the outline of the copper pour. The shape must extend under the
regulator heatsink and the middle of the Xilinx chip package to connect them through
vias. Using the appropriate zoom factor (e.g.: 200-400%) during the drawing is a
suggestion.
When you are done splitting, your design may look something like this. (Find this phase
of the project in the file /Examples/PCB/FPGA placed split.tpc.)
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Plane layers are negative layers, so you can only see the isolation on the screen.
Before beginning other tasks, you should assign the 2.5V net to the splitted area.
Double click onto the shape then select 2.5V net and click OK.
Note, if you create nested copper pours on a plane player, which overlap themselves,
specify the plane layer priority. The higher the priority number, the higher the copper
pour sits above the lower ones owning the overlapping region.
Now, if you connect all the power connection you will get similar result than FPGA all
power routed split.tpc shown below. The PCB Designer automatically places thermal
relieved through-hole pins and vias whenever appropriate.
The rest of the process and the movements are similar to those which we applied in the
case with the unpartitioned plane layers.