1

VHDL
Memory Models
EL 310
Erkay Sava!
Sabanc University
2
ROM
library ieee;
use ieee.std_logic_1164.all;
entity rom16x8 is
port(address: in integer range 0 to 15;
data: out std_ulogic_vector(7 downto 0));
end entity;
architecture sevenseg of rom16x8 is
type rom_array is array (0 to 15) of std_ulogic_vector (7
downto 0);
constant rom: rom_array := ( 11111011, 00010010,
10011011, 10010011, 01011011, 00111010,
11111011, 00010010, 10100011, 10011010,
01111011, 00010010, 10101001, 00110110,
11011011, 01010010);
begin
data <= rom(address);
end architecture;
3
Static RAM
Static RAM
2
n
word of
m bits
n
m
CS
OE
WE
Address
Data input/output
CS - when asserted low, memory read and write operations are possible.
OE - when asserted low, memory output is enabled onto an external bus
WE - when asserted low, memory can be written
4
A Cell of Static RAM
The RAM contains address decoders and a memory
array.
A cell of RAM that stores one bit of data
D
G
Q
data_out
data_in
SEL
WR
Read mode: SEL = 0 and WR = 1, (G=0) and data_out = Q
Write mode: SEL = 0 and WR = 0, (G=1) and Q = data_in
When SEL = 1 or WR = 1, the data is stored in the latch
When SEL = 1, data_out = Z
5
Truth Table of Static RAM
data_in write L X L
data_out read H L L
high-Z output
disabled
H H L
high-Z not
selected
X X H
I/O pins Mode WE OE CS
6
6116 Static CMOS RAM
Memory Matrix
128 x 128
Row
Decoder
Column I/O
Column Decoder
input
data
control
A
10
A
4
A
3
A
2
A
1
A
0
I/O
7
I/O
0
OE
WE
CS
7
Read Cycle Timing I
t
RC
Adress
dout previous data valid
data valid
t
OH
t
AA
t
OH
CS = 0, OE = 0 WE = 1
After the address changes, the old data remains at the
output for a time t
OH
Then there is a transition period during which the data
may change (cross-hatching section)
The new data is stable at the memory after the address access
time t
AA
The address must be stable for the read cycle time, t
RC
8
Read Cycle Timing II
CS
dout
data valid
t
CLZ
t
ACS
t
CHZ
Address is stable, OE = 0, WE = 1
9
WE Controlled Write Cycle Time (OE =0).
address
CS
t
WC
CS goes low before or at the same time as WE goes low
WE goes high before or at the same time as CS goes high
t
CW
t
WR
WE
t
AS
t
WP
t
AW
dout
t
WHZ
t
OW
din
t
DW
valid data
t
DH
10
CS controlled write cycle time (OE =0).
Adress
CS
t
WC
WE goes low before or at the same time as CS goes low
CS goes high before or at the same time as WE goes high
t
CW
t
WR
WE
t
AS
t
AW
dout
din
t
DW
new data
t
DH
high - Z
old data or high-Z
11
Writing to the Memory
In both CS and WE controlled write cycles,
writing to memory occurs when both CS and
WE are low,
writing is completed when either one of these
signals goes high.
12
Timing Specifications for CMOS SRAM
43258A-25 61162-2 Symbol Parameter
- 3 - 10 t
OH
Output hold from address change
10 3 40 10 t
OHZ
Chip disable to output in high-Z
10 3 40 10 t
CHZ
Chip de-selection to output in
high-Z
- 0 - 10 t
OLZ
Output enable to output in low-Z
12 - 80 - t
OE
Output enable to output valid
- 3 - 10 t
CLZ
Chip selection to output in low-Z
25 - 120 - t
ACS
Chip Select Access Time
25 - 120 - t
AA
Address Access Time
- 25 - 120 t
RC
Read Cycle Time
max min max min
13
Timing Specifications for CMOS SRAM
- 0 - 0 t
DH
Data hold from end of write
43258A-25 61162-2 Symbol Parameter
- 0 - 10 t
OW
Output active from end of write
- 12 - 35 t
DW
Data valid to end of write
10 3 35 10 t
WHZ
Write enable to output in high-Z
- 0 - 0 t
WR
Write recovery time
- 15 - 70 t
WP
Write pulse width
- 0 - 0 t
AS
Address setup time
- 15 - 105 t
AW
Address valid to end of write
- 15 - 70 t
CW
Chip selection to end of write
- 25 - 120 t
WC
Write Cycle Time
max min max min
14
Simple Memory Model
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ram6116 is
port(address: in unsigned(7 downto 0);
data: inout std_logic_vector(7 downto 0);
WE_b, CS_b, OE_b: in std_ulogic);
end entity ram6116;
15
Simple Memory Model
architecture simple_ram of ram6116 is
type ram_type is array (0 to 2**8-1) of
std_logic_vector(7 downto 0);
signal ram1: ram_type:= (others => (others => 0));
begin
process
begin
data <= (others => Z); -- chip is not selected
if (CS_b = 0) then
if rising_edge(WE_b) then -- write
ram1(conv_integer(addressdelayed)) <= data;
wait for 0 ns;
end if;
if WE_b = 1 and OE_b = 0 then -- read
data <= ram1(conv_integer(address));
else
data <= (others => Z);
end if;
end if;
wait on WE_b, CS_b, OE_b, address;
end process; end simple_ram;
16
Synthesizeable Memory Model
architecture simple_ram of ram6116 is
type ram_type is array (0 to 2**8) of
std_logic_vector(7 downto 0);
signal ram1: ram_type;
begin
process (address, CS_b, WE_b, OE_b) is
begin
data <= (others => Z); -- chip is not selected
if (CS_b = 0) then
if WE_b = 0 then -- write
ram1(conv_integer(address)) <= data;
end if;
if WE_b = 1 and OE_b = 0 then -- read
data <= ram1(conv_integer(address));
else
data <= (others => Z);
end if;
end if;
end process;
end simple_ram;
17
Timing Model for SRAM I
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ram6116 is
generic (constant t_AA: Time := 120 ns;
constant t_ACS: Time := 120 ns;
constant t_CLZ: Time := 10 ns;
constant t_CHZ: Time := 10 ns;
constant t_OH: Time := 10 ns;
constant t_WC: Time := 120 ns;
constant t_AW: Time := 105 ns;
constant t_WP: Time := 70 ns;
constant t_WHZ: Time := 35 ns;
constant t_DW: Time := 35 ns;
constant t_DH: Time := 0 ns;
constant t_OW: Time := 10 ns);
port(address: in unsigned(7 downto 0);
data: inout std_logic_vector(7 downto 0);
WE_b, CS_b, OE_b: in std_ulogic);
end entity ram6116;
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Timing Model for SRAM II
architecture SRAM of ram6116 is
type ram_type is array(0 to 2**8) of std_logic_vector(7 downto 0);
signal ram1: ram_type := (others => (others => 0));
begin
ram: process
begin
if (rising_edge(WE_b) and CS_bdelayed = 0)
or (rising_edge(CS_b) and WE_bdelayed = 0) then
-- write
ram1(conv_integer(addressdelayed)) <= datadelayed;
-- datadelayed is the value of data just before the falling_edge
data <= transport datadelayed after t_OW;
end if;
if (falling_edge(WE_b) and CS_b = 0) then
- enter write mode
data <= transport ZZZZZZZZ after t_WHZ;
end if;
19
Timing Model for SRAM III
architecture SRAM of ram6116 is
...
begin
ram: process
begin
...
if CS_bevent and OE_b = 0 then
if CS_b = 1 then -- RAM is de-selected
data <= transport ZZZZZZZZ after t_CHZ;
elsif WE_b = 1 then - read
data <= XXXXXXXX after t_CLZ;
data <= transport ram1((conv_integer(address)) after t_ACS;
end if;
end if;
if addressevent and CS_b = 0 and OE_b = 0 and WE_b = 1
then
data <= XXXXXXXX after t_OH;
data <= transport ram1(conv_integer(address)) after t_AA;
end if;
wait on CS_b, WE_b, address;
end process RAM;
...
20
Timing Model for SRAM IV
architecture SRAM of ram6116 is
...
begin
...
check: process
begin
if CS_bdelayed = 0 and NOW /= 0 ns then
if addressevent then
assert (addressdelayedstable(t_WC)) - t_RC = t_WC
report address cycle is too short
severity WARNING;
end if;
...
21
Timing Model for SRAM V
architecture SRAM of ram6116 is
...
begin
...
check: process
begin
if CS_bdelayed = 0 and NOW /= 0 ns then
...
if rising_edge(WE_b) then
assert (addressdelayedstable(t_AW))
report address not long enough to end of write
severity WARNING;
assert (WE_bdelayedstable(t_WP))
report write pulse is too short severity WARNING;
assert (datadelayedstable(t_DW))
report data setup time is too short severity WARNING;
wait for t_DH;
assert (datalast_event >= t_DH)
report data hold time is too short severity WARNING;
end if;
end if;
wait on WE_b, address, CS_b;
end process check;
end architecture sram;
22
Dynamic RAM
library ieee;
use ieee.std_logic_1164.all;
entity dram1024 is
port(address: in integer range 0 to 2**5-1;
data: inout std_ulogic_vector(7 downto 0);
RAS, CAS, WE: in std_ulogic);
end entity;
23
Dynamic RAM
architecture beh of dram1024 is
begin
p0: process(RAS, CAS, WE) is
type dram_array is array (0 to 2**10-1) of
std_ulogic_vector (7 downto 0);
variable row_address: integer range 0 to 2**5-1;
variable mem_address: integer range 0 to 2**10-1;
variable mem: dram_array;
begin
...
end process p0;
end architecture;
24
Dynamic RAM
architecture beh of dram1024 is
begin
p0: process(RAS, CAS, WE) is
begin
data <= (others => Z);
if falling_edge(RAS) then row_address := address;
elsif falling_edge(CAS) then
mem_address := row_address*2**5 + address;
if RAS = 0 and WE = 0 then
mem(mem_address) := data;
end if;
if CAS = 0 and RAS = 0 and WE = 1 then
data <= mem(mem_address);
end if;
end process p0;
end architecture;