1

CHAPTER 1
INTRODUCTION
1.1 GENERAL
Recently developed needs of domestic policy goals, Global impact, energy
independence, developing nation and climate changing factors which motivate us to
embrace new technology of electric and hybrid electric vehicle (EV or HEV). These
hybrid electric vehicles (HEVs) and electric vehicles (EVs) are gaining increased
attention due to their higher efficiencies and lower emissions. Both Hybrid Electric
Vehicles (HEVs) and Electric Vehicles (EVs) need a traction motor and a power
inverter to drive the traction motor. The requirements for the power inverter include
high peak power, optimum consumption of energy, low output harmonics and
inexpensive circuit. These inverter constitute from basic conventional 3 level inverter
to upgraded inverters. Among them multilevel inverter have great influence and the
concept of multilevel inverter has been introduced since 1975.
Advantages of multilevel inverter for traction drive in EVs:
1) They are suitable for large VA-rated motor drives, and traditional 230
V or 460 V motors can be used.
2) Higher efficiency is expected for these multilevel converter systems
because higher voltages can be utilized and the switching frequency of the
devices is at a minimum.
3) Low voltage switching devices can be used.
4) No electromagnetic interference (EMI) problem or common-mode
voltage/current problem exists.
5) No charge unbalance problem during charge mode or drive mode
Development of the electric drive trains for these large vehicles will result in
increased fuel efficiency, lower emissions, and likely better vehicle performance
2

(acceleration and braking). One of the important issues in the mentioned machines is
optimum consumption of energy. For this reason, power consumption of driving
circuits of machines driving inverter should be reduced. On the other hand, when
inverter switches sustain high voltage, their switching frequency is restricted. In this
state, the output waveform of inverter is distorted and the reliability of the motor is
reduced. Therefore, in order to over-come to the problem, voltage of switches must be
decreased.
Subsequently several multi level inverter topologies have been developed
such as diode clamped or neutral clamped multilevel inverter, flying capacitor multi
level inverter, generalized multilevel inverter, reversing voltage multi level inverter,
modular multilevel inverter, generalized multilevel current source inverter, cascaded
H bridge multi level inverters etc. There are several methods to reduce the device
voltage. One of them is dc-dc converters, which divides the voltage by the capacitors
connected in series . For instance, in this method, when three capacitors are connected
in series, the voltage of each capacitor becomes one third. The other method to reduce
the device voltage is cascade H-bridge (CHB) inverter, which increase the number of
output voltage levels by increasing the number of H-bridges. In this method, when the
number of output voltage levels is increased, the number of switches is also increased.
Therefore, in two mentioned methods, increase of the number of output voltage levels
makes both multilevel inverter and converter more complicated. Another method to
reduce the voltage stress on the switching device that proposed recently is a multi-
level inverter that uses dc voltage sources by switching them in series and in parallel .
In this paper, a new structure of multilevel inverter with reduced number of
switches for electric vehicle applications is proposed. The proposed structure has been
reduced the size and power consumption in the driving circuits. The same number of
voltage sources is needed to output the same number of voltage levels compared to the
conventional CHB inverters. Since, output voltage waveforms of inverter which are
produced by switching the dc voltage sources in series by this conversion, the voltage
of switches are decreased. Therefore, switching frequency is not restricted. Then, this
inverter is best choice to use in high speed switching devices such as traction motor
3

drives. The harmonics of the output voltage waveforms are also reduced. Capacitors,
batteries, and other dc voltage sources can be used as the voltage sources of the
proposed multilevel inverter.
Basically cascaded multilevel inverter are nothing but the series combination of
several single phase inverters. These have the capability to achieve medium output
voltage levels using standard low voltage mature technological components and obtain
the required output by connecting three to ten inverters in series. Further the increase
in levels result more steps in staircase pure sinusoidal waveform
Here we are implementing a new cascade multilevel inverter for electric
vehicle and hybrid electric vehicle application, which uses only one dc source. Hence
it is easy to overcome all the disadvantages of existing topology. Traditionally, each
H-bridge of a cascaded multilevel inverter needs a dc power supply. The proposed
cascaded H-bridge multilevel boost inverter uses a standard three-leg inverter (one leg
for each phase) and an H-bridge in series with each inverter leg which uses a capacitor
as the dc power source . In this topology, the need for large inductors is eliminated. A
fundamental switching scheme is used to do modulation control and to output five-
level phase voltages.
1.2 LITERATURE REVIEW
Tim cunnyngam [2001] have put forward a new idea to minimize the total
harmonic distortion of synthesized multilevel waveform and improve the voltage
balancing capacity of battery. On summarizing these contribution a new cascaded
multilevel inverter, an alternative to conventional pwm technique for large hybrid
electric vehicle was implemented. As expected the line to line voltage of three phase
multilevel inverter was observed to be zero, while using a low pass filters. However
the significant increase of THD for both phase and line voltage are due to decreased
voltage levels. The new switching pattern that would help to balance and equalize the
individual battery voltage within an HEV battery pack was developed.
Jose Rodriguez et al [2002] provide a brief summary of multilevel inverter
circuit topology and their control strategies. Here the intention of the authors was
4

simply to provide ground work to interested readers, in looking back on the evolution
of multilevel inverter topologies. Hence he present the most important topologies like
diode clamped multilevel inverters, flying capacitor multilevel inverters, cascaded
multilevel inverters and also the emerging topologies like asymmetrical hybrid cells
and soft switched multilevel inverters with relevant control and modulation methods.
Leopoldo .G. Franguelo et al [2008] put forward a new idea for power
application using multilevel inverters, due to the fact that they can achieve high
power using mature medium power semiconductor technology. In order to show the
improved quality output voltage of multilevel inverters. Here the author compare a
single phase two level converter with three and nine level multilevel inverters
waveforms. According to his article, converter can overcome the technical barrier that
had been the curb for their deep use, as an optimized solution in power market. Hence
multilevel inverters topologies such as diode clamped multilevel inverter, flying
capacitor multilevel inverter and cascaded H bridge multilevel inverter which provides
interesting features in terms of power quality, power range, modularity and other
characteristics of achieving high quality output signals being designed for medium
and high power applications.
Rokan Ali Ahmed et al [2010] have discussed about a new topology for
symmetrical and asymmetrical multilevel inverter which result in the reduction of
installation area, cost and simplicity of control system. A new algorithm for
determining the dc source magnitude has also been implemented in this. The
important features of this system is being convenient for expanding and increasing the
number of output level simply with less number of bidirectional switch.
Mariusz malinowski et al [2010] implemented a cascaded multilevel inverter
which synthesize a medium voltage output based on series connection of power cells
which uses standard low voltage components configurations. This also includes
different regenerative and advanced topologies, control strategies and modulation
technique used by these inverter.
5

Andreas Nordvall [2011] present the information about several multilevel
inverter topologies. Some of them are well known with their application on market. In
his work he compared the multilevel inverters with 2 level inverter, in simulation,
modulation strategies, component comparison and solution to multilevel voltage
balancing problems and so on. He also proves that multilevel inverter of 1KHZ
frequency provides only 22% to 32% voltage THD while 2 level inverter of same
range produce 115% voltage THD. Other than that at lower switching frequency a 2
level inverter generates 25.1W switching losses, while multilevel inverter only
produce 2.1 to 2.2W switching losses.
T.Prathiba et al [2012] proposed the three level topologies(3LNPC, 3LFC-VSI,
5 level CHB) to cover different needs of day today applications. To reduce the
harmonics and to improve the efficiency, they introduce PWM modulation control
technique. This proposed techniques are validated through the detailed simulation
along with conventional 2 level voltage source inverter.
C. R. Balamurugan et al [2012] proposed a three phase 5 level diode clamped
multilevel inverter to simulate various modulating technique for induction motor
loads. These PWM technique includes carrier overlapping, variable frequency
strategies, phase shift PWM, sub harmonic PWM, phase opposition disposition and so
on. Using these technique the THD, crest factor, form factor and distortion factor are
evaluated. Among them phase opposition disposition provide output with relatively
low distortion and carrier overlapping is found to be better, since it provide higher
fundamental rms output voltage for induction motors.
Varsha sahu et al [2013] had developed a new idea 5 level diode clamped
multilevel inverter topology which can be used for low medium power industrial
applications. Here a five level diode clamped multilevel inverter using auxiliary
switch is implemented. The main concept of this inverter is that , the use of diode is to
limit the voltage stress and provide effective solution for largest output levels and
reduced THD values.

6

CHAPTER 2
MULTILEVEL INVERTERS
2.1 THE CONCEPT OF MULTILEVEL INVERTERS

Numerous industrial applications have begun to require higher power apparatus
in recent years. Some medium voltage motor drives and utility applications require
medium voltage and megawatt power level. For a medium voltage grid, it is
troublesome to connect only one power semiconductor switch directly. As a result, a
multilevel power converter structure has been introduced as an alternative in high
power and medium voltage situations. A multilevel converter not only achieves high
power ratings, but also enables the use of renewable energy sources. Renewable
energy sources such as photovoltaic, wind, and fuel cells can be easily interfaced to a
multilevel converter system for a high power applications.
Multilevel inverters are significantly different from the ordinary inverter where
only two levels are generated. The semiconductor devices are not connected in series
to for one single high-voltage switch. In which each group of devices contribute to a
step in the output voltage waveform. The steps are increased to obtain an almost
sinusoidal waveform. The number of switches involved is increased for every level
increment. The term multilevel began with the three-level converter. Subsequently,
several multilevel converter topologies have been developed. However, the
elementary concept of a multilevel converter to achieve higher power is to use a series
of power semiconductor switches with several lower voltage dc sources to perform the
power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries,
and renewable energy voltage sources can be used as the multiple dc voltage sources.
The commutation of the power switches aggregate these multiple dc sources in order
to achieve high voltage at the output; however, the rated voltage of the power
semiconductor switches depends only upon the rating of the dc voltage sources to
which they are connected.
7


Figure 2.1 block diagram of the general multilevel inverter
A multilevel converter has several advantages over a conventional two-level
converter that uses high switching frequency pulse width modulation (PWM).

2.2 FEATURES OF A MULTILEVEL INVERTER

Staircase waveform quality: Multilevel converters not only can generate the
output voltages with very low distortion, but also can reduce the dv/dt stresses;
therefore electromagnetic compatibility (EMC) problems can be reduced.
Common-mode (CM) voltage: Multilevel converters produce smaller CM
voltage; therefore, the stress in the bearings of a motor connected to a
multilevel motor drive can be reduced. Furthermore, CM voltage can be
eliminated by using advanced modulation strategies.
Input current: Multilevel converters can draw input current with low distortion.
Switching frequency: Multilevel converters can operate at both fundamental
switching frequency and high switching frequency PWM. It should be noted
that lower switching frequency usually means lower switching loss and higher
efficiency.
Unfortunately, multilevel converters do have some disadvantages. One particular
disadvantage is the greater number of power semiconductor switches needed.
Although lower voltage rated switches can be utilized in a multilevel converter, each
switch requires a related gate drive circuit. This may cause the overall system to be
8

more expensive and complex. Plentiful multilevel converter topologies have been
proposed during the last two decades. Contemporary research has engaged novel
converter topologies and unique modulation schemes. Moreover, three different major
multilevel converter structures have been reported in the literature: cascaded H-
bridges converter with separate dc sources, diode clamped (neutral-clamped), and
flying capacitors (capacitor clamped). Moreover, abundant modulation techniques and
control paradigms have been developed for multilevel converters such as sinusoidal
pulse width modulation (SPWM), selective harmonic elimination (SHE-PWM), space
vector modulation (SVM), and others. In addition, many multilevel converter
applications focus on industrial medium-voltage motor drives, utility interface for
renewable energy systems, flexible AC transmission system (FACTS), and traction
drive systems.
2.3 TYPES OF MULTILEVEL INVERTER

The general purpose of the multilevel inverter is to synthesize a nearly
sinusoidal voltage from several levels of dc voltages, typically obtained from
capacitor voltage sources. As the number of level increases, the synthesized output
waveform has more steps, which produce a staircase wave that approaches a desired
waveform. Also as more steps added to the waveform, the harmonic distortion of the
output waveform decreases, approaching zero as the level increases. As the number
of level increases, the voltage that can be summing multiple voltage levels also
increases. Three converter topologies have been considered to have
commercial potential. They are
A) Diode-clamped multilevel inverter
B) Flying-capacitor multilevel inverter
C) Cascaded H Bridge multilevel inverter
Among the three familiar topologies, cascaded multilevel inverter is an effective one.
So by skipping the other topologies, the cascaded multilevel inverter is explained
below. Cascaded multilevel inverter is having an unique and attractive topology such
as simplicity in structure, usage of less number of
components,etc.
9

2.3.1 Diode-clamped / Neutral point clamped multilevel Inverter
In recent years many industries starts to demand high power equipments having
megawatt ratings. Among them controlled AC drives of these range are highly
preferable for medium networks. But due to the development of advanced
technologies, it is difficult to connect a single power semiconductor switch directly to
medium voltage grids. Hence a new family of multilevel inverter emerges as a
solution for working with high voltage levels.
The invention of multilevel inverter starts with cascaded inverters ,with diode
blocking the source. Further these are derived as diode clamped multilevel inverter or
Neutral point clamped multilevel inverter. In these type of inverters clamping diodes
plays an important role. Depending on the voltage level in the inverter the dc bus is
divided into even numbers, by means of bulk capacitors in series with the neutral
point. The early description of this topology limited to 3 level with two capacitors
connected in series across the dc supply resulting one additional level. The additional
level to be the neutral point of dc bus, hence the terminology of neutral point clamped
inverter was introduced. However the neutral point is not accessible for even numbers
of voltage levels. Particularly these inverters become more attractive because of
increased power rating, improved harmonic performance and reduced EMI emission
and so on. But the main advantage of NPC topology is that it requires only one dc
supply similar to a two level inverter. Hence the increase in level not only increase the
number of clamping diodes but also increase the problem of ensuring the dc link
balance become more complicated. So that this topology is mainly used for three level
inverters only.
Advantages:
All of the phases share a common dc bus, which minimizes the capacitance
requirements of the converter. For this reason, a back-to-back topology is not
only possible but also practical for uses such as a high-voltage back-to-back
inter-connection or an adjustable speed drive.
The capacitors can be pre-charged as a group.
10

Vdc
Vdc/2
Vdc/4
-Vdc/4
-Vdc/2
D1
D1'
D2
D2'
D3
D4
S1
S2
S3
S4
S1'
S2'
S3'
S4'
n
a
b

Figure 2.3.1 five level diode clamped multilevel inverter
Disadvantages:
Real power flow is difficult for a single inverter because the intermediate dc
levels will tend to overcharge or discharge without precise monitoring and
control.
The number of clamping diodes required is quadratic ally related to the number
of levels, which can be cumbersome for units with a high number of levels.

2.3.2 Flying capacitor multilevel inverter
Another fundamental multilevel topology, the flying capacitor which is
alternatively known as capacitor clamped inverter, proposed by Meynard and Foch in
the year of 1992.These involves series connection of capacitor clamped switching
cells.
The structure of this inverter is similar to that of diode clamped multilevel
inverter except the use of ladder structured dc side capacitors instead of clamping
diodes. These ladder structure provides same voltage rating across each capacitor as
that of main power switch. Here the output waveform will be the combination of
various states of inner voltage levels. The redundancies of inner voltage level is one of
the main advantage of these type of inverters. Unlike in diode clamped multilevel
11

inverter this doesnt requires the conduction of all the switches in a consecutive series.
Moreover the phase redundancies of these inverters allows the charging or discharging
of specific capacitor and also can balance the voltage across various levels.
The disadvantages of flying capacitor multilevel inverters like conventional
initialization, complicated control to track the voltage level of all the capacitor,
precharging of all capacitors to same level, poor efficiency and switch utilisation
which minimizes the further use of these inverters. Also the large number of
capacitors, which are expensive and bulky than clamping diodes leads less interest
towards these inverters.

Vdc
Vdc/2
Vdc/4
-Vdc/4
-Vdc/2
c3
c2
c1
S1
S2
S3
S4
S1'
S2'
S3'
S4'
n
a
b

Figure 2.3.2 five level flying capacitor multilevel inverter
Advantages:
Phase redundancies are available for balancing the voltage levels of the
capacitors.
Real and reactive power flow can be controlled.
The large number of capacitors enables the inverter to ride through short
duration outages and deep voltage sags.



12

Disadvantages:
Control is complicated to track the voltage levels for all of the capacitors. Also,
precharging all of the capacitors to the same voltage level and start up are
complex.
Switching utilization and efficiency are poor for real power transmission.
The large numbers of capacitors are both more expensive and bulky than
clamping diodes in multilevel diode-clamped converters. Packaging is also
more difficult in inverters with a high number of levels.

2.3.3 Cascaded Multilevel Inverter

The cascaded multilevel inverter synthesizes a desired voltage from several
independent sources of DC voltages which may be obtained from batteries, fuel cells
or solar cells. This configuration has recently become very popular in high-power AC
supplies and adjustable-speed drive applications. Cascaded inverters have also been
proposed for use as the main traction drive in electric vehicles, where several
batteries or ultra capacitors are well suited to serve as SDCSs. The cascaded inverter
could also serve as a rectifier/charger for the batteries of an electric vehicle while the
vehicle was connected to an ac supply. Additionally, the cascade inverter can act as a
rectifier in a vehicle that uses regenerative braking. This converter can avoid extra
clamping diodes or voltage-balancing capacitors.
A single phase, m-level configuration of the cascaded multilevel inverter
shown below. Each single DC sources is associated with a single H-bridge converter.
The AC terminal voltages of different level converters are connected in series.
Through different combinations of the four switches, S1-S4, each converter level can
generate three different voltage outputs ,+Vdc, -Vdc and zero. The AC outputs of
different full-bridge converters in the same phase are connected in series such that the
synthesized voltage waveform is the sum of the individual converter outputs .Note
that the number of output waveform is the sum of the individual converter outputs
.Note that the number of output-phase voltage levels is defined in a different way from
those of the two previous converters .In this topology, the number of output-phase
13

voltage levels is defined by m=2N+1,where N is the number of DC sources .A five
level cascaded converter ,For example ,consists of two DC sources and two full bridge
converters. Minimum harmonic distortion can be obtained by controlling the
conduction angles at different converter levels.


Figure 2.3.3 five level cascade H bridge multilevel inverter

Advantages:
The series structure allows a scalable, modularized circuit layout and
packaging since each bridge has the same structure.
Switching redundancy for inner voltage level is possible because the phase
voltage output sum of each bridges output.
Potential of electrical shock is reduced due to separate DC sources.
Requires less number of components when compared to other two types.

Disadvantages:
Limited to certain applications where separate DC sources are available.
Usage of the power semiconductor switches increases exponentially whenever the
level is to be increased.

14

2.4 COMPARISON STUDY OF PROPOSED POWER CONVERTER
This topology employs a cascade of low voltage H-bridges each with
independent and isolated dc sources. The phase output voltage is synthesized by the
sum of series of H-bridges plus one. One major advantage of this approach is that the
number of the output can be further increased without addition of any new
components, requiring only the dc sources with different voltage levels. The
advantages of the cascaded multilevel H-bridge converter are the following:
The series structure allows a scalable, modularized circuit layout and
packaging due to the identical structure of each H-bridge.
No extra clamping diodes or voltage balancing capacitors is necessary.
The main disadvantage of this topology is that it needs separate dc sources for
real power conversions, thereby limiting its applications.
In high power systems, the multilevel inverter appropriately replaces the existing
system that uses traditional multilevel converters without the need for transformers.
Table 1 compares the power component requirement per phase leg among the three
multilevel voltage source inverters mentioned above. The table shows that the number
of main switches and main diodes needed by the inverters to achieve the same number
of voltage levels is the same.
Table 2.1 Comparison of multilevel inverter topologies
Configuration Diode clamped Capacitor clamped cascaded
Main switch 2(m-1) 2(m-1) 2(m-1)
Main diode 2(m-1) 2(m-1) 2(m-1)
Clamping diode (m-1)(m-2) 0 0
Dc bus capacitor (m-1) (m-1) (m-1)/2
Balancing Capacitor 0 (m-1)(m-2)/2 0
15


Table.2.2: Comparison for five level multilevel topologies

Inverter
configuration
Diode
clamped
Flying
capacitor
Cascaded
H-Bridge
Proposed
Method
Main switching
device
8 8 8 8
Main diodes 8 8 8 8
Clamping diodes 12 0 0 0
DC bus capacitors 4 4 2 2
Balancing
capacitor
0 6 0 0
DC Source 1 1 3 1


Comparison chart


Figure 2.4.1 comparison chart for various multilevel inverter

1 1.5 2 2.5 3 3.5 4
0
2
4
6
8
10
12
diode clamped Flying Capacitor Cascaded H bridge Proposed method


dc bus capacitor
unnamed2(:,2)
switching device
clamping diodes
balancing capacitor
dc sources
16

CHAPTER 3
PROPOSED TOPOLOGY

3.1 PROPOSED INDUCTORLESS H -BRIDGE MULTI LEVEL INVERTER
Basically an h bridge is an electronic circuit that enables a voltage to be applied
across a load in either direction. These circuits maintains a link between digital
circuitry and mechanical action and are often used in robotics and other applications
to allow dc motor to run. Here an inductor less h bridge multilevel boost inverter for
electric or hybrid electric vehicle is proposed. Traditionally each H-Bridge consists of
separate dc source. But in this proposed system uses a standard three leg inverter and
an h bridge in series with each inverter leg which uses a capacitor as a DC source. A
fundamental switching scheme is used here to obtain a five level output. Figure 1
depicts the basic block diagram of proposed power converter. To explain the
operation, here we are considering a single phase topology is considered followed
with the modes of operation. The simultaneous operation of switches S
1
,S
4
,S
6
a
1,1
,a
1,3

b
1,3
,b
1,4
produces an output voltage of V
DC
. This voltage will be +V
DC
. Similarly
when switch S
1
,S
4
,S
6
a
1,1
,a
1,4
b
1,3
,b
1,4
produces an output voltage of 2V
DC
. This
voltage will be -2V
DC
. Here each leg of inverter is connected in series with a full H-
Bridge, which in turn is supplied by a capacitor voltage. In the below system
capacitors are considered to be fully charged at the beginning which provide different
voltage levels according to the switching. The brief operation of various modes is
explained in below.
17


Figure 3.1: proposed power converter using single DC source
The circuit diagram of proposed dcac cascaded H-bridge multilevel boost
inverter topology is shown in Fig.3.1. The inverter uses a standard three-leg inverter
(one leg for each phase) and an H-bridge with a capacitor as its dc source in series
with each phase leg.

3.2 MODES OF OPERATION
3.2.1 Single phase topology of N level inverter
The single phase structure of the dc-ac cascaded n-level inverter is shown in
Figure. 3.2. The circuit operates with the help of switching actions. The outputs are
generated according to the switching actions. If the switch
5
S is closed in the bottom
level inverter, the output voltage of
1
V will be 2
dc
V .Similarly the switch
6
S closed
the output of the
1
V is 2
dc
V .This output is given to the H-bridge, which is supplied
18

by a capacitor voltage. The capacitor is kept charged to 2
dc
V , then the switches
2
S
and
3
S is closed. Similarly switches
1
S and
4
S are closed, the H-bridge output
2
V is
taken to 2
dc
V .If the output voltage is 0, when the switches
1
S and
4
S or
2
S and
3
S will be closed.

Figure.3.2.1: Single phase of the dc-ac cascaded H-bridge multilevel boost
converter.
In this inverter which uses fundamental frequency switching modulation control, a
staircase waveform output is produced with a sinusoidal load current waveform.
Accordingly the capacitor voltage regulation depends on the phase angle difference of
the output voltage and current otherwise the highest output ac voltage of the inverter
depends on the displacement power factor of the load.The magnitudes of the Fourier
coefficients when normalized with respect to V
dc
are as follows,
)] cos( ......... ) cos( ) [cos(
4
) (
2 1 s
n n n
n
n H

(3)

Where n = 1, 3, 5, 7...
19

The switching angles
k
,...... ,
2 1
, can be selected optimally by using the proposed
hybrid method, so that the voltage total harmonic distortion is minimum. The
operation of the inverter during the switches
5
S ,
2
S and
3
S closed is described in the
following section.
Switch
5
S ,
2
S and
3
S closed
This section describes the multilevel inverter mode operation with
5
S ,
2
S and
3
S
switches that are closed, which is shown in Figure.3. The output voltage
1
V of the
bottom inverter (with respect to the ground) is 2
dc
V when the switch
5
S is closed.
This leg is connected in series with a full H-bridge and it is supplied by a capacitor
voltage. The capacitor is kept charged to 2
dc
V , and then the output voltage of the H-
bridge can take on the values 2
dc
V switches
2
S and
3
S are closed. The output 0
means
1
S and
4
S is closed.

Figure.3.2.2: Mode of operation at switches
5
S ,
2
S and
3
S are closed
20

The number of levels chosen are high, to produce better sinusoidal voltage waveform.
Similarly the other modes are operated. Depending on the inverter output voltage the
proposed controller predicts the switching angle, which can eliminate the harmonic
contents presents in the inverter output voltage. The proposed technique is
implemented in the PRO-SPICE platform and the corresponding performances are
analyzed. Also the proposed methods effectiveness is analyzed by comparing with
the other techniques, which is briefly described in the following section 2.7.

3.3 MULTILEVEL INVERTERS PWM STRATEGY

Traditional PWM techniques have been successfully extended for multilevel
converter topologies, by using multiple carriers to control each power switch of the
converter. Therefore, they are known as multicarrier PWM methods. For multi cell
topologies, like FC and CHB, each carrier can be associated to a particular power cell
to be modulated independently using sinusoidal bipolar PWM and unipolar PWM,
respectively, providing an even power distribution among the cells. For a converter
with m cells, a carrier phase shift of 180/m for the CHB and of 360/m for the FC is
introduced across the cells to generate the stepped multilevel output waveform with
low distortion. Therefore, this method is known as phase shifted PWM (PS-PWM).

3.3.1 Space Vector Modulation Techniques
Space vector modulation (SVM) is a technique where the reference voltage is
represented as a reference vector to be generated by the power converter. All the
discrete possible switching states of the converter lead to discrete output voltages and
they can be also represented as the possible voltage vectors (usually named state
vectors) that can be achieved. The SVM technique generates the voltage reference
vector as a linear combination of the state vectors obtaining an averaged output
voltage equal to the reference over one switching period. In recent years, several space
vector algorithms extended to multilevel converters have been found in the research.
Most of them are particularly designed for a specific number of levels of the converter
21

and the computational cost and the algorithm complexity are increased with the
number of levels. Besides, these general modulation techniques for multilevel
converters involve trigonometric function calculations, look-up tables, or coordinated
system transformations, which increase the computational load. Recent SVM
strategies have drastically reduced the computational effort and the complexity of the
algorithms compared with other conventional SVM and sinusoidal PWM modulation
techniques. These techniques provide the nearest state vectors to the reference vector
forming the switching sequence and calculating the corresponding duty cycles using
extremely simple calculations without involving trigonometric functions, look-up
tables, or coordinate system transformations. Therefore, these methods drastically
reduce the computational load maintained, permitting the online computation of the
switching sequence and the on-state durations .













22

CHAPTER 4
HARDWARE DISCRIPTION
The hardware for five level cascaded h bridge multilevel inverter is assembled
by using control circuit, Driver circuit and Power circuit. The control circuit consist
of PIC16f777 which is shown in figure 4.1. The driver circuit consist of TLP250
optically isolated driver and MOSFET IRF740 which having a ratings of 400V
10A.The detailed study of hardware is explained below.
4.1 CONTROL CIRCUIT
P
I
C
1
6
F
7
7
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MCLR/PP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/TOCKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RB0/INT/AN12
RD1/AN10
RB2/AN8
RB3/CCP2(1)/AN9
RB4/AN11
RB5/AN13/CCP3
RB6/PGC
RB7/PGD

Figure 4.1 PIC16F777 controller

The PIC16F777 features 14 channels of 10-bit Analog-to-Digital (A/D)
converter, 3 timers, 3 Capture/Compare/PWM functions, the synchronous serial port
can be configured as either 3-wire Serial Peripheral Interface (SPI) or the 2-wire
Inter-Integrated Circuit (IC) bus and a Universal Asynchronous Receiver
Transmitter (USART), 2 comparators, internal RC oscillator and Advanced Low
23

Power Oscillator controls. All of these features make it ideal for applications
including automotive, appliance, battery, RF, motor control and utility metering.
4.1.1 Low-Power Features
- Primary Run(XT, RC, Oscillator, 76 A, 1MHz, 2V)
- RC_RUN (7A, 31.25kHz, 2V)
- Timer1 Oscillator (1.8 A, 32kHz, 2V)
- Watchdog Timer(0.7 A, 2V)
- Two-Speed Oscillator Start-up
4.1.2 Oscillators
- Three Crystal modes: LP, XT, HS (up to 20 MHz)
- Two External RC modes
- ECIO (up to 20 MHz)
- 8 user-selectable frequencies
4.1.3 Analog Features
- 10-bit, up to 14-channel Analog-to-Digital Converter
- Dual Analog Comparators
- Programmable Low-Current Brown-out Reset (NOR)
4.1.4 Peripheral Features
- Two 8-bit timer/counter with Prescalar
- One 16-bit timer/counter
- High source/sink current: 25mA
- Master Synchronous Serial Port (MSSP)
- Parallel Slave Port (PSP): 40/44 pin-device only
4.1.5 Special Microcontroller Features
- Fail-Safe Clock Monitor
- Power-On Reset
- Power-up Timer (PWRT) and Oscillator Start-Up Timer (OST)
- Two-Speed Start-Up mode
24

- Programmable Code Protection
- Power-Saving Sleeping Mode
4.2 PARAMETERS OF PIC16F777
Table 4.2 Parameters of PIC16F777
Parameter Name Value
Program Memory Type Flash
Program Memory (KB) 14
CPU Speed (MIPS) 5
RAM Bytes 368
Digital Communication
Peripherals
1-UART, 1-A/E/USART, 1-SPI,
1-I2C1-MSSP(SPI/I2C)
Capture/Compare/PWM
Peripherals
3 CCP
Timers 2 x 8-bit, 1 x 16-bit
ADC 14 ch, 10-bit
Comparators 2
Temperature Range (C) -40 to 125
Operating Voltage Range (V) 2 to 5.5
Pin Count 40

4.3 DRIVER CIRCUIT
For providing opto-isolation between the power stage and the drive signal stage,
the opto-isolator driver IC TLP 250 is used.
Following reasons justify the advantages of using TLP 250.
1. Input threshold voltage current If = 5mA (max)
2. Supply Voltage 10V-35V
3. Output Peak current 2A
4. Response speed 0.5us
25

Isolation voltage 2500Vrms In this TLP250 is used as driver circuit. TLP250 consists
of a GaAlAs light emitting diode and a integrated photo detector. This unit is 8lead
DIP package. TLP250 is suitable for gate driving circuit of IGBT or power MOS FET.
The image of TLP250 is as below.


Figure 4.3 TLP250 Driver IC

4.3.1 Pin Configuration


Figure 4.3.1 TLP250 pin configuration
4.3.2 Truth Table
Table 4.3.2 Truth table of TLP250

Input LED Tr1 Tr2
ON ON OFF
OFF OFF ON

26

The above is the pin configuration for TLP250 driver IC.It consist of eight pins
as specified above. As any other driver circuit this also consist of an input stage,
output stage and power supply connection. The speciality is that is an optically
isolated driver which means that input and the output are optically isolated. The
isolation is optical hence the input is consist of an LED and receiving output stage is
light sensitive photo detectors. Fig. 1 clearly shows the input LED side and the
receiving photo detector as well as the totem-pole driver stage. Pins 1 and 4 are not
internally connected to anything, and hence are labelled N.C. meaning no connection.
Pins 2 and 3 are the inputs to the LED, anode and cathode respectively. Like regular
LEDs, it has an input forward voltage and a peak forward current. The forward
voltage will typically be between 1.6V and 1.8V. The forward current should be less
than 20mA. The threshold input current for output transition from low to high is
typically 1.2mA, but may be as high as 5mA. Thus, 10mA current should be good.
Pin 8 is VCC the positive supply. Pin 5 is GND the ground supply or the
return path for the driving power supply. The supply voltage must be at least 10V. The
maximum voltage is dependent on the operating temperature. If the temperature is
lower than 70C, up to 30V can be used. For temperatures between 70C and 85C, up
to 20V can be used. However, there shouldnt be a need to use higher than 20V
anyways. In most cases, youll be using 12V or 15V or perhaps in some cases 18V.
The TLP250, being an optically isolated driver, has relatively slow propagation
delays (not to say that optically isolated drivers cant be fast; there are optically
isolated drivers faster than TLP250). The propagation delay time will typically lie
between 0.15s and 0.5s. An important thing to remember is that the datasheet
specifies the maximum operating frequency to be 25kHz. Ive used the TLP250 for
frequencies up to about 16kHz.
Even though pins 6 and 7 are shown to be internally connected, the output
should be taken from pin 6 as the image - datasheet - shows pin 6 labeled as Vo
(Output). Output voltage will tend to rise to supply voltage when high (it will actually
be slightly lower) and fall to ground level when low.

27

4.4 POWER CIRCUIT

The cascaded h bridge multilevel inverter is chosen among the three topologies
of multilevel inverter since it does not require any voltage balancing capacitors or
clamping diodes. The power circuit connected with the TLP250 driver circuit. Here
the power circuit is done for three phase five level multilevel inverter. It consist of
standard three leg inverter and an h bridge in series with each of these phase. The five
level inverter circuit using MOSFET is as below.

LOAD
12V
DC
SUPPLY
D
G
S

Figure 4.4 Power Circuit of Hardware

Here the hardware is done for 400v and 40A current and IRF740 MOSFET is
as switch. It having a capacity of 400v and 10A.Hence a switch module consist of four
IRF740 switches in parallel to obtain the required rating. Power circuit works at a
higher voltage than control circuit. The low voltage of control circuit is boosted to the
required power circuit voltage with the help of driver circuit. As explained above the
28

controller output is train of PWM pulses. There are three PWM pulse train from
PIC16f777 controller. The pulse trains are processed using gates and required pulses
are produced separately for positive and negative set of switches. Similarly the three
phase circuit is developed. The produced pulses are given to each switches and
inverted pulses are given through logic gates.

4.4.1 IRF740
Here the MOSFET used is IRF740. This switch having a voltage rating of 400V and a
current rating of 10A.Here to obtain a voltage of 400v and current of 40A four IRF740
MOSFET switches are connected in parallel. Below are some of the features of the
selected MOSFET.


Figure 4.4.1 IRF740 MOSFET switch


4.4.2 Features


Dynamic dV/dt Rating
Repetitive Avalanche Rated
Fast Switching
Ease of Paralleling
Simple Drive Requirements
Compliant to RoHS Directive 2002/95/EC

29


4.4.3 Specifications
Table 4.4.3 IRF740 Specifications


4.5 HARDWARE PCB LAYOUT

The PCB layout of various circuit is shown in following figure


Figure 4.5.1 PCB Layout of Voltage Source Inverter
30


Figure 4.5.2 PCB Layout of H bridge

Figure 4.5.3 PCB Layout of Driver circuit

Figure 4.5.4 PCB Layout of Logic circuit


Figure 4.5.5 PCB Layout of Logic circuit



31

CHAPTER 5
RESULTS AND DISCUSSION
5.1 SIMULATION STUDY
The proposed method is verified using PRO-SPICE simulation tool. Initially
the lower level inverter is considered upper level inverter is kept ideal. Lets consider
the Mode I for the VDC voltage. The switches S
2
,S
3
,a
13
and a
14
closed the output is
depicted in Figure 4.1.

Figure.5.1.1 : Mode of operation at switches S
2
,S
3
,a
13
and a
14
closed
Lets consider the Mode II for the Vdc voltage. The switches S
2,
S
3,
a
13,
and a
12
aer closed and the output is depicted in the figure 4.2. The circuit shown in the Figure
6 depicts the proposed DC-AC cascaded H-Bridge multilevel inverter topology. To
explain the operation, here we are considering a single phase topology. The
simultaneous operation of switches S
1
and S
4
produces an output voltage of V
1
. This
voltage V
1
will be +VDC when switch S1 is close and VDC when S
4
is closed.
Here each leg of inverter is connected in series with a full h bridge, which in turn is
supplied by a capacitor voltage.
32









Figure.5.1.2 : Mode of operation at switches S
2
,S
3
,a
13
and a
12
closed
In the above system capacitors are considered to be fully charged at the
beginnings which provide different voltage levels according to the switching.

Figure.5.1.3 : Circuit diagram of the proposed method

33

Table.5.1: Output voltage for various switching stages

Mode
Switches
Output
Voltage 1 2 3 4 5 6
a1
1
a1
2
a1
3
a1
4
b1
1
b1
2
b1
3
b1
4
c1
1
c1
2
c1
3
c1
4
I 1 1 0 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 Vdc
II 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 2Vdc
III 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 -Vdc
IV 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 -2Vdc

5.2 SIMULATION RESULT
The simulation of the proposed method was checked by using PROTEUS
software version 7.10 and output was obtained successfully. The pulses produced with
the help of this software as below. The logical signals are produced with the help of
PIC programming in PIC16f877A. The input to the driver circuit is pulses produced
with the help of logic gates such as AND gates and OR gates. The driver circuit will
boost up the input pulse to suitable voltage, in this case pulses are boosted to 24v i.e
the gate source voltage of MOSFET. The driver output is as below.
The three PWM pulses are processed with the help of logic gates to produce
both negative and positive set of pulses which are to be applied to the positive and
negative set of switches in the H bridge respectively. Similarly the same pulses are
applied to the switches in the R phase i.e S1 and S4. The negative pulses to be applied
to negative set of switches i.e S2 and S3. Similarly the for other H bridge pulses are
connected and are connected in series to produce the five level output.
Here the simulation is done for single phase and obtain a five level output. The
simulation circuit and the obtained output waveforms are as below.
The PWM pulse obtained from PIC controller is as below. This is given to
logical gate input to generate the required output signals.
34


Figure 5.2.1 Pulses produced by PIC controller
The output produced by the logic gates are as below. These pulses are given as
the input pulses to the driver circuit. Here logical gates such as AND, OR, XOR are
used for generating the required step pulses. The logical gate output are given to the
input of driver circuits. The driver circuit consist of PN2222 thyristor complimentary
pairs. the positive and negative output generated by the driver circuit is as below.


Figure 5.2.2 Positive pulse to driver circuit
35


Figure 5.2.3 Negative pulse to driver circuit
The waveform below is the positive output obtained due to the switching of positive
switches.

Figure 5.2.4 Positive output from driver circuit


36

5.3 SIMULATION CIRCUIT OF PROPOSED TOPOLOGY

Figure 5.3.1 Simulation circuit of cascaded five level inverter using PROTEUS


Figure 5.3.2 Positive and negative half of Output wave form obtained using
PROTEUS

37

The simulation circuit and the output obtained is given above. Here the
simulation is obtained only for the single phase and similarly we can obtain the output
for three phase also. By increasing the number of h bridge, the level in the output can
be increase. The three PWM pulses are processed with the help of logic gates to
produce both negative and positive set of pulses which are to be applied to the positive
and negative set of switches in the H bridge respectively. Similarly the same pulses
are applied to the switches in the R phase i.e S1 and S4. The negative pulses to be
applied to negative set of switches i.e S2 and S3. Similarly the for other H bridge
pulses are connected and are connected in series to produce the five level output.















38

CHAPTER 6
SUMMARY AND CONCLUSIONS

The proposed cascaded H-bridge multilevel inverter is applicable for
electric/hybrid electric vehicle applications. It consist of a standard three-leg inverter
(one leg for each phase) and an H-bridge in series with each inverter leg. Here a
fundamental switching scheme is used for modulation control, to obtain a five-level
phase voltages output . To obtain the five level output here space vector pulse width
modulation using sampled reference frame algorithm was used. Unlike the
conventional SVPWM techniques the present technique can work in the over
modulation region using amplitude of reference frame voltages. This technique does
not consist of any sector identification hence it reduce the computation time
considerably.
Multilevel carrier based PWM offers many more degrees of freedom than
traditional two level PWM. In multilevel PWM, the switching frequency can be less
than or greater than the carrier frequency and is a function of the displacement phase
angle between the carrier and modulation waveform. The space vector PWM
generates less harmonics distortions where as sine PWM generates high harmonic
distortion. Also the space vector PWM is more efficient use of supply voltage where
as sine PWM is less efficient use of supply voltage. This technique does not involves
any sector identification hence it reduces the computation time. Also any n level
Inverter can be implemented for various electric or hybrid electric vehicle applications
without any additional complexity with required number of carrier waveforms.




39

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41

PUBLICATIONS
Navya Nagath, S. Veerakumar Presented a paper based on A New Approach
of Cascaded H Multilevel Inverter for Electric/Hybrid Electric Vehicle
Applications in the International conference organized by Coimbatore
Institute of Technology, Coimbatore with Oklahoma state university,
Stillwater, USA.

Navya Nagath, S. Veerakumar Presented a paper based on A Cascaded H-
Bridge Multilevel Inverter Using A Single DC Source For Vehicle
Applications in the National conference organized by Info Institute of
Engineering, Coimbatore


Navya Nagath, S. Veerakumar Presented a paper based on A 5 Level
Single DC Source Cascaded H Bridge Multilevel Inverter For
Electric/Hybrid Electric Vehicle Applications in the National conference
organized by Bannari Amman Institute of technology, Sathyamangalam.