D D D D D D D D D: Description/ordering Information
D D D D D D D D D: Description/ordering Information
D D D D D D D D D: Description/ordering Information
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (N) Tube of 25 MAX232N MAX232N
SOIC (D)
Tube of 40 MAX232D
MAX232
0C to 70C
SOIC (D)
Reel of 2500 MAX232DR
MAX232
0C to 70C
SOIC (DW)
Tube of 40 MAX232DW
MAX232 SOIC (DW)
Reel of 2000 MAX232DWR
MAX232
SOP (NS) Reel of 2000 MAX232NSR MAX232
PDIP (N) Tube of 25 MAX232IN MAX232IN
SOIC (D)
Tube of 40 MAX232ID
MAX232I
40C to 85C
SOIC (D)
Reel of 2500 MAX232IDR
MAX232I
40 C to 85 C
SOIC (DW)
Tube of 40 MAX232IDW
MAX232I SOIC (DW)
Reel of 2000 MAX232IDWR
MAX232I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinASIC is a trademark of Texas Instruments.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C1+
V
S+
C1
C2+
C2
V
S
T2OUT
R2IN
V
CC
GND
T1OUT
R1IN
R1OUT
T1IN
T2IN
R2OUT
MAX232 . . . D, DW, N, OR NS PACKAGE
MAX232I . . . D, DW, OR N PACKAGE
(TOP VIEW)
MAX232, MAX232I
DUAL EIA232 DRIVERS/RECEIVERS
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. Maximum power dissipation is a function of T
J
(max),
JA
, and T
A
. The maximum allowable power dissipation at any allowable
ambient temperature is P
D
= (T
J
(max) T
A
)/
JA
. Operating at the absolute maximum T
J
of 150C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage (T1IN,T2IN) 2 V
V
IL
Low-level input voltage (T1IN, T2IN) 0.8 V
R1IN, R2IN Receiver input voltage 30 V
T
A
Operating free-air temperature
MAX232 0 70
C T
A
Operating free-air temperature
MAX232I 40 85
C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 4)
PARAMETER TEST CONDITIONS MIN TYP
MAX UNIT
I
CC
Supply current
V
CC
= 5.5 V,
T
A
= 25C
All outputs open,
8 10 mA
MAX UNIT
V
OH
High-level output voltage T1OUT, T2OUT R
L
= 3 k to GND 5 7 V
V
OL
Low-level output voltage
T1OUT, T2OUT R
L
= 3 k to GND 7 5 V
r
o
Output resistance T1OUT, T2OUT V
S+
= V
S
= 0, V
O
= 2 V 300
I
OS
The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
MAX UNIT
V
OH
High-level output voltage R1OUT, R2OUT I
OH
= 1 mA 3.5 V
V
OL
Low-level output voltage
R1OUT, R2OUT I
OL
= 3.2 mA 0.4 V
V
IT+
Receiver positive-going input
threshold voltage
R1IN, R2IN V
CC
= 5 V, T
A
= 25C 1.7 2.4 V
V
IT
Receiver negative-going input
threshold voltage
R1IN, R2IN V
CC
= 5 V, T
A
= 25C 0.8 1.2 V
V
hys
Input hysteresis voltage R1IN, R2IN V
CC
= 5 V 0.2 0.5 1 V
r
i
Receiver input resistance R1IN, R2IN V
CC
= 5, T
A
= 25C 3 5 7 k
The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
NOTE 4: Test conditions are C1C4 = 1 F at V
CC
= 5 V 0.5 V.
switching characteristics, V
CC
= 5 V, T
A
= 25C (see Note 4 and Figure 1)
PARAMETER TYP UNIT
t
PLH(R)
Receiver propagation delay time, low- to high-level output 500 ns
t
PHL(R)
Receiver propagation delay time, high- to low-level output 500 ns
NOTE 4: Test conditions are C1C4 = 1 F at V
CC
= 5 V 0.5 V.
MAX232, MAX232I
DUAL EIA232 DRIVERS/RECEIVERS
C4
C3 can be connected to V
CC
or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown. In addition to the 1-F capacitors shown, the MAX202 can operate with 0.1-F capacitors.
+
+