This document is a resume for Kumar Vishal. It summarizes his objective, which is to become an accomplished VLSI engineer working in areas like digital design and verification to reduce verification cycle times. It then details his technical skills and experience, which include 6 months of ASIC design training, languages like Verilog and VHDL, and EDA tools from companies like Synopsys, Cadence, and Mentor Graphics. Finally, it lists his educational background and projects, which involve designing processors, peripherals, and going through the full custom design flow from RTL to layout.
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This document is a resume for Kumar Vishal. It summarizes his objective, which is to become an accomplished VLSI engineer working in areas like digital design and verification to reduce verification cycle times. It then details his technical skills and experience, which include 6 months of ASIC design training, languages like Verilog and VHDL, and EDA tools from companies like Synopsys, Cadence, and Mentor Graphics. Finally, it lists his educational background and projects, which involve designing processors, peripherals, and going through the full custom design flow from RTL to layout.
This document is a resume for Kumar Vishal. It summarizes his objective, which is to become an accomplished VLSI engineer working in areas like digital design and verification to reduce verification cycle times. It then details his technical skills and experience, which include 6 months of ASIC design training, languages like Verilog and VHDL, and EDA tools from companies like Synopsys, Cadence, and Mentor Graphics. Finally, it lists his educational background and projects, which involve designing processors, peripherals, and going through the full custom design flow from RTL to layout.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
This document is a resume for Kumar Vishal. It summarizes his objective, which is to become an accomplished VLSI engineer working in areas like digital design and verification to reduce verification cycle times. It then details his technical skills and experience, which include 6 months of ASIC design training, languages like Verilog and VHDL, and EDA tools from companies like Synopsys, Cadence, and Mentor Graphics. Finally, it lists his educational background and projects, which involve designing processors, peripherals, and going through the full custom design flow from RTL to layout.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
To become an Accomplished VLSI engineer. I am passionate about Digital design involving RTL design and verification. I am Interested in working on areas to reduce verification cycle time.
TECHNICAL SUMMARY
• Working as graduate Trainee at R.V-VLSI Design Center (Bangalore).
• 6 months of solid training and experince in ASIC Design at R.V. VLSI Design Center. • 7 weeks training on VHDL in CETPA Infotech Pvt. Ltd.(Greater Noida) • 1 month training in Switch, Networks and OMC in Idea Cellular Ltd.(Meerut)
CORE COMPETENCY
• Knowledge of the complete ASIC flow (RTL to GDS).
• Good knowledge of System Verilog, Verilog HDL, VHDL • Knowledge of Functional coverage, Code coverage. • Knowledge of scripting in PERL. • Written Regression scripts in PERL for Test bench in Verilog and System Verilog • Posess expertise in Digital Circuit design, FSM’s. • Knowledge of Formal verification using Equivalence Checking. • Posess strong Synthesis and Timing analysis experince to meet better timing requirements. • Knowledge and experince in Physical Design- Floorplanning, routing, CTS, and physical verification- DRC,LVS, PEX. • Knowledge of FPGA and CPLD to reduce verification time
Hardware Languages : Verilog, System Verilog (HVL), VHDL
Scripting : Perl Software Languages : C Assembly : 8085, 8086 Operating Systems : Working knowledge of UNIX / LINUX / Solaris, Win XP, 2000. IDE’s/Tools/Packages : VI/VIM/GVIM Editors. EDA Tools Experience : VCS, ModelSim, LEDA, Questa, Design Compiler, Formality, Prime time, SPECTRE/COMPOSER-Schematics, VIRTUOSO Schematic/Layout Editor, Mentor Graphics Calibre LVS/DRC/PEX, ASTRO, Xilinx ISE
EDUCATIONAL BACKGROUND Advanced Diploma in ASIC DESIGN and Engineering RV-VLSI design center (Banglore)
B.Tech– Electronics and communication
Shobhit Institute Of Engineering & technology (Uttarpradesh Technical University) Percentage: 73%
Title Verification of LC3 (little computer 3) using System Verilog
My Role To come up with a layered test bench based on VMM methodology and constrained randomization, for two stage pipelined architecture consisting of an Execute pre-processor and an ALU block having operations like shift, arithmetic, memory write and memory read and to define covergroup, coverpoints and bins based on specification to ensure 100 % real functional coverage is achieved during verification. Issues faced Deciding verification plan in order to reduce verification cycle time. Deciding various layers & resolved in the test bench, deciding functional coverage of the design, creating synchronization between DUT and test Bench to get proper results. Tools used Questa (Mentor Graphics)
Title RTL Design of UART 16550 using Verilog
My Role To design Receiver of UART Core as per given specification. Receiver performs serial to parallel conversions, validation of the received data by performing various checks like frame error, parity error, overrun error, break error, setting of error flags in line status register, detection of false start bit and self recovery from frame error and pushes the data in 128-byte FIFO at the baud rate. Issues faced Deciding coding style, which would bring up better hardware after synthesis to meet timing & resolved requirements. Handling multiple clock domains. Tools used VCS (Synopsys), Design Compiler (Synopsys), Prime Time
Title RTL Design of 16 bit Processor based on Intel 8086 architecture using VHDL My Role To design processor based on Intel 8086 architecture having maximum features of it like memory segmentation, pipelining, minimum mode of operation, interrupts (software and hardware), extraction of 2-byte word from memory at the same time. Issues faced Creating synchronization between Bus interface unit and Execution Unit for sharing the bus & resolved so that both can run in parallel. At the time of call instruction decrementing Instruction pointer register to hold the offset of the instruction (already fetched) present in Queue. Added some extra blocks in architecture to facilitate different operation. Tools used ModelSim (Mentor Graphics)
Title Physical design and verification of I2C
My Role To do the Floor Planning, Placement, Clock Tree Synthesis, Routing and physical verification of I2C. Issues faced & Antenna violations, Nwell Continuity, Metal Density resolved Tools used Astro, Virtuoso, Calibre (DRC, LVS, XRC)
Title Simulation of Simulation of RC-Circuit and to understand the various factors influencing the delay of the circuit. Objective To compute the time taken to charge and discharge the capacitor and to determine various factors which contribute to the rate of charging and discharging of capacitor. Tools used Virtuoso Schematic composer, Spectre.
Title Design of Inverter
Objective To understand the delay variation depending on the supply voltage, Transistor sizing, input transition and output load, Tools used Virtuoso, SPECTRE, CALIBRE (DRC, LVS, XRC).
Mini B.E. Projects-Traffic light controller (using VHDL), laser based perimeter protection system, Sound operated light, Infrared Counter/Detector, Automatic Night light. COURSE WORK
• Concept to Chip highlighting on the ASIC flow, difference between custom, ASIC and FPGA flow. • Logic design use of Combinatorial, sequential logic, buiding FSM machines based on specification, FPGA flow. • Verilog HDL (RTL) undestanding of coding style to infer different hardware at synthesis stage, different coding styles for FSMs, use of blocking and non blocking assignments. Leda check for design. • Writing Testbenches in System Verilog and Verilog based on given specification gathering functional coverage(SV), code coverage(SV and Verilog). • Formal verification using equivalece checking. • Synthesis flow, generating a netlist of the design, understanding DRC, environment, optimization constraints, Synthesis strategies top down and bottom up. Using Design Compiler (synopsys) Tcl to optimize design, setting up the path, target library, link library knowing the different lib purposes and uses.Understanding the library file .db,.lib in perspective to transition , delay calculation of delay for the cells Mapping design to a specific technology (180nm) and mapping design from one technology to other. • STA flow, concepts, importance and use of Setup,hold, recovery & removal timing,false path, multicycle path, Launch edge, Capture edge, Virtual clock, min, max delay, timing exceptions, Optimistic and pessimistic approach of setting the constraints and understanding the timing. Analysis with respect to different clock domains restrictive edge setup & hold analysis. Using PimeTime Tcl to generate automated script, specifying path groups, generating timing reports by specifying(.sdc) file.
Physical Design
• Floorplanning, placement & routing,CTS, analysing congestion and summarizing reports to meet Congestion & timing . • Using Synopsys Astro for the Physical design Implementation taking a i2c netlist through the PD flow. • Study of 180nm Technology Foundry Document
ACHIEVEMENTS
• 1st prize in project making contest held on Inspirer’s day Feb 2007. • 1st prize in project making contest held on Inspirer’s day Feb 2008. • 1st prize in VHDL coding competition in “ASIMO’08” (A national level tech fest held every year in Subharti University Meerut).
AREA OF INTEREST
• RTL Design, verification, Synthesis, Timing analysis, Microprocessors, Digital electronics,
electronics, Interested in working on areas to reduce verification cycle time.
EXTRA CURRICULAR ACTIVITIES
• Active participation in paper presentation contests.
• Active member of Electronics club in college. • Active participation in Group Discussion. • Active participation in debate competition • Organized cultural events in college. • Attended workshop on VLSI-design organized by CDAC-NOIDA SUMMARY
• 6 months experience in ASIC Design.
• Exposure to EDA Design Tools from Synopsys, Cadence & Mentor Graphics.
• Strong interpersonal skills.
• Believe in teamwork and uphold team strength. • A keen and quick learner • Creative, problem solving and able to handle last minute change in work plan.
PERSONAL DETAILS
Name KUMAR VISHAL
Date of birth 12/09/1987
Father’s Name AJEET KUMAR SINHA Gender Male Languages Known English, Hindi Phone num +919019420224 Email ID [email protected]
