Mobil INTEL 4 Series Express Chipset Family PDF

Document Number: 320122-006
Mobile Intel 4 Series Express

Chipset Family
Datasheet
J une 2009
2 Datasheet
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Datasheet 3
Contents
1 Introduction............................................................................................................ 13
1.1 Intel PM45 Express Chipset Feature Support ...................................................... 14
1.1.1 Processor .............................................................................................. 14
1.1.2 System Memory..................................................................................... 14
1.1.3 Discrete Graphics Using PCI Express* Graphics Attach Port .......................... 14
1.1.4 Direct Management Interface (DMI).......................................................... 15
1.1.5 Power Management ................................................................................ 15
1.1.6 Thermal Management ............................................................................. 15
1.1.7 Intel Trusted Execution Technology (Intel TxT) ..................................... 15
1.1.8 Intel Virtualization Technology (Intel VT) DMA ...................................... 15
1.1.9 Intel Active Management Technology (Intel AMT) 4.0 ............................ 16
1.1.10 Integrated Trusted Platform Module (ITPM)................................................ 16
1.1.11 Package................................................................................................ 16
1.2 Intel GM45 Express Chipset Feature Support ...................................................... 16
1.2.1 Processor .............................................................................................. 16
1.2.2 System Memory..................................................................................... 16
1.2.3 PCI Express Graphics Attach Port.............................................................. 17
1.2.4 Internal Graphics ................................................................................... 17
1.2.4.1 Dual-Channel LVDS................................................................... 17
1.2.4.2 DisplayPort* (DP) ..................................................................... 17
1.2.4.3 Integrated HDMI (iHDMI)* ......................................................... 18
1.2.4.4 SDVO Ports.............................................................................. 18
1.2.4.5 Analog CRT.............................................................................. 18
1.2.4.6 TV-Out .................................................................................... 18
1.3 Intel GS45 Express Chipset Feature Support ...................................................... 19
1.3.1 Processor .............................................................................................. 19
1.3.2 Memory ................................................................................................ 19
1.3.4 ICH Support .......................................................................................... 19
1.3.5 Package................................................................................................ 19
1.4 Intel GL40 Express Chipset Feature Support....................................................... 20
1.4.1 Processor .............................................................................................. 20
1.4.2 System Memory..................................................................................... 20
1.4.4 ICH Support .......................................................................................... 20
1.4.6 Unsupported Features............................................................................. 20
1.5 Intel GS40 Express Chipset Feature Support ...................................................... 20
1.5.1 Processor .............................................................................................. 21
1.5.2 System Memory..................................................................................... 21
1.5.4 ICH Support .......................................................................................... 21
1.5.6 Unsupported Features............................................................................. 21
1.6 Reference Documents ........................................................................................ 22
2 Signal Description ................................................................................................... 23
2.1 Host Interface................................................................................................... 23
2.1.1 Host Interface Signals............................................................................. 24
2.2 Memory Interface.............................................................................................. 27
4 Datasheet
2.2.1 Memory Channel A Interface ....................................................................27
2.2.2 Memory Channel B Interface ....................................................................28
2.2.3 Memory Reference and Compensation .......................................................29
2.3 PCI Express-Based Graphics Interface Signals .......................................................30
2.3.1 DisplayPort (DP), iHDMI and SDVO on PCI Express Based Graphics ...............30
2.4 DMI GMCH to ICH Serial Interface.....................................................................30
2.5 Integrated Graphics Interface Signals...................................................................31
2.5.1 CRT DAC Signals ....................................................................................31
2.5.2 Analog TV-out Signals .............................................................................31
2.5.3 LVDS Signals .........................................................................................32
2.5.4 Display Data Channel (DDC) and GMBUS Support .......................................33
2.6 Intel High Definition Audio (Intel HD Audio) Signals ..........................................33
2.7 Intel Management Engine Interface
(Intel MEI) Signals ..........................................................................................34
2.8 PLL Signals .......................................................................................................34
2.9 Reset and Miscellaneous Signals ..........................................................................35
2.10 Non-Critical to Function (NCTF) ...........................................................................36
2.11 Power and Ground .............................................................................................36
3 Host Interface..........................................................................................................39
3.1 FSB Source Synchronous Transfers ......................................................................39
3.2 FSB IOQ Depth..................................................................................................39
3.3 FSB OOQ Depth.................................................................................................39
3.4 FSB AGTL+ Termination .....................................................................................39
3.5 FSB Dynamic Bus Inversion.................................................................................39
3.6 FSB Interrupt Overview......................................................................................40
3.7 APIC Cluster Mode Support .................................................................................40
3.8 FSB Dynamic Frequency Switching.......................................................................40
4 System Address Map................................................................................................41
4.1 Legacy Address Range........................................................................................44
4.1.1 MS-DOS Range (0000_0000h 0009_FFFFh) .............................................45
4.1.2 Legacy Video Area (000A_0000h to 000B_FFFFh)........................................45
4.1.2.1 Compatible SMRAM Address Range (000A_0000h to 000B_FFFFh) ...45
4.1.2.2 Monochrome Adapter (MDA) Range (000B_0000h to 000B_7FFFh)...45
4.1.3 Expansion Area (000C_0000h to 000D_FFFFh) ...........................................45
4.1.4 Extended System BIOS Area (000E_0000h to 000E_FFFFh)..........................46
4.1.5 System BIOS Area (000F_0000h to 000F_FFFFh) ........................................46
4.1.6 Programmable Attribute Map (PAM) Memory Area Details.............................47
4.2 Main Memory Address Range (1 MB to TOLUD) ......................................................47
4.2.1 ISA Hole (15 MB to 16 MB) ......................................................................48
4.2.2 TSEG ....................................................................................................48
4.2.3 DPR (DMA Protected Range).....................................................................48
4.2.4 Pre-allocated Memory..............................................................................48
4.3 PCI Memory Address Range (TOLUD to 4 GB) ........................................................49
4.3.1 APIC Configuration Space (FEC0_0000h to FECF_FFFFh) ..............................51
4.3.2 HSEG (FEDA_0000h to FEDB_FFFFh) .........................................................51
4.3.3 FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF) .............................51
4.3.4 High BIOS Area ......................................................................................51
4.4 Main Memory Address Space (4 GB to TOUUD) ......................................................52
4.4.1 Memory Remap Background.....................................................................52
4.4.2 Memory Remapping (or Reclaiming) ..........................................................53
4.5 PCI Express Configuration Address Space..............................................................53
4.5.1 PCI Express Graphics Attach ....................................................................53
4.5.2 Graphics Aperture...................................................................................53
4.6 Graphics Memory Address Ranges........................................................................54
Datasheet 5
4.6.1 Graphics Register Ranges ........................................................................ 54
4.6.1.1 VGA and Extended VGA Control Registers (0000_0000h to
0000_0FFFh)............................................................................ 54
4.6.1.2 Instruction, Memory, and Interrupt Control Registers (0000_1000h
to 0000_2FFFh) ........................................................................ 54
4.6.2 I/O Mapped Access to Device 2 MMIO Space .............................................. 54
4.7 System Management Mode (SMM) ....................................................................... 56
4.7.1 SMM Space Definition ............................................................................. 56
4.8 SMM Space Restrictions ..................................................................................... 57
4.8.1 SMM Space Combinations........................................................................ 57
4.8.2 SMM Control Combinations ...................................................................... 57
4.8.3 SMM Space Decode and Transaction Handling ............................................ 58
4.8.4 Processor WB Transaction to an Enabled SMM Address Space....................... 58
4.9 Memory Shadowing ........................................................................................... 58
4.10 I/O Address Space............................................................................................. 58
4.10.1 PCI Express I/O Address Mapping............................................................. 59
4.11 GMCH Decode Rules and Cross-Bridge Address Mapping......................................... 60
4.11.1 Legacy VGA and I/O Range Decode Rules .................................................. 60
5 System Memory Controller ...................................................................................... 61
5.1 Functional Overview .......................................................................................... 61
5.2 Memory Channel Access Modes ........................................................................... 62
5.2.1 Dual-Channel Interleaved Mode................................................................ 62
5.2.1.1 Intel Flex Memory Technology (Dual-Channel Interleaved Mode
with Unequal Memory Population) ............................................... 62
5.2.2 Dual-Channel Asymmetric Mode............................................................... 63
5.3 DRAM Technologies and Organization................................................................... 64
5.3.1 Rules for Populating SO-DIMM Slots.......................................................... 65
5.3.1.1 Single-Channel Population Rules for Systems with Intel
Management Engine Enabled...................................................... 65
5.3.2 Pin Connectivity for Dual-Channel Modes ................................................... 65
5.4 DRAM Clock Generation...................................................................................... 66
5.5 DDR2/DDR3 On Die Termination ......................................................................... 66
5.6 DRAM Power Management .................................................................................. 66
5.6.1 Self Refresh Entry and Exit Operation........................................................ 66
5.6.2 Dynamic-Power-Down Operation .............................................................. 67
5.6.3 DRAM I/O Power Management ................................................................. 67
5.7 System Memory Throttling.................................................................................. 67
6 PCI Express-Based External Graphics ...................................................................... 68
6.1 PCI Express Configuration Mechanism.................................................................. 68
6.2 Concurrent Operation of Digital DisplayPorts Multiplexed with the GMCH PCI Express
Interface.......................................................................................................... 69
6.2.1 SDVO Multiplexed on the PCI Express Interface.......................................... 69
6.2.1.1 SDVO Signal Mapping................................................................ 71
6.2.2 Integrated HDMI/DVI (iHDMI) Multiplexed on the PCI Express Interface ........ 72
6.3 Co-Existence of DisplayPorts............................................................................... 74
7 Integrated Graphics Controller ................................................................................ 75
7.1 Gen 5.0 3D and Video Engines for Graphics Processing........................................... 75
7.1.1 3D Engine Execution Units (EUs) .............................................................. 76
7.1.2 3D Pipeline............................................................................................ 76
7.1.2.1 Vertex Fetch (VF) Stage............................................................. 76
7.1.2.2 Vertex Shader (VS) Stage.......................................................... 76
7.1.2.3 Geometry Shader Stage............................................................. 76
7.1.2.4 Clip Stage................................................................................ 76
7.1.2.5 Strips and Fans Stage ............................................................... 76
6 Datasheet
7.1.2.6 Windower/IZ (WIZ) Stage ..........................................................76
7.2 Video Engine.....................................................................................................77
7.3 2D Engine.........................................................................................................77
7.3.1 Chipset VGA Registers.............................................................................77
7.3.2 Logical 128-Bit Fixed BLT and 256 Fill Engine .............................................77
8 Display Interfaces....................................................................................................78
8.1 GMCH Display Overview .....................................................................................78
8.1.1 Display Planes........................................................................................78
8.1.1.1 Planes A and B..........................................................................79
8.1.1.2 Sprite A and B ..........................................................................79
8.1.1.3 Cursors A and B........................................................................79
8.1.1.4 VGA ........................................................................................79
8.1.2 Display Pipes..........................................................................................79
8.1.3 DisplayPorts...........................................................................................79
8.2 Analog DisplayPorts ...........................................................................................80
8.2.1 CRT ......................................................................................................80
8.2.1.1 Integrated DAC.........................................................................80
8.2.1.2 Sync Signals.............................................................................80
8.2.2 TV ........................................................................................................80
8.3 Digital DisplayPorts............................................................................................81
8.3.1 LVDS ....................................................................................................81
8.3.1.1 LVDS Pair States .......................................................................82
8.3.1.2 Single-Channel versus Dual-Channel Mode ...................................82
8.3.1.3 Panel Power Sequencing.............................................................82
8.3.1.4 LVDS DDC................................................................................83
8.3.2 iHDMI ...................................................................................................83
8.3.2.1 HDCP.......................................................................................84
8.3.3 DisplayPort (DP) .....................................................................................84
8.3.3.1 DP Aux Channel ........................................................................85
8.3.3.2 DP Hot-Plug Detect (HPD) ..........................................................85
8.3.4 SDVO....................................................................................................85
8.3.4.1 SDVO Control Bus .....................................................................86
8.4 Co-Existence of DisplayPorts ...............................................................................86
9 Power Management and Sequencing........................................................................88
9.1 Power Management Features...............................................................................88
9.1.1 Dynamic Power Management on I/O..........................................................88
9.1.1.1 Host ........................................................................................88
9.1.1.2 System Memory........................................................................88
9.1.1.3 PCI Express..............................................................................88
9.1.1.4 DMI.........................................................................................88
9.1.1.5 Intel Management Engine...........................................................88
9.1.2 System Memory Power Management .........................................................89
9.1.2.1 Disabling Unused System Memory Outputs ...................................89
9.1.2.2 Dynamic Power Management of Memory.......................................89
9.1.2.3 Conditional Self-Refresh.............................................................89
9.2 ACPI States Supported .......................................................................................90
9.2.1 System .................................................................................................90
9.2.2 Processor ..............................................................................................90
9.2.3 Internal Graphics Display Device Control....................................................90
9.2.4 Internal Graphics Adapter ........................................................................91
9.3 Interface Power States Supported........................................................................91
9.3.1 PCI Express Link States ...........................................................................91
9.3.2 Main Memory States................................................................................91
9.4 Chipset State Combinations ................................................................................92
9.4.1 CPU Sleep (H_CPUSLP#) Signal Definition..................................................93
Datasheet 7
9.5 CLKREQ# - Mode of Operation ............................................................................ 93
9.6 Intel Display Power Saving Technology
(Intel DPST) 4.0............................................................................................. 93
9.7 FSB Dynamic Frequency Switching ...................................................................... 93
9.8 Render Standby States ...................................................................................... 93
9.9 Render Thermal Throttling.................................................................................. 94
10 Absolute Maximum Ratings ..................................................................................... 95
10.1 Power Characteristics......................................................................................... 97
11 Thermal Management ............................................................................................ 102
11.1 Internal Thermal Sensor................................................................................... 102
11.1.1 Internal Thermal Sensor Operation ......................................................... 102
11.1.1.1 Recommended Programming for Available Trip Points .................. 103
11.1.1.2 Thermal Sensor Accuracy (Taccuracy) ....................................... 103
11.1.2 Hysteresis Operation............................................................................. 104
11.2 Memory Thermal Throttling Options ................................................................... 104
11.3 External Thermal Sensor Interface Overview....................................................... 104
11.4 THERMTRIP# Operation ................................................................................... 105
11.5 TSATN# Operation .......................................................................................... 105
12 DC Characteristics ................................................................................................. 106
12.1 I/O Buffer Supply Voltages ............................................................................... 110
12.2 General DC Characteristics ............................................................................... 111
12.3 CRT DAC DC Characteristics.............................................................................. 117
12.4 TV DAC DC Characteristics................................................................................ 118
13 Clocking ................................................................................................................ 119
13.1 Overview ....................................................................................................... 119
13.2 GMCH Reference Clocks ................................................................................... 119
13.3 GMCH Host/Memory/Graphics Core Clock Frequency Support ................................ 120
14 Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d)
Technology............................................................................................................ 121
14.1 Intel VT-d Terminology .................................................................................... 121
14.1.1 GCH/Intel VT-d Chipset Components....................................................... 122
14.1.2 DMA Address Remapping....................................................................... 122
14.1.3 Capabilities of GMCH DMAr hardware ...................................................... 123
14.1.4 Handling Interrupt Messages.................................................................. 124
14.2 Intel Trusted Execution Technology (Intel TXT) ................................................... 124
15 GMCH Strapping Configuration .............................................................................. 125
16 Ballout and Package Information........................................................................... 126
16.1 Mobile Intel 4 Series Express Chipset Ballout Diagrams ........................................ 126
16.2 GMCH Signal List by Ball .................................................................................. 130
16.3 Standard GMCH Package Information................................................................. 142
16.4 Intel GS45 Express Chipset Ballout Diagrams...................................................... 144
16.5 Intel GS45 Express Chipset Package Information................................................. 148
17 (G)MCH Register Description................................................................................. 163
18 (G)MCH Configuration Process and Registers ........................................................ 165
19 Host Bridge Device 0 Configuration Registers (D0:F0)........................................... 177
20 Device 0 Memory Mapped I/O Register.................................................................. 217
21 PCI Express Graphics Device 1 Configuration Registers (D1:F0) ............................ 313
22 Internal Graphics Device 2 Configuration Register (D2:F0-F1) .............................. 365
23 Intel Management Engine Subsystem PCI Device 3............................................. 409
8 Datasheet
Figures
1 Block Diagram .........................................................................................................13
2 System Address Ranges ............................................................................................43
3 Microsoft MS-DOS* Legacy Address Range...................................................................44
4 Main Memory Address Range (1 MB to TOLUD).............................................................47
5 PCI Memory Address Range (TOLUD to 4 GB)...............................................................50
6 Graphics Register Memory and I/O Map.......................................................................55
7 Intel Flex Memory Technology Operation .....................................................................63
8 System Memory Styles..............................................................................................64
9 PCI Express Related Register Structures in GMCH .........................................................68
10 SDVO/PCI Express Non-Reversed Configurations ..........................................................70
11 SDVO/PCI Express Reversed Configurations .................................................................70
12 GMCH Graphics Controller Block Diagram.....................................................................75
13 Mobile Intel 4 Series Express Chipset Family Display Block Diagram................................78
14 LVDS Signals and Swing Voltage ................................................................................81
15 LVDS Clock and Data Relationship ..............................................................................81
16 Panel Power Sequencing............................................................................................83
17 Integrated HDMI w/HDCP on Intel Centrino 2...............................................................84
18 SDVO Conceptual Block Diagram................................................................................85
19 Platform External Sensor ......................................................................................... 105
20 DMA Address Translation......................................................................................... 123
21 Ballout Diagram (Top View) Upper Left Quadrant ........................................................ 126
22 Ballout Diagram (Top View) Upper Right Quadrant ...................................................... 127
23 Ballout Diagram (Top View) Lower Left Quadrant ........................................................ 128
24 Ballout Diagram (Top View) Lower Right Quadrant ...................................................... 129
25 Mobile Intel 4 Series Express Chipset Drawing............................................................ 143
26 Ballout Diagram (Top View) Upper Left Quadrant ........................................................ 144
27 Ballout Diagram (Top View) Upper Right Quadrant ...................................................... 145
28 Ballout Diagram (Top View) Lower Right Quadrant ...................................................... 146
29 Ballout Diagram (Top View) Lower Left Quadrant ........................................................ 147
30 Intel GS45 Express Chipset Drawing ......................................................................... 149
Datasheet 9
Tables
1 Expansion Area Memory Segments............................................................................. 46
2 Extended System BIOS Area Memory Segments........................................................... 46
3 System BIOS Area Memory Segments......................................................................... 46
4 Pre-allocated Memory Example for 512-MB DRAM, 64-MB VGA, and 1-MB TSEG ............... 48
5 SMM Space Definition Summary................................................................................. 56
6 SMM Space Table..................................................................................................... 57
7 SMM Control Table ................................................................................................... 58
8 System Memory Organization Support for DDR2........................................................... 61
9 System Memory Organization Support for DDR3........................................................... 62
10 DDR2/DDR3 Dual-Channel Pin Connectivity ................................................................. 65
11 Concurrent SDVO/PCI Express Configuration Strap Controls........................................... 69
12 Configuration Mapping of SDVO Signals on the PCI Express Interface.............................. 71
13 Configuration Mapping of iHDMI Signals on the PCI Express Interface ............................. 72
14 Configuration Mapping of DisplayPort Signals on the PCI Express Interface ...................... 73
15 Concurrent DisplayPort (HDMI)/PCI Express Configuration Strap Controls ........................ 74
16 Analog Port Characteristics........................................................................................ 80
17 DisplayPort Co-Existence Table .................................................................................. 86
18 Display Port Co-Existence Table ................................................................................. 87
19 Targeted Memory State Conditions ............................................................................. 89
20 G-, S- and C-State Combinations ............................................................................... 92
21 D-, S-, and C-State Combinations .............................................................................. 92
22 Absolute Maximum Ratings ....................................................................................... 95
23 Thermal Design Power Number .................................................................................. 97
24 Power Characteristics ............................................................................................... 98
25 DDR2 (667/800 MTs) Power Characteristics............................................................... 100
26 DDR3 (800 /1066 MTs) Power Characteristics ............................................................ 101
27 V
CC
Auxiliary Power Characteristics........................................................................... 101
28 Signal Groups........................................................................................................ 107
29 DC Characteristics.................................................................................................. 111
30 CRT DAC DC Characteristics: Functional Operating Range
(V
CCA_CRT_DAC
= 3.3 V 5%)................................................................................... 117
31 TV DAC DC Characteristics: Functional Operating Range
(V
CCA_TV_DAC
[A,B,C]=3.3 V 5%) ........................................................................... 118
32 GMCH Strapping Signals and Configuration................................................................ 125
33 Mobile Intel 4 Series Express Chipset Ball List ............................................................ 130
34 Intel GS45 Chipset Pinlist ........................................................................................ 150
10 Datasheet
Revision History
Document
Number
Revision
Number
Description Date
320122 001 Initial Release July 2008
320122 002
Chapter 1
Added Section 1.3: GS45 Feature Support
Added Section 1.4: GL40 Feature Support
Chapter 10
Added GS45 and GL40 power characteristic data to Table 24
Added GS45 and GL40 current data to Table 24
Added GS45 current data to Table 27
Section 13.3: Added clocking information for GS45 and GL40
Section 16.4 and Section 16.5: Added Ballout and Signal Names
for GS45
Section 19.1.36: Added Configuration Register Description for
GS45 and GL40
August 2008
320122 003
Chapter 1
Section 1.3: Added GM47 Feature Support
Section 1.3.3: Updated GS45 Graphics Core Render Clock
Section 1.4.3: Updated GL40 Graphics Core Render Clock
Chapter 5
Section 5.1:Added GS45 memory-down support on two
channels
Chapter 10
Section 10.1: Added GM47, updated GS45 and GL40 TDP
numbers in Table 23
Section 10.1: Added GM47, GS45 I
VCC
and updated GL40
I
VCC_AXG
specification in Table 24
Section 10.1: Added GM47 and GL40 I
VCC_AXF
specification
in Table 27
Chapter 13
Section 13.3: Added GM47 GMCH Clock Frequency Support
Section 13.3: Added GL40 conversion stepping updates to
Clock Frequency Support
Chapter 16
Section 16.3: Updated Intel 4 Series Express Chipset
package drawing in Figure 25
Chapter 19
Section 19.1.36: Added GM47 GFX Software and DDR2
Capability and updated DDR3 and FSB Capability in CAPID
Register
Chapter 20
Section 20.4.4: Updated RST_EVNT definition in SLFRCS
Register
Chapter 21
Section 21.1.5: Added conversion A-1 stepping revision ID
in RID Register
Chapter 23
Section 23.1.1: Corrected Intel ME Identifier Register
default value
December 2008
Datasheet 11
320122 004
Chapter 1
Removed Section 1.3 GM47 Feature Support
Chapter 10
Section 10.1: Removed GM47 in Table 23
Section 10.1: Removed GM47 I
VCC
in Table 24
Section 10.1: Removed GM47 I
VCC_AXF
specification in
Table 27
Chapter 13
Section 13.3: Removed GM47 GMCH Clock Frequency
Support
Chapter 19
Section 19.1.36: Removed GM47 GFX Software and DDR2
Capability
January 2009
320122 005
Chapter 1
Section 1.1.1: Updated processor list for PM45
Section 1.2.1: Updated processor list for GM45
Section 1.2.2: Added DDR3 667 MHz support at FSB 667
MHz only for GM45
Section 1.3.1: Updated processor list for GS45
Section 1.3.4: Added ICH9 Support for GS45
Section 1.4.1: Updated processor list for GL40
Section 1.4.2: Added 800MHz support for DDR2/DDR3 and
DDR3 667 MHz support at FSB 667 MHz only for GL40
Section 1.4.5: Updated list of features not supported
Chapter 5
Section 5.1:Rearranged the contents and added a note that
mixed CAS latency memory combination is not supported
Section 5.1: Added DDR2 2 Gb memory support in Table 8
Section 5.1: Added DDR3 2 Gb memory support in Table 9
Chapter 6
Section 6.2: Updated configuration strap controls in
Table 15
Chapter 8
Section 8.4: Removed Embedded DP support in Table 17
Chapter 9
Removed Section 9.10 PWROK Timing Requirements for
Power-Up, Resume from S3
Removed Section 9.11 GFX VR Timing Requirements for
Power-Up, Resume from Sx
Chapter 10
Section 10.1: Updated GM45 I
VCC_AXG
specification in
Table 24
Chapter 13
Section 13.3: Removed GM47 GMCH Clock Frequency
Support, updated GM45 and GL40 Memory Clock Frequency
Support and added note
Chapter 19
Section 19.1.36: Removed 667 MHz Render Clock definition
from CAPID Register
February 2009
Document
Number
Revision
Number
Description Date
12 Datasheet
320122 006
Chapter 1
Section 1.3.1: Updated FSB Support for GS45
Section 1.5: Added GS40 Feature Support
Chapter 5
Section 5.1:Added GS40 memory support note
Chapter 10
Section 10: Added GS40 storage temperature and updated
notes in Table 22
Section 10.1: Added GS40 TDP numbers in Table 23
Section 10.1: Updated notes for GS40 Power
Characteristics in Table 24
Section 10.1: Updated notes for GS40 Vcc Auxiliary Power
Characteristics in Table 27
Chapter 12
Section 12: Updated signal groups for DC RSTIN#, PWROK,
and CL_PWROK in Table 28
Section 12.1: Added V
IL
and V
IH
and updated DC
Characteristics for CL_VREF, SM_PWROK, HDA interface in
Table 29
Chapter 13
Section 13.3: Added GS40 to GMCH Host/Memory/Graphics
Core Clock Frequency Support matrix
Chapter 19
Section 19.1.36: Added GS40 GFX Software Capability ID in
CAPID Register
June 2009
Document
Number
Revision
Number
Description Date
Datasheet 13
I ntroduction
1 I ntroduction
This document provides specifications for the Mobile Intel 4 Series Express Chipset
Family. In this document, the Mobile Intel 4 Series Express Chipset Family is referred to
as the GMCH.
The GMCH manages the flow of information between various components through four
main interfaces:
Front Side Bus (FSB)
System Memory Interface (DDR2/DDR3)
Graphics Interfaces (CRT, TV-Out, LVDS, SDVO, DisplayPort*, iHDMI* (DVI also)
and PCI Express Graphics)
Direct Management Interface (DMI)
Figure 1 provides a block diagram of the GMCH.
Figure 1. Block Diagram
USB
SIO/EC
TPM
IntelHigh
Definition Audio
SATA
CRT
LVDS
DMI
(x2/x4)
L
P
C
FSB
(667/800/1066 MHz)
TV-OUT
Mobile Intel
4 Series
Express
Chipset
Processor
82801 IBM
I/O Controller
Hub (ICH9M)
Discrete
Graphics
Memory
Memory
DDR2(667/800 MHz)
DDR3 (1066/800 MHz)
12 USB 2.0 Ports
6 PCI Express x1 Ports
WLAN/WiMAX
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Bus
SDVO
10/100 LCI
Controller Link 1
Controller
Link 0
GLCI
4 Serial ATA Ports
PCI Express* x16
iHDMI/DVI
DisplayPort*
2 SDVO Ports
2 HDMI/DVI Ports
3 DP Ports
33 MHz
LAN
I ntroduction
14 Datasheet
1.1 Intel PM45 Express Chipset Feature Support
1.1.1 Processor
Intel Core2 Extreme, Intel Core2 Quad, and Intel Core2 Duo mobile
processors based on the 45-nm process
667-MHz, 800-MHz and 1066-MHz FSB
Source synchronous double-pumped (2x) address
Source synchronous quad-pumped (4x) data
Support for Dynamic FSB Frequency Switching
Other key features are:
Support for Intel Trusted Execution Technology (Intel TXT) commands and
signaling
Support for Data Bus Inversion (DBI)
Support for Intel Virtualization Technology (Intel VT) for Directed I/O
(Intel VT-d) (DMA)
Support for Message Signaled Interrupt (MSI)
36-bit interface to addressing, allowing the CPU to access the entire 64 GB of
the GMCHs memory address space
12-deep, in-order queue to pipeline FSB commands
AGTL+ bus driver with integrated AGTL termination resistors
1.1.2 System Memory
Supports DDR2 and DDR3 SDRAM
Support for DDR2 at 667 MHz and 800 MHz
Support for DDR3 at 667, 800 and 1066 MHz
One SO-DIMM connector (or memory module) per channel
Two Memory Channel Configurations supported
Dual-channel Symmetric (with Interleaved access)
Dual-channel Asymmetric (with or without Intel Flex Memory Technology)
8-GB maximum memory support
64-bit wide per channel
256-Mb, 512-Mb, 1-Gb, and 2-Gb memory technologies supported
Support for x8 and x16 DDR2 and DDR3 devices
Support for DDR2/DDR3 On-Die Termination (ODT)
Supports partial writes to memory using data mask signals (DM)
No support for Fast Chip Select mode
No support for ECC
No support for 1N operation
1.1.3 Discrete Graphics Using PCI Express* Graphics Attach Port
One, 16-lane (x16) PCI Express port for external PCI Express-based graphics card
Datasheet 15
I ntroduction
1.1.4 Direct Management Interface (DMI)
Chip-to-chip interface between GMCH and ICH
Configurable as x2 or x4 DMI lanes
x2 and x4 lane-reversal support
DMI Polarity inversion support
2-GB/s (1 GB/s each direction), point-to-point interface to ICH
32-bit downstream address
DMI asynchronously coupled to core
APIC and MSI interrupt messaging support
Supports SMI, SCI and SERR error indication
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
1.1.5 Power Management
Supports ACPI 3.0
S-States: S0, S3, S4, S5
C-States: C0, C1/C1E, C2/C2E, C3, C4/C4E, Intel Enhanced Deeper Sleep and
Deep Power Down technology (code named C6) states
M-States: M0, M1, M-off
PCI Express Link States: L0, L0s, L1, L2/L3 ready, L3
H_CPUSLP# output
H_DPWR# support
Intel Rapid Memory Power Management (Intel RMPM)
Dynamic Memory Rank power-down
1.1.6 Thermal Management
Programmable Aux Trip point notification (via HW pin) support
Support for External Thermal Sensor
1.1.7 Intel Trusted Execution Technology (Intel TxT)
Memory protection from bus masters via No-DMA support (in a secure
environment)
1.1.8 Intel Virtualization Technology (Intel VT) DMA
DMA remapping support via a GMCH Remapping engine
Chipset support for hardware address translation GPA (Guest Physical Address) to
HPA (Host Physical Address)
Accelerated DMA translation performance via GMCH cache support
Protected Low-Memory Region (<4 GB) and High-Memory Region (>4 GB) to
securely store VMM data
I ntroduction
16 Datasheet
1.1.9 Intel Active Management Technology (Intel AMT) 4.0
The GMCH supports Intel Active Management Technology 4.0 (Intel AMT) with both
wired and wireless LAN support via a Controller Link interface to ICH for extended
manageability functionality.
An Intel AMT engine integrated within the GMCH combines hardware and software
solutions to provide:
Remote Asset Management
Remote Diagnosis and Repair
Remote Agent Presence
Wireless OOB Management
Circuit Breaker Network Isolation
Mobile Power Management Policies
3rd Party Non-Volatile Storage
Controller link is the Intel Management Engine (ME) link between the GMCH and ICH.
1.1.10 Integrated Trusted Platform Module (ITPM)
The GMCH supports an Integrated Trusted Platform Module (ITPM) 1.2 unit within the
Intel Management Engine subsystem of the platform. ITPM support can be enabled/
disabled via a strapping option.
The GMCH executes validated TPM firmware out of a portion of hardware isolated DDR
DRAM.
1.1.11 Package
1329-ball FCBGA
Package Size: 34 mm x 34 mm
Ball pitch: 0.7 mm
1.2 Intel GM45 Express Chipset Feature Support
All features supported by Intel PM45 Express Chipset are supported by Intel GM45
Express Chipset unless otherwise noted below. Additional features are listed below.
The GM variant can be enabled to support either integrated graphics or external
graphics. When external graphics is enabled, the x16 PCI Express Graphics attach port
is utilized, and the internal graphics ports are disabled.
1.2.1 Processor
Intel Pentium and Intel Celeron mobile processors on 45nm technology
Intel Celeron T1700, T1600, 585 and 575 processors on 65nm technology
1.2.2 System Memory
Support for DDR3 at 667MHz when FSB at 667MHz only
Datasheet 17
I ntroduction
1.2.3 PCI Express Graphics Attach Port
One 16-lane (x16) PCI Express port for external PCI Express-based graphics card
May also be configured as a PCI Express x1 port for video capture
1.2.4 Internal Graphics
Intel Gen 5.0 integrated graphics engine with ten, fully-programmable cores
533-MHz core render clock @ 1.05-V core voltage
Supports iHDMI/DVI, DP, TV-Out, LVDS, CRT and SDVO
Intel Dynamic Video Memory Technology (Intel DVMT 5.0)
Video Capture via x1 concurrent PCI Express port
PAVP (Protected Audio-Video Path) support for Protected Intel HD Audio (Video
and Audio) Playback
High performance MPEG-2 decoding
WMV9 (VC-1) and H.264 (AVC) support
Hardware acceleration for MPEG2 VLD/iDCT
Microsoft DirectX*10 support
Blu-ray* support @ 40 Mb/s
Hardware motion compensation
Intermediate Z in classic rendering
1.2.4.1 Dual-Channel LVDS
25-112-MHz single/dual-channel
Single channel LVDS interface support: 1 x 18 bpp OR 1 x 24 bpp (Type 1 only,
compatible with VESA LVDS color mapping)
Dual-channel LVDS interface support:2 x 18 bpp OR 2 x 24 bpp panel support
TFT panel type supported
Pixel dithering for 18-bit TFT panel to emulate 24-bpp true color displays
Panel Fitting. Panning and Center mode supported
Standard Panel Working Group (SPWG) v.3.5 specification compliant
Spread spectrum clocking support
Panel power sequencing support
Integrated PWM interface for LCD backlight inverter control
1.2.4.2 DisplayPort* (DP)
The GMCH supports three DP ports muxed on the PCI Express interface
1.62 Gb/s and 2.7 Gb/s
1, 2 or 4 data lanes
8b 10b coding
Hot-Plug detect support
HDCP support
I ntroduction
18 Datasheet
1.2.4.3 Integrated HDMI (iHDMI)*
DVI also supported on same interface
Single TMDS Link
8 bpc only supporting RGB - no YCrCb4:4:4 and YCrCb4:2:2 support
Data Island Packets including null, AVI Infoframe, audio samples and more
Video support for CEA modes 480i/p, 576i/p, 720p, 1080i/p and PC modes though
dot clock
HDMI Source only not a receiver device
HDCP support
Support for HDMI repeaters
Intel HD Audio support
Integrated Intel HD Audio codec
Dolby* AC3 compress, Dolby* Digital, Dolby* DTS (full support)
PCM audio support
1.2.4.4 SDVO Ports
Two SDVO ports supported
SDVO pins are muxed onto the PCI Express Graphics-attach port pins
DVI 1.0 support for External Digital Monitor
Downstream HDCP Support but no upstream HDCP support
Display Hot-Plug support
Supports appropriate external SDVO components (HDMI, DVI, LVDS, TV-Out)
I
2
C channel provided for control
1.2.4.5 Analog CRT
Integrated 300-MHz DAC
Analog monitor support up to QXGA
Support for CRT Hot-Plug
1.2.4.6 TV-Out
Macrovision* not supported
Overscaling
NTSC/PAL
Component, S-Video and Composite Output Interfaces
HDTV graphics mode support
Datasheet 19
I ntroduction
Graphics Display Adapter States: D0, D3
Intel Display Power Saving Technology (Intel DPST) 4.0
Graphics Render Standby Mode
Render Standby Voltages: RS2 (0.55 V)
Graphics Render Thermal Throttling
Support for Frame Buffer Compression 2 (FBC2)
1.3 Intel GS45 Express Chipset Feature Support
All features supported by the Intel GM45 Express chipset are supported by Intel GS45
Express chipset unless otherwise noted below. Additional features are listed below.
1.3.1 Processor
Intel Core2 Duo, Intel Core2 Solo and Intel Celeron mobile processors
based on the 45-nm process
Low power configuration: 800 MHz FSB support
High performance configuration: 800- and 1066- MHz FSB Support
1.3.2 Memory
Low-power configuration
Support for DDR2 at 667 MHz
High performance configuration
Support for DDR3 at 667 MHz, 800 MHz and 1066 MHz
Low-power configuration: 320-MHz core render clock at 1.05-V core voltage
High performance configuration: Same as Intel GM45 Express chipset
1.3.4 ICH Support
Support for ICH9M-SFF-Enhanced only
1.3.5 Package
1363 Ball FCBGA
Package Size: 27 mm x 25 mm
0.593-mm minimum ball pitch
I ntroduction
20 Datasheet
1.4 Intel GL40 Express Chipset Feature Support
All features supported by the Intel GM45 Express chipset are supported by Intel GL40
Express chipset unless otherwise noted below. Additional features are also listed below.
1.4.1 Processor
Intel Pentium and Intel Celeron mobile processors based on the 45-nm
process
Intel Celeron Processors T1700, T1600, 585 and 575
667 MHz and 800 MHz
1
FSB support
1.4.2 System Memory
Support for DDR3 at 667 MHz when FSB at 667 MHz only
Maximum memory supported: 4 GB
400-MHz core render clock at 1.05-V core voltage
1.4.4 ICH Support
Support for ICH9M (base) only
No support for
Intel DPST 4.0
Graphics Render Standby Modes
Intel
Display Refresh Rate Switching

FSB Dynamic Frequency Switching
1.4.6 Unsupported Features
Discrete Graphics using PCI Express Graphics Attach Port
ITPM
Intel VT DMA
Intel TxT
Intel AMT
1.5 Intel GS40 Express Chipset Feature Support
All features supported by the Intel GM45 Express chipset are supported by Intel GS40
Express chipset unless otherwise noted below. Additional features are also listed below.
Datasheet 21
I ntroduction
1.5.1 Processor
Intel Celeron mobile processor 723
800 MHz FSB support
1.5.2 System Memory
Support for DDR3 at 667 MHz when FSB at 667 MHz only
Maximum memory supported: 4 GB
400-MHz core render clock at 1.05-V core voltage
1.5.4 ICH Support
Support for ICH9M SFF Enhanced only
No support for
Intel DPST 4.0
Graphics Render Standby Modes
Intel
Display Refresh Rate Switching

FSB Dynamic Frequency Switching
1.5.6 Unsupported Features
Discrete Graphic s using PCI Express Graphics Attach Port
ITPM
Intel VT DMA
Intel TxT
Intel AMT
I ntroduction
22 Datasheet
1.6 Reference Documents

Document
Document
No./Location
Mobile Intel 4 Series Express Chipset Family Specification
Update
http://www.intel.com/design/
mobile/specupdt/
32012301.pdf
Intel Core2 Duo Mobile Processor and Intel Core2
Extreme Mobile Processor on 45nm Technology Datasheet
http://download.intel.com/
design/mobile/datashts/
32012001.pdf
Intel Core2 Duo Mobile Processor and Intel Core2
Extreme Mobile Processor on 45nm Technology Specification
Update
http://download.intel.com/
design/mobile/specupdt/
32012101.pdf
Intel I/O Controller Hub 9 (ICH9) Family Datasheet
http://www.intel.com/Assets/
PDF/datasheet/316972.pdf
Intel I/O Controller Hub 9 (ICH9) Family Specification Update
http://www.intel.com/Assets/
PDF/specupdate/316973.pdf
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0
http://www.pcisig.com/
specifications
PCI Express Specification 1.1 http://www.pcisig.com
Standard Panel Working Group (SPWG) v.3.5 Specification http://www.spwg.org/
JEDEC Double Data Rate 2 (DDR2) SDRAM Specification http://www.jedec.com
JEDEC Double Data Rate 3 (DDR3) SDRAM Specification http://www.jedec.com
PCI Express Specification 1.0a Mobile Graphics Low Power
Addendum to the PCI Express Base Specification Revision 1.0
http://www.pcisig.org
VESA Specification http://www.vesa.org
TIA/EIA-644 Standard http://www.tiaonline.org
Datasheet 23
Signal Description
2 Signal Description
This section describes the GMCH signals. These signals are arranged in functional
groups according to their associated interface. The following notations are used to
describe the signal type:
The signal description also includes the type of buffer used for the particular signal:
Note: System Address and Data Bus signals are logically inverted signals. The actual values
are inverted of what appears on the system bus. This must be considered and the
addresses and data bus signals must be inverted inside the GMCH. All processor control
signals follow normal convention: A 0 indicates an active level (low-voltage), and a 1
indicates an active level (high-voltage).
Note: All pins marked RESERVED should be left NC, unless otherwise specified.
2.1 Host Interface
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the host bus (V
TT
).
Notations Signal Type
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
Signal Description
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The GMCH integrates AGTL+ termination resistors, and
supports V
TT
=1.05 V.
PCI Express
PCI Express interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications. The buffers are not 3.3-V
tolerant. Refer to the PCIe specification.
CMOS CMOS buffers. 1.5-V tolerant.
HVCMOS High-voltage CMOS buffers. 3.3-V tolerant.
LVCMOS Low-voltage CMOS buffers. V
TT
tolerant.
COD CMOS Open Drain buffers. 3.3-V tolerant.
SSTL-1.8 Stub Series Termination Logic: These are 1.8-V capable buffers.
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
LVDS Low-Voltage Differential Signal Interface.
Ref Voltage reference signal.
Signal Description
24 Datasheet
2.1.1 Host Interface Signals
(Sheet 1 of 4)
Signal Name Type Description
H_A# [35:3]
I/O
AGTL+ 2X
Host Address Bus: HA# [35:3] connects to the processor
address bus. During processor cycles the HA# [35:3] are
inputs. The GMCH drives HA# [35:3] during snoop cycles on
behalf of PCI Express/Internal Graphics or ICH. HA# [35:3]
are transferred at 2x rate.
Note that the address is inverted on the processor bus.
H_ADS#
I/O
AGTL+
Host Address Strobe: The system bus owner asserts
H_ADS# to indicate the first of two cycles of a request
phase. The GMCH can also assert this signal for snoop cycles
and interrupt messages.
H_ADSTB# [1:0]
I/O
AGTL+ 2X
Host Address Strobe: HA# [31:3] connects to the
processor address bus. During processor cycles, the source
synchronous strobes are used to transfer HA# [35:3] and
HREQ# [4:0] at the 2x transfer rate.
H_AVREF
H_DVREF
I
A
Host Reference Voltage: Reference voltage input for the
Data, Address, and Common clock signals of the Host AGTL+
interface
H_BNR# I/O AGTL+
Host Block Next Request: Used to block the current
request bus owner from issuing a new request. This signal is
used to dynamically control the processor bus pipeline
depth.
H_BPRI#
O
AGTL+
Host Bus Priority Request: The GMCH is the only Priority
Agent on the system bus. It asserts this signal to get the
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the
H_LOCK# signal was asserted.
H_BREQ#
I/O
AGTL+
Host Bus Request: The GMCH pulls the processor bus
H_BREQ# signal low during H_CPURST#. The signal is
sampled by the processor on the active-to-inactive transition
of H_CPURST#.
H_BREQ# should be tri-stated after the hold time
requirement has been satisfied.
H_CPURST#
O
AGTL+
Host CPU Reset: The H_CPURST# pin is an output from the
GMCH. The GMCH asserts H_CPURST# while RSTIN# is
asserted and for approximately 1 ms after RSTIN# is
deasserted.
H_CPURST# allows the processor to begin execution in a
known state.
Strobe Address Bits
HADSTB#0 HA# [15:3], HREQ# [4:0]
HADSTB#1 HA# [35:16]
Datasheet 25
Signal Description
H_CPUSLP#
O
LVCMOS
Host CPU Sleep: When asserted in the Stop-Grant state,
causes the processor to enter the Sleep state. During Sleep
state, the processor stops providing internal clock signals to
all units, leaving only the Phase-Locked Loop (PLL) still
operating.
Processors in this state will not recognize snoops or
interrupts. (This is a CMOS type buffer with V
TT
- not 3.3 V.)
H_D# [63:0]
I/O
AGTL+ 4X
Host Data: These signals are connected to the processor
data bus. HD [63:0]# are transferred at 4x rate.
Note that the data signals are inverted on the processor bus
depending on the HDINV# [3:0] signals.
H_DBSY#
I/O
AGTL+
Host Data Bus Busy: Used by the data bus owner to hold
the data bus for transfers requiring more than one cycle.
H_DEFER#
O
AGTL+
Host Defer: Signals that the GMCH will terminate the
transaction currently being snooped with either a deferred
response or with a retry response.
H_DINV# [3:0]
I/O
AGTL+
Host Dynamic Bus Inversion: Driven along with the HD
[63:0]# signals. Indicates if the associated signals are
inverted or not. HDINV [3:0]# are asserted such that the
number of data bits driven electrically low (low-voltage)
within the corresponding 16-bit group never exceeds 8.
H_DPWR#
I/O
AGTL+
Host Data Power: Used by GMCH to indicate that a data
return cycle is pending within 2 H_CLK cycles or more.
Processor uses this signal during a read-cycle to activate the
data input buffers in preparation for H_DRDY# and the
related data.
H_DRDY#
I/O
AGTL+
Host Data Ready: Asserted for each cycle that data is
transferred.
H_DSTBP# [3:0]
H_DSTBN# [3:0]
I/O
AGTL+ 4X
Host Differential Host Data Strobes: The differential
source synchronous strobes are used to transfer HD [63:0]#
and HDINV# [3:0] at the 4x transfer rate.
(Sheet 2 of 4)
H_DINV# Data Bits
H_DINV#3 H_D# [63:48]
H_DINV#2 H_D# [47:32]
H_DINV#1 H_D# [31:16]
H_DINV#0 H_D# [15:0]
Strobe Data Bits
H_DSTBP#3, H_DSTBN#3 H_D# [63:48], H_DINV# [3]
Signal Description
26 Datasheet
H_HIT#
I/O
AGTL+
Host Hit: Indicates that a caching agent holds an
unmodified version of the requested line.
Also, driven in conjunction with H_HITM# by the target to
extend the snoop window.
H_HITM#
I/O
AGTL+
Host Hit Modified: Indicates that a caching agent holds a
modified version of the requested line and that this agent
assumes responsibility for providing the line.
Also, driven in conjunction with H_HIT# to extend the snoop
window.
H_LOCK#
I
AGTL+
Host Lock: All processor bus cycles sampled with the
assertion of H_LOCK# and H_ADS#, until the negation of
H_LOCK# must be atomic.
H_RCOMP
I/O
A
Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.
H_REQ# [4:0]
I/O
AGTL+ 2X
Host Request Command: Defines the attributes of the
request. H_REQ# [4:0] are transferred at 2x rate. Asserted
by the requesting agent during both halves of the Request
Phase. In the first half the signals define the transaction type
to a level of detail that is sufficient to begin a snoop request.
In the second half the signals carry additional information to
define the complete transaction type.
H_RS# [2:0]
O
AGTL+
Host Response Status: Indicates the type of response
according to the following the table:
H_SWING
I
A
Host Voltage Swing: These signals provide reference
voltages used by the H_RCOMP circuits.
H_TRDY#
O
AGTL+
Host Target Ready: Indicates that the target of the
processor transaction can enter the data transfer phase.
(Sheet 3 of 4)
HRS [2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit write back
111 Normal data response
Datasheet 27
Signal Description
2.2 Memory Interface
2.2.1 Memory Channel A Interface
THERMTRIP#
O
AGTL+
Connects between the Processor, GMCH and the ICH:
Assertion of THERMTRIP# (Thermal Trip) indicates the GMCH
junction temperature has reached a level beyond which
damage may occur. Upon assertion of THERMTRIP#, the
GMCH will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the GMCH core junction
temperature. To protect the GMCH, its core voltage (V
CC
)
must be removed following the assertion of THERMTRIP#.
Once activated, THERMTRIP# remains latched until RSTIN#
is asserted. While the assertion of the RSTIN# signal will
deassert THERMTRIP#, if the GMCHs junction temperature
remains at or above the trip level, THERMTRIP# will again be
asserted.
(Sheet 1 of 2)
SA_BS [2:0]
O
SSTL-1.8/1.5
Bank Select: These signals define which banks are selected
within each SDRAM rank.
SA_WE#
O
SSTL-1.8/1.5
Write Enable Control Signal: Used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM
commands.
SA_RAS#
O
SSTL-1.8/1.5
RAS Control Signal: Used with SA_CAS# and SA_WE#
(along with SA_CS#) to define the SDRAM commands.
SA_CAS#
O
SSTL-1.8/1.5
CAS Control Signal: Used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SDRAM commands.
SA_DM [7:0]
O
SSTL-1.8/1.5
2x
Data Mask: These signals are used to mask individual bytes
of data in the case of a partial write, and to interrupt burst
writes.
When activated during writes, the corresponding data groups
in the SDRAM are masked. There is one SA_DM [7:0] for
every data byte lane.
SA_DQS [7:0]
I/O
SSTL-1.8/1.5
2x
Data Strobes: SA_DQS [7:0] and its complement signal
group make up a differential strobe pair. The data is captured
at the crossing point of SA_DQS [7:0] and its SA_DQS
[7:0]# during read and write transactions.
SA_DQS# [7:0]
I/O
SSTL-1.8/1.5
2x
Data Strobe Complements: These are the complementary
strobe signals.
SA_DQ [63:0]
I/O
SSTL-1.8/1.5
2x
Data Bus: Channel A data signal interface to the SDRAM
data bus.
SA_MA [14:0]
O
SSTL-1.8/1.5
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
(Sheet 4 of 4)
Signal Description
28 Datasheet
2.2.2 Memory Channel B Interface
SA_CK [1:0]
O
SSTL-1.8/1.5
SDRAM Differential Clock: Channel A SDRAM Differential
Clock signal-pair.
The crossing of the positive edge of SM_CKx and the
negative edge of its complement SM_CKx# are used to
sample the command and control signals on the SDRAM.
SA_CK# [1:0]
O
SSTL-1.8/1.5
SDRAM Inverted Differential Clock: Channel A SDRAM
Differential Clock signal-pair complement.
SA_CKE [1:0]
O
SSTL-1.8/1.5
Clock Enable: (1 per Rank) used to:
Initialize the SDRAMs during power-up
Power-down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh during
STR.
SA_CS# [1:0]
O
SSTL-1.8/1.5
Chip Select: (1 per Rank): Used to select particular SDRAM
components during the active state. There is one Chip Select
for each SDRAM rank.
SA_ODT [1:0]
O
SSTL-1.8/1.5
On Die Termination: Active Termination Control.
(Sheet 1 of 2)
SB_BS [2:0]
O
SSTL-1.8/1.5
Bank Select: These signals define which banks are selected
within each SDRAM rank.
SB_WE#
O
SSTL-1.8/1.5
Write Enable Control Signal: Used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM
commands.
SB_RAS#
O
SSTL-1.8/1.5
RAS Control Signal: Used with SB_CAS# and SB_WE#
(along with SB_CS#) to define the SDRAM commands.
SB_CAS#
O
SSTL-1.8/1.5
CAS Control Signal: Used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SDRAM commands.
SB_DM [7:0]
O
SSTL-1.8/1.5
2x
Data Mask: These signals are used to mask individual bytes
of data in the case of a partial write, and to interrupt burst
writes.
When activated during writes, the corresponding data groups
in the SDRAM are masked. There is one SB_DM [7:0] for
every data byte lane.
SB_DQS# [7:0]
I/O
SSTL-1.8/1.5
2x
Data Strobe Complements: These are the complementary
strobe signals.
SB_DQS [7:0]
I/O
SSTL-1.8/1.5
2x
Data Strobes: SB_DQS [7:0] and its complement signal
group make up a differential strobe pair. The data is captured
at the crossing point of SB_DQS [7:0] and its SB_DQS
[7:0]# during read and write transactions.
(Sheet 2 of 2)
Datasheet 29
Signal Description
2.2.3 Memory Reference and Compensation
SB_MA [14:0]
O
SSTL-1.8/1.5
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SB_DQ [63:0]
I/O
SSTL-1.8/1.5
2x
Data Bus: Channel B data signal interface to the SDRAM
data bus.
SB_CK [1:0]
O
SSTL-1.8/1.5
SDRAM Differential Clock: Channel B SDRAM Differential
Clock signal-pair. The crossing of the positive edge of
SM_CKx and the negative edge of its complement SM_CKx#
are used to sample the command and control signals on the
SDRAM.
SB_CK# [1:0]
O
SSTL-1.8/1.5
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential Clock signal-pair complement.
SB_CKE [1:0]
O
SSTL-1.8/1.5
Clock Enable (1 per Rank): Used to initialize the SDRAMs
during power-up, power-down SDRAM ranks, place all
SDRAM ranks into and out of self-refresh during STR.
SB_CS# [1:0]
O
SSTL-1.8/1.5
Chip Select (1 per Rank): Used to select particular SDRAM
components during the active state. There is one Chip Select
for each SDRAM rank.
SB_ODT [1:0]
O
SSTL-1.8/1.5
On Die Termination: Active Termination Control
SM_RCOMP
I
A
System Memory Impedance Compensation
SM_RCOMP#
I
A
System Memory Impedance Compensation
SM_RCOMP_VO
H
I
A
System Memory Pull-up Impedance Compensation
SM_RCOMP_VOL
I
A
System Memory Pull-down Impedance Compensation
SM_VREF
I
A
System Memory Reference Voltage: For all data and data
strobe signals.
SM_REXT
IO
A
Constant Circuit Reference for Clocks
(Sheet 2 of 2)
Signal Description
30 Datasheet
2.3 PCI Express-Based Graphics Interface Signals
Unless otherwise specified, these signals are AC coupled.
2.3.1 DisplayPort (DP), iHDMI and SDVO on PCI Express Based
Graphics
The DP, iHDMI and SDVO interfaces are multiplexed on to the GMCH PCI Express
Interface. See Chapter 6 for more details.
2.4 DMI GMCH to ICH Serial Interface
PEG_COMPI
I
A
PCI Express Graphics Input Current Compensation
PEG_COMPO
I
A
PCI Express Graphics Output Current and Resistance
Compensation
PEG_RX [15:0]
PEG_RX# [15:0]
I
PCI Express*
PCI Express Graphics Receive Differential Pair
PEG_TX [15:0]
PEG_TX# [15:0]
O
PCI Express
PCI Express Graphics Transmit Differential Pair
DMI_RXN [3:0]
DMI_RXP [3:0]
I
PCI Express*
DMI Input from ICH: Direct Media Interface receive
differential pair.
DMI_TXN [3:0]
DMI_TXP [3:0]
O
PCI Express
DMI Output to ICH: Direct Media Interface transmit
differential pair.
Datasheet 31
Signal Description
2.5 Integrated Graphics Interface Signals
2.5.1 CRT DAC Signals
2.5.2 Analog TV-out Signals
CRT_RED
O
A
RED Analog Video Output: This signal is a CRT analog
video output from the internal color palette DAC.
CRT_GREEN
O
A
GREEN Analog Video Output: This signal is a CRT
analog video output from the internal color palette DAC.
CRT_BLUE
O
A
BLUE Analog Video Output: This signal is a CRT analog
video output from the internal color palette DAC.
CRT_TVO_IREF
O
A
Resistor Set and TV Reference Current: Set point
resistor for the internal color palette DAC and TV
reference current.
CRT_VSYNC
O
HVCMOS
CRT Vertical Synchronization: This signal is used as
the vertical sync (polarity is programmable).
CRT_HSYNC
O
HVCMOS
CRT Horizontal Synchronization: This signal is used as
the horizontal sync (polarity is programmable) or sync
interval.
CRT_IRTN
O
A
Resistor Set: Set point resistor for the internal color
palette DAC.
TV_DCONSEL
[1:0]
O
COD
TV D-connector Select: Selects appropriate full-voltage
discernment signals for TV-out D-connector.
TVA_DAC
O
A
TVDAC Channel A Output: Can map to any one of the
following:
Composite Video, Blank, and Sync (CVBS)
Component Pb
TVB_DAC
O
A
TVDAC Channel B Output: Can map to any one of the
following:
Svideo - Y
Component Y
TVC_DAC
O
A
TVDAC Channel C Output: Can map to any one of the
following:
Svideo - C
Component Pr
TV_RTN
O
A
Current Return for TV DAC Channel A/B/C: Connect
to ground on board
Signal Description
32 Datasheet
2.5.3 LVDS Signals
LDVS Channel A
LVDSA_CLK
O
LVDS
LVDS Channel A differential clock output positive
LVDSA_CLK#
O
LVDS
LVDS Channel A differential clock output negative
LVDSA_DATA# [3:0]
O
LVDS
LVDS Channel A differential data output negative
LVDSA_DATA [3:0]
O
LVDS
LVDS Channel A differential data output positive
LDVS Channel B
LVDSB_CLK
O
LVDS
LVDS Channel B differential clock output positive
LVDSB_CLK#
O
LVDS
LVDS Channel B differential clock output negative
LVDSB_DATA# [3:0]
O
LVDS
LVDS Channel B differential data output negative
LVDSB_DATA [3:0]
O
LVDS
LVDS Channel B differential data output positive
Panel Power and Backlight Control
L_BKLT_CTRL
O
HVCMOS
Panel Backlight Brightness Control: Panel brightness
control.
This signal is also called VARY_BL in the CPIS specification
and is used as the PWM Clock input signal.
L_BKLT_EN
O
HVCMOS
LVDS Backlight Enable: Panel backlight enable control.
This signal is also called ENA_BL in the CPIS specification
and is used to gate power into the backlight circuitry.
L_VDD_EN
O
HVCMOS
LVDS Panel Power Enable: Panel power control enable
control.
This signal is also called VDD_DBL in the CPIS specification
and is used to control the VDC source to the panel logic.
LVDS Reference Signals
LVDS_IBG
I/O
Ref
LVDS Reference Current
LVDS_VBG
O
A
Leave as NC
LVDS_VREFH
I
Ref
Must Be Connected to Ground
LVDS_VREFL
I
Ref
Must Be Connected to Ground
Datasheet 33
Signal Description
2.5.4 Display Data Channel (DDC) and GMBUS Support
2.6 Intel High Definition Audio (Intel HD Audio)
Signals
CRT_DDC_CLK
I/O
COD
CRT DDC Clock Monitor Control Support
CRT_DDC_DATA
I/O
COD
CRT DDC Data Monitor Control Support
L_CTRL_CLK
I/O
COD
Control Signal (Clock) for External SSC clock chip control
optional
L_CTRL_DATA
I/O
COD
Control signal (data) for External SSC clock chip control
optional
L_DDC_CLK
I/O
COD
EDID support for flat panel display
L_DDC_DATA
I/O
COD
EDID support for flat panel display
SDVO_CTRLCLK
I/O
COD
HDMI Port B Control Clock (This pin is shared with SDVO)
SDVO_CTRLDATA
I/O
COD
HDMI Port B Control Data (This pin is shared with SDVO)
DDPC_CTRLCLK
I/O
COD
HDMI Port C Control Clock
DDPC_CTRLDATA
I/O
COD
HDMI Port C Control Data
HDA_SDO
I
CMOS
Intel HD Audio Serial Data Input to GMCH Audio HW:
Driven by Intel HD Audio controller.
HDA_SDI
I/O
CMOS
Point-to-Point ICH Intel HD Audio Serial Response Output
HDA_RST#
I
CMOS
Global Intel HD Audio Link Reset
HDA_BCLK
I
CMOS
Global Intel HD Audio 24.00-MHz clk
HDA_SYNC
I
CMOS
Global 48-kHz Frame Sync and Inbound Tag Signal:
SYNC is sourced from the Intel HD Audio controller and input
to GMCH Audio HW.
Signal Description
34 Datasheet
2.7 Intel Management Engine Interface
(Intel MEI) Signals
Note: The signals below are used as the Intel Management Engine Interface (Intel MEI)
between the GMCH and the ICH. For details on implementing Intel Management Engine
on the platform, please see the Platform Intel ME-EC Interaction Specification
document.
2.8 PLL Signals
CL_CLK
I/O
GTL
Controller Link Bi-Directional Clock
CL_DATA
I/O
GTL
Controller Link Bi-Directional Data
CL_RST#
I
GTL
Controller Link Reset
CL_VREF
I
A
External Reference Voltage for Controller Link Input Buffers
CL_PWROK
I
HVCMOS
Intel Management Engine/Controller Link Power OK
(Sheet 1 of 2)
DPLL_REF_CLK
I
Diff Clk
Display PLLA Differential Clock In: 96 MHz
Display PLL Differential Clock In, no SSC support
DPLL_REF_CLK#
I
Diff Clk
Display PLLA Differential Clock In Complement:
Display PLL Differential Clock In Complement - no SSC
support.
DPLL_REF_SSCLK I
Diff Clk
Display PLLB Differential Clock In: 100 MHz
Optional Display PLL Differential Clock In for SSC support
NOTE: Differential Clock input for optional SSC support for
LVDS display.
DPLL_REF_SSCLK# I
Diff Clk
Display PLLB Differential Clock In Complement:
Optional Display PLL Differential Clock In Complement for
SSC support.
NOTE: Differential Clock input for optional SSC support for
LVDS display.
HPLL_CLK
I
Diff Clk
Differential Host Clock In:
Differential clock input for the Host PLL. Used for phase
cancellation for FSB transactions. This clock is used by all of
the GMCH logic that is in the Host clock domain. Also used to
generate core and system memory internal clocks. This is a
low-voltage differential signal and runs at the FSB data
rate.
Datasheet 35
Signal Description
2.9 Reset and Miscellaneous Signals
HPLL_CLK#
I
Diff Clk
Differential Host Clock Input Complement
PEG_CLK
I
Diff Clk
Differential PCI Express Based Graphics/DMI Clock In:
These pins receive a differential 100-MHZ Serial Reference
clock from the external clock synthesizer. This clock is used to
generate the clocks necessary for the support of PCI Express.
PEG_CLK#
I
Diff Clk
Differential PCI Express Based Graphics/DMI Clock In
Complement
(Sheet 1 of 2)
CLKREQ#
O
COD
External Clock Request: GMCH drives CLKREQ# to
control the PCI Express differential clock input to itself.
GFX_VID [4:0]
O
HVCMOS
Voltage ID to Support Graphics Render Standby
Mode
GFX_VR_EN
O
HVCMOS
VR Enable Signal to Support Graphics Render
Standby Mode
ICH_SYNC#
O
HVCMOS
ICH Synchronization: Asserted to synchronize with ICH
on faults. ICH_SYNC# must be connected to ICHs
MCH_SYNC# signal.
PM_SYNC#
I
HVCMOS
Power Management Sync: Used to indicate a Cx state
transition between ICH and GMCH.
DPRSLPVR
I
HVCMOS
Deeper Sleep - Voltage Regulator: Deeper Sleep
Voltage signal from ICH.
PM_DPRSTP#
I
LVCMOS
Deeper Sleep State: Deeper Sleep State signal coming
from the ICH.
PM_EXT_TS# [1:0]
I
HVCMOS
External Thermal Sensor Input: If the system
temperature reaches a dangerously high value then this
signal can be used to trigger the start of system memory
throttling.
SM_PWROK
I
CMOS
DDR3 Power Good Monitor: Connected to V
SS
in DDR2.
Driven by platform logic for DDR3.
SM_DRAMRST#
O
SSTL-1.5
DDR3 DRAM Reset: Reset signal from GMCH to DRAM
devices. One for all channels or SO-DIMMs. Used only in
DDR3 mode.
PWROK
I
HVCMOS
Power OK: Indication to the GMCH that core power is
stable. This input buffer is 3.3-V tolerant.
RSTIN#
I
HVCMOS
Reset In: When asserted this signal will asynchronously
reset the GMCH logic. This signal is connected to the
PLTRST# output of the ICH.
This input has a Schmitt trigger to avoid spurious resets.
This input buffer is 3.3-V tolerant.
(Sheet 2 of 2)
Signal Description
36 Datasheet
2.10 Non-Critical to Function (NCTF)
Non-Critical To Function (NCTF) solder balls on packages can improve the overall
package-to-board solder joint strength and reliability.
Ball locations/signal ID's followed with the suffix of NCTF have been designed into the
package footprint to enhance the package to board solder joint strength/reliability of
this product by absorbing some of the stress introduced by the Characteristic Thermal
Expansion (CTE) mismatch of the die to package interface.
Caution: Where board stresses are excessive, the NCTF balls may crack partially or completely.
However, cracks in the NCTF balls will have no impact to our product performance or
reliability. These balls have been added primarily to serve as stress absorbers.
2.11 Power and Ground
TSATN#
O
AGTL+
Thermal Sensor Aux Trip Notification: Output from the
GMCH to the EC indicating the Aux2 trip point (SW
programmable) has been crossed.
JTAG_TDI
I
CMOS
Intel Management Engine JTAG Test Data Input
JTAG_TDO
I/O
CMOS
Intel Management Engine JTAG Test Data Output
JTAG_TCK
I
CMOS
Intel Management Engine JTAG Test Clock
JTAG_TMS
I
CMOS
Intel Management Engine JTAG Test Mode Select
NC NC No Connects: This signals should be left as no connects.
(Sheet 2 of 2)
(Sheet 1 of 3)
Voltage Ball Name Description
Host
1.05 VTT Host Interface I/O Voltage
1.05 VTTLF
These balls are internally connected to power and
require decoupling capacitors.
1.05 VCC_AXF Host Interface I/O and HSIO Voltage
System Memory
1.5/1.8 VCC_SM I/O Voltage
1.5/1.8 VCC_SM/NC I/O Voltage - May be left NC on DDR2 motherboards
1.5/1.8 VCC_SM_LF
These balls are internally connected to power and
require a decoupling capacitor.
1.5/1.8 VCC_SM_CK Clock I/O Voltage
1.05 VCCA_SM I/O Logic and DLL Voltage
Datasheet 37
Signal Description
1.05 VCCA_SM_CK Clock Logic Voltage
PCI Express* Based Graphics/DMI
1.05 VCC_PEG
Analog, I/O Logic, and Term Voltage for PCI Express*
Based Graphics
1.5 VCCA_PEG_BG Band Gap Voltage for PCI Express Based Graphics
Ground VSSA_PEG_BG Band Gap Ground for PCI Express Based Graphics
1.05 VCC_DMI TX Analog and Termination Voltage for DMI
PLL
1.05 VCCA_HPLL Host PLL Analog Supply
1.05 VCCD_HPLL Host PLL Digital Supply
1.05 VCCA_MPLL MPLL Analog Circuits
1.05 VCCA_DPLLA Display A PLL Power Supply
1.05 VCCA_DPLLB Display B PLL Power Supply
1.05 VCCA_PEG_PLL Analog PLL Voltage for PCI Express Based Graphics
1.05 VCCD_PEG_PLL Digital PLL Voltage for PCI Express Based Graphics
High-voltage
3.3 VCC_HV HV buffer Power Supply
CRT
3.3 VCCA_CRT_DAC Analog Power Supply
1.5 VCCD_QDAC
Quiet Digital Power Supply (same as VCCD_QDAC for
TV)
LVDS
1.8 VCCD_LVDS Digital Power Supply
1.8 VCC_TX_LVDS I/O Power Supply
1.8 VCCA_LVDS Analog Power Supply
Ground VSSA_LVDS Analog Ground
TV
1.5 VCCD_TVDAC TV DAC Power Supply
3.3 VCCA_TV_DAC TVDAC IO Voltage
1.5 VCCD_QDAC
Quiet Digital TV DAC Power Supply (Shared with
CRTDAC)
3.3 VCCA_DAC_BG TV DAC Band Gap Power
Ground VSSA_DAC_BG TV DAC Band Gap Ground
Intel HD Audio
1.5 VCC_HDA Intel HD Audio Power Supply
Intel Management Engine
1.05 VCC Intel Management Engine voltage is tied to V
CC
(Sheet 2 of 3)
Signal Description
38 Datasheet

Core
1.05 VCC Core Chipset Voltage Supply
1.05 (Nominal) VCC_AXG Graphics Voltage Supply
1.05 VCC_AXG_SENSE GFX Voltage Supply Sense Signal
Ground VSS_AXG_SENSE V
SS
Sense Signal
Ground VSS Ground
Ground VSS_SCB
Sacrificial Corner Balls for Improved Package
Reliability
(Sheet 3 of 3)
Datasheet 39
Host I nterface
3 Host I nterface
3.1 FSB Source Synchronous Transfers
The GMCH supports the Intel Core 2 Duo mobile processor subset of the Enhanced
Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is
used for the address and data signals. The address signals are double pumped and a
new address can be generated every other bus clock. At bus clock speeds of 166 MHz,
200 MHz and 266 MHz, address signals run at 667 MT/s, 800 MT/s and 1066 MT/s,
which amounts to a maximum address queue rate of 83, 100 and 133 Mega-addresses/
sec, respectively. Data signals are quad pumped and an entire 64-B cache line can be
transferred in two bus clocks.
At 166-MHz, 200-MHz and 266-MHz bus clocks, data signals run at 667 MT/s, 800 MT/
s and 1066 MT/s for a maximum bandwidth of 5.3 GB/s, 6.4 GB/s and 8.5 GB/s,
respectively.
3.2 FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions. The GMCH
has a 12 deep IOQ.
3.3 FSB OOQ Depth
The GMCH supports only one outstanding deferred transaction on the FSB.
3.4 FSB AGTL+ Termination
The GMCH integrates AGTL+ termination resistors on die.
3.5 FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving
data from the processor. DBI limits the number of data signals that are driven to a low-
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the GMCH. H_DINV [3:0]# indicate if the corresponding 16 bits of data
are inverted on the bus for each quad pumped data phase:
Whenever the processor or the GMCH drives data, each 16-bit segment is analyzed. If
there are more than eight (out of sixteen) signals driven low on the H_D# bus, a
corresponding H_DINV# signal is asserted. As a result, the data is inverted prior to
H_DINV# [3:0] Data Bits
H_DINV#0 H_D# [15:0]
H_DINV#1 H_D# [31:16]
H_DINV#2 H_D# [47:32]
H_DINV#3 H_D# [63:48]
Host I nterface
40 Datasheet
being driven on the bus. Whenever the processor or the GMCH receives data, it
monitors H_DINV# [3:0] to determine if the corresponding data segment should be
inverted.
3.6 FSB Interrupt Overview
The Intel Core 2 Duo mobile processor and Intel Core 2 Extreme mobile processor
support FSB interrupt delivery, but do not support the APIC serial bus interrupt
delivery mechanism. Interrupt related messages are encoded on the FSB as Interrupt
Message Transactions. FSB interrupts may originate from the CPU(s) on the FSB, or
from a downstream device on the DMI or PCI Express Graphics Attach. In the latter
case, the GMCH drives the Interrupt Message Transaction on the FSB.
In the IOxAPIC environment, an interrupt is generated from the IOxAPIC to a processor
in the form of an upstream Memory Write. The ICH contains IOxAPICs, and its
interrupts are generated as upstream DMI Memory Writes. A PCI device may generate
an interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the
IOxAPIC. The MSI may be directed to the IOxAPIC. The IOxAPIC in turn generates an
interrupt as an upstream DMI Memory Write. Alternatively, the MSI may directly route
to the FSB. The target of an MSI depends on the address of the interrupt Memory
Write. The GMCH forwards upstream DMI and PCI Express Graphics Attach low-priority
Memory Writes to address 0FEEx_xxxxh to the FSB as Interrupt Message Transactions.
The GMCH also broadcasts EOI cycles generated by a processor downstream to the PCI
Express Port and DMI interfaces.
3.7 APIC Cluster Mode Support
APIC Cluster Mode support is required for backwards compatibility with existing
software, including various operating systems. For example, beginning with Microsoft
Windows* 2000 operating system, there is a mode (boot.ini) that allows an end-user to
enable the use of cluster addressing support of the APIC.
3.8 FSB Dynamic Frequency Switching
Dynamic FSB frequency switching effectively reduces the internal bus clock frequency
in half to further decrease the minimum processor operating frequency. This feature
does not entail a change in the external bus signal (BCLK) frequency. Instead, both the
processor and GMCH internally lower their BCLK reference frequency to 50% of the
externally visible frequency. The down-shift and up-shift transitions are done following
a handshake between the processor and chipset.

Datasheet 41
System Address Map
4 System Address Map
The GMCH supports up to 64 GB of addressable memory space and 64 KB+3 of
addressable I/O space. There is a programmable memory address space under the 1-
MB region, which is divided into regions that can be individually controlled with
programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
This section specifies how the memory space is partitioned and what the separate
memory regions are used for I/O address space has simpler mapping and is explained
in Section 4.10.
Note: In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI. The exception to this rule is VGA ranges, which may be mapped to
PCI Express, DMI, or to the internal graphics device (IGD).
In the absence of more specific references, cycle descriptions referencing PCI should be
interpreted as the DMI/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The GMCH
does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable
DRAM). The TOLUD register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
Device0
EPBAR Egress port registers. Necessary for setting up VC1 as an isochronous
channel using time based weighted round robin arbitration. (4-KB window)
MCHBAR Memory mapped range for internal GMCH registers.
PCIEXBAR Flat memory-mapped address spaced to access device
configuration registers. This mechanism can be used to access PCI
configuration space (0-FFh) and extended configuration space (100h-FFFh) for
PCI Express devices. This enhanced configuration access mechanism is defined
in the PCI Express specification. (64-MB, 128-MB, or 256-MB window)
DMIBAR This window is used to access registers associated with the Direct
Media Interface (DMI) register memory range. (4-KB window)
GGC GMCH graphics control register. Used to select the amount of main
memory that is pre-allocated to support the internal graphics device in VGA
(non-linear) and Native (linear) modes. (0 to 64-MB options)
Device 1, Function 0:
MBASE1/MLIMIT1 PCI Express port non-prefetchable memory access window
PMBASE1/PMLIMIT1 PCI Express port prefetchable memory access window
(PMUBASE/PMULIMIT) - are applicable for 36-bit SKUs
IOBASE1/IOLIMIT1 PCI Express port IO access window
MMADR IGD registers and internal graphics instruction port. (512-KB
window)
IOBAR I/O access window for internal graphics. Through this window
address/data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be accessed.
Note: This allows accessing the same registers as MMADR. In addition, the IOBAR can be
used to issue writes to the GTTADR table.
System Address Map
42 Datasheet
GMADR Internal graphics translation window. (256-MB window)
GTTADR Internal graphics translation table location. (256-KB window)
MMADR Function 1 IGD registers and internal graphics instruction port.
(512-KB window)
EPHECIBAR - Function 0 HECI memory mapped registers (16-B window)
EPHECI2BAR - Function 0 HECI memory mapped registers (16-B window)
EPKTBAR - Function 3 Keyboard and Text IO space (8-B window)
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designers responsibility to limit memory population so that
adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped
space, and APIC memory space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given
priority.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of memory (register TOLUD)
are DMI to PCI Express VGA range writes. Note that peer to peer cycles to the
Internal Graphics VGA range are not supported.
Figure 2 represents system memory address map in a simplified form.
Datasheet 43
System Address Map
NOTE: BARs mapped to the REMAPLIMIT-64 GB space can also be mapped to the TOLUD-4 GB space. GMCH
variants not supporting 36-bit addressing will require these BARs to be mapped to the TOLUD-4 GB space.
Figure 2. System Address Ranges
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System Address Map
44 Datasheet
4.1 Legacy Address Range
This area is divided into the following address regions:
0 - 640 KB MS-DOS* Area
640 - 768 KB Legacy Video Buffer Area
768 - 896 KB in 16-KB sections (total of eight sections) Expansion Area
896 - 960 KB in 16-KB sections (total of four sections) Extended System BIOS
Area
960 KB - 1 MB - Memory System BIOS Area
Figure 3. Microsoft MS-DOS* Legacy Address Range
Microsoft
MS-DOS* Area
640 KB
Legacy Video Area (SMM Memory)
128 KB
Expansion Area
128 KB (8 x 16 KB)
Extended SystemBIOS (Lower)
64 KB (4 x 16 KB)
SystemBIOS (Upper)
64 KB
0000_0000h
000F_FFFFh
000A_0000h
000C_0000h
000E_0000h
000F_0000h
000E_FFFFh
000D_FFFFh
000B_FFFFh
0009_FFFFh
640 KB
0
768 KB
896 KB
960 KB
1 MB
Datasheet 45
System Address Map
4.1.1 MS-DOS Range (0000_0000h 0009_FFFFh)
The MS-DOS area is 640 KB (0000_0000h to 0009_FFFFh) in size and is always
mapped to the main memory controlled by the GMCH.
4.1.2 Legacy Video Area (000A_0000h to 000B_FFFFh)
The legacy 128-KB VGA memory range, frame buffer, (000A_0000h to 000B_FFFFh)
can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI. The
appropriate mapping depends on which devices are enabled and the programming of
the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is
constant. The GMCH always decodes internally mapped devices first. Internal to the
GMCH, decode precedence is always given to IGD. The GMCH always positively decodes
internally mapped devices, namely the IGD and PCI Express. Subsequent decoding of
regions mapped to PCI Express or the DMI depends on the Legacy VGA configuration
bits (VGA Enable and MDAP). This region is also the default for SMM space.
4.1.2.1 Compatible SMRAM Address Range (000A_0000h to 000B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at 000A 0000h to 000B FFFFh. Non-SMM-mode
processor accesses to this range are considered to be to the Video Buffer Area as
described above. PCI Express and DMI originated cycles to enabled SMM space are not
allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the
VGA device. PCI Express and DMI initiated cycles are attempted as peer cycles, and will
master abort on PCI if no external VGA device claims them.
4.1.2.2 Monochrome Adapter (MDA) Range (000B_0000h to 000B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,
or the DMI (depending on configuration bits). Since the monochrome adapter may be
mapped to any one of these devices, the GMCH must decode cycles in the MDA range
(000B_0000h to 000B_7FFFh) and forward either to IGD, PCI Express, or the DMI. This
capability is controlled by a VGA steering bits and the legacy configuration bit (MDAP
bit). In addition to the memory range B0000h to B7FFFh, the GMCH decodes IO cycles
at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either IGD, PCI
Express, and/or the DMI.
4.1.3 Expansion Area (000C_0000h to 000D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h 000D_FFFFh) is divided into eight,
16-KB segments. Each segment can be assigned one of four Read/Write states: read-
only, write-only, read/write, or disabled. Typically, these blocks are mapped through
GMCH and are subtractively decoded to ISA space. Memory that is disabled is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
System Address Map
46 Datasheet
4.1.4 Extended System BIOS Area (000E_0000h to 000E_FFFFh)
This 64-KB area (000E_0000h to 000E_FFFFh) is divided into four, 16-KB segments.
Each segment can be assigned independent read and write attributes so it can be
mapped either to main DRAM or to DMI. Typically, this area is used for RAM or ROM.
Memory segments that are disabled are not remapped elsewhere.
DRAM.
4.1.5 System BIOS Area (000F_0000h to 000F_FFFFh)
This area is a single 64-KB segment (000F_0000h 000F_FFFFh). This segment can be
assigned read and write attributes. It is by default (after reset) Read/Write disabled
and cycles are forwarded to DMI. By manipulating the Read/Write attributes, the GMCH
can shadow the BIOS into the main DRAM. When disabled, this segment is not
remapped.
DRAM.
Table 1. Expansion Area Memory Segments
Memory Segments Attributes Comments
000C_0000h to 000C_3FFFh W/R Add-on BIOS
000C_4000h to 000C_7FFFh W/R Add-on BIOS
000C_8000h to 000C_BFFFh W/R Add-on BIOS
000C_C000h to 000C_FFFFh W/R Add-on BIOS
000D_0000h to 000D_3FFFh W/R Add-on BIOS
000D_4000h to 000D_7FFFh W/R Add-on BIOS
000D_8000h to 000D_BFFFh W/R Add-on BIOS
000D_C000h to 000D_FFFFh W/R Add-on BIOS
Table 2. Extended System BIOS Area Memory Segments
000E_0000h to 000E_3FFFh W/R BIOS Extension
000E_4000h to 000E_7FFFh W/R BIOS Extension
000E_8000h to 000E_BFFFh W/R BIOS Extension
000E_C000h to 000E_FFFFh W/R BIOS Extension
Table 3. System BIOS Area Memory Segments
000F_0000h to 000F_FFFFh WE RE BIOS Area
Datasheet 47
System Address Map
4.1.6 Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area.
The GMCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there normally will not be
IWB cycles targeting DMI.
However, DMI becomes the default target for processor and DMI originated accesses to
disabled segments of the PAM region. If the MTRRs covering the PAM regions are set to
WB or RD it is possible to get IWB cycles targeting DMI. This may occur for DMI
originated cycles to disabled PAM regions.
In an example scenario, a particular PAM region is set for Read Disabled and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is Read Disabled the default target for the Memory Read becomes
DMI. The IWB associated with this cycle will cause the GMCH to hang.
4.2 Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted
to be accessible by the GMCH (as programmed in the TOLUD register). All accesses to
addresses within this range will be forwarded by the GMCH to the DRAM unless they fall
into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
Figure 4. Main Memory Address Range (1 MB to TOLUD)
Main Memory
ISA Hole (optional)
Main Memory
DOS Compatibility Memory
TSEG (optional)
Internal Graphics (optional)
PCI Memory Range
APIC
Flash
FFFF_FFFFh
0100_0000h
00F0_0000h
0010_0000h
0000_0000h
4 GB
TOLUD
16 MB
15 MB
1 MB
0
Contains: Device 0, 1, 2,
BARs & ICH/PCI ranges
DPR (optional)
System Address Map
48 Datasheet
4.2.1 ISA Hole (15 MB to 16 MB)
A hole can be created at 15 MB to 16 MB as controlled by the fixed hole enable in
Device0 space. Accesses within this hole are forwarded to the DMI. The range of
physical DRAM memory disabled by opening the hole is not remapped to the top of the
memory that physical DRAM space is not accessible. This 15-MB to 16-MB hole is an
optionally enabled ISA hole.
Video accelerators originally used this hole. It is also used for validation by customer
teams for some of their test cards. That is why it is being supported. There is no
inherent BIOS request for the 15-MB to 16-MB window.
4.2.2 TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of physical memory. System management software may partition
this region of memory so it is accessible only by system management software. SMM-
mode processor accesses to enabled TSEG access the physical DRAM at the same
address. Non-processor originated accesses are not allowed to SMM space. PCI
Express, DMI, and Internal Graphics originated cycles to enabled SMM space are
handled as invalid cycle type with reads and writes to location 0 and byte enables
turned off for writes. When the extended SMRAM space is enabled, processor accesses
to the TSEG range without SMM attribute or without WB attribute are also forwarded to
memory as invalid accesses (see Table 5). Non-SMM-mode Write Back cycles that
target TSEG space are completed to DRAM for cache coherency. When SMM is enabled
the maximum amount of memory available to the system is equal to the amount of
physical DRAM minus the value in the TSEG register which is fixed at 1 MB, 2 MB or
8 MB.
4.2.3 DPR (DMA Protected Range)
DMA protected memory only applies to DMAs and GMADR translations. This memory
range will be protected from all DMA accesses, including translated CPU accesses and
Graphics. The maximum amount of memory supported by DPR is 255 MB. The top of
the protected range is the BASE of TSEG -1. If TSEG is not enabled, then the top of this
range becomes the base location of the space TSEG (if enabled) would have occupied.
4.2.4 Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode and
legacy VGA graphics compatibility. It is the responsibility of BIOS to properly
initialize these regions. Table 4 details the location and attributes of the regions.
How to enable and disable these ranges are described in the GMCH Control Register
Device0 (GGC).
Table 4. Pre-allocated Memory Example for 512-MB DRAM, 64-MB VGA, and 1-MB TSEG
0000_0000h to 1BEF_FFFFh R/W Available System Memory 447 MB
1BF0_0000h to 1BFF_FFFFh
SMM Mode Only -
Processor Reads
TSEG Address Range & Pre-allocated
Memory
1C00_0000h t 1FFF_FFFFh R/W
Pre-allocated Graphics VGA memory.
64 MB when IGD is enabled.
Datasheet 49
System Address Map
4.3 PCI Memory Address Range (TOLUD to 4 GB)
This address range, from the top of physical memory to 4 GB, is normally mapped to
the DMI Interface.
Exceptions to this mapping include the BAR memory mapped regions, which include:
EPBAR, MCHBAR, and DMIBAR.
In the PCI Express port, there are two exceptions to this rule:
1. Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1 registers are mapped to PCI Express
2. Addresses decoded to PCI Express Configuration Space are mapped based on Bus,
Device, and Function number (PCIEXBAR range)
Note: AGP Aperture no longer exists with PCI Express.
In an internal graphics configuration, there are three exceptions to this rule:
1. Addresses decoded to the Graphics Memory Range. (GMADR range)
2. Addresses decoded to the Graphics Translation table range (GTTADR range)
3. Addresses decoded to the Memory Mapped Range of the Internal Graphics Device
(MMADR range). There is a MMADR range for Device2 function 0 and a MMADR
range for Device2 function 1. Both ranges are forwarded to the internal graphics
device.
In Intel Management Engine configuration, there are exceptions to this rule:
1. Addresses decoded to the Intel Management Engine keyboard and Text MMIO
range (EPKTBAR)
The exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with APIC Configuration Space, FSB Interrupt Space and High BIOS
Address Range.
Note: With the exception of certain BARs, all the above mentioned BARs can be mapped in
the TOUUD to 64-GB range in the case of chipset variants supporting 36-bit addressing.
See Figure 2 for details.
System Address Map
50 Datasheet
Figure 5. PCI Memory Address Range (TOLUD to 4 GB)
High BIOS
DMI Interface
(subtractive decode)
FSB Interrupts
DMI Interface
Local (CPU) APIC
I/O APIC
DMI Interface
PCI Express Configuration
Space
DMI Interface
4 GB
4 GB minus 2 MB
4 GB minus 17 MB
4 GB minus 18 MB
4 GB minus 19 MB
4 GB minus 20 MB
4 GB minus 256 MB
4 GB minus 512 MB
TOLUD
E000_0000h
F000_0000h
FEC0_0000h
FEC8_0000h
FED0_0000h
FEE0_0000h
FEF0_0000h
FFE0_0000h
FFFF_FFFFh
Internal Graphics
ranges
PCI Express Port
Possible address
range
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
Datasheet 51
System Address Map
4.3.1 APIC Configuration Space (FEC0_0000h to FECF_FFFFh)
This range is reserved for APIC configuration space which includes the default I/O APIC
configuration space from FEC0_0000h to FEC7_0FFFh. The default Local (processor)
APIC configuration space goes from FEC8_0000h to FECF_FFFFh.
Processor accesses to the Local APIC configuration space do not result in external bus
activity since the Local APIC configuration space is internal to the processor. However,
an MTRR must be programmed to make the Local APIC range uncacheable (UC). The
Local APIC base address in each processor should be relocated to the FEC0_0000h (4
GB minus 20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64 KB
for the Local and I/O APICs. The I/O APIC(s) usually reside in the ICH portion of the
chip set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first
I/O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h
where x is I/O APIC unit number 0 through F (hex). This address range will normally be
mapped to DMI.
Note: There is no provision to support an I/O APIC device on PCI Express.
4.3.2 HSEG (FEDA_0000h to FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM memory. It is sometimes called the High SMM memory space. SMM-mode
processor accesses to the optionally enabled HSEG are remapped to 000A_0000h to
000B_FFFFh. Non-SMM mode processor accesses to enabled HSEG are considered
invalid and are terminated immediately on the FSB. The exceptions to this rule are
Non-SMM mode Write Back cycles which are remapped to SMM space to maintain cache
coherency. PCI Express and DMI originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is
not accessible. All Cacheline writes with WB attribute or implicit write backs to the
HSEG range are completed to DRAM like an SMM cycle.
4.3.3 FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express, internal graphics, or DMI may issue a Memory Write to
0FEEx_xxxxh. The GMCH will forward this Memory Write along with the data to the FSB
as an Interrupt Message Transaction. The GMCH terminates the FSB transaction by
providing the response and asserting H_TRDY#. This Memory Write cycle does not go
to DRAM.
4.3.4 High BIOS Area
The top 2 MB (FFE0_0000h to FFFF_FFFFh) of the PCI Memory Address Range is
reserved for system BIOS (High BIOS), extended BIOS for PCI devices, and the A20
alias of the system BIOS. The processor begins execution from the High BIOS after
reset. This region is mapped to DMI so that the upper subset of this region aliases to
the 16-MB minus 256-KB range. The actual address space required for the BIOS is less
than 2 MB, but the minimum processor MTRR range for this region is 2 MB so a full
2 MB must be considered.
System Address Map
52 Datasheet
4.4 Main Memory Address Space (4 GB to TOUUD)
Earlier chipsets supported a maximum main memory size of 4-GB total memory. This
would result in a hole between TOLUD (Top of Low Usable DRAM) and 4 GB when main
memory size approached 4 GB, resulting in a certain amount of physical memory being
inaccessible to the system.
The new reclaim configuration registers (TOUUD, REMAPBASE, REMAPLIMIT) exist to
reclaim lost main memory space. The greater than 32-bit reclaim handling will be
handled similar to other MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by PCI Express Graphics and DMI.
The Top of Memory (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped IO above
TOM).
The Intel ME stolen memory is located at the top of physical memory. TOM is used to
allocate the Intel MEs stolen memory; the Intel ME stolen memory base is calculated
by subtracting the amount of memory stolen by the Intel ME from TOM. The Intel ME
stolen size register reflects the total amount of physical memory stolen by the Intel ME.
The Top of Upper Usable DRAM (TOUUD) register reflects the total amount of
addressable memory. If reclaim is disabled, TOUUD will reflect TOM minus Intel MEs
stolen size. If reclaim is enabled, then it will reflect the reclaim limit. Also, the reclaim
base will be the same as TOM minus Intel Management Engine stolen memory size to
the nearest 64-MB alignment.
4.4.1 Memory Remap Background
The following examples of Memory Mapped I/O devices are typically located below
4 GB:
High BIOS
H-Seg
T-Seg
Graphics Stolen Memory
Local APIC
FSB Interrupts
Mbase/Mlimit
Memory Mapped I/O space that supports only 32-bit addressing
The GMCH provides the capability to remap or reclaim the physical memory overlapped
by the Memory Mapped I/O logical address space. The GMCH re-maps physical memory
from the Top of Low Usable DRAM (TOLUD) boundary up to the 4-GB boundary to an
equivalent sized logical address range located just below the Intel MEs stolen memory.
Datasheet 53
System Address Map
4.4.2 Memory Remapping (or Reclaiming)
An incoming address (referred to as a logical address) is checked to see if it falls in the
memory re-map window. The bottom of the re-map window is defined by the value in
the REMAPBASE register. The top of the re-map window is defined by the value in the
REMAPLIMIT register. An address that falls within this window is remapped to the
physical memory starting at the address defined by the TOLUD register. The TOLUD
register must by 64-MB aligned when remapping is enabled, but can be 1-MB aligned
when remapping is disabled.
4.5 PCI Express Configuration Address Space
The Device0 register (PCIEXBAR), defines the base address for the configuration space
associated with all devices and functions that are potentially a part of the PCI Express
root complex hierarchy. This is a 256-MB block of addresses below top of addressable
memory (currently 4 GB) and is aligned to a 256-MB boundary. BIOS must assign this
address range such that it will not conflict with any other address ranges.
4.5.1 PCI Express Graphics Attach
The GMCH can be programmed to direct memory accesses to the PCI Express interface
when addresses are within either of two ranges specified via registers in GMCHs
Device1 configuration space.
The first range is controlled via the Memory Base Register (MBASE) and Memory
Limit Register (MLIMIT) registers.
The second range is controlled via the Prefetchable Memory Base (PMBASE/
PMBASEU) and Prefetchable Memory Limit (PMLIMIT/PMLIMITU) registers.
The GMCH positively decodes memory accesses to PCI Express memory address space
as defined by the following equations:
Memory_Base_Address Address Memory_Limit_Address
Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range to apply USWC attribute (from
the processor point of view) to that range. The USWC attribute is used by the processor
for write combining.
Note that the GMCH Device1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express that
require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the Device1 PCICMD1
register to enable the memory base/limit and prefetchable base/limit windows.
4.5.2 Graphics Aperture
Unlike AGP, PCI Express has no concept of aperture for PCI Express devices. As a
result, there is no need to translate addresses from PCI Express. Therefore, the GMCH
has no APBASE and APSIZE registers.
System Address Map
54 Datasheet
4.6 Graphics Memory Address Ranges
The GMCH can be programmed to direct memory accesses to IGD when addresses are
within any of three ranges specified via registers in GMCHs Device2 configuration
space.
The Memory Map Base Register (MMADR) is used to access graphics control
registers.
The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
The Graphics Translation Table Base Register (GTTADR) is used to access the
translation table.
Normally these ranges will reside above the Top-of-Main-DRAM and below high BIOS
and APIC address ranges. They normally reside above the top of memory (TOLUD) so
they do not steal any physical DRAM memory space. GMADR is a Prefetchable range to
apply USWC attribute (from the processor point of view) to that range. The USWC
attribute is used by the processor for write combining.
4.6.1 Graphics Register Ranges
This section provides a high-level register map (register groupings per function) for the
integrated graphics. The memory and I/O maps for the graphics registers are shown in
Figure 6, except PCI Configuration registers, which are described in Volume 2 of this
document. The VGA and Extended VGA registers can be accessed via standard VGA I/O
locations as well as via memory-mapped locations. In addition, the memory map
contains allocation ranges for various functions. The memory space address listed for
each register is an offset from the base memory address programmed into the MMADR
register (PCI configuration offset 14h). The same memory space can be accessed via
dword accesses to I/OBAR. Through the IOBAR, I/O registers MMIO_index and
MMIO_data are written.
4.6.1.1 VGA and Extended VGA Control Registers (0000_0000h to
0000_0FFFh)
These registers are located in both I/O space and memory space. The VGA and
Extended VGA registers contain the following register sets: General Control/Status,
Sequencer (SRxx), Graphics Controller (GRxx), Attribute Controller (ARxx), VGA Color
Palette, and CRT Controller (CRxx) registers.
4.6.1.2 Instruction, Memory, and Interrupt Control Registers (0000_1000h to
0000_2FFFh)
The Instruction and Interrupt Control registers are located in this space and contain the
types of registers listed in the following sections.
4.6.2 I/O Mapped Access to Device 2 MMIO Space
If Device 2 is enabled, and Function 0 within Device 2 is enabled, then IGD registers
can be accessed using the IOBAR.
MMIO_Index: MMIO_INDEX is a 32-bit register. An I/O write to this port loads the
address of the MMIO register that needs to be accessed. I/O Reads returns the current
value of this register.
MMIO_Data: MMIO_DATA is a 32-bit register. An I/O write to this port is re-directed to
the MMIO register pointed to by the MMIO-index register. An I/O read to this port is re-
directed to the MMIO register pointed to by the MMIO-index register.
Datasheet 55
System Address Map
Figure 6. Graphics Register Memory and I/O Map
Host Port Registers
Bit Engine Control Status
(RO)
Overlay Registers
Reserved
Display Palette Registers
Reserved
Misc I/O Control Registers
Clock Control Registers
TV Out Registers
Misc. Multimedia Registers
Cursor Registers
Display Registers
Pixel Pipe Registers
Reserved
Local Memory Interface
Control Registers
Instruction Control Registers
Interrupt Control
VGA and Ext. VGA Registers
0000_0000h
0000_1000h
0000_3000h
0000_4000h
0000_5000h
0000_6000h
0000_7000h
0000_A000h
0000_B000h
0001_0000h
0003_0000h
0004_0000h
0005_0000h
0006_0000h
0007_0000h
0000_0FFFh
0000_2FFFh
0000_3FFFh
0000_4FFFh
0000_5FFFh
0000_6FFFh
0000_9FFFh
0000_AFFFh
0000_FFFFh
0002_FFFFh
0003_FFFFh
0004_FFFFh
0005_FFFFh
0006_FFFFh
0007_FFFFh
Offset From
Base_Reg
Memory Space Map
(512 kB allocation)
MMADR Register (Base Address)
31 19
VGA and Ext. VGA Registers
I/O Space Map
(Standard graphics locations)
Note:
Some Overlay registers are
double-buffered with an
additional address range in
graphics memory
System Address Map
56 Datasheet
4.7 System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SM
RAM). The GMCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. GMCH provides three
SMRAM options:
Below 1-MB option that supports compatible SMI handlers.
Above 1-MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
stolen memory.
The above 1-MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
Note: DMI and PCI Express masters are not allowed to access the SMM space.
4.7.1 SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space are different address ranges. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 5 describes three unique
address ranges:
Compatible Transaction Address (Adr C)
High Transaction Address (Adr H)
TSEG Transaction Address (Adr T)
Table 5. SMM Space Definition Summary
SMM Space
Enabled
Transaction Address Space DRAM Space (DRAM)
Compatible (Adr C) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh
High (Adr H) FEDA_0000h to FEDB_FFFFh 000A_0000h to 000B_FFFFh
TSEG (Adr T)
(TOLUD minus STOLEN minus
TSEG) to (TOLUD minus STOLEN)
(TOLUD minus STOLEN minus
TSEG) to (TOLUD minus STOLEN)
Datasheet 57
System Address Map
4.8 SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
The Compatible SMM space must not be set-up as cacheable.
High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any PCI devices (including DMI, PCI Express, and
graphics devices). This is a BIOS responsibility.
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
Any address translated through the GMADR must not target DRAM from A_0000-
F_FFFF.
4.8.1 SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM
space is effectively disabled. Processor originated accesses to the Compatible SMM
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise
they are forwarded to the DMI. PCI Express and DMI originated accesses are never
allowed to access SMM space.
4.8.2 SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at power up. The D_LCK bit limits the SMM range
access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be
forwarded to the DMI or PCI Express. The SMM software can use this bit to write to
video memory while running SMM code out of DRAM.
Table 6. SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Adr C Range
Adr H
Range
Adr T
Range
0 X X Disable Disable Disable
1 0 0 Enable Disable Disable
1 0 1 Enable Disable Enable
1 1 0 Disabled Enable Disable
1 1 1 Disabled Enable Enable
System Address Map
58 Datasheet
4.8.3 SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
4.8.4 Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQ [1]# = 0) to enabled SMM address space must
be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
4.9 Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
shadowed into GMCH DRAM memory. Typically, this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
4.10 I/O Address Space
The GMCH does not support the existence of any other I/O devices beside itself on the
processor bus. The GMCH generates either DMI or PCI Express bus cycles for all
processor I/O accesses that it does not claim. Within the host bridge the GMCH
contains two internal registers in the processor I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA).
These locations are used to implement a configuration space access mechanism.
The processor allows 64 KB plus 3 B to be addressed within the I/O space. The GMCH
propagates the processor I/O address without any translation on to the destination bus
and therefore provides addressability for 64-KB plus 3-B locations.
Table 7. SMM Control Table
G_SMRAME D_LCK D_CLS D_OPEN
Processor
in SMM
Mode
SMM Code
Access
SMM Data
Access
0 X X X X Disable Disable
1 0 X 0 0 Disable Disable
1 0 0 0 1 Enable Enable
1 0 0 1 X Enable Enable
1 0 1 0 1 Enable Disable
1 0 1 1 X Invalid Invalid
1 1 X X 0 Disable Disable
1 1 0 X 1 Enable Enable
1 1 1 X 1 Enable Disable
Datasheet 59
System Address Map
Note: The upper three locations can be accessed only during I/O address wrap-around when
processor bus H_A#16 address signal is asserted. H_A#16 is asserted on the processor
bus whenever an I/O access is made to four bytes from address 0000_FFFDh,
0000_FFFEh, or 0000_FFFFh. H_A#16 is also asserted when an I/O access is made to 2
bytes from address 0000_FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI bus unless they fall within the PCI Express I/O address range as
defined by the mechanisms explained below. I/O writes are NOT posted. Memory
writes to ICH or PCI Express are posted. The PCICMD1 register can disable the routing
of I/O cycles to PCI Express.
The GMCH responds to I/O cycles initiated on PCI Express or DMI with a UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to memory address 0h so a completion is naturally
generated (whether the original request was a read or write). The transaction will
complete with a UR completion status.
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from
the processor as 1 transaction. The GMCH will break this into two separate
transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries
are assumed to be split into two transactions by the processor.
4.10.1 PCI Express I/O Address Mapping
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when processor initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address (IOBASE)
and I/O Limit Address (IOLIMIT) registers in GMCH Device1 configuration space.
The GMCH positively decodes I/O accesses to PCI Express I/O address space as defined
by the following relation:
I/O_Base_Address Processor I/O Cycle Address I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device1 configuration registers BCTRL (VGA Enable) and PCICMD1
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI.
The presence of a second graphics adapter is determined by the MDAP configuration
bit. When MDAP is set, the GMCH will decode legacy monochrome IO ranges and
forward them to the DMI Interface. The IO ranges decoded for the monochrome
adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.
Note: The GMCH Device 1 I/O address range registers defined above are used for all I/O
space allocation for any devices requiring such a window on PCI Express.
System Address Map
60 Datasheet
4.11 GMCH Decode Rules and Cross-Bridge Address
Mapping
VGAA = 000A_0000 to 000A_FFFF
MDA = 000B_0000 to 000B_7FFF
VGAB = 000B_8000 to 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
4.11.1 Legacy VGA and I/O Range Decode Rules
The legacy 128-KB VGA memory range 000A_0000h to 000B_FFFFh can be mapped to
IGD (Device 2), to PCI Express (Device1), and/or to the DMI depending on the
programming of the VGA steering bits. Priority for VGA mapping is constant in that the
GMCH always decodes internally mapped devices first. Internal to the GMCH, decode
precedence is always given to IGD. The GMCH always positively decodes internally
mapped devices, namely the IGD and PCI Express. Subsequent decoding of regions
mapped to PCI Express or the DMI depends on the Legacy VGA configurations bits
(VGA Enable and MDAP).

Datasheet 61
System Memory Controller
5 System Memory Controller
5.1 Functional Overview
The Mobile Intel 4 Series Express Chipset Family system memory controller supports
DDR2 and DDR3 SDRAMs.
Two memory channel organizations are supported:
Dual-channel interleaved (single SO-DIMM per channel)
Dual-channel asymmetric (single SO-DIMM per channel)
Each channel has a 64-bit data interface and the frequencies supported are:
667 MHz and 800 MHz for DDR2
800 MHz and 1066 MHz for DDR3
Each channel can have one or two ranks populated. There can be a maximum of four
ranks (two, double-sided SO-DIMMs) populated.
Note: The Mobile Intel GS45 and GS40 Express Chipsets can support memory-down on one
channel and SO-DIMM on the other channel. The Mobile Intel GS45 and GS40 Express
Chipsets can support memory-down on two channels, but not validated.
Note: The Mobile Intel 4 Series Express Chipset Family supports only one SO-DIMM connector
per channel.
Note: The Mobile Intel 4 Series Express Chipset Family supports Channel A only for single
channel configuration.
Note: The Mobile Intel 4 Series Express Chipset Family does not support mixed CAS Latency
memory combination.
NOTES:
1. Not validated.
Table 8. System Memory Organization Support for DDR2
DDR2
Tech Config
Page Size
(Device/
Module)
Banks
Smallest
Increments
Largest
Increments
Maximum
Capacity (2
SO-DIMMs)
Note
256 Mb 32 Mb x 8 1 k/8 k 4 256 MB 512 MB 1 GB 1
256 Mb 16 Mb x 16 1 k/4 k 4 128 MB 256 MB 512 MB 1
512 Mb 64 Mb x 8 1 k/8 k 4 512 MB 1 GB 2 GB
512 Mb 32 Mb x 16 2 k/8 k 4 256 MB 512 MB 1 GB
1 Gb 128 Mb x 8 1 k/8 k 8 1 GB 2 GB 4 GB
1 Gb 64 Mb x 16 2 k/8 k 8 512 MB 1 GB 2 GB
2 Gb 256 Mb x 8 1 k/8 k 8 2 GB 4 GB 8 GB
2 Gb 128 Mb x 16 2 k/8 k 8 1 GB 2 GB 4 GB
62 Datasheet
NOTES:
1. Not validated, memory product is currently not available.
5.2 Memory Channel Access Modes
The system memory controller supports two styles of memory access: dual-channel
Interleaved and dual-channel Asymmetric. Rules for populating SO-DIMM slots are
included in this chapter.
5.2.1 Dual-Channel Interleaved Mode
This mode provides maximum performance on real applications. Addresses alternate
between the channels after each cache line (64-byte boundary). The channel selection
address bit is controlled by DCC [10:9]. If a second request sits behind the first, and
that request is to an address on the second channel, that request can be sent before
data from the first request has returned. Due to this feature, some progress is made
even during page conflict scenarios. If two consecutive cache lines are requested, both
may be retrieved simultaneously, since they are guaranteed to be on opposite
channels. The drawback of conventional Interleaved mode is that the system designer
must populate both channels of memory so that they have equal capacity, however the
technology and device width may vary from one channel to the other.
5.2.1.1 Intel Flex Memory Technology (Dual-Channel Interleaved Mode with
Unequal Memory Population)
The GMCH supports Interleaved addressing in dual-channel memory configurations
even when the two channels have unequal amounts of memory populated. This is
called Intel Flex Memory Technology.
Intel Flex Memory Technology provides higher performance with different sized channel
populations than Asymmetric mode (where no interleaving is used) by allowing some
interleaving.
The memory addresses up to the twice the size of the smaller SO-DIMM are Interleaved
on a 64-B boundary using address Bit 6 (including any XOR-ing already used in
Interleaved mode). Above this, the rest of the address space is assigned to the
remaining memory in the larger channel. Figure 7 shows various configurations of
memory populations.
Table 9. System Memory Organization Support for DDR3
DDR3
Tech Config
Page Size
(Device/
Module)
Banks
Smallest
Increments
Largest
Increments
Maximum
Capacity
(2 SO-DIMMs)
Note
512 Mb 64 Mb x 8 1 k/8 k 8 512 MB 1 GB 2 GB 1
512 Mb 32 Mb x 16 2 k/8 k 8 256 MB 512 MB 1 GB 1
1 Gb 128 Mb x 8 1 k/8 k 8 1 GB 2 GB 4 GB
1 Gb 64 Mb x 16 2 k/8 k 8 512 MB 1 GB 2 GB
2 Gb 256 Mb x 8 1 k/8 k 8 2 GB 4 GB 8 GB
2 Gb 128 Mb x 16 2 k/8 k 8 1 GB 2 GB 4 GB
Datasheet 63
NOTES:
1. To enable Intel Flex Memory Technology, BIOS should program both channels DRBs
(DRAM Rank Boundaries) to the size of memory in that channel, as if for fully interleaved
memory (should not add the top of one channel to the other as in Asymmetric mode).
Interleaved mode operation should also be enabled.
2. To disable Intel Flex Memory Technology, BIOS should program as usual for the
Asymmetric mode.
5.2.2 Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility, by allowing unequal
amounts of memory to be populated in the two channels. Unlike the previous mode,
addresses start in Channel A and stay there until the end of the highest rank in Channel
A, then addresses continue from the bottom of Channel B to the top. Real world
applications are unlikely to make requests that alternate between addresses that sit on
opposite channels with this memory organization. Therefore, in most cases bandwidth
will be limited. The system designer is free to populate or not to populate any rank on
either channel, including either degenerate single channel case. Because Channel A is
addressed first when using only one channel, Channel A should be the channel used.
Figure 7. Intel Flex Memory Technology Operation
B: Smaller of the two physical memory amounts: (accessed in dual-channel Interleaved mode)
C: Extra memory populated over B: (accessed in Non-Interleaved mode)
64 Datasheet
5.3 DRAM Technologies and Organization
All standard 256-Mb, 512-Mb, 1-Gb, and 2-Gb technologies and addressing are
supported for x16 and x8 devices.
The GMCH supports various page sizes. Page size is individually selected for every
rank; 4 k and 8 k for Interleaved and Asymmetric dual-channel modes.
The DRAM sub-system supports only dual-channel with 64-bit width per channel.
The number of ranks each channel can have populated is one or two.
Mixed mode double-sided SO-DIMMs (x8 and x16 on the same SO-DIMM) are not
supported.
Figure 8. System Memory Styles
CH1
CH0
CH1
CH0
CH1
CH0
Channel selector
controlled by DCC[10:9]
CL
0
Top of
Memory
CL
0
CH1
CH0
CH0-top
DRB
Dual Channel Interleaved
(memory sizes must match)
Dual Channel Asymmetric
(memory sizes can differ)
Top of
Memory
Datasheet 65
5.3.1 Rules for Populating SO-DIMM Slots
In all modes, the frequency of system memory will be the lowest frequency of all
SO-DIMMs in the system, as determined through the SPD registers on the SO-DIMMs.
The GMCH supports only one SO-DIMM connector per channel.
In dual-channel Interleaved mode, both SO-DIMM slots must be populated and the
total amount of memory in each channel must be the same. The device
technologies may differ.
In dual-channel Asymmetric mode, the total memory in the two channels need not
be equal (one slot could even be unpopulated).
5.3.1.1 Single-Channel Population Rules for Systems with Intel Management
Engine Enabled
Channel 0 should always be populated in either of the below cases, as it will be required
for Intel Management Engine operation.
Intel AMT enabled
iTPM enabled
In case of Non-AMT AND non-iTPM systems, either Channel 0 or Channel 1 may be
populated.
5.3.2 Pin Connectivity for Dual-Channel Modes
NOTES:
1. Applicable only in DDR3 mode.
Table 10. DDR2/DDR3 Dual-Channel Pin Connectivity
JEDEC Signal
Name
Channel A Channel B
CK [1:0] SA_CK [1:0] SB_CK [1:0]
CKB [1:0] SA_CK# [1:0] SB_CK# [1:0]
CSB [1:0] SA_CS# [1:0] SB_CS# [1:0]
CKE [1:0] SA_CKE [1:0] SB_CKE [1:0]
ODT [1:0] SA_ODT [1:0] SB_ODT [1:0]
BS [2:0] SA_BS [2:0] SB_BS [2:0]
MA [14:0] SA_MA [14:0] SB_MA [14:0]
RAS# SA_RAS# SB_RAS#
CAS# SA_CAS# SB_CAS#
WE# SA_WE# SB_WE#
DQ [63:0] SA_DQ [63:0] SB_DQ [63:0]
DQS [7:0] SA_DQS [7:0] SB_DQS [7:0]
DM [7:0] SA_DM [7:0] SB_DM [7:0]
RESETB
1
SM_DRAMRST#
66 Datasheet
5.4 DRAM Clock Generation
The GMCH generates two differential clock pairs for every supported SO-DIMM. There
are total of four clock pairs driven directly by the GMCH to two SO-DIMMs.
5.5 DDR2/DDR3 On Die Termination
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal
termination resistance for each DQ, DQS/DQS# and DM signal for x8 configurations via
the ODT control pin. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DRAM controller to independently turn on/off
termination resistance for any or all DRAM devices.
The ODT feature is designed to improve signal integrity of the memory channel by
allowing the termination resistance for the DQ, DM, DQS, and DQS# signals to be
located inside the DRAM devices themselves instead of on the motherboard. The GMCH
drives out the required ODT signals, based on memory configuration and which rank is
being written to or read from, to the DRAM devices on a targeted SO-DIMM rank to
enable or disable their termination resistance.
ODT operation follows these general rules:
WRITE
Chipset: ODT off
DRAM:
If one slot is populated but has two ranks, turn on termination in the written
rank.
If one slot/one rank, turn on that ranks termination.
READ
Chipset: ODT on
DRAM: ODT off
5.6 DRAM Power Management
The GMCH implements extensive support for power management on the SDRAM
interface.
5.6.1 Self Refresh Entry and Exit Operation
When entering the Suspend-To-RAM (STR) state, GMCH will flush pending cycles and
then enter all SDRAM ranks into self refresh. In STR, the CKE signals remain LOW so
the SDRAM devices will perform self-refresh.
Datasheet 67
5.6.2 Dynamic-Power-Down Operation
The GMCH implements aggressive CKE control to dynamically put the DRAM devices in
a power down state. The GMCH controller can be configured to put the devices in active
power down (CKE deassertion with open pages) or precharge power down (CKE
deassertion with all pages closed). Precharge power down provides greater power
savings but has a bigger performance impact, since all pages are needed to be closed
before putting the devices in power down mode.
If dynamic-power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
5.6.3 DRAM I/O Power Management
GMCH implements several power saving features where different groups of IO buffers
are disabled when safe to do so in a dynamic fashion thereby saving IO power. These
features are listed below.
SO-DIMM clock disable The GMCH has two clock pairs per SO-DIMM. If only one
SO-DIMM is populated, it allows the other 2 clock pairs to be disabled.
Unused CKE pins can be tri-stated.
Address and control tri-state enable If CKE for any given rank is deasserted, the
CS# to that rank is disabled. If all CKEs are deasserted (such as in S3), All address
and control buffers (excluding CKEs) are disabled.
Self refresh master/slave DLL disable - When all the SDRAMs ranks have been put
in a self refresh state, all DLLs are disabled.
Data sense amp disable (self refresh, dynamic) - When all the SDRAM ranks have
been put in a self refresh state, or during normal operation, if no memory accesses
are pending, the sense amplifiers for all data buffers are turned off.
Output only sense amp disable Sense amplifiers of all IO buffers which are
functionally outputs only (everything except DQ and DQS) are turned off.
5.7 System Memory Throttling
The GMCH has two, independent mechanisms GMCH Thermal Management and
DRAM Thermal Management that cause system memory bandwidth throttling. For
more information on system memory throttling, see Section 11.3.

PCI Express- Based External Graphics
68 Datasheet
6 PCI Express- Based External
Graphics
This chapter details the PCI Express interface capabilities of the GMCH and also the
digital display ports that can be multiplexed on it. See the PCI Express Specification for
details of PCI Express.
This GMCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express Hierarchy. The control registers for this
functionality are located in Device1 configuration space and two Root Complex Register
Blocks (RCRBs).
6.1 PCI Express Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
NOTE: Details of both the PCI compatible and PCI Express Enhanced configuration mechanisms
and transaction rules are provided in the PCI Express Specification.
Note: DMA transfers on some latency-sensitive devices may incur completion delays during
heavy external PCI Express Graphics traffic to cacheable memory regions. These
latency sensitive devices have been typically used in AC mode. The completion delays
do not violate platform or industry specifications. If such completion delays are
encountered, a system BIOS configuration change to disable C3 allows a device to be
serviced during heavy external PCI Express Graphics traffic.
Figure 9. PCI Express Related Register Structures in GMCH
GMCH
PCI-to-PCI
Bridge
representing
root PCI
Express Port
(Device 1)
PCI
Compatible
Host Bridge
Device
(Device 0)
RCRB for
Egress Port
(access to
Main Memory)
RCRB for DMI
(ICH attach)
PCI Express*
Graphics
Device
PCI Express Link
x16 down to x1
I CH
Datasheet 69
6.2 Concurrent Operation of Digital DisplayPorts
Multiplexed with the GMCH PCI Express Interface
The GMCH supports concurrent operation of the multiplexed Digital display ports with a
x1 PCI Express interface. In addition to supporting video capture, this port may be con-
figured as an additional general-purpose PCIe port, thus bringing the total number of
PCIe ports on the Intel Centrino 2 platform to 7.
6.2.1 SDVO Multiplexed on the PCI Express Interface
The SDVO interface is muxed onto the PCI Express x16 port pins. The AC/DC
specifications are identical to the PCI Express Graphics interface.
SDVO slot reversal is also supported on the GMCH. The GMCH allows SDVO and x1 PCI
Express to operate concurrently on the PCI Express-based graphics link.
The PCI Express lanes comprise a standard PCI Express link and must always originate
with Lane 0 on the PCI Express connector. The only supported PCI Express width when
SDVO is present is x1.
This concurrency is supported in reversed and non-reversed configurations. Mirroring/
Reversing are always about the axis between Lane 7 and Lane 8. When SDVO is
reversed, SDVO Lane 0 corresponds to what would be PCI Express pin/
connector Lane15 (mirrored to higher lane numbers).
Hardware reset straps are used to determine which of the six configurations in Table 11
is desired.
NOTES:
1. Details of the implementations corresponding to the configuration number are shown in Figure 10 and
Figure 11.
2. SDVO_CTRLCLK should be pulled up if SDVO_CTRLDATA is HIGH.
Table 11. Concurrent SDVO/PCI Express Configuration Strap Controls
Configuration
Number
Description
Slot Reversed
Strap (CFG9)
SDVO Present Strap
(SDVO_CTRLDATA)
Digital Display
Port/PCI Express
Concurrent Strap
(CFG20)
1
PCI Express*-only not
reversed
High Low Low
2 PCI Express-only Reversed Low Low Low
3 SDVO-only not reversed High High Low
4 SDVO-only Reversed Low High Low
5
SDVO and PCI Express not
reversed
High High High
6
SDVO and PCI Express
Reversed
Low High High
70 Datasheet
Figure 10. SDVO/PCI Express Non-Reversed Configurations
0
15
x16
PCIe
Card
0
15
1
0
15
x4
sDVO
x8
sDVO
3
0
15
5
Video Out
Video In
sDVO
PCIe
sDVO Lane0
sDVO Lane7
PCIe Lane0
0
P
C
I

E
x
p
r
e
s
s

x
1
6

C
o
n
n
e
c
t
o
r
P
C
I

E
x
p
r
e
s
s

x
1
6

C
o
n
n
e
c
t
o
r
P
C
I

E
x
p
r
e
s
s

x
1
6

C
o
n
n
e
c
t
o
r
N
o
t

R
e
v
e
r
s
e
d
0
15
(G)MCH PCIe
Lane Numbering
Figure 11. SDVO/PCI Express Reversed Configurations
2 4 6
0
15
x16
PCIe
Card
0
15
x4
sDVO
x8
sDVO
0
0
15
Video Out
Video In
sDVO
PCIe
sDVO Lane 0
sDVO Lane 7
PCIe Lane 0
P
C
I

E
x
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15
0
(G)MCH PCIe
Lane Numbering
0
15
Datasheet 71
6.2.1.1 SDVO Signal Mapping
Table 12 shows the mapping of SDVO signals to the PCI Express lanes in the various
possible configurations as determined by the strapping configuration.
Note: Slot-reversed configurations do not apply to the integrated graphics only variants.
Table 12. Configuration Mapping of SDVO Signals on the PCI Express Interface
SDVO Signal
Configuration-wise Mapping
SDVO Only Normal
(3)
SDVO Only
Reversed (4)
Concurrent
SDVO and PCI
Express
Normal (5)
Concurrent SDVO
and PCI Express
Reversed (6)
SDVOB_RED# PEG_TXN0 PEG_TXN15 PEG_TXN15 PEG_TXN0
SDVOB_RED PEG_TXP0 PEG_TXP15 PEG_TXP15 PEG_TXP0
SDVOB_GREEN# PEG_TXN1 PEG_TXN14 PEG_TXN14 PEG_TXN1
SDVOB_GREEN PEG_TXP1 PEG_TXP14 PEG_TXP14 PEG_TXP1
SDVOB_BLUE# PEG_TXN2 PEG_TXN13 PEG_TXN13 PEG_TXN2
SDVOB_BLUE PEG_TXP2 PEG_TXP13 PEG_TXP13 PEG_TXP2
SDVOB_CLK# PEG_TXN3 PEG_TXN12 PEG_TXN12 PEG_TXN3
SDVOB_CLK PEG_TXP3 PEG_TXP12 PEG_TXP12 PEG_TXP3
SDVOC_RED# PEG_TXN4 PEG_TXN11 PEG_TXN11 PEG_TXN4
SDVOC_RED PEG_TXP4 PEG_TXP11 PEG_TXP11 PEG_TXP4
SDVOC_GREEN# PEG_TXN5 PEG_TXN10 PEG_TXN10 PEG_TXN5
SDVOC_GREEN PEG_TXP5 PEG_TXP10 PEG_TXP10 PEG_TXP5
SDVOC_BLUE# PEG_TXN6 PEG_TXN9 PEG_TXN9 PEG_TXN6
SDVOC_BLUE PEG_TXP6 PEG_TXP9 PEG_TXP9 PEG_TXP6
SDVOC_CLK# PEG_TXN7 PEG_TXN8 PEG_TXN8 PEG_TXN7
SDVOC_CLK PEG_TXP7 PEG_TXP8 PEG_TXP8 PEG_TXP7
SDVO_TVCLKIN# PEG_RXN0 PEG_RXN15 PEG_RXN15 PEG_RXN0
SDVO_TVCLKIN PEG_RXP0 PEG_RXP15 PEG_RXP15 PEG_RXP0
SDVOB_INT# PEG_RXN1 PEG_RXN14 PEG_RXN14 PEG_RXN1
SDVOB_INT PEG_RXP1 PEG_RXP14 PEG_RXP14 PEG_RXP1
SDVO_FLDSTALL# PEG_RXN2 PEG_RXN13 PEG_RXN13 PEG_RXN2
SDVO_FLDSTALL PEG_RXP2 PEG_RXP13 PEG_RXP13 PEG_RXP2
SDVOC_INT# PEG_RXN5 PEG_RXN10 PEG_RXN10 PEG_RXN5
SDVOC_INT PEG_RXP5 PEG_RXP10 PEG_RXP10 PEG_RXP5
72 Datasheet
6.2.2 Integrated HDMI/DVI (iHDMI) Multiplexed on the PCI
Express Interface
Table 13 shows the mapping of the Integrated HDMI/DVI pins on to the GMCH PCI
Express interface.
NOTE: DisplayPort multiplexed on the PCI Express Interface.
Table 14 shows the mapping of the DisplayPort pins on to the GMCH PCI Express
interface.
Table 13. Configuration Mapping of iHDMI Signals on the PCI Express Interface
iHDMI Signal Name Description
Multiplexed with
PCIe Normal
Operation
PCIe Lane-
Reversed
TMDS_B_CLK HDMI port B Clock PEG_TXP_3 PEG_TXP_12
TMDS_B_CLK# HDMI port B Clock complement PEG_TXN_3 PEG_TXN_12
TMDS_B_DATA0 HDMI port B Data0 PEG_TXP_2 PEG_TXP_13
TMDS_B_DATA0# HDMI port B Data0 Complement PEG_TXN_2 PEG_TXN_13
TMDS_B_HPD# HDMI port B Hot-plug detect PEG_RXP_3 PEG_RXP_12
TMDS_C_CLK HDMI port C Clock PEG_TXP_7 PEG_TXP_8
TMDS_C_CLK# HDMI port C Clock complement PEG_TXN_7 PEG_TXN_8
TMDS_C_DATA0 HDMI port C Data0 PEG_TXP_6 PEG_TXP_9
TMDS_C_DATA0# HDMI port C Data0 Complement PEG_TXN_6 PEG_TXN_9
TMDS_C_HPD# HDMI port C Hot-plug detect PEG_RXP_7 PEG_RXP_8
Datasheet 73
Table 14. Configuration Mapping of DisplayPort Signals on the PCI Express Interface
DisplayPort
Signal Name
Description
Multiplexed with
PCIE Normal
Operation
PCIE Lane-
Reversed
DPB_LANE3 DisplayPort B Lane3 PEG_TXP_3 PEG_TXP_12
DPB_LANE3# DisplayPort B Lane3 Complement PEG_TXN_3 PEG_TXN_12
DPB_HPD# DisplayPort B Hot-plug detect PEG_RXP_3 PEG_RXP_12
DPB_AUX DisplayPort B Aux PEG_RXP_2 PEG_RXP_13
DPB_AUX# DisplayPort B Aux Complement PEG_RXN_2 PEG_RXN_13
DPC_LANE3 DisplayPort C Lane3 PEG_TXP_7 PEG_TXP_8
DPC_LANE3# DisplayPort C Lane3 Complement PEG_TXN_7 PEG_TXN_8
DPC_HPD# DisplayPort C Hot-plug detect PEG_RXP_7 PEG_RXP_8
DPC_AUX DisplayPort C Aux PEG_RXP_6 PEG_RXP_9
DPC_AUX# DisplayPort C Aux Complement PEG_RXN_6 PEG_RXN_9
DPD_LANE3 DisplayPort D Lane3 PEG_TXP_11 PEG_TXP_4
DPD_LANE3# DisplayPort D Lane3 Complement PEG_TXN_11 PEG_TXN_4
DPD_HPD# DisplayPort D Hot-plug detect PEG_RXP_11 PEG_RXP_4
DPD_AUX DisplayPort D Aux PEG_RXP_10 PEG_RXP_5
DPD_AUX# DisplayPort D Aux Complement PEG_RXN_10 PEG_RXN_5
74 Datasheet
NOTES:
1. SDVO_CTRLCLK should be pulled up if SDVO_CTRLDATA is HIGH.
2. DDPC_CTRLCLK should be pulled up if DDPC_CTRLDATA is HIGH.
3. L_DDC_CLK should be pulled up if L_DDC_DATA is HIGH.
6.3 Co-Existence of DisplayPorts
In Integrated Graphics mode, a maximum of two DisplayPorts can simultaneously
operate on the GMCH. See Section 8.4 for a matrix detailing the possible combinations.

Table 15. Concurrent DisplayPort (HDMI)/PCI Express Configuration Strap Controls
Configuration
Number
Description
Local Flat
Panel (LFP)
Present Strap
(L_DDC_DATA)
DP/HDMI Present
Strap
(DDPC_CTRLDATA)
SDVO Present
Strap
(SDVO_CTRLDATA)
Digital Display
Port/PCI
Express
Concurrent Strap
(CFG20)
1
DP/HDMI
Port-B
enabled
X X High Low
2
DP/HDMI
Port-C
enabled
X High High Low
3
DP Port-D
enabled
High X High Low
4
DP/HDMI
Port-B and
PCI
Express*
X X High High
5
DP/HDMI
Port-C and
PCI Express
X High High High
6
DP Port-D
and PCI
Express
High X High High
Datasheet 75
I ntegrated Graphics Controller
7 I ntegrated Graphics Controller
This chapter details the chipset integrated graphics engines (3D, 2D and Video), 3D
pipeline and their respective capabilities.
The GMCH graphics is powered by the Gen-5.0 Graphics Architecture and supports ten
fully programmable execution cores, enabling greater performance than previous
generation chipsets. GMCH graphics supports full-precision, floating-point operations to
enhance the visual experience of compute-intensive applications.
The GMCH internal graphics devices (IGD) contain several types of components. The
major components in the IGD are the engines, planes, pipes and ports. The GMCH has
a 3D/2D Instruction Processing unit to control the 3D and 2D engines respectively. The
IGDs 3D and 2D engines are fed with data through the memory controller. The outputs
of the engines are surfaces sent to memory, which are then retrieved and processed by
GMCH planes.
7.1 Gen 5.0 3D and Video Engines for Graphics
Processing
The 3D graphics pipeline for the chipset has a deep pipelined architecture in which each
stage can simultaneously operate on different primitives or on different portions of the
same primitive. All the cores are fully programmable, increasing the versatility of the
3D Engine.
The Gen 5.0 3D engine also has a number of performance and power-management
enhancements, providing improved power/performance ratios over the Gen 4.0 IGD.
These include:
Execution Units increased to 10 from 8 EUs
Support for full decoding of VC-1 and AVC in hardware
Graphics support for Intel Virtualization Technology DMA
Improved Anti-aliasing support in hardware
Figure 12. GMCH Graphics Controller Block Diagram
Plane A
Cursor B
Sprite B
Plane B
Cursor A
Sprite A
Pipe B
Pipe A
Memory
M
U
X
CRT
SDVO
B/C
TVOUT
LVDS
VGA
Video Engine
2D Engine
3D Engine
Clipper
Strip & Fan/Setup
Alpha
Blend/
Gamma
/Panel
Fitter
Geometry Shader
Vertex Fetch/Vertex
Shader
Windower/IZ
iHDMI
DP
76 Datasheet
7.1.1 3D Engine Execution Units (EUs)
The 3D processing hardware includes support for two more EUs over the previous
generation. The EUs perform 128-bit wide execution per clock and are support SIMD8
instructions for vertex processing and SIMD16 instructions for pixel processing.
7.1.2 3D Pipeline
7.1.2.1 Vertex Fetch (VF) Stage
The VF stage performs one major function: executing 3DPRIMITIVE commands. Some
enhancements have been included to better support legacy D3D APIs as well as
OpenGL.
7.1.2.2 Vertex Shader (VS) Stage
The VS stage of the Gen 5.0 3D pipeline is used to perform shading of vertices output
by the VF function. The VS unit will thus produce an output vertex reference for every
input vertex reference received from the VF unit, in the order received.
7.1.2.3 Geometry Shader Stage
As a stage of the Gen 5.0 3D pipeline, the GS stage receives inputs from the previous
(VS) stage. Compiled application-provided GS shader programs, specifying an
algorithm to convert the vertices of an input object into some output primitives. For
example, a GS shader may convert lines of a line strip into polygons representing a
corresponding segment of a blade of grass centered on the line. Or it could use
adjacency information to detect silhouette edges of triangles and output polygons
extruding out from the those edges.
7.1.2.4 Clip Stage
The CLIP stage can be used to perform general processing on incoming 3D objects.
However, it also includes specialized logic to perform a ClipTest function on incoming
object. The Clip Test optimizes generalized 3D Clipping. The Clip unit examines the
position of incoming vertices, and accepts/rejects 3D objects based on its Clip
algorithm.
7.1.2.5 Strips and Fans Stage
The Strips and Fans (SF) stage of the Gen 5.0 3D pipeline is responsible for performing
setup operations required to rasterize 3D objects. The outputs from the SF stage to the
Windower stage comprise of implementation-specific information required for the
rasterization of objects and also supports clipping of primitives to some extent.
7.1.2.6 Windower/IZ (WIZ) Stage
The WIZ unit performs an early depth test, a major performance-optimization feature
where failing pixels are removed, thus eliminating unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels.
The Windower is also capable of performing dithering, whereby the illusion of a higher
resolution when using low-bpp channels in color buffers is possible. Color dithering
tends to diffuse the sharp color bands seen on smooth-shaded objects.
Datasheet 77
7.2 Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for full MPEG2, VC-1 and AVC decode in hardware to support high-definition content,
including next generation optical media (Blu-Ray Disc). The Gen 5.0 chipset engine
includes a number of encompassments over the previous generation capabilities, which
have been listed above. More details will be provided in a future revision of this
document.
7.3 2D Engine
The GMCH contains BLT (Block Level Transfer) functionality and an extensive set of 2D
instructions. To take advantage of the 3D drawing engines functionality, some BLT
functions make use of the 3D renderer.
7.3.1 Chipset VGA Registers
The 2D registers are a combination of registers for the original Video Graphics Array
(VGA) and others to support graphics modes that have color depths, resolutions, and
hardware acceleration features that go beyond the original VGA standard.
7.3.2 Logical 128-Bit Fixed BLT and 256 Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft
Windows* operating systems. The 128-bit GMCH BLT Engine provides hardware
acceleration of block transfers of pixel data for many common Windows operations. The
term BLT refers to a block transfer of pixel data between memory locations. The BLT
engine can be used for the following:
Move rectangular blocks of data between memory locations
Data Alignment
Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern will always be 8 x 8 pixels wide and may be 8, 16, or 32 bits
per pixel.
The BLT engine has the ability to expand monochrome data into a color depth of 8, 16,
or 32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data
specified to the destination. Transparent transfers compare destination color to source
color and write according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the GMCH can specify which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(Source, Pattern, and Destination) defined by Microsoft, including transparent BLT.
The GMCH has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The GMCH can perform
hardware clipping during BLTs.

Display I nterfaces
78 Datasheet
8 Display I nterfaces
The display converts a set of source images or surfaces, combines them and sends
them out at the proper timing to an output interface connected to a display device.
Along the way, the data can be converted from one format to another, stretched or
shrunk, and color corrected or gamma converted.
This chapter details the units of the GMCH that perform the action of formatting and
displaying the images generated by the IGDs graphics engines.
8.1 GMCH Display Overview
Integrated Graphics Display on the GMCH can be broken down into three components:
Display Planes
Display Pipes
DisplayPorts
8.1.1 Display Planes
A Display Plane is a single displayed surface in memory, usually containing one image
(desktop, cursor, overlay). It is the portion of the display HW logic which defines the
format and location of a rectangular region of memory that can be displayed on display
output device and delivers that data to a display pipe. This is clocked by the Core
Display Clock.
Figure 13. Mobile Intel 4 Series Express Chipset Family Display Block Diagram
Plane A
Cursor B
Sprite B
Plane B
Cursor A
Sprite A
Pipe B
Pipe A
Alpha
Blend/
Gamma/
Panel
Fitter
M
U
X
CRT
SDVO B/
C
TVOUT
LVDS
VGA
iHDMI
DP
Datasheet 79
Display I nterfaces
8.1.1.1 Planes A and B
Planes A and B are the main display Planes and are associated with Pipes A and B
respectively. The two display pipes are independent, allowing for support of two
independent display streams. They are both double-buffered, thus minimizing latency
and improving visual quality.
8.1.1.2 Sprite A and B
Sprite A and Sprite B are planes optimized for video decode, and are associated with
Planes A and B respectively. Sprite A and B are also double-buffered. Overlay is
supported through Sprite.
Note:
1. Overlay color control feature (brightness, contrast and saturation) is not supported
2. Overlay does not support planar YUV format (IMC3 and YUV12)
8.1.1.3 Cursors A and B
Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
and are associated with Planes A and B, respectively. These planes support resolutions
up to 256 x 256 each.
8.1.1.4 VGA
Used for boot, safe mode, legacy games etc. Can be changed by an application without
OS/driver notification, due to legacy requirements.
8.1.2 Display Pipes
The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is to be
displayed. This is clocked by the Display Reference clock inputs to the GMCH.
The display pipes A and B operate independently of each other at the rate of 1 pixel per
clock. They can attach to any of the display ports.
8.1.3 DisplayPorts
The DisplayPorts comprise output logic and pins that transmit the data to a display
device (CRT, panel, TV etc.) and the associated encoding logic. These are clocked by
GMCH clock outputs corresponding to the particular display device in use. This chapter
shall primarily discuss DisplayPorts. The GMCH supports the following DisplayPorts:
Analog
CRT
TV out
Digital
LVDS
SDVOB & SDVOC
iHDMI
DisplayPort (DP)
The next sections detail the capabilities of the analog and digital DisplayPorts.
Display I nterfaces
80 Datasheet
8.2 Analog DisplayPorts
8.2.1 CRT
The analog DisplayPort provides a RGB signal output along with a HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins
dedicated to the analog port. The intended target device is for a CRT based monitor
with a VGA connector. Display devices such as LCD panels with analog inputs may work
satisfactory but no functionality has been added to the signals to enhance that
capability.
8.2.1.1 Integrated DAC
The display function contains a Digital-to-Analog Converter (DAC) that transforms the
digital data from the graphics and video subsystems to analog data for the CRT
monitor, capable of supporting resolutions up to QXGA.
8.2.1.2 Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
These signals can be polarity adjusted and individually disabled in one of the two
possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support is included.
8.2.2 TV
The GMCH converts RGB data into various analog television standards (NTSC, PAL) and
formats (composite, S-Video) and provides it via the TV port. The data can be either
interlaced or progressive format. The TVout port has one 10-bit DAC for each of the
three analog outputs.
Table 16. Analog Port Characteristics
Signal Port Characteristic Support
RGB
Voltage Range 0.7 V p-p only
Monitor Sense Analog Compare
Analog Copy Protection No
Sync on Green No
HSYNC
VSYNC
Voltage 3.3 V
Enable/Disable Port control
Polarity Adjust VGA or port control
Composite Sync Support No
Special Flat Panel Sync No
Stereo Sync No
DDC
Voltage Externally buffered to 5 V
Control Through GPIO interface
Datasheet 81
Display I nterfaces
8.3 Digital DisplayPorts
8.3.1 LVDS
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an
electrical standard only defining driver output characteristics and receiver input
characteristics.
Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which
provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on
the input. When using both channels, each carry a portion of the data, thus doubling
the throughput to a maximum theoretical pixel rate of 224 MP/s.
There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS
interface. Channel A and Channel B consist of 4-data pairs and a clock pair each.
The LVDS data pair is used to transfer pixel data as well as the LCD timing control
signals.
Figure 14 shows a pair of LVDS signals and swing voltage.
1s and 0s are represented the differential voltage between the pair of signals. As
shown in the Figure 15 a serial pattern of 1100011 represents one cycle of the clock.
Figure 14. LVDS Signals and Swing Voltage
Figure 15. LVDS Clock and Data Relationship
Display I nterfaces
82 Datasheet
8.3.1.1 LVDS Pair States
The LVDS pairs can be put into one of five states:
Active
Powered down tri-state
Powered down 0 V
Common mode
Send zeros
When in the active state, several data formats are supported. When in powered down
state, the circuit enters a low-power state and drives out 0V or tri-states on both the
output pins for the entire channel. The common mode tri-state is both pins of the pair
set to the common mode voltage. When in the send zeros state, the circuit is powered
up but sends only zero for the pixel color data regardless what the actual data is with
the clock lines and timing signals sending the normal clock and timing data.
The LVDS Port can be enabled/disabled via Software. A disabled port enters a low-
power state. Once the port is enabled, individual driver pairs may be disabled based on
the operating mode. Disabled drivers can be powered down for reduced power
consumption or optionally fixed to forced 0s output.
Individual pairs or sets of LVDS pairs can be selectively powered down when not being
used. The panel power sequencing can be set to override the selected power state of
the drivers during power sequencing.
8.3.1.2 Single-Channel versus Dual-Channel Mode
In the single channel mode, only Channel-A is used. Channel-B cannot be used for
single channel mode. In the dual-channel mode, both Channel-A and Channel-B pins
are used concurrently to drive one LVDS display.
In Single-channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of
timing control (HSYNC/VSYNC/DE) and output them on three differential data pair
outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data
pair outputs. A dual-channel interface converts 36 or 48 bits of color information plus
the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of
differential data outputs respectively.
Dual-channel mode uses twice the number of LVDS pairs and transfers the pixel data at
twice the rate of the single channel. In general, one channel will be used for even pixels
and the other for odd pixel data. The first pixel of the line is determined by the display
enable going active and that pixel will be sent out Channel-A. All horizontal timings for
active, sync, and blank will be limited to be on two pixel boundaries in the two channel
modes.
Note: The GMCH supports 2- bpp display panels of Type 1 only (compatible with VESA LVDS
color mapping).
8.3.1.3 Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel
power, the backlight enable and the LVDS data timing delivery. to meet the panel power
timing specification requirements two signals, LFP_VDD_EN and LFP_BKLT_EN, are
provided to control the timing sequencing function of the panel and the backlight power
supplies.
Datasheet 83
Display I nterfaces
A defined power sequence is recommended when enabling the panel or disabling the
panel. The set of timing parameters can vary from panel to panel vendor, provided that
they stay within a predefined range of values. The panel VDD power, the backlight on/
off state and the LVDS clock and data lines are all managed by an internal power
sequencer.
NOTE: Support for programming parameters TX and T1 through T5 via SW is provided.
8.3.1.4 LVDS DDC
The display pipe selected by the LVDS display port is programmed with the panel timing
parameters that are determined by installed panel specifications or read from an
onboard EDID ROM. The programmed timing values are then locked into the registers
to prevent unwanted corruption of the values. From that point on, the display modes
are changed by selecting a different source size for that pipe, programming the VGA
registers, or selecting a source size and enabling the VGA.
8.3.2 iHDMI
The GMCH supports integrated HDMI multiplexed onto the PCI Express interface. For
details on the pin-mapping, see Chapter 6. As the PCI Express interface is AC coupled,
a level-shifter is required to translate the signals to the HDMI logic levels. The
integrated solution saves BOM cost compared to HDMI over SDVO.
The GMCH provides two ports capable of supporting HDMI. However, Intel HD Audio
can be supported on any one of the iHDMI ports at any given point. A separate audio
path shall be required for the other port.
For Integrated HDMI, the integrated HDMI transmitter receives both the digital video
and audio data which it synchronizes before it transmits the data across a single cable
connection to the HDMI receiver on the HDMI sink.
Figure 16. Panel Power Sequencing
Power On Sequence from off state and
Power Off Sequence after full On
Panel VDD
Enable
Panel
BackLight
Enable
Clock/Data Lines
T1+T2 T5 T3
Valid
T4
Panel
On
Off Off
TX T4
Display I nterfaces
84 Datasheet
Note:
1. Even V-Total Interlaced mode is not supported.
2. Integrated Intel High Definition Audio can be used only with iHDMI.
3. OEMs need to ensure that when using integrated Intel High Definition Audio, the
Intel High Definition Audio power supply on the ICH side also needs to be 1.5 V. If
not, damage to the GMCH may result.
8.3.2.1 HDCP
The GMCH supports HDCP via the iHDMI interface on any one iHDMI port at a given
point. A high-level block diagram of integrated HDMI/HDCP on the Intel Centrino 2
platform is in Figure 17.
8.3.3 DisplayPort (DP)
The DisplayPort abbreviated as DP (different than the generic term display port)
specification is a VESA standard aimed at consolidating internal and external
connection methods to reduce device complexity, supporting key cross industry
applications, and providing performance scalability to enable the next generation of
displays. The GMCH supports HDCP on the DP interface also.
The DP is multiplexed onto the PCI Express interface. For details on the pin-mapping,
see Chapter 6.
The GMCH has 3 DP ports, each capable of supporting link-speeds of 1.62 Gbps and
2.7 Gbps on 1, 2 or 4 data lanes.
Note:
1. Even V-Total Interlaced mode is not supported.
2. The GMCH can support a maximum of 2 DP ports simultaneously. See Section 8.4
for details.
3. The Embedded DisplayPort (eDP) is a dedicated DP port for the embedded display
(e.g., Local Flat Panel) and is supported via port D of the DP interface. Ports B and
C of the DP interface are also occasionally referred to as the Integrated
DisplayPort.
Figure 17. Integrated HDMI w/HDCP on Intel Centrino 2
(G)MCH
ICH
Level
Shifter
Intel HD
Audio Bus
HDMI with HDCP
DMI
HDMI
Display
Datasheet 85
Display I nterfaces
8.3.3.1 DP Aux Channel
A bi-directional AC coupled AUX channel interface replaces the I
2
C on the DP. These
pins are also muxed onto the PCI Express interface. I
2
C-to-Aux bridges shall be
required to connect legacy EDID DP devices.
8.3.3.2 DP Hot-Plug Detect (HPD)
The GMCH supports HPD for Hot-Plug and sink events on the DP interface.
8.3.4 SDVO
SDVO supports a variety of display types LVDS, DVI, TV-Out, HDMI, and external CE
type devices. Though the SDVO electrical interface is based on the PCI Express
interface, the protocol and timings are completely unique. The GMCH utilizes an
external SDVO device to translate from SDVO protocol and timings to the desired
display format and timings.
The internal graphics controller can have one or two SDVO ports multiplexed on the
x16 PCI Express interface.
The ports can be dynamically configured in the following modes:
Standard Baseline SDVO functionality. Supports Pixel Rates between 25 and
225 MP/s. Utilizes three data pairs to transfer RGB data.
Dual Standard Utilizes two standard data streams across both SDVO B and
SDVO C. There are two types of dual standard modes:
Dual Independent Standard - Each SDVO channel will see a different pixel
stream. The data stream across SDVO B will not be the same as the data
stream across SDVO C.
Figure 18. SDVO Conceptual Block Diagram
Digital
Display
Device(s)
or TV
Internal
Graphics
PCI
Express
Logic
P
C
I

E
x
p
r
e
s
s

x
1
6

P
o
r
t

P
i
n
s
S
D
V
O

P
o
r
t

B
S
D
V
O

P
o
r
t

C
3
rd
Party
SDVO
External
Device(s)
TV Clock In
Stall
Interrupt
Control Clock
Control Data
ClockC
RedC
GreenC
BlueC
ClockB
RedB
GreenB
BlueB
Analog RGB Monitor
GMCH
Display I nterfaces
86 Datasheet
Dual Simultaneous Standard - Both SDVO channels will see the same pixel
stream from a single pixel pipeline. The display timings will be identical, but the
transfer timings may not, for example the timing between the two channels as
seen at the SDVO device(s) may not be perfectly aligned.
8.3.4.1 SDVO Control Bus
The SDVO Control clock (SDVO_CTRLCLK) and data (SDVO_CTRLDATA) provide similar
functionality to I
2
C. Traffic destined for the PROM or DDC will travel across the control
bus, and will then require the SDVO device to act as a switch and direct traffic from the
control bus to the appropriate receiver. Additionally, the control bus can operate at up
to 1 MHz.
8.4 Co-Existence of DisplayPorts
The Table 17 describes the valid interoperability between display technologies.
Single Pipe Single Display is a mode with one display port activated to display
the output to one display device.
Intel Dual Display Clone is a mode with both display ports activated to display
the same output to two different display devices with the same color depth setting,
but different refresh rate and resolution settings.
Intel Dual Display Twin is a mode with one display port activated to display the
same output to two different display devices with the same color depth, refresh
rate, and resolution settings.
Extended Desktop is a mode with both display ports activated used to display two
different outputs to two different display devices with different color depth, refresh
rate, and resolution settings.
Table 17. DisplayPort Co-Existence Table (Sheet 1 of 2)
Display
Not
Attached
DAC
Integrated
LVDS
TV Out
Integrated
DP
HDMI
CRT TV
Not
Attached
X S S S S S
DAC CRT S X S
1
, C, E, T S
1
, C, E A A
Integrated
LVDS
S S
1
, C, E, T X S
1
, C, E S
1
, C, E, T S
1
, C, E, T
TV
Out
TV S S
1
, C, E S
1
, C, E X S
1
, C, E S
1
, C, E
Integrated
DP
S A S
1
, C, E, T S
1
, C, E A A
HDMI S A S
1
, C, E, T S
1
, C, E A X
SDVO CRT S A S
1
, C, E, T S
1
, C, E A A
SDVO DVI S A S
1
, C, E, T S
1
, C, E A A
SDVO HDMI S A S
1
, C, E, T S
1
, C, E A X
Datasheet 87
Display I nterfaces

SDVO LVDS S S
1
, C, E, T X S
1
, C, E S
1
, C, E, T S
1
, C, E, T
SDVO TV S S
1
, C, E S
1
, C, E X S
1
, C, E S
1
, C, E
A = Single Pipe Single Display, Dual Display Clone/Twin Mode (Only 24 bpp), or Extended
Desktop Mode
C = Clone Mode
E = Extended Desktop Mode
S = Single Pipe Single Display
S
1
= Single Pipe Single Display With One Display Device Disabled
T = Twin Mode (Only 24 bpp) Supported By Displaying SSC Clock
X = Unsupported
Table 18. Display Port Co-Existence Table
Display SDVO CRT SDVO DVI SDVO HDMI SDVO LVDS SDVO TV
Not Attached S S S S S
DAC CRT A A A S
1
, C, E, T S
1
, C, E
Embedded DP S
1
, C, E, T S
1
, C, E, T S
1
, C, E, T X S
1
, C, E
Integrated
LVDS
S
1
, C, E, T S
1
, C, E, T S
1
, C, E, T X S
1
, C, E
TV Out TV S
1
, C, E S
1
, C, E S
1
, C, E S
1
, C, E X
Integrated DP A A A S
1
, C, E, T S
1
, C, E
HDMI A A X S
1
, C, E, T S
1
, C, E
SDVO CRT A A A A A
SDVO DVI A A A A A
SDVO HDMI A A X A A
SDVO LVDS A A A X A
SDVO TV A A A A A
A = Single Pipe Single Display, Dual Display Clone/Twin Mode (Only 24 bpp), or Extended
Desktop Mode
C = Clone Mode
E = Extended Desktop Mode
S = Single Pipe Single Display
S
1
= Single Pipe Single Display With One Display Device Disabled
T = Twin Mode (Only 24 bpp) Supported By Displaying SSC Clock
X = Unsupported
Table 17. DisplayPort Co-Existence Table (Sheet 2 of 2)
Display
Not
Attached
DAC
Integrated
LVDS
TV Out
Integrated
DP
HDMI
CRT TV
Power Management and Sequencing
88 Datasheet
9 Power Management and
Sequencing
This chapter details the various power management capabilities of the GMCH.
9.1 Power Management Features
Refer to the ACPI Specification Revision 3.0 for an overview of the system power states
mentioned in this chapter.
9.1.1 Dynamic Power Management on I/O
The GMCH provides several features to reduce I/O power dynamically.
9.1.1.1 Host
H_DPWR# signal disables processor sense amps when no read return data is
pending.
9.1.1.2 System Memory
Dynamic-power-down of unused ranks of memory.
Intel Rapid Memory Power Management conditionally places memory into self-
refresh based on C state, PCI Express link states, and graphics/display activity.
9.1.1.3 PCI Express
Active power management support using L0s, and L1 states.
All inputs and outputs disabled in L2/L3 Ready state.
9.1.1.4 DMI
Active power management support using L0s/L1 state.
All inputs and outputs disabled in L2/L3 Ready state.
9.1.1.5 Intel Management Engine
Active power management support for Intel AMT capable systems via M0, M1 and
M-off states.
Datasheet 89
9.1.2 System Memory Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
9.1.2.1 Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a SO-DIMM connector in which
it is not connected to any actual memory devices (such as SO-DIMM connector is
unpopulated, or is single-sided) will be tri-stated.
The benefits of disabling unused SM signals are:
Reduce power consumption
Reduce possible overshoot/undershoot signal quality issues seen by the GMCH
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated (as determined by the DRAM Rank Boundary
register values) then the corresponding chip select and SCKE signals will not be driven.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
9.1.2.2 Dynamic Power Management of Memory
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. If the pages for a rank have
all been closed at the time of power down, then the device will enter the precharge
power-down state. If pages remain open at the time of power-down the devices will
enter the active power-down state.
9.1.2.3 Conditional Self-Refresh
The GMCH supports Intel Rapid Memory Power Management which conditionally places
memory into self-refresh in the C3, C4, C5 and Deep Power-Down Technology (code
named C6) state, based on the graphics/display (if internal graphics is being used) and
on the state of the PCI Express links.
The target behavior is to enter self-refresh for C3/C4/C5/Deep Power-Down Technology
(code named C6) state as long as there is no memory requests to service. The target
usage is shown in the Table 19.
Table 19. Targeted Memory State Conditions
Mode Memory State with Internal Graphics Memory State with External Graphics
C0, C1, C2
Dynamic memory rank power-down based on
idle conditions.
idle conditions.
C3, C4, C5,
Deep Power
Down
Technology
(code
named C6)
idle conditions.
If graphics engine is idle, no display requests,
and permitted display configuration, then enter
self-refresh. Otherwise use dynamic memory
rank power-down based on idle conditions.
idle conditions.
If there are no memory requests, then enter
self-refresh. Otherwise use dynamic memory
rank power down based on idle conditions.
S3 Self Refresh Mode Self Refresh Mode
S4 Memory power-down (contents lost) Memory power-down (contents lost)
90 Datasheet
9.2 ACPI States Supported
This section details the support provided by the GMCH corresponding to the various
CPU/Display/System ACPI states. Descriptions provided in this section shall be used in
Section 9.4.
9.2.1 System
9.2.2 Processor
9.2.3 Internal Graphics Display Device Control
State Description
G0/S0 Full On
G1/S1 Not supported
G1/S2 Not supported
G1/S3-Cold
Suspend to RAM (STR). Context saved to memory (S3-Hot is not supported by
the GMCH)
G1/S4 Suspend to Disk (STD). All power lost (except wakeup on ICH)
G2/S5 Soft off. All power lost (except wakeup on ICH). Total reboot
G3 Mechanical off. All power (AC and battery) removed from system
State Description
C0 Full On
C1/C1E Auto Halt
C2/C2E Stop Grant. Clock stopped to processor core.
C3 Deep Sleep. Clock to processor stopped.
C4/C4E Deeper Sleep. Same as C3 with reduced voltage on the processor.
C5
Enhanced Deeper Sleep. Lower core voltage than C4 and L2 cache
flushed.
Deep Power Down
Technology (code
named C6)
Deep Power Down Technology state. Core power below VCC_min, with L2
cache invalidated.
State Description
D0 Display Active
D1 Low-power state, low latency recovery, Standby display
D2 Suspend display
D3 power-off display
Datasheet 91
9.2.4 Internal Graphics Adapter
9.3 Interface Power States Supported
9.3.1 PCI Express Link States
9.3.2 Main Memory States
State Description
D0 Full on, display active
D3 Cold power-off
State Description
L0 Full on Active transfer state
L0s First Active Power Management low-power state Low exit latency
L1 Lowest Active Power Management - Longer exit latency
L2/L3 Ready Lower link state with power applied Long exit latency
L3 Lowest power state (power-off) Longest exit latency
State Description
Power up CKE asserted. Active mode
Pre-charge Power down CKE deasserted (not self-refresh) with all banks closed
Active Power down CKE deasserted (not self-refresh) with min. one bank active
Self-Refresh CKE deasserted using device self-refresh
92 Datasheet
9.4 Chipset State Combinations
GMCH supports the state combinations listed in the Table 20 and Table 21.

Table 20. G-, S- and C-State Combinations
Global
(G) State
Sleep
(S) State
CPU
(C) State
Processor
State
System Clocks Description
G0 S0 C0 Full On On Full On
G0 S0 C1 Auto-Halt On Auto Halt
G0 S0 C2 Stop Grant On Stop Grant
G0 S0 C3 Deep Sleep On Deep Sleep
G0 S0 C4 Deeper Sleep On
Deep Sleep with
processor voltage
lowered.
G0 S0
IC5/Deep
Power Down
Technology
(code
named C6)
On
Deep Sleep with
processor voltage
lowered.
G1 S3 power-off - Off, except RTC Suspend to RAM
G1 S4 power-off - Off, except RTC Suspend to Disk
G2 S5 power-off - Off, except RTC Soft Off
G3 NA power-off - power-off Hard Off
Table 21. D-, S-, and C-State Combinations
Graphics Adapter
(D) State
Sleep (S)
State
CPU (C) State Display Device State
D0 S0 C0 Displaying
D0 S0 C1 Displaying
D0 S0 C2 Displaying
D0 S0 C3 Displaying
D0 S0 C4 Displaying
D0 S0
C5/Deep Power Down Technology
(code named C6)
Displaying
D3 S0
C0-2/ C3/C4/C5/Deep Power Down
Technology (code named C6)
Not Displaying
D3 S3 -
Not Displaying
GMCH may power-off
D3 S4 -
Not Displaying
Suspend to disk
Datasheet 93
9.4.1 CPU Sleep (H_CPUSLP#) Signal Definition
The processors sleep signal (SLP#) reduces power in the processor by gating off
unused clocks in the C2-popup states or lower. This signal can be driven only by the
GMCHs H_CPUSLP# signal.
The GMCH host interface controller will ensure that no transactions will be initiated on
the FSB without having first met the required timing from the SLP# deassertion to the
assertion of BPRI#.
GMCH will control H_CPUSLP# and enforce the associated configured timing rules
associated.
9.5 CLKREQ# - Mode of Operation
The CLKREQ# signal is driven by the GMCH to control the PCI Express clock to the
external graphics and the DMI clock. When both the DMI and PCI Express links (if sup-
ported) are in L1, with CPU in C4 (and lower states), the GMCH deasserts CLKREQ# to
the clock chip, allowing it to gate the GCLK differential clock pair to the GMCH, in turn
disabling the PCI Express and DMI clocks inside the GMCH. For the GMCH to support
CLKREQ# functionality, ASPM must enabled on the platform.
9.6 Intel Display Power Saving Technology
(Intel DPST) 4.0
Intel DPST maintains apparent visual experience by managing display image brightness
and contrast while adaptively dimming the backlight. As a result, the display backlight
power can be reduced by up to 25% with minimal visual impact depending on Intel
DPST settings and system use.
Intel DPST 4.0 provides enhanced image quality over the previous version of Intel
DPST.
9.7 FSB Dynamic Frequency Switching
See Section 3.8 for details on FSB Dynamic Frequency Switching.
9.8 Render Standby States
Graphics Render Standby is a technique designed to optimize the average power to the
GMCH. (This technique requires a separate Graphics VRM.) GMCH will put the Graphics
Render engine to Render Standby (RS) state, during times of inactivity or basic video
modes. While in Render Standby state, the GMCH will place the VR into a low voltage
state through VID signals. To indicate a condition where GMCH Render core is in a very
low-power state, the GMCH will place the render engine into a RS-state and will change
the VID code to the Render core VR to a lower voltage state.
Below is the Render Core Standby-states supported and corresponding voltages on the
GMCH. The Render Core clock is gated in all the below states.
RSx Core Voltage (V)
RS2 0.55 V
94 Datasheet
9.9 Render Thermal Throttling
Render Thermal Throttling of the graphics core allows for the reduction of frequency of
the render core engine, thus reducing graphics power and chipset thermals.
Performance is degraded, but the platform's thermal burden is relieved.
Render Thermal Throttling uses several P-states that can be used to throttle the render
core. Each P-state has a frequency assigned to it. As the temperature of chipset
thermal sensor exceeds the Hot-trip point, the graphics engine begins to reduce
frequency, dropping to the first p-state. After a timeout, the DTS is rechecked, and if
the DTS temperature is still greater than the designed hysteresis, frequency is again
reduced. Render frequency will not increase in frequency unless the DTS temperature
falls below the hysteresis. Once this point occurs, P-states immediately step back up to
the previous highest frequency (one before trip point).
Datasheet 95
Absolute Maximum Ratings
10 Absolute Maximum Ratings
Table 22 specifies the GMCHs absolute maximum and minimum ratings. Within
functional operation limits (specified in Chapter 12 and 13), functionality and long-term
reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the GMCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
Table 22. Absolute Maximum Ratings (Sheet 1 of 2)
Symbol Parameter Min Max Unit Notes
T
die
Die Temperature under Bias 0 100 C 1
T
storage
Storage Temperature
-55 150 C 2, 3, 4
-25 150 C 2, 3, 5
GMCH
V
CC
1.05-V Core Supply Voltage with respect to V
SS
-0.3 1.155 V
V
CC_AXG
1.05-V Graphics Voltage with respect to V
SS
-0.3 1.155 V
M LINK
V
CC
1.05-V Controller link voltage with respect to V
SS
-0.3 1.115 V
Host Interface
V
TT
(FSB V
CCP
)
1.05-V AGTL+ buffer DC Input Voltage with
respect to V
SS

-0.3 1.32 V
V
CC_AXF
1.05-V DC Input Voltage for AGTL+ buffer logic
with respect to V
SS

-0.3 1.155 V
DDR2 (667-MTs/800-MTs)/ DDR3 (800-MTs/1066-MTs) Interfaces
V
CC_SM
1.5/1.8-V DDR3/DDR2 Supply Voltage with
Respect to V
SS
.
-0.3 2.1 V
V
CC_SM_CK
1.5/1.8-V DDR3/DDR2 Clock IO Voltage with
Respect to V
SS
.
-0.3 2.1 V
V
CCA_SM
1.05-V DDR3/DDR2 Voltage connects to IO logic
and DLLs with Respect to V
SS
.
-0.3 1.155 V 6
96 Datasheet
NOTES:See next page.
V
CCA_SM_CK
1.05-V DDR2/DDR3 Voltage for clock module to
avoid noise with Respect to V
SS
.
-0.3 1.155 V 6
DMI /PCI Express Graphics/SDVO Interface/HDMI/DP
V
CC_PEG
1.05-V PCI-Express Supply Voltage with respect to
V
SS
-0.3 1.155 V
V
CC_DMI
1.05-V DMI Terminal Supply Voltage with respect
to V
SS
-0.3 1.155 V
V
CCA_PEG_BG
3.3-V Analog Band Gap Voltage with respect to
VSSA_PEG_BG
-0.3 3.63 V
V
CCA_PEG_PLL
Analog PLL Voltage for PCI Express-Based
Graphics
-0.3 1.155 V
V
CCD_PEG_PLL
Digital PLL Voltage for PCI Express-Based
Graphics
-0.3 1.155 V
CRT DAC Interface (8 bit DAC)
V
CCA_CRT_DAC
3.3-V DAC IO Supply Voltage -0.3 3.63 V
V
CCD_QDAC
1.5-V CRT Quiet Digital Voltage -0.3 1.65 V
HV CMOS Interface
V
CC_HV
3.3-V Supply Voltage with respect to V
SS
-0.3 3.63 V
TV OUT Interface (10 bit DAC)
V
CCD_TVDAC
1.5-V TV Supply -0.3 1.65 V
V
CCA_TV_DAC
3.3-V TV Analog Supply -0.3 3.63 V
V
CCA_DAC_BG
3.3-V TV DAC Band Gap voltage -0.3 3.63 V
V
CCD_QDAC
1.5-V Quiet Supply -0.3 1.65 V
LVDS Interface
V
CCD_LVDS
1.8-V LVDS Digital Power Supply -0.3 1.98 V
V
CC_TX_LVDS
1.8-V LVDS Data/Clock Transmitter Supply
Voltage with respect to V
SS
-0.3 1.98 V
V
CCA_LVDS
1.8-V LVDS Analog Supply voltage with respect to
V
SS
-0.3 1.98 V
PLL Analog Power Supplies
V
CCA_HPLL
V
CCD_HPLL
V
CCA_MPLL
V
CCA_DPLLA
V
CCA_DPLLB
1.05-V Power Supply for various PLL -0.3 1.155 V
Intel High Definition Audio
V
CC_HDA
1.5 V -0.3 1.65 V
Table 22. Absolute Maximum Ratings (Sheet 2 of 2)
Datasheet 97
1. Functionality is not guaranteed for parts that exceed Tdie temperature above 100 C. Tdie is measured
using the integrated digital thermal sensor (DTS). Performance may be affected if the on-die thermal
sensor is enabled and the die temperature spec is exceeded.
2. Possible damage to the GMCH may occur if the GMCH storage temperature exceeds 150 C. Intel does not
guarantee functionality for parts that have exceeded temperatures above 150 C due to spec violation.
3. Storage temperature is applicable to storage conditions only. In this scenario, the device must not receive
a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long-
term reliability of the device. This rating applies to the silicon and does not include any tray or packaging.
4. This storage temperature data is for all Mobile Intel 4 Series Express Chipset Family except Mobile Intel
GS45 and GS40 Express Chipsets.
5. This storage temperature data is for the Mobile Intel GS45 and GS40 Express Chipsets.
6. These values assume that MPLL is turned ON.
10.1 Power Characteristics
NOTES:
1. Thermal design power (TDP) does not represent the worst case possible power of the product and is not
intended for power delivery or Icc,max specifications. TDP is an Intel characterized value intended to
represent the maximum measured 5 second moving average power of the product while running typical
application workloads and is useful for the product thermal design requirements. This characterized value
is valid with the product Tj operation range and nominal Vcc.
2. FSB/DDR2 667 MHz/667 MHz and FSB/DDR3 800 MHz/800 MHz with no-ODT.
Table 23. Thermal Design Power Number
SKU
GFX/GMCH Core
voltage (V)
Max GFX Core
Frequency (MHz)
TDP (W) Notes
Intel GM45 1.05/1.05 533 12 1
Intel GS45 (Low-power)
1.00/1.05 320 7 1,2
1.05/1.05 533 (for playback) 8 1,2
Intel GS45 (High-
Performance)
1.05/1.05 533 12 1
Intel GL40 1.05/1.05 400 12 1
Intel GS40 1.05/1.05 400 12 1
Intel PM45 0/1.05 NA 7 1
98 Datasheet
Table 24. Power Characteristics (Sheet 1 of 2)
Symbol Parameter Signal Names Min Typ Max Unit Notes
GMCH
I
VCC
(totalw/E GFX)

Core + IMEL + HSIO 3060 mA 8
I
VCC
(totalw/I GFX)

Core + IMEL + HSIO
2400 mA 8, 11
2200 mA 8, 10
1900 mA 8,12
1800 mA 8, 9
I
VCC_AXG
Graphics Core Supply
Current
9600 mA 1
7700 mA 1, 10
8000 mA 1, 11
6387 mA 1, 12
4700 mA 1, 9
Host Interface
I
VTT
FSB at 1066
MHz
V
TT
Supply Current
(1.05 V)
852 mA
DMI /PCI Express Graphics/SDVO Interface
I
VCC_PEG

1.05 V PCI-Express
Supply Current
1782 mA 1, 2, 5
I
VCC_DMI

1.05 V DMI
termination Supply
current
456 mA 1
I
VCCA_PEG_BG
Band Gap Current 414 A 1
CRT DAC Interface (8 bit DAC)
I
VCCA_CRT_DAC
3.3-V DAC IO Supply
Current
73 mA 1, 5
I
VCCD_QDAC
1.5-V CRT Quiet
Digital Current
500 A
HV CMOS Interface
I
VCC_HV
3.3-V Supply Current 105.3 mA 1
TV OUT Interface (10 bit DAC)
I
VCCD_TVDAC
1.5-V TV Supply 35 mA 1, 5
I
VCCA_TV_DAC
3.3-V TV Analog
Supply
79 mA 1, 5
I
VCCA_DAC_BG
3.3-V TV Analog
Supply
5 mA 1
I
VCCD_QDAC
1.5-V Quiet Supply 500 A 1
Thermal Sensor
I
VCCD_QDAC
1.5-V Thermal Sensor
Current
1700 A
Datasheet 99
NOTES:
1. Estimate is only for max current coming through the chipsets supply balls.
2. Rail includes PLL current.
3. Includes worst case Leakage.
4. Calculated for highest stretch goal frequencies.
5. I
CCMAX
is determined on a per-interface basis, and all can not happen simultaneously.
6. I
CCMAX
number includes max current for all signal names listed in this table.
7. CLink power consumption is only for the Intel ME core logic.
8. Intel ME Link and DDR HSIO are on the V
CC_CORE
rail.
9. This current data is for Mobile Intel GS45 Express Chipset in low-power mode.
10. This current data is for Mobile Intel GS45 Express Chipset in high-performance mode.
11. This current data is for Mobile Intel GM45 Express Chipset.
12. This current data is for Mobile Intel GL40 and GS40 Express Chipsets.
LVDS Interface
I
VCCD_LVDS
1.8-V LVDS Digital
Power Supply
30 mA 1
I
VCC_TX_LVDS
1.8-V LVDS Data/
Clock Transmitter
Supply Voltage with
respect to V
SS
80 mA 1
I
VCCA_LVDS
1.8-V LVDS Analog
Supply voltage with
respect to V
SS
10 mA 1
PLL Analog Power Supplies
I
VCCA_HPLL
Host PLL Supply
Current
V
CCA_HPLL
24 mA 1
I
VCCD_HPLL
HPLL Supply Current
for Digital Interface
V
CCD_HPLL
157.2 mA 1
I
VCCA_DPLLA
I
VCCA_DPLLB
Display PLLA Supply
Current
Display PLLB Supply
Current
V
CCA_DPLLA
V
CCA_DPLLB
64.8 mA 1
I
VCCA_MPLL
Memory PLL Supply
Current
V
CCA_MPLL
139.2 mA 1
I
VCCA_PEG_PLL
Analog PLL Supply
current
V
CCA_PEG_PLL
50 mA 1
I
VCCD_PEG_PLL
Digital PLL Supply
current
V
CCD_PEG_PLL
50 mA 1
I
VCC_HDA
1.5-V Intel HD Audio
Supply Current
50 mA 1
Table 24. Power Characteristics (Sheet 2 of 2)
Symbol Parameter Signal Names Min Typ Max Unit Notes
100 Datasheet
NOTE: CLink power consumption is only for the Intel Management Engine core logic. Standby in Table 25 refers to
system memory in Self Refresh during S3 (STR).
Table 25. DDR2 (667/800 MTs) Power Characteristics
Symbol Parameter Min Typ Max Unit Notes
I
VCC_SM
DDR2 System Memory Interface
(1.8 V, 667 MTs) Supply Current
2600 mA
I
VCC_SM
(1.8 V, 800 MTs) Supply Current
3000 mA
I
VCC_SM_CK
DDR2 System Memory Interface Clock Supply
Current (667 MTs)
119.85 mA
I
VCC_SM_CK
DDR2 System Memory Interface Clock Supply
Current (800 MTs)
124 mA
I
VCCA_SM
IO Logic and DLL Current(1.05 V, 667 MTs) 480 mA
I
VCCA_SM
IO Logic and DLL Current(1.05 V, 800 MTs) 720 mA
I
VCCA_SM_CK
Clock Logic Current (1.05 V, 667 MTs) 24 mA
I
VCCA_SM_CK
Clock Logic Current (1.05 V, 800 MTs) 26 mA
I
SUS_VCCSM
(1.8 V) Standby Supply Current
1 mA
See
Note
I
SMVREF
DDR2 System Memory Interface Reference
Voltage (0.90 V) Supply Current
50 A
I
SUS_SMVREF
Voltage (0.90 V) Standby Supply Current
200 A
See
Note
I
TTRC
DDR2 System Memory Interface Resister
Compensation Voltage (1.8 V) Supply Current
2 mA
I
SUS_TTRC
Compensation Voltage (1.8 V) Standby Supply
Current
2 mA
Datasheet 101
NOTE: Standby in Table 4 refers to system memory in Self Refresh during S3(STR).
NOTES:
1. This current data is for Mobile Intel GM45 Express Chipset and Mobile Intel GS45 Express
Chipset in high-performance mode.
2. This current data is for Mobile Intel GS45 Express Chipset in low-power mode.
3. This current data is for Mobile Intel GL40 and GS40 Express Chipsets.

Table 26. DDR3 (800 /1066 MTs) Power Characteristics
I
VCC_SM
DDR3 Supply Current
(1.5 V, 1066 MTs)
4140 mA
I
VCC_SM
DDR3 Supply Current (1.5 V, 800 MTs) 3162.5 mA
I
VCC_SM_CK
DDR3 Clock Supply Current (1.5 V, 1066 MTs) 149.5 mA
I
VCC_SM_CK
DDR3 Clock Supply Current
(1.5 V, 800 MTs)
143.75 mA
I
VCCA_SM
IO Logic and DLL Current
(1.05 V, 1066 MTs)
747.5 mA
I
VCCA_SM
IO Logic and DLL Current (1.05 V,
800 MTs)
575 mA
I
VCCA_SM_CK
Clock Logic Current (1.05 V, 1066 MTs) 37.95 mA
I
VCCA_SM_CK
Clock Logic Current (1.05 V, 800 MTs) 28.75 mA
I
SUS_VCCSM
(1.5-V) Standby Supply Current
1 mA
See
Note
I
SMVREF
Voltage Supply Current
50 A
I
SUS_SMVREF
Voltage Standby Supply Current
200 A
See
Note
I
TTRC
Compensation Voltage (1.5-V) Supply Current
2 mA
I
SUS_TTRC
Compensation Voltage (1.5-V) Standby Supply
Current
2 mA
Table 27. V
CC
Auxiliary Power Characteristics
I
VCC_AXF
Supply current FSB IO and HSIO
440 mA 1
324 mA 2
330 mA 3
Thermal Management
102 Datasheet
11 Thermal Management
System level thermal management requires comprehending thermal solutions for two
domains of operation:
1. Robust Thermal Solution Design: The systems thermal solution should be capable
of dissipating the platforms TDP power while keeping all components below the
relevant Tdie_max under the intended usage conditions. Such conditions include
ambient air temperature and available airflow inside the laptop.
2. Thermal Failsafe Protection Assistance: As a backup to the implemented thermal
solution, the system design should provide a method to provide additional thermal
protection for the components of concern. The failsafe assistance mechanism is to
help manage components from being damaged by excessive thermal stress under
situations in which the implemented thermal solution is inadequate or has failed.
The GMCH provides two internal thermal sensors, plus hooks for an external thermal
sensor mechanism. These can be used for detecting the component temperature and
for triggering thermal control within the GMCH. The GMCH has implemented several
silicon level thermal management features that can lower both GMCH and DDR power
during periods of high activity. These features can help control temperature of the
GMCH and DDR and thus help prevent thermally induced component failures. These
features include:
Memory throttling triggered by memory heating
Memory throttling triggered by GMCH heating
THRMTRIP# support
11.1 Internal Thermal Sensor
The GMCH incorporates two on-die thermal sensors for thermal management.
The thermal sensors may be programmed to cause hardware throttling and/or software
interrupts. Hardware throttling includes render and main memory programmable
throttling thresholds. Sensor trip points may also be programmed to generate various
interrupts including SCI, SMI, SERR, or an internal graphics interrupt.
11.1.1 Internal Thermal Sensor Operation
The internal thermal sensor reports six trip points: Aux0, Aux1, Aux2, Aux3, Hot and
Catastrophic trip points in the order of increasing temperature.
Aux0, 1, 2, 3 Temperature Trip Points
These trip points may be set dynamically if desired and provides an interrupt to ACPI
(or other software) when it is crossed in either direction. These auxiliary temperature
trip points do not automatically cause any hardware throttling but may be used by
software to trigger interrupts. Additionally, the Aux2 trip point supports an output pin -
TSATN#. This pin can be used to notify platform logic when GMCH temperature crosses
the Aux2 setting. See Section 11.5 for more details.
Datasheet 103
Thermal Management
Hot Temperature Trip Point
This trip point is set at the temperature at which the GMCH must start throttling. It may
optionally enable GMCH throttling when the temperature is exceeded. This trip point
may provide an interrupt to ACPI (or other software) when it is crossed in either
direction. Software could optionally set this as an Interrupt when the temperature
exceeds this level setting.
Catastrophic Trip Point
This trip point is set at the temperature at which the GMCH must be shut down
immediately without any software support. This trip point may be programmed to
generate an interrupt, enable throttling, or immediately shut down the system (via
Halt, or via THERMTRIP# assertion).
Crossing a trip point in either direction may generate several types of interrupts. Each
trip point has a register to select what type of interrupt is generated. Crossing a trip
point is implemented as edge detection, used to trigger the interrupts. Either edge
(i.e., crossing the trip point in either direction) generates the interrupt.
11.1.1.1 Recommended Programming for Available Trip Points
Thermal Sensors are not located in hotspot of GMCH. Thermal Sensors may be up to
3C lower than maximum T
j
of GMCH. Trip points should be set to account for
temperature offset between thermal sensors and maximum T
j
hotspot and thermal
sensor accuracy.
Aux Trip Points (0, 1, 2, 3) should be programmed for software and firmware control
via interrupts. Tjmax is 100 C. Intel suggests that Hot Trip Point should be set to
throttle at 102 C due to DTS trim accuracy adjustments. Intel guarantees functionality
up until 102 C. Catastrophic Trip Point should be set to halt operation to avoid
maximum T
j
of 130 C.
Note: Crossing a trip point in either direction may generate several types of interrupts. Each
trip point has a register that can be programmed to select the type of interrupt to be
generated. Crossing a trip point is implemented as edge detection on each trip point to
generate the interrupts.
11.1.1.2 Thermal Sensor Accuracy (T
accuracy
)
T
accuracy
for GMCH is 5 C for temperature range 80 C to 110 C. Temperature
reading accuracy from Thermal sensor will degrade further with junction temperatures
below +80 C. Temperature readings from Thermal Sensor may not be available below
+40 C. GMCH may not operate above +102 C. This value is based on product
characterization and is not guaranteed by manufacturing test.
Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip
points should be selected with consideration for the thermal sensor accuracy and the
quality of the platform thermal solution. Overly conservative (unnecessarily low)
temperature settings may unnecessarily degrade performance due to frequent
throttling, while overly aggressive (dangerously high) temperature settings may fail to
protect the part against permanent thermal damage.
Thermal Management
104 Datasheet
11.1.2 Hysteresis Operation
Hysteresis provides a small amount of positive feedback to the thermal sensor circuit to
prevent a trip point from flipping back and forth rapidly when the temperature is right
at the trip point.
The digital hysteresis offset is programmable to be 0,1, 215, which corresponds to an
offset in the range of approximately 0 to 7 C.
11.2 Memory Thermal Throttling Options
The GMCH has two independent mechanisms that cause system memory throttling.
GMCH Thermal Management: Ensures that the chipset is operating within thermal
limits. The mechanism can be initiated by a thermal sensor (internal) trip or by
virtual thermal sensor bandwidth measurement exceeding a programmed threshold
via a weighted input averaging filter.
DRAM Thermal Management: Ensures that the DRAM chips are operating within
thermal limits. The GMCH can control the amount of GMCH - initiated bandwidth
per rank to a programmable limit via a weighted input averaging filter.
11.3 External Thermal Sensor Interface Overview
The GMCH supports two inputs for external thermal sensor notifications, based on
which it can regulate memory accesses.
Note: The thermal sensors should be capable of measuring the ambient temperature only and
should be able to assert PM_EXT_TS# [1:0] if the pre-programmed thermal limits/
conditions are met or exceeded.
An external thermal sensor with a serial interface may be placed next to a SO-DIMM (or
any other appropriate platform location), or a remote Thermal Diode may be placed
next to the SO-DIMM (or any other appropriate platform location) and connected to the
external Thermal Sensor.
The external sensor can be connected to the ICH via the SMBus Interface to allow
programming and setup by BIOS software over the serial interface.
Additional external thermal sensors outputs, for multiple sensors, can be wire-ORd
together allow signaling from multiple sensors that are physically located separately.
Software can, if necessary, distinguish which SO-DIMM(s) is the source of the over-
temp through the serial interface. However, since the SO-DIMMs is located on the
same Memory Bus Data lines, any GMCH-based Read throttle will apply equally.
Thermal sensor can either directly routing to the GMCH pins or indirectly routing to
GMCH by invoking an Embedded Controller (EC) or KSC connected in between the
thermal sensor and GMCH pins. Both routing methods are applicable for both thermal
sensors placed on the motherboard (TS on board) and/or thermal sensors located on
the memory modules (TS-on-DIMM).
Datasheet 105
Thermal Management
11.4 THERMTRIP# Operation
Assertion of the GMCHs THERMTRIP# (Thermal Trip) indicates that its junction
temperature has reached a level beyond which damage may occur. Upon assertion of
THERMTRIP#, the GMCH will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the core junction temperature. Once activated,
THERMTRIP# remains latched until RSTIN# is asserted.
11.5 TSATN# Operation
TSATN# is an AGTL+ output pin of the GMCH which indicates when the AUX2
temperature trip point of the internal thermal sensor has been crossed. This may be
connected to platform logic (a level-shifter may be required), optionally. This input can
then trigger the GMCH fan to a higher setting to increase GMCH cooling.

Figure 19. Platform External Sensor
(G)MCH
TS TS
ICH
R
V
SMBdata
SMBclock
PM_EXT_TS
External Pull-up R
is associated with
the voltage rail of
the MCH Input
SO-DIMMs
T
H
E
R
M
#
DC Characteristics
106 Datasheet
12 DC Characteristics
The following notations are used to describe the signal types
The signal description includes the type of buffer used for the particular signal
Notations Signal Type
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
Signal Description
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The GMCH integrates AGTL+ termination resistors, and
supports V
TT
= 1.05 V.
PCI Express*
PCI Express interface signals. These signals are compatible with PCI Express
1.0. Signaling Environment AC Specifications. The buffers are not 3.3-V
tolerant. Refer to the PCIE specification.
CMOS CMOS buffers. 1.5-V tolerant.
HVCMOS High-voltage CMOS buffers. 3.3-V tolerant.
LVCMOS Low-voltage CMOS buffers. V
TT
tolerant
COD CMOS Open Drain buffers. 3.3-V tolerant
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
LVDS Low-voltage Differential signal interface
Ref Voltage reference signal
Datasheet 107
DC Characteristics
Table 28. Signal Groups (Sheet 1 of 4)
Signal
Group
Signal Type Signals Notes
Host Interface Signal Groups
(a)
I/O
AGTL+
H_ADS#, H_BNR#, H_BREQ#,H_DBSY#, H_DRDY#,
H_DINV# [3:0], H_A# [35:3], H_ADSTB# [1:0], H_D#
[63:0],H_DSTBP# [3:0], H_DPWR#, H_DSTBN# [3:0],
H_HIT#, H_HITM#, H_REQ# [4:0], H_DINV# [3:0],
(b)
O
AGTL+
H_BPRI#, H_CPURST#, H_DEFER#, H_TRDY#, H_RS#
[2:0], THERMTRIP#,
(c)
O
LVCMOS
H_CPUSLP#
(d)
I
AGTL+
H_LOCK#
(e)
I
A
H_AVREF, H_DVREF, H_SWING
(f)
I/O
A
H_RCOMP
Serial DVO/PCI-Express* Graphics/iHDMI/DP Interface Signal Groups
(g)
I
PCI Express
PCI-E GFX Interface: PEG_RX [15:0], PEG_RX# [15:0]
SDVO Interface: SDVO_TVCLKIN#, SDVO_TVCLKIN,
SDVOB_INT, SDVOB_INT#, SDVOC_INT,
SDVOC_INT#,SDVO_FLDSTALL#, SDVO_FLDSTALL
iHDMI: TMDSB_HPD#, TMDSC_HDP#
DP interface: DPB_HPD#, DPB_AUX, DPB_AUX#,
DPC_HPD#, DPC_AUX, DPC_AUX#, DPD_HPD#,
DPD_AUX, DPD_AUX#
See Section 6.2 for
SDVO/DP/HDMI &
PCI Express GFX
Pin Mapping
(h)
O
PCI Express
PCI Express GFX Interface: PEG_TX [15:0], PEG_TX#
[15:0]
SDVO Interface: SDVOB_RED#, SDVOB_RED,
SDVOB_GREEN#, SDVOB_GREEN, SDVOB_BLUE#,
SDVOB_BLUE, SDVOB_CLK, SDVOB_CLK#,
SDVOC_RED#, SDVOC_RED, SDVOC_GREEN#,
SDVOC_GREEN, SDVOC_BLUE#, SDVOC_BLUE,
SDVOC_CLK, SDVOC_CLK#
iHDMI: TMDS_B_CLK, TMDS_B_CLK#, TMDS_B_DATA0,
TMDS_B_DATA0#, TMDS_B_DATA1, TMDS_B_DATA1#,
TMDS_B_DATA2, TMDC_B_DATA2#, TMDS_C_CLK,
TMDS_C_CLK#, TMDS_C_DATA0, TMDS_C_DATA0#,
TMDS_C_DATA1, TMDS_C_DATA1#, TMDS_C_DATA2,
TMDS_C_DATA2#
DP Interface: DPB_LANE3, DPB_LANE3#, DPB_LANE2,
DPB_LANE2#, DPB_LANE1, DPB_LANE1#, DPB_LANE0,
DPB_LANE0#, DPC_LANE3, DPC_LANE3#, DPC_LANE2,
DPC_LANE2#, DPC_LANE1, DPC_LANE1#, DPC_LANE0,
DPC_LANE0#, DPD_LANE3, DPD_LANE3#, DPD_LANE2,
DPD_LANE2#, DPD_LANE1, DPD_LANE1#, DPD_LANE0,
DPD_LANE0#
See Section 6.2 for
SDVO/DP/HDMI &
PCI Express GFX
Pins Mapping
DC Characteristics
108 Datasheet
(i)
I
COD
iHDMI: SDVO_CTRLCLK, SDVO_CTRLDATA,
DDPC_CTRLCLK, DDPC_CTRLDATA
(j)
I
A
PEG_COMPO
PEG_COMPI
Analog
PCI Express GFX/
SDVO I/F
Compensation
Signals
DDR Interface Signal Groups
(k)
I/O
SSTL-1.8/1.5
SA_DQ [63:0], SB_DQ [63:0]
SA_DQS [7:0], SB_DQS [7:0], SA_DQS# [7:0],
SB_DQS# [7:0]
(l)
O
SSTL-1.8/1.5
SA_DM [7:0], SB_DM [7:0], SA_MA [14:0], SB_MA
[14:0], SA_BS [2:0], SB_BS [2:0], SA_RAS#, SB_RAS#,
SA_CAS#, SB_CAS#, SA_WE#, SB_WE#, SA_CK# [1 :0],
SA_CK [1 :0], SA_CKE [1 :0], SA_CS# [1 :0], SA_ODT
[1 :0], SB_CK [1 :0], SB_CK# [1 :0], SB_CKE [1 :0],
SB_CS# [1 :0], SB_ODT [1 :0]
(m)
I
CMOS
SM_PWROK
(n)
I/O
A
SM_REXT
(o)
I
A
SM_RCOMP, SM_RCOMP#, SM_VREF, SM_RCOMP_VOL,
SM_RCOMP_VOH
LVDS Signal Groups
(p)
O
LVDS
LVDSA_DATA [3:0], LVDSA_DATA# [3:0], LVDSA_CLK,
LVDSA_CLK#, LVDSB_DATA [3:0], LVDSB_DATA# [3:0],
LVDSB_CLK, LVDSB_CLK#
(q)
I/O
Ref
LVDS_IBG
(r)
I
Ref
LVDS_VREFH, LVDS_VREFL
Must be connected
to Ground
(s)
O
HVCMOS
L_BKLT_CTRL, L_BKLT_EN, L_VDD_EN
(t)
O
A
LVDS_VBG Leave as NC
CRT DAC Signal Groups
(u)
O
A
CRT_RED, CRT_GREEN, CRT_BLUE, CRT_IRTN,
CRT_TVO_IREF
Refer to CRT/
Analog VESA spec
(v)
O
HVCMOS
CRT_HSYNC, CRT_VSYNC
Refer to CRT/
Analog VESA spec
Signal
Group
Datasheet 109
DC Characteristics
TV DAC Signal Groups
(w)
O
A
TVA_DAC, TVB_DAC, TVC_DAC, TV_RTN
(x)
O
COD
TV_DCONSEL [1:0]
Clocks, Reset, and Miscellaneous Signal Groups
(y)
O
HVCMOS
ICH_SYNC#, GFX_VID [4:0], GFX_VR_EN
(z)
I
Diff Clk
DPLL_REF_CLK, DPLL_REF_CLK#, DPLL_REF_SSCLK,
DPLL_REF_SSCLK#, HPLL_CLK, HPLL_CLK#, PEG_CLK,
PEG_CLK#
PLL Signals
(aa)
O
AGTL+
TSATN#
(ab)
I
LVCMOS
PM_DPRSTP#
(ac)
I
HVCMOS
PM_EXT_TS [1:0]#, DPRSLPVR, PM_SYNC#
(ad)
I
HVCMOS
RSTIN#, PWROK, CL_PWROK
(ae)
O
SSTL-1.5
SM_DRAMRST#
I/O Buffer Supply Voltages
(af)
AGTL+ Termination
Voltage
VTT (Vccp)
(ag)
SDVO, HDMI,DP,
PCI Express GFX
Voltages
VCC_DMI, VCCA_PEG_BG, VSSA_PEG_BG,
VCCD_PEG_PLL, VCCA_PEG_PLL
(ah)
1.8-V DDR2/ 1.5-V
DDR3 Supply
Voltage
VCC_SM, VCC_SM_CK, VCCA_SM, VCCA_SM_CK
(ai) GMCH Core VCC, VCC_AXG, VCC_AXF, VCC_AXG_SENSE
(aj) HV Supply Voltage VCC_HV
(ak)
TV DAC Supply
Voltage
VCCD_TVDAC, VCCA_TV_DAC, VCCD_QDAC,
(al)
TV DAC Band Gap
and Channel Supply
VCCA_DAC_BG, VSSA_DAC_BG
(am)
CRT DAC Supply
Voltage
VCCA_CRT_DAC, VCCD_QDAC
(an) PLL Supply Voltages
VCCA_HPLL, VCCA_MPLL, VCCD_HPLL, VCCA_DPLLA,
VCCA_DPLLB
(ao)
1.8-V LVDS Digital
Supply
VCCD_LVDS, VCC_TX_LVDS, VCCA_LVDS
Signal
Group
DC Characteristics
110 Datasheet
12.1 I/O Buffer Supply Voltages
The I/O buffer supply voltage is measured at the GMCH package pins. The tolerances
shown in Table 29 are inclusive of all noise from DC up to 20 MHz. In the lab, the
voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of
3 dB/decade above 20 MHz under all operating conditions. Table 29 indicates which
supplies are connected directly to a voltage regulator or to a filtered voltage rail.
For voltages that are connected to a filter, they should be measured at the input of the
filter. If the recommended platform decoupling guidelines cannot be met, the system
designer will have to make tradeoffs between the voltage regulator output DC tolerance
and the decoupling performance of the capacitor network to stay within the voltage
tolerances listed below.
(ap)
1.5-V Intel HD
Audio Power Supply
VCC_HDA
Intel Management Engine Interface
(aq)
I/O
GTL
CL_DATA, CL_CLK
(ar)
I
GTL
CL_RST#
(as)
I
A
CL_VREF
Intel High Definition Audio (Intel HD Audio)
(at)
I
CMOS
HDA_BCLK, HDA_SYNC, HDA_SDO, HDA_RST#
(au)
I/O
CMOS
HDA_SDI
GMCH ICH Serial Interface
(av)
I
PCIE
DMI_RXP [3:0], DMI_RXN [3:0]
(aw)
O
PCIE
DMI_TXP [3:0], DMI_TXN [3:0]
Display Data Channel (DDC) and GMBUS Support
(ax)
I/O
COD
CRT_DDC_CLK, CRT_DDC_DATA, L_CTRL_CLK,
L_CTRL_DATA, L_DDC_CLK, L_DDC_DATA,
SDVO_CTRLCLK, SDVO_CTRLDATA, DDPC_CTRLCLK,
DDPC_CTRLDATA
Signal
Group
Datasheet 111
DC Characteristics
12.2 General DC Characteristics
Table 29. DC Characteristics (Sheet 1 of 6)
Symbol
Signal
Group
Parameter Min Nom Max Unit Notes
I/O Buffer Supply Voltage
V
TT
(af)
1.05-V Host AGTL+
Termination Voltage
0.9975 1.05 1.1025 V
V
CC_AXF
(ai)
1.05-V DC Input Voltage
for IO
0.9975 1.05 1.1025 V
V
CC
(ai)
1.05-V GMCH Core Supply
Voltage
0.9975 1.05 1.1025 V
V
CC_AXG
(ai) 1.05-V Graphics Voltage 0.9975 1.05 1.1025 V
V
CC_SM
(ah) DDR2 I/O Supply Voltage 1.7 1.8 1.9 V
V
CC_SM
(ah) DDR3 I/O Supply Voltage 1.5 V
V
CC_SM_CK
(ah)
1.8-V DDR2 Clock IO
Voltage
1.7 1.8 1.9 V 1
VCC_SM_CK
(ah)
1.5-V DDR3 Clock IO
Voltage
1.425 1.5 1.575 V
VCCA_SM
(ah)
1.05-V DDR2 Voltage
Connects to IO Logic and
DLLs
0.9975 1.05 1.1025 V
I/O Buffer Supply Voltage
V
CCA_SM_CK
(ah)
1.05-V DDR2 Voltage for
Clock Module to Avoid
Noise
0.9975 1.05 1.1025 V
V
CC_PEG
(ag)
1.05-V PCI Express Supply
Voltage
0.9975 1.05 1.1025 V
V
CC_DMI
(ag) 1.05-V DMI Supply Voltage 0.9975 1.05 1.1025 V
V
CCA_PEG_BG
(ag) Analog Band Gap Voltage 1.425 1.5 1.575 V 1
V
CC_HV
(aj) HV CMOS Supply Voltage 3.135 3.3 3.465 V
V
CCD_TVDAC
(ak) TV DAC Supply Voltage 1.425 1.5 1.575 V
V
CCD_QDAC
(ak)
TV/CRT DAC Quiet Supply
Voltage
1.425 1.5 1.575 V 1
V
CCA_TV_DAC
V
CCA_DAC_BG
(al)
TV DAC Analog & Band Gap
Supply Voltage
3.135 3.3 3.465 V 1
V
CCA_CRT_DAC
(am) CRT DAC Supply Voltage 3.135 3.3 3.465 V 1
V
CCA_HPLL
V
CCA_MPLL
V
CCD_HPLL
V
CCA_PEG_PLL
V
CCD_PEG_PLL
V
CCA_DPLLA
V
CCA_DPLLB
(an)
Various PLLS Analog
Supply Voltages
0.9975 1.05 1.1025 V 1
DC Characteristics
112 Datasheet
V
CCD_LVDS
(ao)
Digital LVDS Supply
Voltage
1.71 1.8 1.89 V
V
CC_TX_LVDS
(ao)
Data/Clock Transmitter
LVDS Supply Voltage
1.71 1.8 1.89 V 1
V
CCA_LVDS
(ao)
Analog LVDS Supply
Voltage
1.71 1.8 1.89 V 1
V
CC_HDA
(ap)
1.5-V Intel HD Audio Power
Supply
1.425 1.5 1.575 V
Reference Voltages
H_VREF (e)
Host Address and Data
Reference Voltage
2/3 x V
TT
2%
2/3 x
V
TT
2/3 x V
TT
+
2%
V
H_SWING (e)
Host Compensation
Reference Voltage
0.3125x V
TT

2%
0.3125
x V
TT
0.3125x V
TT
+
2%
V
SM_VREF (o) DDR2/3 Reference Voltage 0.49 x V
CC_SM

0.50 x
V
CC_SM
0.51 x V
CC_SM
V
16
Host Interface
V
IL_H
(a, d)
Host AGTL+ Input Low-
voltage
-0.10 0
(2/3 x V
TT
)
0.1

V
V
IH_H
(a, d)
Host AGTL+ Input High-
voltage
(2/3 x V
TT
) +
0.1

V
TT

(1.05)
V
TT
+ 0.1 V
V
OL_H
(a, b,
aa)
Host AGTL+ Output Low-
voltage
0.3125 x V
TT
)
+ 0.1
V
V
OH_H
(a, b,
aa)
Host AGTL+ Output High-
voltage
V
TT
-0.1 V
TT
V
I
OL_H
(a, b,
aa)
Host AGTL+ Output Low
Current
13.2 mA
I
LEAK_H
(a, d)
Host AGTL+ Input Leakage
Current
11 A
C
PAD
(a, d)
Host AGTL+ Input
Capacitance
1.5 2.0 2.5 pF
V
OL_H
(c) CMOS Output Low-voltage 0.1 V
TT
V
I
OL
=
1 mA
V
OH_H
(c) CMOS Output High-voltage 0.9 V
TT
V
TT
V
I
OH
=
1 mA
Symbol
Signal
Group
Datasheet 113
DC Characteristics
DDR2 Interface
V
IL(DC)
(k) DDR2 Input Low-voltage
SM_VREF

0.075
V
V
IH(DC)
(k) DDR2 Input High-voltage
SM_VREF

+
0.075
V
V
IL(AC)
SM_VREF

0.100
V
V
IH(AC)
SM_VREF

+
0.100
V
V
OL
(k, l) DDR2 Output Low-voltage 0.102 V 2
V
OH
(k, l) DDR2 Output High-voltage 1.698 V 2
I
Leak
(k) Input Leakage Current 10 A
C
I/O
(k, l)
DDR2 Input/Output Pin
Capacitance
2.3 pF
DDR3 Interface
V
IL(DC)
SM_VREF

0.075
V 5
V
IH(DC)
SM_VREF

+
0.075
V 5
V
IL(AC)
SM_VREF

0.100
V
V
IH(AC)
SM_VREF

+
0.100
V
V
OL
(k, l) DDR3 Output Low-voltage 0.159 V 5
V
OH
(k, l) DDR3 Output High-voltage 1.34 V 5
I
Leak
(k) Input Leakage Current 10 A 5
C
I/O
(k, l)
DDR3 Input/Output Pin
Capacitance
2.3 pF 5
1.05 V PCI Express Interface (includes PCI Express GFX/SDVO/HDMI/DP)
V
TX-DIFF P-P
(g, h)
Differential Peak to Peak
Output Voltage
0.400 0.600 V 3, 4
V
TX_CM-ACp
(g, h)
AC Peak Common Mode
Output Voltage
20 mV 3
Z
TX-DIFF-DC
(g,h)
DC Differential TX
Impedance
80 100 120
V
RX-DIFF p-p
(g, h)
Differential Input Peak to
Peak Voltage
0.175 1.2 V 3, 4
V
RX_CM-ACp
(g, h)
AC peak Common Mode
Input Voltage
150 mV
Symbol
Signal
Group
DC Characteristics
114 Datasheet
Clocks, Reset, and Miscellaneous Signals
V
IL
(ac) Input Low-voltage 0.8 V
V
IH
(ac) Input High-voltage 2.0 V
V
IL
(ad) Input Low-voltage 0.4 V
V
IH
(ad) Input High-voltage 3.0 V
I
LEAK
(ac) Input Leakage Current 10 A
C
IN
(ac) Input Capacitance 3.0 6.0 pF
V
IL
(z) Input Low-voltage -0.150 0 V
6, 13,
14
V
IH
(z) Input High-voltage 0.660 0.710 1.150 V 6, 13
V
CROSS
(z) Crossing Voltage 0.300 0.550 V
7, 12,
15
VCROSS(REL) Range of Crossing Points 0.140 V
7, 12,
10
V
SWING
(z) Differential Output Swing 0.300 V 6, 11
I
LEAK
(z) Input Leakage Current -0.5 +5 A 6, 8
C
IN
(z) Pad Capacitance 1.0 3.0 pF 6, 9
V
OL
(y)
Output Low-voltage (CMOS
Outputs)
0.4 V
V
OH
(y)
Output High-voltage
(CMOS Outputs)
2.8 V
I
OL
(y)
Output Low Current (CMOS
Outputs)
1 mA
@V
OL_
HI

max
I
OH
(y)
Output High Current
(CMOS Outputs)
-1 mA
@V
OH
_HI

min
V
IL
(ab) Input Low-voltage (DC)
2/3 * V
TT

0.2V
V
V
IH
(ab) Input High-voltage (DC)
2/3 * V
TT
+
0.2V
V
I
LEAK
(ab) Input Leakage Current 10 A
C
IN
(ab) Input Capacitance 10 pF
V
IL
(ac) Input Low-voltage 0.8 V
V
IH
(ac) Input High-voltage 2.0 V
I
LEAK
(ac) Input Leakage Current 10 A
C
IN
(ac) Input Capacitance 10 pF
Symbol
Signal
Group
Datasheet 115
DC Characteristics
LVDS Interface: Functional Operating Range (V
CC
=1.8 V 5%)
V
OD
(p) Differential Output Voltage 250 350 450 mV
V
OD
(p)
Change in V
OD
between
Complementary Output
States
50 mV
V
OS
(p) Offset Voltage 1.125 1.25 1.375 V
V
OS
(p)
Change in V
OS
between
Complementary Output
States
50 mV
I
Os
(p)
Output Short Circuit
Current
-3.5 -10 mA
I
OZ
(p) Output TRI-STATE Current 1 10 A
Intel Management Engine Interface
V
IL
(aq, ar) Input Low-voltage VSS
CL_VREF
-80 mV
V
V
IH
(aq, ar) Input High-voltage
CL_VREF
+80 mV
V
CC
V
I
LEAK
(aq, ar Input Leakage Current 20 A
C
IN
(aq, ar) Input Capacitance 2.0 pF
I
OL
(aq)
Output Low Current (CMOS
Outputs)
1.0 mA
@V
OL_
HI

max
I
OH
(aq)
Output High Current
(CMOS Outputs)
6 mA
@V
OH
_HI

min
V
OL
(aq)
Outputs)
0.06 V
V
OH
(aq)
Output High-voltage
(CMOS Outputs)
0.61 0.8 0.98 V
CL_VREF (as)
(ME) reference voltage
343 350 357 mV
SDVO_CTRLDATA, SDVO_CTRLCLK
V
IL
(i) Input Low-voltage 0.3xV
CCP
V
V
IH
(i) Input High-voltage 0.6xV
CCP
V
I
LEAK
(i) Input Leakage Current 10 A
C
IN
(i) Input Capacitance 10.0 pF
V
OL
(i) Output Low-voltage 0.4 @ 3 mA V
SM_PWROK
V
IL
(m) Input Low-voltage 0.2 V
V
IH
(m) Input High-voltage 1.4 V
Symbol
Signal
Group
DC Characteristics
116 Datasheet
NOTES:
1. Refer to the design guidelines for filter recommendations for these rails.
2. Determined with 2x GMCH DDR2 buffer strength settings into a 50 to 0.5xVCC_SM (DDR2) test load.
3. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter
compliance eye diagram of PCI Express specification and measured over any 250 consecutive TX Ul's.
Specified at the measurement point and measured over any 250 consecutive ULS. The test load shown in
receiver compliance eye diagram of PCI Express specification. Should be used as the RX device when taking
measurements.
4. Low-voltage PCI Express (PCI Express Graphics/SDVO) interface.
CRT_DDC_DATA, CRT_DDC_CLK, L_DDC_CLK, L_DDC_DATA, L_CTRL_CLK, L_CTRL_DATA,
TV_DCONSEL_0, TV_DCONSEL_1, CLKREQ#
V
IL
Input Low-voltage 0.3*V
CCP
V
V
IH
Input High-voltage 0.7*V
CCP
V
I
LEAK
Input Leakage Current 150 A
C
IN
Input Capacitance 10.0 pF
V
OL
Output Low-voltage 0.4 @ 3 mA V
CRT_HSYNC, CRT_VSYNC
V
OL
Output Low-voltage 0.5 @ 8 mA V
V
OH
Output High-voltage 2.4 @ 8 mA V
ICH_SYNC#, VDD_EN, BKLT_EN, BKLT_CTRL, GFX_VID [4:0], GFX_VR_EN
V
IL
Input Low-voltage 0.8 V
V
IH
Input High-voltage 2.0 V
I
LEAK
Input Leakage Current 150 A
C
IN
Input Capacitance 10.0 pF
V
OL
Outputs)
0.4 @ 6 mA V
V
OH
Output High-voltage
(CMOS Outputs)
Vccp-0.5 @
2 mA
V
DPB_HPD#, DPC_HPD#,TMDS_B_HPD#, TMDS_C_HPD#
V
IL
Input Low-voltage -0.3 0.3 V
V
IH
Input High-voltage 0.6 1.155 V
I
LEAK
Input Leakage Current
C
IN
Input Capacitance
V
IL_HDA
(at, au) Input Low-voltage 0.2 (V
CC_HDA
) V
V
IH_HDA
(at, au) Input High-voltage 0.8 (V
CC_HDA
) V
V
OL_HDA
(au) Output Low-voltage
0.1 (V
CC_HDA
)
@ 1.5 mA
V
V
OH_HDA
(au) Output High-voltage
0.9 (V
CC_HDA
)
@ -0.5 mA
V
Symbol
Signal
Group
Datasheet 117
DC Characteristics
5. DDR3
6. Unless otherwise noted all specifications in this table apply to all FSB frequencies.
7. Crossing Voltage is defined as absolute voltage where rising edge of H
PLL_CLK
is equal to the falling edge of
H
PLL_CLK
#.
8. For V
IN
between 0 V and VH.
9. CPAD includes die capacitance only. No package parasitics are included.
10. V
CROSS
is defined as the total variation of all crossing voltages as defined in Note 6.
11. Measurement taken from Differential Waveform.
12. Measurement taken from Single Ended waveform.
13. The max voltage including overshoot.
14. The min voltage including undershoot.
15. Only applies to the differential rising edge. (Clock rising and Clock # falling).
16. V
CC_SM
may be 1.5-V (DDR3) or 1.8-V (DDR2).
12.3 CRT DAC DC Characteristics
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure Evaluation of Analog Display
Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75- termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA video signal standards.
7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).
Symbol Parameter Min Typ Max Unit
R
TT
Termination Resistance 50 55 61
R
CN
Buffer On Resistance 22 25 28
Table 30. CRT DAC DC Characteristics: Functional Operating Range
(V
CCA_CRT_DAC
= 3.3 V 5%)
Parameter Min Typical Max Units Notes
DAC Resolution 8 Bits (1)
Max Luminance (full-scale) 0.665 0.700 0.770 V
(1, 2, 4) white video level
voltage
Min Luminance 0.000 V
(1, 3, 4) black video level
voltage
LSB Current 73.2 A (4, 5)
Integral Linearity (INL) -1.0 +1.0 LSB (1, 6)
Differential Linearity (DNL) -1.0 +1.0 LSB (1, 6)
Video channel-channel voltage
amplitude mismatch
6 % (7)
Monotonicity Guaranteed
DC Characteristics
118 Datasheet
12.4 TV DAC DC Characteristics
NOTES:
1. Max steady-state amplitude.
2. Min steady-state amplitude.
3. Defined for a double 75- termination.
4. Set by external reference resistor value.
5. INL and DNL measured and calculated based on the method given in VESA video signal standards.
6. Max full-scale voltage difference among the outputs (percentage of steady-state full-scale voltage).

Table 31. TV DAC DC Characteristics: Functional Operating Range
(V
CCA_TV_DAC
[A,B,C]=3.3 V 5%)
Parameter Min Typical Max Units Notes
DAC Resolution 10 Bits Measured at low-frequency
ENOB (Effective Number of
Bits)
7.5 Bits @ NTSC/PAL Video BW
For composite video signal
Note: 1,3,4
For S-Video signal
Note: 1,3,4
For component video signal
Note: 1,3,4
Min Luminance -0.1 0 +0.1 mV Measured at DC, Note: 2
Integral Linearity (INL) -1 +3.5 LSB Note: 5
Differential Linearity (DNL) -0.5 +0.5 LSB Note: 5
SNR 48 dB RMS @ NTSC/PAL Video BW
Video channel-channel
voltage amplitude
mismatch
-3 +3 % Note: 6
Monotonicity Guaranteed
Datasheet 119
Clocking
13 Clocking
13.1 Overview
The GMCH has a total of four main PLLs that are used for many internal clocks. Each
PLL requires one reference clock from the platform clock generator. The PLLs are:
Host/Memory/Graphics Core PLL Generates the main core clocks in the host clock
domain. Also used to generate memory and internal graphics core clocks. Uses the
Host clock (HPLL_CLK /HPLL_CLK#) as a reference.
PCI Express PLL Generates all PCI Express related clocks, including the DMI that
connects to the ICH. This PLL uses the 100 MHz (PEG_CLK/PEG_CLK#) as a
reference.
Display PLL A Generates the internal clocks for Display A or Display B. Uses the
low-voltage 96-MHz differential clock, DPLL_REF_CLK/DPLL_REF_CLK#, as a
reference.
Display PLL B 100-MHz differential clock, DPLL_REF_CLK/DPLL_REF_CLK#, as a
reference. Also may optionally use DPLL_REF_SSCLK/DPLL_REF_SSCLK#as a
reference for SSC support for LVDS display.
13.2 GMCH Reference Clocks
Reference Input Clocks Input Frequency Associated PLL
HPLL_CLK/HPLL_CLK# 166, 200, 266 Host/Memory/Graphics Core
PEG_CLK/PEG_CLK# 100 MHz PCI Express/DMI PLL
DPLL_REF_CLK/DPLL_REF_CLK# 96 MHz Display PLL A or B
DPLL_REF_SSCLK/DPLL_REF_SSCLK#
96 MHz (Non-SSC)
100 MHz (SSC)
Display PLL A or B
Clocking
120 Datasheet
13.3 GMCH Host/Memory/Graphics Core Clock
Frequency Support
Note: 1. Support for DDR3 at 667 MHz when FSB at 667 MHz only
Chipset Variant
Host Clock
(MHz)
Memory Clock
(MHz)
Render Clock @
Core-voltage
(MHz@V)
Display Clock
(MHz)
Mobile Intel GM45 Express
Chipset
667/800/1066
667/800(DDR2);
667
1
/800/
1066(DDR3)
533/500 @1.05 320/333
Mobile Intel PM45 Express
Chipset
667/800/1066
667/800(DDR2);
800/1066(DDR3)
NA NA
Mobile Intel GS45 Express
Chipset (Low-power)
800
667(DDR2);
667/800(DDR3)
320 @1.05
533/500 @1.05
(Turbo mode)
222/228
Chipset (High-performance)
800/1066
667/800(DDR2);
667/800/
1066(DDR3)
533/500 @1.05 320/333
Mobile Intel GL40 Express
Chipset
800/667
800/667(DDR2)
800/667
1
(DDR3)
400/380 @1.05 320/333
Chipset
800
800/667(DDR2)
800/667(DDR3)
400 @1.05 320/333
Host
Clock
(MHz)
Memory
Clock
(MHz)
Render Clock/Display Clock (MHz)
Mobile
Intel GM45
Express
Chipset
Mobile Intel
GS45 Express
Chipset (High-
performance)
Mobile
Intel GS45
Express
Chipset
(Low-
power)
Mobile
Intel GL40
Express
Chipset
Mobile
Intel GS40
Express
Chipset
667 667 533/333 380/333
800 667 500/333 500/333 333/222 400/333 400/333
800 800 533/320 533/320 320/228 400/320 400/320
1066 667 533/333 533/333
1066 800 533/320 533/320
1066 1066 533/320 533/320
Datasheet 121
I ntel Virtualization Technology ( I ntel VT) for Directed I / O ( I ntel VT- d) Technology
14 I ntel Virtualization Technology
( I ntel VT) for Directed I / O
( I ntel VT- d) Technology
Intel Virtualization Technology (Intel VT) comprises technology components to support
virtualization of platforms based on Intel architecture microprocessors. This section
describes the chipset hardware components supporting IO virtualization that are
architected for implementation in the GMCH.
For the GMCH, the key Intel VT-d functions are domain based isolation and
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same OS or there can be multiple operating system instances running
on the same system offering benefits such as system consolidation, legacy migration,
activity partitioning or security.
14.1 Intel VT-d Terminology
Term Description
Chipset /Root-Complex
Refers to one or more hardware components that connect processor
complexes to the I/O and memory subsystems. The chipset may
include a variety of integrated devices.
Context
A hardware representation of state that identifies a device and the
domain to which the device is assigned.
Context Cache Remapping hardware cache that stores device to domain mappings
DMA Remapping
The act of translating the address in a DMA request to a host physical
address (HPA).
Domain
A collection of physical, logical, or virtual resources that are allocated
to work together. Used as a generic term for virtual machines,
partitions, etc.
DVA
DMA Virtual Address: a virtual address in a DMA request. For certain
virtualization usages of remapping, DVA can be the Guest Physical
Address (GPA).
GAW
Guest Address Width: the DMA virtual addressability limit for a Guest
partition.
GPA
Guest Physical Address: the view of physical memory from software
running in a partition. GPA is used in this document as an example of
DVA.
Guest Software running within a virtual machine environment (partition).
HAW
Host Address Width: the DMA physical addressability limit for a
platform.
HPA Host Physical Address.
IEC
Interrupt Entry Cache: A translation cache in remapping hardware
unit that caches frequently used interrupt-remapping table entries.
122 Datasheet
14.1.1 GCH/Intel VT-d Chipset Components
The GMCH supports four DMAr (DMA-remapping) engines. Three of these are contained
in a central Intel VT-d block. This block also serves as the dispatcher for arbitration and
forwarding the DMAr requests to memory for the Intel ME DMAr engine.
PEG and DMI (non-HDA) DMAr Engine
The PEG and DMI bus hierarchies share a single remap engine, but have
dedicated caching structures. The dedicated cache elements ensure that a
given bus hierarchy cannot dominate a shared cache resource at the expense
of the other bus.
HDA-DMI DMAr Engine
Used for only the Intel HD Audio engine to provide maximum isolation for the
isochronous nature of the engine.
Intel Management Engine DMAr Engine
Intel Management Engine in the GMCH is implemented as a stand-alone DMAr
engine, and has a dedicated interface to the Intel VT dispatcher.
Integrated Gfx DMAr Engine
This DMAr engine supports a prefetch mechanism which reduces the maximum
fetches from Intel VT lookup tables to 2, thus improving performance.
Translation logic is implemented within the GMCH in order to minimize latency. The
DMA-remapping engines support logging of Translation Faults, and Enable/Disable of
Translation (TE). Protected memory regions for secure operations are supported.
14.1.2 DMA Address Remapping
Address translation functionality for I/O device DMA requests shall be referred to as
DMA remapping in this chapter.
IOTLB
I/O Translation Lookaside Buffer: an address translation cache in
remapping hardware unit that caches effective translations from DVA
(GPA) to HPA.
I/OxAPIC I/O Advanced Programmable Interrupt Controller
Interrupt Remapping
The act of translating an interrupt request before it is delivered to the
CPU complex.
MGAW
Maximum Guest Address Width: the maximum DMA virtual
addressability supported by a remapping hardware implementation.
MSI Message Signalled Interrupts.
PDE Cache
Page Directory Entry cache: address translation caches in a
remapping hardware unit that caches page directory entries at the
various page-directory levels. Also referred to as non-leaf caches in
this document.
Source ID
A 16-bit identification number to identify the source of a DMA or
interrupt request. For PCI family devices this is the Requester ID
which consists of PCI Bus number, Device number, and Function
number.
VMM
Virtual Machine Monitor: a software layer that controls virtualization.
Also referred to as hypervisor in this document.
Term Description
Datasheet 123
This section describes the hardware architecture concepts of DMA remapping. The
DMA-remapping architecture facilitates flexible assignment of I/O devices to multiple
domains. Each domain has a view of physical address space that may be different than
the host physical address space. DMA-remapping treats the address specified in DMA
requests as DMA virtual addresses (DVA). DMA-remapping provides the transformation
of address in a DMA request issued by an I/O device to its corresponding host-physical
address (HPA).
For simplicity, the rest of the document describes the input address to the DMA-
remapping hardware as GPA. Figure 20 illustrates the I/O physical address translation.
I/O Devices 1 and 2 are assigned to Domains 1 and 2, respectively. The software
responsible for creating and managing the domains allocates system physical memory
for both domains and sets up the DMA address translation function. GPA in DMA
requests initiated by Devices 1 and 2 are translated to appropriate HPAs by the DMA
remapping hardware.
14.1.3 Capabilities of GMCH DMAr hardware
The GMCH supports the following Intel VT-d capabilities in Hardware:
Address translation and Address protection functions are provided. This is required
to support the OS robustness, virtualization and security usages.
Multiple devices can be assigned to the same domain, and hence may share the
same view of physical memory.
Legacy and virtualization-aware guest operating systems may be run on the
hardware. Direct device assignment without device driver modifications is allowed.
DMA virtual address space sizes up to the addressing (HPA) capacity of the
underlying host platform are supported.
The DMI non-HDA DMAr engine can support DVAs up to 48 bits.
Allocation of physical memory to domains at a CPU page-size granularity (minimum
4 KB) is supported.
Hardware-caching of translation structures for performance is supported.
Remapping of translation structures at runtime under software control is
supported.
A notification mechanism to inform software about translation faults is provided. It
also supports recording of translation faults (error-logging) which may be used by
software to isolate faulty devices/drivers.
Figure 20. DMA Address Translation

124 Datasheet
To support security usages, memory protection required for secure launch,
operation and tear-down of an MVMM is provided.
14.1.4 Handling Interrupt Messages
On Intel platforms, interrupt requests from IOAPICs and MSI-capable devices appear to
the root-complex as upstream memory write requests to the address range
0xFEE0_0000h to 0xFEEF_FFFFh. Since this interrupt message address range is
architectural and identical between the guest and the host, upstream DMA requests to
addresses in the MSI address range are not subject to DMA-remapping.
Hardware decodes the address in DMA requests to check if it falls in the interrupt
address range and bypass DMA-remapping for such transactions. DMA write requests
to this range are validated and interpreted as interrupt messages, and DMA read
requests to this range are treated as error.
Software must ensure that the DMA-remapping page tables are programmed to not
remap regular DMA requests to the above interrupt address range. Hardware behavior
is undefined for DMA requests remapped to the interrupt address range through the
DMA-remapping structures.
14.2 Intel Trusted Execution Technology (Intel TXT)
Intel Trusted Execution Technology is a platform initiative to address system security
issues. It provides protection against software attacks or viruses, and also some level
of protection against hardware attacks. The chipset will provide new features that
'fence off' DMA and other I/O from those pages the OS has marked as secure.
The GMCH leverages its Intel VT-d capabilities to isolate and secure trusted and
privileged operations.
When used in conjunction with Intel VT, Intel TXT provides hardware-rooted trust for
virtual applications.
The chipset protects confidential information mainly through preventing I/O DMA from
accessing certain physical pages in memory. This mechanism is facilitated by the Intel
VT-d table.

Datasheet 125
GMCH Strapping Configuration
15 GMCH Strapping Configuration
NOTES:
1. All strap signals are sampled with respect to the leading edge of the GMCH Power OK (PWROK) signal.
2. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
3. Refer to Table 15 for Concurrent DP(HDMI)/PCIE configuration strap controls.
Table 32. GMCH Strapping Signals and Configuration
Pin Name Strap Description Configuration
CFG2:0 FSB Frequency
000 = FSB1066
010 = FSB800
011 = FSB667
Others = Reserved
CFG4:3 Reserved
CFG5 DMI X2 Select
Low = DMI X2
High = DMI X4 (Default)
CFG[8:6] Reserved
CFG9 PCIE Graphics Lane
Low = Reverse Lanes, 15->0, 14->1 etc
High = Normal operation (default): Lane Numbered in Order
CFG[11:10] Reserved
CFG12 ALLZ
Low = ALLZ mode enabled
3
High = Disabled (default)
CFG13 XOR
Low = XOR mode enabled
3
High = Disabled (default)
CFG14 Reserved
CFG15 Reserved
CFG16 FSB Dynamic ODT
Low = Dynamic ODT disabled
High = Dynamic ODT enabled (default)
CFG17 Reserved
CFG18 Reserved
CFG19 DMI Lane Reversal
Low = Normal operation (Default): Lane Numbered in Order
High = Reverse Lanes
DMI x4 mode [GMCH->ICH]: (3->0, 2-> 1, 1->2 and 0->3)
DMI x2 mode [GMCH->ICH]: (3->0, 2->1)
CFG20
Digital Display Port (SDVO/
DP/iHDMI) Concurrent with
PCIE
4
Low = Only digital display port (SDVO/DP/iHDMI) or PCIE is
operational (default)
High = Digital display port (SDVO/DP/iHDMI) and PCIE are
operating simultaneously via the PEG port
SDVO_CTRLDATA
SDVO/iHDMI*/DP Interface
enabled
4
Low = SDVO/iHDMI/DP interface disabled (default)
High = SDVO/HDMI/DP interface enabled
L_DDC_DATA
Local Flat Panel (LFP)
Present
Low = LFP Disabled (default)
High = LFP Card Present; PCIe disabled
DDPC_CTRLDATA
Digital Display (iHDMI/DP)
interface enabled
4
Low = Digital display (iHDMI/DP) interface disabled (default)
High = Digital display (iHDMI/DP) interface enabled
Ballout and Package I nformation
126 Datasheet
16 Ballout and Package
I nformation
16.1 Mobile Intel 4 Series Express Chipset Ballout
Diagrams
Figure 21. Ballout Diagram (Top View) Upper Left Quadrant
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
BH
VSS_SC
B
NC NC NC NC
SB_DQ
S#_2
SB_DQ_
28
VSS
SB_DQ
S#_3
SB_DQ_
26
SB_DQ_
31
VCC_S
M
VCC_S
M
VCC_S
M
SM_RC
OMP_V
OL
SA_MA_
12
VSS
BG
NC NC NC
SB_DQ_
18
VSS
SB_DQ
S_2
VSS
SB_DQ_
29
SB_DQ_
24
SB_DQ
S_3
VSS
SB_DQ_
27
SB_DQ_
30
VSS
VCC_S
M
VCC_S
M
VCC_S
M
VCC_S
M
VSS
SA_MA_
7
SA_MA_
11
SA_MA_
4
BF
NC NC VSS
SB_DQ_
19
SB_DQ_
23
SB_DQ_
22
SB_DQ_
25
VSS
SB_DM_
3
VSS
VCC_S
M
VCC_S
M
VCC_S
M
SM_RC
OMP_V
OH
VSS
SA_MA_
8
BE
NC
SB_DQ_
20
BD
NC VSS
SA_DQ_
19
VSS
SB_DM_
2
SA_DQ_
25
SA_DQ
S#_3
VSS
SB_MA_
9
VCC_S
M
VCC_S
M
VSS VSS
BC
NC
SB_DQ_
15
SB_DQ_
16
SB_DQ_
17
VSS
SB_DQ_
21
SA_DQ_
23
VSS
SA_DQ
S_3
SM_DR
AMRST
#
VSS
VCC_S
M
VCC_S
M
SA_CKE
_0
SB_MA_
2
BB
VSS
SA_DQ_
22
VSS
SA_DQ_
29
VSS
SB_CKE
_1
SB_BS_
2
VCC_S
M
VCC_S
M
SB_MA_
5
VSS
BA
SB_DQ_
10
SB_DQ_
14
VSS
SA_DQ
S#_2
SA_DQ
S_2
SA_DQ_
18
VSS
VCC_S
M_LF
VCC_S
M/NC
VSS
VCC_S
M
VCC_S
M
VSS
SB_MA_
1
AY
SB_DQ_
11
SB_DM_
1
VSS
SA_DQ_
17
SA_DQ_
21
VSS
SA_DM_
2
SA_DQ_
28
SA_DQ_
24
SB_CKE
_0
SB_MA_
12
VCC_S
M
VCC_S
M
SA_CKE
_1
SA_MA_
14
AW
VSS VSS
SA_DQ_
31
SB_MA_
11
VCC_S
M
VCC_S
M
SB_MA_
7
SB_MA_
4
AV
SB_DQ
S_1
SB_DQ
S#_1
VSS
VCC_S
M_LF
VSS
SM_VR
EF
SA_DQ_
20
VSS
SA_DQ_
16
SA_DQ_
26
SA_DQ_
30
VSS
VCC_S
M
VCC_S
M
VSS VSS
AU
VSS
SB_DQ_
8
SB_DQ_
9
SA_DQ_
14
VSS
SA_DQ_
15
VSS
SA_DQ_
10
SA_DM_
3
VSS VSS
SB_MA_
14
VCC_S
M
VCC_S
M
SB_MA_
6
SB_MA_
3
AT
SB_DQ_
12
SA_DQ
S_1
SA_DQ
S#_1
VSS
SA_DM_
1
PWROK VSS
SA_DQ_
11
VSS
SA_DQ_
27
SB_MA_
8
VCC_S
M
VCC_S
M
VSS
SA_BS_
2
AR
VSS
SB_DQ_
13
VSS
SM_PW
ROK
VSS
VCC_S
M
VCC_S
M
VSS VSS
AP
SB_DQ_
7
SB_DQ_
2
SB_DQ_
3
VCC_S
M
VCC_S
M
VCC_S
M
VCCA_S
M_CK
VCCA_S
M_CK
AN
VSS
SA_DQ_
9
SA_DQ_
8
VSS
SA_DQ_
12
VSS
SA_DQ_
13
SA_DQ_
2
VSS
CL_PW
ROK
ME_J TA
G_TDO
VCC_S
M
VCC_S
M
VSS
VCCA_S
M_CK
VCCA_S
M_CK
AM
SB_DQ_
6
SB_DM_
0
VSS
SA_DQ_
6
VSS
SA_DQ_
7
VSS
VCC_S
M_LF
VSS
SA_DQ_
3
SA_DM_
0
VSS
ME_J TA
G_TMS
VSS VCC
VCC_N
CTF
VCC_N
CTF
VSS_NC
TF
VCCA_S
M_CK_
NCTF
VCCA_S
M_CK_
NCTF
VCCA_S
M_CK_
NCTF
AL
VSS
SB_DQ
S_0
SB_DQ
S#_0
ME_J TA
G_TCK
VSS
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCCA_S
M_CK_
NCTF
AK
SB_DQ_
0
ME_J TA
G_TDI
VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
AJ
SB_DQ_
5
VSS
SB_DQ_
4
SA_DQ
S_0
SA_DQ
S#_0
VSS
SA_DQ_
1
SA_DQ_
5
VSS
SA_DQ_
0
VSS
SA_DQ_
4
CL_RST
#
VSS VCC
VCC_N
CTF
VSS_NC
TF
VCC_N
CTF
VSS VCC VSS
AH
VCC_D
MI
VCC_D
MI
SB_DQ_
1
VSS
DMI_TX
P_3
DMI_TX
N_3
VSS
DMI_RX
P_3
DMI_RX
N_3
VSS CL_CLK
CL_DAT
A
VSS
CL_VRE
F
VSS
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC VSS VCC
AG
VCC_D
MI
VCC VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VSS VCC VCC
AF
VCC_D
MI
VSS
DMI_TX
P_2
VSS VCC
VSS_NC
TF
VCC_N
CTF
VSS_NC
TF
VCC VSS VCC
AE
DMI_RX
P_2
DMI_RX
N_2
DMI_TX
N_2
DMI_TX
P_1
DMI_TX
N_1
VSS
DMI_RX
N_0
DMI_RX
P_0
VSS
DMI_RX
P_1
DMI_RX
N_1
VSS
DMI_TX
N_0
VSS VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VSS VCC
VCC_AX
G
Datasheet 127
Figure 22. Ballout Diagram (Top View) Upper Right Quadrant
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SA_MA_
3
VSS
SM_RC
OMP#
VCC_S
M_CK
RESER
VED
SA_MA_
13
SB_MA_
13
SB_DQ_
32
SB_DQ_
36
SB_DQ_
34
SB_DQ
S_4
VSS NC NC NC NC
VSS_SC
B
BH
SA_MA_
2
RESER
VED
SM_RC
OMP
VSS
VCC_S
M_CK
VSS
SA_BS_
1
VSS
SB_CAS
#
VSS VSS VSS
SB_DQ_
33
SB_DM_
4
VSS
SB_DQ
S#_4
SB_DQ_
35
SB_DQ_
39
VSS NC NC NC
BG
VSS
RESER
VED
VCC_S
M_CK
VCC_S
M_CK
RESER
VED
SM_RE
XT
SB_ODT
_0
SB_WE
#
VSS
SB_DQ_
37
VSS
SB_DQ_
38
SB_DQ_
44
SB_DQ_
45
NC NC
BF
VSS NC
BE
SA_MA_
6
SA_BS_
0
SA_CAS
#
SA_ODT
_0
VCC_S
M/NC
SA_DQ_
32
SA_DQ_
38
VSS
SA_DQ_
45
SA_DQ
S#_5
VSS
SB_DQ_
47
NC
BD
SA_MA_
1
SA_MA_
10
VSS VSS
SB_BS_
0
VSS
SA_DQ_
39
SA_DQ_
34
VSS
SA_DQ
S_5
SB_DQ_
41
SB_DQ_
40
VSS
SB_DQ
S#_5
NC
BC
VCC_S
M/NC
VCC_S
M/NC
SA_RAS
#
SB_BS_
1
SB_MA_
10
VCC_S
M_LF
SA_DM_
4
VSS
SA_DQ_
40
VSS
SB_DQ
S_5
BB
SA_MA_
5
SA_MA_
0
VSS
SA_CS#
_0
VSS VSS
SA_DQ_
35
SA_DQ_
44
SA_DQ_
41
SA_DQ_
47
VSS
SB_DM_
5
VSS
SB_DQ_
46
BA
VSS
RESER
VED
SA_WE
#
SA_ODT
_1
SA_CS#
_1
SB_ODT
_1
SA_DQ
S#_4
VSS
SA_DQ_
46
VSS
SA_DM_
5
VCC_S
M_LF
SB_DQ_
42
SB_DQ_
52
SB_DQ_
43
AY
SA_MA_
9
VSS VSS VSS
VCC_S
M/NC
VCC_S
M/NC
SA_DQ
S_4
VSS
AW
SB_CK_
0
VCC_S
M_LF
SB_CK#
_1
SB_MA_
0
SB_CS#
_0
SA_DQ_
37
VSS VSS
SA_DQ_
43
VSS
SA_DQ_
49
VSS
SA_DQ_
48
VSS
SB_DQ_
48
SB_DQ_
53
AV
SB_CK#
_0
VSS
SB_CK_
1
SB_RAS
#
VSS
SA_DQ_
36
SA_DQ_
33
SA_DQ_
42
SA_DQ
S#_6
SA_DQ
S_6
VSS
SA_DQ_
53
SA_DQ_
52
SB_DQ_
49
VSS
SB_DQ
S_6
AU
VSS
SA_CK_
1
VSS VSS
VCCA_S
M
VCC_S
M/NC
VSS RSTIN# VSS
SA_DQ_
50
VSS
SA_DM_
6
VSS
SA_DQ_
54
SB_DQ
S#_6
AT
SA_CK#
_0
SA_CK#
_1
VCCA_S
M
VCCA_S
M
VCCA_S
M
SB_CS#
_1
SB_DQ_
50
VSS
SB_DQ_
55
AR
SA_CK_
0
VSS
VCCA_S
M
VCCA_S
M
VCCA_S
M
SB_DQ_
54
VSS
SB_DM_
6
AP
VCCA_S
M_CK
VSS
VCCA_S
M
VCCA_S
M
VSS
VCC_AX
G
VSS
SA_DQ_
60
VSS
SA_DQ_
55
VSS
SA_DQ_
51
VSS
SB_DQ
S_7
SB_DQ
S#_7
SB_DQ_
51
AN
VCCA_S
M_CK_
NCTF
VCCA_S
M_CK_
NCTF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
VCC_AX
G
SA_DQ_
61
VSS
SA_DQ_
56
VCC_S
M_LF
VSS
SA_DQ
S#_7
SA_DQ
S_7
VSS
SA_DQ_
57
SB_DQ_
61
SB_DQ_
60
VSS
AM
VCCA_S
M_CK_
NCTF
VCCA_S
M_CK_
NCTF
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G
VSS
SB_DQ_
57
SB_DQ_
56
AL
VCC_N
CTF
VCC_N
CTF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VSS
SB_DM_
7
AK
VSS VCC
VCC_AX
G
VSS
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G
VCC_AX
G_SEN
SE
VSS
SA_DQ_
63
SA_DQ_
62
VSS
SA_DQ_
58
SA_DQ_
59
VSS VSS
SA_DM_
7
SB_DQ_
63
VSS
SB_DQ_
58
AJ
VSS VCC VSS
VCC_AX
G
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
VSS_AX
G_SEN
SE
RESER
VED
RESER
VED
VSS
RESER
VED
RESER
VED
VSS
HPLL_C
LK
HPLL_C
LK#
VSS
SB_DQ_
62
VSS
SB_DQ_
59
AH
VCC VSS
VCC_AX
G
VSS
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
H_D#_6
2
AG
VSS VCC VSS
VCC_AX
G
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
H_D#_5
6
VSS
VCCD_
HPLL
AF
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
H_D#_5
5
VSS
H_D#_4
8
H_D#_6
0
VSS
H_D#_4
9
H_D#_6
1
VSS
H_DSTB
N#_3
H_DSTB
P#_3
H_D#_5
8
VSS
VCCA_
MPLL
AE
128 Datasheet
Figure 23. Ballout Diagram (Top View) Lower Left Quadrant
AD
VCCA_P
EG_BG
VSS
PEG_TX
_15
VSS
PEG_TX
#_14
PEG_TX
_14
VSS
PEG_R
X_15
PEG_R
X#_15
VSS
PEG_R
X#_13
PEG_R
X_13
DMI_TX
P_0
AC
PEG_R
X_14
PEG_R
X#_14
PEG_TX
#_15
VCC VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC VCC VSS
AB
VSS VCC VSS
VSS_NC
TF
VCC_N
CTF
VSS_NC
TF
VSS VSS
VCC_AX
G
AA
VCCA_P
EG_PLL
VCCD_
PEG_PL
L
PEG_TX
#_11
VSS
PEG_R
X#_12
PEG_R
X_12
VSS
PEG_TX
#_13
PEG_TX
_13
VSS
PEG_TX
#_12
PEG_TX
_12
VSS VCC VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC VSS
VCC_AX
G
Y
PEG_R
X#_10
VSS
PEG_TX
_11
VSS
PEG_R
X#_9
PEG_R
X_9
VSS
PEG_TX
#_10
PEG_TX
_10
VSS
PEG_R
X_11
PEG_R
X#_11
VSS VCC VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VSS
VCC_AX
G
VSS
W
PEG_R
X_10
VSS VCC
VCC_N
CTF
VCC_N
CTF
VCC_N
CTF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
V
VCC_PE
G
VCC_PE
G
VSS VCC VCC
VSS_NC
TF
VCC_N
CTF
VCC_N
CTF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
U
VCC_PE
G
VCC_PE
G
VCC_PE
G
VSS
PEG_R
X#_8
PEG_R
X_8
VSS
PEG_TX
#_9
PEG_TX
_9
VSS
PEG_TX
#_8
PEG_TX
_8
VSS VCC VCC
VCC_N
CTF
VCC_N
CTF
VSS VSS
VSS_NC
TF
VSS
T
VSS VSS
PEG_R
X#_7
PEG_R
X_7
VSS
PEG_TX
#_7
PEG_TX
_7
VSS
PEG_C
OMPI
PEG_C
OMPO
VSS
RESER
VED
VCC VSS CFG_20 CFG_0
R
PEG_TX
#_5
PEG_TX
_5
VSS
RESER
VED
DPRSLP
VR
PM_SY
NC#
CFG_19 CFG_1
P
PEG_R
X#_5
PEG_R
X_5
VSS VSS VSS
PM_EXT
_TS#_1
CFG_18 VSS CFG_2
N
VSS
PEG_R
X#_6
PEG_R
X_6
VSS
PEG_R
X#_4
PEG_R
X_4
VSS
PEG_TX
#_6
PEG_TX
_6
RESER
VED
PM_EXT
_TS#_0
VSS VSS
DDPC_
CTRLCL
K
VSS
M
PEG_TX
_2
PEG_TX
#_2
PEG_TX
#_1
VSS
PEG_TX
_4
PEG_TX
#_4
VSS
PEG_TX
#_3
PEG_TX
_3
VCCD_L
VDS
RESER
VED
L_CTRL
_DATA
L_CTRL
_CLK
L_VDD_
EN
DDPC_
CTRLD
ATA
VCCD_
TVDAC
L
VCCA_
DPLLB
VSS
PEG_TX
_1
PEG_R
X#_2
PEG_R
X_2
VSS
PEG_R
X_3
PEG_R
X#_3
VSS
VCCD_L
VDS
VSS VSS
L_BKLT
_CTRL
CRT_VS
YNC
VCCD_
QDAC
VSS
K
VCC_TX
_LVDS
LVDSB_
DATA_3
CLKRE
Q#
L_DDC_
CLK
VSS VSS VSS
TVC_DA
C
J
VCCA_L
VDS
VSSA_L
VDS
PEG_R
X#_1
PEG_R
X_1
VSS
PEG_TX
_0
PEG_TX
#_0
VSS
LVDSB_
DATA#_
3
VSS
L_DDC_
DATA
CRT_D
DC_DA
TA
CRT_H
SYNC
CRT_R
ED
VSS
H
LVDSA_
DATA_0
LVDSA_
DATA#_
0
VSS
PEG_R
X#_0
PEG_R
X_0
VSS
LVDSB_
DATA#_
1
VSS
ICH_SY
NC#
VSS
CRT_D
DC_CLK
VSS VSS
TVB_DA
C
G
VSS VSS
LVDSA_
DATA#_
2
LVDSB_
DATA_1
LVDSB_
DATA#_
2
SDVO_
CTRLCL
K
GFX_VI
D_2
L_BKLT
_EN
CRT_IR
TN
CRT_G
REEN
VSS
F
NC
VCCA_
DPLLA
VSS VSS
PEG_CL
K
DPLL_R
EF_SSC
LK#
LVDSA_
DATA_2
VSS
LVDSB_
DATA_2
VSS
GFX_VI
D_3
VSS VSS VSS
TVA_DA
C
E
NC
LVDSA_
DATA#_
1
PEG_CL
K#
DPLL_R
EF_SSC
LK
VSS
LVDS_V
REFL
LVDS_V
REFH
SDVO_
CTRLD
ATA
GFX_VI
D_4
TV_DC
ONSEL_
1
CRT_TV
O_IREF
CRT_BL
UE
VSS
D
NC
LVDSA_
DATA_1
C
NC NC
LVDS_I
BG
VSS
LVDSA_
CLK#
LVDSA_
CLK
VSS VSS
VCC_H
V
GFX_VR
_EN
VSS
TV_DC
ONSEL_
0
HDA_S
DO
VSS VSS CFG_5
B
NC NC NC
LVDS_V
BG
LVDSB_
DATA_0
VSS
LVDSA_
DATA_3
VSS
DPLL_R
EF_CLK
LVDSB_
CLK#
VSS
VCC_H
V
VSS
GFX_VI
D_0
GFX_VI
D_1
RESER
VED
HDA_R
ST#
HDA_S
DI
HDA_B
CLK
VCCA_
CRT_D
AC
VSS
VSSA_D
AC_BG
A
VSS_SC
B
NC NC NC NC
LVDSB_
DATA#_
0
LVDSA_
DATA#_
3
DPLL_R
EF_CLK
#
LVDSB_
CLK
VCC_H
V
VSS
VCC_H
DA
VSS VSS
HDA_SY
NC
VCCA_
CRT_D
AC
VCCA_
DAC_B
G
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Datasheet 129
Figure 24. Ballout Diagram (Top View) Lower Right Quadrant
H_D#_3
3
H_D#_4
7
VSS
H_D#_4
5
H_D#_4
6
VSS
H_D#_5
1
H_D#_5
4
H_D#_6
3
VSS
H_D#_5
3
VSS
VCCA_
HPLL
AD
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VSS
H_D#_5
9
VSS
H_D#_5
7
AC
VSS
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
VTTLF
AB
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G
VSS
H_D#_4
2
VSS
H_D#_4
4
VSS
H_D#_4
3
H_D#_4
0
VSS
H_DSTB
P#_2
H_DSTB
N#_2
H_D#_5
2
H_D#_5
0
VSS
AA
VCC_AX
G
VSS
VCC_AX
G
VSS
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
H_D#_3
7
H_DINV
#_2
H_D#_3
6
VSS
H_D#_3
5
H_D#_4
1
VSS
H_D#_3
8
H_D#_3
4
VSS
H_D#_3
2
VSS
H_DINV
#_3
Y
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VSS
H_D#_3
9
W
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G
VTT VTT VTT
V
VSS
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VCC_AX
G_NCT
F
VSS_NC
TF
VCC_AX
G_NCT
F
VCC_AX
G
VCC_AX
G
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
U
RESER
VED
CFG_13
THERM
TRIP#
VCC_AX
G
VCC_AX
G
VCC_AX
G
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
T
VSS VSS CFG_14 VSS
H_A#_1
1
VSS
H_D#_1
8
H_D#_2
4
R
CFG_4 CFG_12 CFG_3
H_A#_1
5
H_A#_1
0
H_D#_2
7
VSS
H_D#_1
6
VSS
P
CFG_6 CFG_11 VSS
H_A#_1
2
VSS VSS
H_D#_1
4
VSS
H_D#_3
0
H_D#_1
9
H_D#_2
8
VSS
H_D#_2
6
H_D#_2
5
H_D#_2
3
N
CFG_7 VSS CFG_15 VSS H_A#_8
H_A#_1
3
H_D#_1
1
VSS
H_D#_1
0
H_DSTB
P#_1
H_DSTB
N#_1
VSS
H_D#_2
1
H_D#_3
1
VSS
RESER
VED
M
VSS CFG_16
H_A#_3
5
H_A#_2
3
H_A#_2
6
VSS VSS
H_DSTB
N#_0
H_DSTB
P#_0
VSS
H_D#_2
9
H_D#_2
0
VSS
H_DINV
#_1
H_D#_1
7
VTTLF
L
VSS
H_A#_3
4
VSS
H_A#_3
1
VSS
H_REQ
#_1
RESER
VED
VSS
K
VSS VSS
H_A#_2
2
H_A#_2
8
H_A#_1
9
H_A#_9 VSS
H_DPW
R#
H_DINV
#_0
VSS
H_D#_1
5
VSS
H_D#_2
2
H_D#_1
3
H_D#_1
2
J
TV_RTN CFG_17
H_A#_2
9
VSS
H_A#_2
1
H_A#_6 H_ADS#
H_LOC
K#
H_HIT# H_D#_5 VSS H_D#_9 H_D#_6 VSS
H
VSS VSS
H_A#_1
7
H_ADST
B#_1
VSS VSS
H_BRE
Q#
VSS VSS H_D#_1 H_D#_4
G
VSS
H_A#_3
3
VSS
H_A#_1
6
H_A#_5
H_REQ
#_2
H_RS#_
1
H_BPRI
#
H_DRD
Y#
H_D#_2 H_D#_7 VSS VSS H_D#_0 NC
F
VSS CFG_8
H_A#_2
0
H_A#_1
4
VSS VSS
H_HITM
#
H_CPU
SLP#
H_DEFE
R#
VSS H_D#_3
H_RCO
MP
NC
E
H_D#_8 NC
D
CFG_10 CFG_9
H_A#_2
7
VSS H_A#_7 VSS H_A#_4 VSS
H_CPU
RST#
VSS
H_TRD
Y#
H_RS#_
2
VSS
H_SWIN
G
NC
VSS_SC
B
C
VCCA_T
V_DAC
VSS
VCC_AX
F
VCC_AX
F
H_A#_3
2
H_A#_1
8
H_A#_3
0
H_A#_2
5
H_ADST
B#_0
H_REQ
#_0
H_REQ
#_4
H_REQ
#_3
TSATN#
H_DVR
EF
H_DBSY
#
VSS VSS
PM_DP
RSTP#
H_RS#_
0
NC
RESER
VED
B
VCCA_T
V_DAC
VSS
VCC_AX
F
VSS VSS
H_A#_2
4
VSS H_A#_3 VSS
H_AVRE
F
H_BNR# VTTLF NC NC
VSS_SC
B
A
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
130 Datasheet
16.2 GMCH Signal List by Ball
Table 33. Mobile Intel 4 Series Express Chipset Ball List (Sheet 1 of 12)
Ball Signal Ball Signal Ball Signal
A11 H_AVREF AR21 SA_CK#_1 C48 NC
A12 VSS AR24 SA_CK#_0 C5 H_SWING
A14 H_A#_3 AR25 VSS C6 VSS
A15 VSS AR28 VSS C8 H_RS#_2
A17 H_A#_24 AR29 VCC_SM C9 H_TRDY#
A18 VSS AR3 SB_DQ_50 D2 NC
A20 VSS AR32 VCC_SM D4 H_D#_8
A21 VCC_AXF AR33 VSS D45 LVDSA_DATA_1
A23 VSS AR36 SM_PWROK D47 NC
A24 VCCA_TV_DAC AR46 VSS E1 NC
A25 VCCA_DAC_BG AR47 SB_DQ_13 E11 H_CPUSLP#
A26 VCCA_CRT_DAC AR48 VSS E12 H_HITM#
A28 HDA_SYNC AT10 VSS E13 VSS
A29 VSS AT11 RSTIN# E16 VSS
A3 VSS_SCB AT12 VSS E17 H_A#_14
A31 VSS AT13 VCC_SM/NC E20 H_A#_20
A32 VCC_HDA AT16 VCCA_SM E21 CFG_8
A34 VSS AT17 VSS E24 VSS
A35 VCC_HV AT2 SB_DQS#_6 E25 VSS
A37 LVDSB_CLK AT20 VSS E28 CRT_BLUE
A38 DPLL_REF_CLK# AT21 SA_CK_1 E29 CRT_TVO_IREF
A40 LVDSA_DATA#_3 AT24 VSS E3 H_RCOMP
A41 LVDSB_DATA#_0 AT25 SA_BS_2 E32 TV_DCONSEL_1
A43 NC AT28 VSS E33 GFX_VID_4
A44 NC AT29 VCC_SM E36 SDVO_CTRLDATA
A46 NC AT32 VCC_SM E37 LVDS_VREFH
A47 NC AT33 SB_MA_8 E38 LVDS_VREFL
A48 VSS_SCB AT36 SA_DQ_27 E40 VSS
A5 NC AT37 VSS E41 DPLL_REF_SSCLK
A6 NC AT38 SA_DQ_11 E43 PEG_CLK#
A8 VTTLF AT39 VSS E46 LVDSA_DATA#_1
A9 H_BNR# AT40 PWROK E48 NC
AA1 VSS AT41 SA_DM_1 E6 H_D#_3
AA10 VSS AT42 VSS E8 VSS
AA11 H_D#_44 AT43 SA_DQS#_1 E9 H_DEFER#
Datasheet 131
AA12 VSS AT44 SA_DQS_1 F1 NC
AA13 H_D#_42 AT47 SB_DQ_12 F11 H_BPRI#
AA14 VSS AT5 SA_DQ_54 F12 H_RS#_1
AA15 VCC_AXG AT6 VSS F13 H_REQ#_2
AA16 VCC_AXG_NCTF AT7 SA_DM_6 F16 H_A#_5
AA17 VSS_NCTF AT8 VSS F17 H_A#_16
AA19 VCC_AXG_NCTF AT9 SA_DQ_50 F2 H_D#_0
AA2 H_D#_50 AU1 SB_DQS_6 F20 VSS
AA20 VCC_AXG AU10 SA_DQ_42 F21 H_A#_33
AA21 VCC_AXG AU11 SA_DQ_33 F24 VSS
AA23 VCC_AXG AU13 SA_DQ_36 F25 TVA_DAC
AA24 VCC_AXG AU16 VSS F28 VSS
AA25 VCC_AXG AU17 SB_RAS# F29 VSS
AA26 VSS AU2 VSS F3 VSS
AA28 VCC AU20 SB_CK_1 F32 VSS
AA29 VCC_NCTF AU21 VSS F33 GFX_VID_3
AA3 H_D#_52 AU24 SB_CK#_0 F36 VSS
AA30 VCC_NCTF AU25 SB_MA_3 F37 LVDSB_DATA_2
AA32 VCC_NCTF AU28 SB_MA_6 F38 VSS
AA33 VCC AU29 VCC_SM F40 LVDSA_DATA_2
AA34 VCC AU3 SB_DQ_49 F41 DPLL_REF_SSCLK#
AA35 VSS AU32 VCC_SM F43 PEG_CLK
AA36 PEG_TX_12 AU33 SB_MA_14 F44 VSS
AA37 PEG_TX#_12 AU36 VSS F46 VSS
AA38 VSS AU38 VSS F47 VCCA_DPLLA
AA39 PEG_TX_13 AU39 SA_DM_3 F48 NC
AA40 PEG_TX#_13 AU40 SA_DQ_10 F5 VSS
AA41 VSS AU41 VSS F6 H_D#_7
AA42 PEG_RX_12 AU42 SA_DQ_15 F8 H_D#_2
AA43 PEG_RX#_12 AU43 VSS F9 H_DRDY#
AA44 VSS AU44 SA_DQ_14 G11 VSS
AA46 PEG_TX#_11 AU46 SB_DQ_9 G12 H_BREQ#
AA47 VCCD_PEG_PLL AU47 SB_DQ_8 G13 VSS
AA48 VCCA_PEG_PLL AU48 VSS G16 VSS
AA5 H_DSTBN#_2 AU5 SA_DQ_52 G17 H_ADSTB#_1
AA6 H_DSTBP#_2 AU6 SA_DQ_53 G2 H_D#_4
AA7 VSS AU7 VSS G20 H_A#_17
AA8 H_D#_40 AU8 SA_DQS_6 G21 VSS
132 Datasheet
AA9 H_D#_43 AU9 SA_DQS#_6 G24 VSS
AB15 VCC_AXG AV1 SB_DQ_53 G25 VSS
AB16 VCC_AXG_NCTF AV10 VSS G28 CRT_GREEN
AB17 VCC_AXG_NCTF AV12 VSS G29 CRT_IRTN
AB19 VCC_AXG_NCTF AV13 SA_DQ_37 G32 L_BKLT_EN
AB2 VTTLF AV16 SB_CS#_0 G33 GFX_VID_2
AB20 VCC_AXG AV17 SB_MA_0 G36 SDVO_CTRLCLK
AB21 VSS AV2 SB_DQ_48 G37 LVDSB_DATA#_2
AB23 VCC_AXG AV20 SB_CK#_1 G38 LVDSB_DATA_1
AB24 VSS AV21 VCC_SM_LF G40 LVDSA_DATA#_2
AB25 VCC_AXG AV24 SB_CK_0 G41 VSS
AB26 VSS AV25 VSS G47 VSS
AB28 VSS AV28 VSS G8 H_D#_1
AB29 VSS_NCTF AV29 VCC_SM G9 VSS
AB30 VCC_NCTF AV3 VSS H1 VSS
AB32 VSS_NCTF AV32 VCC_SM H11 H_LOCK#
AB33 VSS AV33 VSS H12 H_ADS#
AB34 VCC AV36 SA_DQ_30 H13 H_A#_6
AB47 VSS AV37 SA_DQ_26 H16 H_A#_21
AC1 H_D#_57 AV39 SA_DQ_16 H17 VSS
AC15 VSS AV40 VSS H2 H_D#_6
AC16 VCC_AXG_NCTF AV41 SA_DQ_20 H20 H_A#_29
AC17 VCC_AXG_NCTF AV42 SM_VREF H21 CFG_17
AC19 VSS_NCTF AV43 VSS H24 TV_RTN
AC2 VSS AV44 VCC_SM_LF H25 TVB_DAC
AC20 VCC_AXG AV46 VSS H28 VSS
AC21 VCC_AXG AV47 SB_DQS#_1 H29 VSS
AC23 VCC_AXG AV48 SB_DQS_1 H3 H_D#_9
AC24 VCC_AXG AV5 SA_DQ_48 H32 CRT_DDC_CLK
AC25 VSS AV6 VSS H33 VSS
AC26 VCC AV7 SA_DQ_49 H36 ICH_SYNC#
AC28 VCC AV8 VSS H37 VSS
AC29 VCC_NCTF AV9 SA_DQ_43 H38 LVDSB_DATA#_1
AC3 H_D#_59 AW12 SA_DQS_4 H40 VSS
AC30 VCC_NCTF AW13 VCC_SM/NC H43 PEG_RX_0
AC32 VCC_NCTF AW16 VCC_SM/NC H44 PEG_RX#_0
AC33 VCC AW17 VSS H46 VSS
AC34 VCC AW2 VSS H47 LVDSA_DATA#_0
Datasheet 133
AC46 PEG_TX#_15 AW20 VSS H48 LVDSA_DATA_0
AC47 PEG_RX#_14 AW21 VSS H5 VSS
AC48 PEG_RX_14 AW24 SA_MA_9 H6 H_D#_5
AD1 VCCA_HPLL AW25 SB_MA_4 H9 H_HIT#
AD10 H_D#_46 AW28 SB_MA_7 J1 H_D#_12
AD11 H_D#_45 AW29 VCC_SM J11 H_DPWR#
AD12 VSS AW32 VCC_SM J12 VSS
AD13 H_D#_47 AW33 SB_MA_11 J13 H_A#_9
AD14 H_D#_33 AW36 SA_DQ_31 J16 H_A#_19
AD2 VSS AW37 VSS J17 H_A#_28
AD3 H_D#_53 AW47 VSS J2 H_D#_13
AD35 DMI_TXP_0 AY1 SB_DQ_43 J20 H_A#_22
AD36 PEG_RX_13 AY11 VSS J21 VSS
AD37 PEG_RX#_13 AY12 SA_DQS#_4 J24 VSS
AD38 VSS AY13 SB_ODT_1 J25 VSS
AD39 PEG_RX#_15 AY16 SA_CS#_1 J28 CRT_RED
AD40 PEG_RX_15 AY17 SA_ODT_1 J29 CRT_HSYNC
AD41 VSS AY2 SB_DQ_52 J3 H_D#_22
AD42 PEG_TX_14 AY20 SA_WE# J32 CRT_DDC_DATA
AD43 PEG_TX#_14 AY21 RESERVED J33 L_DDC_DATA
AD44 VSS AY24 VSS J36 VSS
AD46 PEG_TX_15 AY25 SA_MA_14 J37 LVDSB_DATA#_3
AD47 VSS AY28 SA_CKE_1 J38 VSS
AD48 VCCA_PEG_BG AY29 VCC_SM J41 PEG_TX#_0
AD5 VSS AY3 SB_DQ_42 J42 PEG_TX_0
AD6 H_D#_63 AY32 VCC_SM J43 VSS
AD7 H_D#_54 AY33 SB_MA_12 J44 PEG_RX_1
AD8 H_D#_51 AY36 SB_CKE_0 J46 PEG_RX#_1
AD9 VSS AY37 SA_DQ_24 J47 VSSA_LVDS
AE1 VCCA_MPLL AY38 SA_DQ_28 J48 VCCA_LVDS
AE10 VSS AY41 SA_DM_2 J5 VSS
AE11 H_D#_60 AY42 VSS J6 H_D#_15
AE12 H_D#_48 AY43 SA_DQ_21 J7 VSS
AE13 VSS AY44 SA_DQ_17 J8 H_DINV#_0
AE14 H_D#_55 AY46 VSS K12 RESERVED
AE15 VCC_AXG AY47 SB_DM_1 K13 H_REQ#_1
AE16 VCC_AXG_NCTF AY48 SB_DQ_11 K16 VSS
AE17 VCC_AXG_NCTF AY5 VCC_SM_LF K17 H_A#_31
134 Datasheet
AE19 VCC_AXG_NCTF AY6 SA_DM_5 K2 VSS
AE2 VSS AY7 VSS K20 VSS
AE20 VCC_AXG AY8 SA_DQ_46 K21 H_A#_34
AE21 VCC_AXG B10 H_DBSY# K24 VSS
AE23 VCC_AXG B11 H_DVREF K25 TVC_DAC
AE24 VCC_AXG B12 TSATN# K28 VSS
AE25 VCC_AXG B13 H_REQ#_3 K29 VSS
AE26 VCC B14 H_REQ#_4 K32 VSS
AE28 VSS B15 H_REQ#_0 K33 L_DDC_CLK
AE29 VCC_NCTF B16 H_ADSTB#_0 K36 CLKREQ#
AE3 H_D#_58 B17 H_A#_25 K37 LVDSB_DATA_3
AE30 VCC_NCTF B18 H_A#_30 K47 VCC_TX_LVDS
AE32 VCC_NCTF B19 H_A#_18 L1 VTTLF
AE33 VCC B2 RESERVED L10 H_DSTBN#_0
AE34 VSS B20 H_A#_32 L12 VSS
AE35 DMI_TXN_0 B21 VCC_AXF L13 VSS
AE36 VSS B22 VCC_AXF L16 H_A#_26
AE37 DMI_RXN_1 B23 VSS L17 H_A#_23
AE38 DMI_RXP_1 B24 VCCA_TV_DAC L2 H_D#_17
AE39 VSS B25 VSSA_DAC_BG L20 H_A#_35
AE40 DMI_RXP_0 B26 VSS L21 CFG_16
AE41 DMI_RXN_0 B27 VCCA_CRT_DAC L24 VSS
AE42 VSS B28 HDA_BCLK L25 VSS
AE43 DMI_TXN_1 B29 HDA_SDI L28 VCCD_QDAC
AE44 DMI_TXP_1 B30 HDA_RST# L29 CRT_VSYNC
AE46 DMI_TXN_2 B31 RESERVED L3 H_DINV#_1
AE47 DMI_RXN_2 B32 GFX_VID_1 L32 L_BKLT_CTRL
AE48 DMI_RXP_2 B33 GFX_VID_0 L33 VSS
AE5 H_DSTBP#_3 B34 VSS L36 VSS
AE6 H_DSTBN#_3 B35 VCC_HV L37 VCCD_LVDS
AE7 VSS B36 VSS L39 VSS
AE8 H_D#_61 B37 LVDSB_CLK# L40 PEG_RX#_3
AE9 H_D#_49 B38 DPLL_REF_CLK L41 PEG_RX_3
AF1 VCCD_HPLL B39 VSS L42 VSS
AF15 VCC_AXG B4 NC L43 PEG_RX_2
AF16 VCC_AXG_NCTF B40 LVDSA_DATA_3 L44 PEG_RX#_2
AF17 VCC_AXG_NCTF B41 VSS L46 PEG_TX_1
AF19 VCC_AXG_NCTF B42 LVDSB_DATA_0 L47 VSS
Datasheet 135
AF2 VSS B43 LVDS_VBG L48 VCCA_DPLLB
AF20 VCC_AXG B45 NC L5 VSS
AF21 VSS B47 NC L6 H_D#_20
AF23 VCC B48 NC L7 H_D#_29
AF24 VSS B6 H_RS#_0 L8 VSS
AF25 VCC B7 PM_DPRSTP# L9 H_DSTBP#_0
AF26 VSS B8 VSS M1 RESERVED
AF28 VCC B9 VSS M10 VSS
AF29 VSS_NCTF BA1 SB_DQ_46 M11 H_D#_11
AF3 H_D#_56 BA11 SA_DQ_44 M13 H_A#_13
AF30 VCC_NCTF BA12 SA_DQ_35 M16 H_A#_8
AF32 VSS_NCTF BA13 VSS M17 VSS
AF33 VCC BA16 VSS M2 VSS
AF34 VSS BA17 SA_CS#_0 M20 CFG_15
AF46 DMI_TXP_2 BA2 VSS M21 VSS
AF47 VSS BA20 VSS M24 CFG_7
AF48 VCC_DMI BA21 SA_MA_0 M25 VCCD_TVDAC
AG15 VCC_AXG BA24 SA_MA_5 M28 DDPC_CTRLDATA
AG16 VCC_AXG_NCTF BA25 SB_MA_1 M29 L_VDD_EN
AG17 VCC_AXG_NCTF BA28 VSS M3 H_D#_31
AG19 VCC_AXG_NCTF BA29 VCC_SM M32 L_CTRL_CLK
AG2 H_D#_62 BA3 SB_DM_5 M33 L_CTRL_DATA
AG20 VSS BA32 VCC_SM M36 RESERVED
AG21 VCC_AXG BA33 VSS M38 VCCD_LVDS
AG23 VSS BA36 VCC_SM/NC M39 PEG_TX_3
AG24 VCC BA37 VCC_SM_LF M40 PEG_TX#_3
AG25 VCC BA38 VSS M41 VSS
AG26 VCC BA40 SA_DQ_18 M42 PEG_TX#_4
AG28 VSS BA43 SA_DQS_2 M43 PEG_TX_4
AG29 VCC_NCTF BA44 SA_DQS#_2 M44 VSS
AG30 VCC_NCTF BA46 VSS M46 PEG_TX#_1
AG32 VCC_NCTF BA47 SB_DQ_14 M47 PEG_TX#_2
AG33 VCC BA48 SB_DQ_10 M48 PEG_TX_2
AG34 VCC BA5 VSS M5 H_D#_21
AG47 VCC_DMI BA6 SA_DQ_47 M6 VSS
AH1 SB_DQ_59 BA9 SA_DQ_41 M7 H_DSTBN#_1
AH10 RESERVED BB11 VSS M8 H_DSTBP#_1
AH11 VSS BB12 SA_DM_4 M9 H_D#_10
136 Datasheet
AH12 RESERVED BB13 VCC_SM_LF N10 H_D#_30
AH13 RESERVED BB16 SB_MA_10 N11 VSS
AH14 VSS_AXG_SENSE BB17 SB_BS_1 N12 H_D#_14
AH15 VCC_AXG BB2 SB_DQS_5 N13 VSS
AH16 VCC_AXG_NCTF BB20 SA_RAS# N16 VSS
AH17 VCC_AXG_NCTF BB21 VCC_SM/NC N17 H_A#_12
AH19 VCC_AXG_NCTF BB24 VCC_SM/NC N2 H_D#_23
AH2 VSS BB25 VSS N20 VSS
AH20 VCC_AXG BB28 SB_MA_5 N21 CFG_11
AH21 VSS BB29 VCC_SM N24 CFG_6
AH23 VCC BB32 VCC_SM N25 VSS
AH24 VSS BB33 SB_BS_2 N28 DDPC_CTRLCLK
AH25 VCC BB36 SB_CKE_1 N29 VSS
AH26 VSS BB37 VSS N32 VSS
AH28 VCC BB38 SA_DQ_29 N33 PM_EXT_TS#_0
AH29 VCC_NCTF BB40 VSS N36 RESERVED
AH3 SB_DQ_62 BB41 SA_DQ_22 N37 PEG_TX_6
AH30 VCC_NCTF BB47 VSS N38 PEG_TX#_6
AH32 VCC_NCTF BB8 VSS N39 VSS
AH33 VSS BB9 SA_DQ_40 N40 PEG_RX_4
AH34 CL_VREF BC1 NC N41 PEG_RX#_4
AH35 VSS BC11 SA_DQ_34 N42 VSS
AH36 CL_DATA BC12 SA_DQ_39 N43 PEG_RX_6
AH37 CL_CLK BC13 VSS N44 PEG_RX#_6
AH38 VSS BC16 SB_BS_0 N47 VSS
AH39 DMI_RXN_3 BC17 VSS N5 H_D#_25
AH40 DMI_RXP_3 BC2 SB_DQS#_5 N6 H_D#_26
AH41 VSS BC20 VSS N7 VSS
AH42 DMI_TXN_3 BC21 SA_MA_10 N8 H_D#_28
AH43 DMI_TXP_3 BC24 SA_MA_1 N9 H_D#_19
AH44 VSS BC25 SB_MA_2 P1 VSS
AH46 SB_DQ_1 BC28 SA_CKE_0 P13 H_D#_27
AH47 VCC_DMI BC29 VCC_SM P16 H_A#_10
AH48 VCC_DMI BC3 VSS P17 H_A#_15
AH5 VSS BC32 VCC_SM P2 H_D#_16
AH6 HPLL_CLK# BC33 VSS P20 CFG_3
AH7 HPLL_CLK BC36 SM_DRAMRST# P21 CFG_12
AH8 VSS BC37 SA_DQS_3 P24 CFG_4
Datasheet 137
AH9 RESERVED BC38 VSS P25 CFG_2
AJ1 SB_DQ_58 BC40 SA_DQ_23 P28 VSS
AJ10 VSS BC41 SB_DQ_21 P29 CFG_18
AJ11 SA_DQ_62 BC43 VSS P3 VSS
AJ12 SA_DQ_63 BC44 SB_DQ_17 P32 PM_EXT_TS#_1
AJ13 VSS BC46 SB_DQ_16 P33 VSS
AJ14 VCC_AXG_SENSE BC47 SB_DQ_15 P36 VSS
AJ15 VCC_AXG BC48 NC P46 VSS
AJ16 VCC_AXG_NCTF BC5 SB_DQ_40 P47 PEG_RX_5
AJ17 VSS_NCTF BC6 SB_DQ_41 P48 PEG_RX#_5
AJ19 VCC_AXG_NCTF BC8 SA_DQS_5 R1 H_D#_24
AJ2 VSS BC9 VSS R16 H_A#_11
AJ20 VSS BD1 NC R17 VSS
AJ21 VCC_AXG BD11 VSS R2 H_D#_18
AJ23 VCC BD12 SA_DQ_38 R20 CFG_14
AJ24 VSS BD13 SA_DQ_32 R21 VSS
AJ25 VSS BD16 VCC_SM/NC R24 VSS
AJ26 VCC BD17 SA_ODT_0 R25 CFG_1
AJ28 VSS BD20 SA_CAS# R28 CFG_19
AJ29 VCC_NCTF BD21 SA_BS_0 R29 PM_SYNC#
AJ3 SB_DQ_63 BD24 SA_MA_6 R3 VSS
AJ30 VSS_NCTF BD25 VSS R32 DPRSLPVR
AJ32 VCC_NCTF BD28 VSS R33 RESERVED
AJ33 VCC BD29 VCC_SM R46 VSS
AJ34 VSS BD3 SB_DQ_47 R47 PEG_TX_5
AJ35 CL_RST# BD32 VCC_SM R48 PEG_TX#_5
AJ36 SA_DQ_4 BD33 SB_MA_9 T10 VTT
AJ37 VSS BD36 VSS T11 VTT
AJ38 SA_DQ_0 BD37 SA_DQS#_3 T12 VTT
AJ39 VSS BD38 SA_DQ_25 T13 VTT
AJ40 SA_DQ_5 BD40 SB_DM_2 T14 VCC_AXG
AJ41 SA_DQ_1 BD41 VSS T16 VCC_AXG
AJ42 VSS BD43 SA_DQ_19 T17 VCC_AXG
AJ43 SA_DQS#_0 BD46 VSS T2 VTT
AJ44 SA_DQS_0 BD48 NC T20 THERMTRIP#
AJ46 SB_DQ_4 BD6 VSS T21 CFG_13
AJ47 VSS BD8 SA_DQS#_5 T24 RESERVED
AJ48 SB_DQ_5 BD9 SA_DQ_45 T25 CFG_0
138 Datasheet
AJ5 SA_DM_7 BE2 NC T28 CFG_20
AJ6 VSS BE4 VSS T29 VSS
AJ7 VSS BE45 SB_DQ_20 T32 VCC
AJ8 SA_DQ_59 BE47 NC T33 RESERVED
AJ9 SA_DQ_58 BF1 NC T35 VSS
AK15 VSS BF11 SB_DQ_37 T36 PEG_COMPO
AK16 VCC_AXG_NCTF BF12 VSS T37 PEG_COMPI
AK17 VCC_AXG_NCTF BF14 SB_WE# T38 VSS
AK19 VCC_AXG_NCTF BF15 SB_ODT_0 T39 PEG_TX_7
AK2 SB_DM_7 BF17 SM_REXT T40 PEG_TX#_7
AK20 VCC_AXG_NCTF BF18 RESERVED T41 VSS
AK21 VCC_AXG_NCTF BF20 VCC_SM_CK T42 PEG_RX_7
AK23 VCC_NCTF BF21 VCC_SM_CK T43 PEG_RX#_7
AK24 VCC_NCTF BF23 RESERVED T44 VSS
AK25 VCC_NCTF BF24 VSS T47 VSS
AK26 VCC_NCTF BF25 SA_MA_8 T5 VTT
AK28 VCC_NCTF BF26 VSS T6 VTT
AK29 VCC_NCTF BF28 SM_RCOMP_VOH T7 VTT
AK30 VCC_NCTF BF29 VCC_SM T8 VTT
AK32 VCC_NCTF BF3 NC T9 VTT
AK33 VCC BF31 VCC_SM U1 VTT
AK34 ME_JTAG_TDI BF32 VCC_SM U10 VTT
AK47 SB_DQ_0 BF34 VSS U11 VTT
AL1 SB_DQ_56 BF35 SB_DM_3 U12 VTT
AL15 VCC_AXG BF37 VSS U13 VTT
AL16 VCC_AXG_NCTF BF38 SB_DQ_25 U14 VCC_AXG
AL17 VSS_NCTF BF40 SB_DQ_22 U15 VCC_AXG
AL19 VCC_AXG_NCTF BF41 SB_DQ_23 U16 VCC_AXG_NCTF
AL2 SB_DQ_57 BF43 SB_DQ_19 U17 VSS_NCTF
AL20 VSS_NCTF BF44 VSS U19 VCC_AXG_NCTF
AL21 VCC_AXG_NCTF BF46 NC U2 VTT
AL23 VCCA_SM_CK_NCTF BF48 NC U20 VCC_AXG_NCTF
AL24 VCCA_SM_CK_NCTF BF5 SB_DQ_45 U21 VCC_AXG_NCTF
AL25 VCCA_SM_CK_NCTF BF6 SB_DQ_44 U23 VSS_NCTF
AL26 VCC_NCTF BF8 SB_DQ_38 U24 VSS
AL28 VCC_NCTF BF9 VSS U25 VSS
AL29 VCC_NCTF BG1 NC U26 VSS_NCTF
AL3 VSS BG10 VSS U28 VSS
Datasheet 139
AL30 VCC_NCTF BG11 SB_DM_4 U29 VSS
AL32 VCC_NCTF BG12 SB_DQ_33 U3 VTT
AL33 VSS BG13 VSS U30 VCC_NCTF
AL34 ME_JTAG_TCK BG14 VSS U32 VCC_NCTF
AL46 SB_DQS#_0 BG15 VSS U33 VCC
AL47 SB_DQS_0 BG16 SB_CAS# U34 VCC
AL48 VSS BG17 VSS U35 VSS
AM1 VSS BG18 SA_BS_1 U36 PEG_TX_8
AM10 VCC_SM_LF BG19 VSS U37 PEG_TX#_8
AM11 SA_DQ_56 BG2 NC U38 VSS
AM12 VSS BG20 VCC_SM_CK U39 PEG_TX_9
AM13 SA_DQ_61 BG21 VSS U40 PEG_TX#_9
AM14 VCC_AXG BG22 SM_RCOMP U41 VSS
AM15 VCC_AXG BG23 RESERVED U42 PEG_RX_8
AM16 VCC_AXG_NCTF BG24 SA_MA_2 U43 PEG_RX#_8
AM17 VCC_AXG_NCTF BG25 SA_MA_4 U44 VSS
AM19 VCC_AXG_NCTF BG26 SA_MA_11 U46 VCC_PEG
AM2 SB_DQ_60 BG27 SA_MA_7 U47 VCC_PEG
AM20 VCC_AXG_NCTF BG28 VSS U48 VCC_PEG
AM21 VCC_AXG_NCTF BG29 VCC_SM U5 VTT
AM23 VCCA_SM_CK_NCTF BG30 VCC_SM U6 VTT
AM26 VCCA_SM_CK_NCTF BG33 VSS U9 VTT
AM28 VCCA_SM_CK_NCTF BG34 SB_DQ_30 V1 VTT
AM29 VSS_NCTF BG35 SB_DQ_27 V15 VCC_AXG
AM3 SB_DQ_61 BG36 VSS V16 VCC_AXG_NCTF
AM30 VCC_NCTF BG37 SB_DQS_3 V17 VCC_AXG_NCTF
AM32 VCC_NCTF BG38 SB_DQ_24 V19 VCC_AXG_NCTF
AM33 VCC BG39 SB_DQ_29 V2 VTT
AM34 VSS BG4 NC V20 VSS_NCTF
AM35 ME_JTAG_TMS BG40 VSS V21 VCC_AXG_NCTF
AM36 VSS BG41 SB_DQS_2 V23 VCC_AXG_NCTF
AM37 SA_DM_0 BG42 VSS V24 VCC_AXG_NCTF
AM38 SA_DQ_3 BG43 SB_DQ_18 V25 VCC_AXG_NCTF
AM39 VSS BG45 NC V26 VCC_AXG_NCTF
AM40 VCC_SM_LF BG47 NC V28 VCC_AXG_NCTF
AM41 VSS BG48 NC V29 VCC_NCTF
140 Datasheet
AM42 SA_DQ_7 BG6 VSS V3 VTT
AM43 VSS BG7 SB_DQ_39 V30 VCC_NCTF
AM44 SA_DQ_6 BG8 SB_DQ_35 V32 VSS_NCTF
AM46 VSS BG9 SB_DQS#_4 V33 VCC
AM47 SB_DM_0 BH1 VSS_SCB V34 VCC
AM48 SB_DQ_6 BH11 SB_DQ_34 V46 VSS
AM5 SA_DQ_57 BH12 SB_DQ_36 V47 VCC_PEG
AM6 VSS BH14 SB_DQ_32 V48 VCC_PEG
AM7 SA_DQS_7 BH15 SB_MA_13 W15 VSS
AM8 SA_DQS#_7 BH17 SA_MA_13 W16 VCC_AXG_NCTF
AM9 VSS BH18 RESERVED W17 VCC_AXG_NCTF
AN10 SA_DQ_55 BH2 NC W19 VCC_AXG_NCTF
AN11 VSS BH20 VCC_SM_CK W2 H_D#_39
AN12 SA_DQ_60 BH21 SM_RCOMP# W20 VCC_AXG_NCTF
AN13 VSS BH23 VSS W21 VCC_AXG_NCTF
AN14 VCC_AXG BH24 SA_MA_3 W23 VCC_AXG_NCTF
AN16 VSS BH25 VSS W24 VCC_AXG_NCTF
AN17 VCCA_SM BH26 SA_MA_12 W25 VCC_AXG_NCTF
AN2 SB_DQ_51 BH28 SM_RCOMP_VOL W26 VCC_AXG_NCTF
AN20 VCCA_SM BH29 VCC_SM W28 VCC_AXG_NCTF
AN21 VSS BH3 NC W29 VCC_NCTF
AN24 VCCA_SM_CK BH31 VCC_SM W30 VCC_NCTF
AN25 VCCA_SM_CK BH32 VCC_SM W32 VCC_NCTF
AN28 VCCA_SM_CK BH34 SB_DQ_31 W33 VCC
AN29 VSS BH35 SB_DQ_26 W34 VSS
AN32 VCC_SM BH37 SB_DQS#_3 W47 PEG_RX_10
AN33 VCC_SM BH38 VSS Y1 H_DINV#_3
AN35 ME_JTAG_TDO BH40 SB_DQ_28 Y10 H_D#_35
AN36 CL_PWROK BH41 SB_DQS#_2 Y11 VSS
AN37 VSS BH43 NC Y12 H_D#_36
AN38 SA_DQ_2 BH44 NC Y13 H_DINV#_2
AN39 SA_DQ_13 BH46 NC Y14 H_D#_37
AN40 VSS BH47 NC Y15 VCC_AXG
AN41 SA_DQ_12 BH48 VSS_SCB Y16 VCC_AXG_NCTF
AN42 VSS BH5 NC Y17 VCC_AXG_NCTF
AN43 SA_DQ_8 BH6 NC Y19 VCC_AXG_NCTF
AN44 SA_DQ_9 BH8 VSS Y2 VSS
AN47 VSS BH9 SB_DQS_4 Y20 VSS
Datasheet 141
NOTE: VCC_SM/NC Pins may be left NC in DDR2 designs for ease of routing.
AN5 SB_DQS#_7 C1 VSS_SCB Y21 VCC_AXG
AN6 SB_DQS_7 C11 VSS Y23 VSS
AN7 VSS C12 H_CPURST# Y24 VCC_AXG
AN8 SA_DQ_51 C14 VSS Y25 VSS
AN9 VSS C15 H_A#_4 Y26 VCC_AXG
AP1 SB_DM_6 C17 VSS Y28 VSS
AP16 VCCA_SM C18 H_A#_7 Y29 VCC_NCTF
AP17 VCCA_SM C20 VSS Y3 H_D#_32
AP2 VSS C21 H_A#_27 Y30 VCC_NCTF
AP20 VCCA_SM C23 CFG_9 Y32 VCC_NCTF
AP21 VSS C24 CFG_10 Y33 VCC
AP24 SA_CK_0 C25 CFG_5 Y34 VCC
AP25 VCCA_SM_CK C26 VSS Y35 VSS
AP28 VCCA_SM_CK C28 VSS Y36 PEG_RX#_11
AP29 VCC_SM C29 HDA_SDO Y37 PEG_RX_11
AP3 SB_DQ_54 C3 NC Y38 VSS
AP32 VCC_SM C31 TV_DCONSEL_0 Y39 PEG_TX_10
AP33 VCC_SM C32 VSS Y40 PEG_TX#_10
AP46 SB_DQ_3 C34 GFX_VR_EN Y41 VSS
AP47 SB_DQ_2 C35 VCC_HV Y42 PEG_RX_9
AP48 SB_DQ_7 C37 VSS Y43 PEG_RX#_9
AR1 SB_DQ_55 C38 VSS Y44 VSS
AR13 SB_CS#_1 C40 LVDSA_CLK Y46 PEG_TX_11
AR16 VCCA_SM C41 LVDSA_CLK# Y47 VSS
AR17 VCCA_SM C43 VSS Y48 PEG_RX#_10
AR2 VSS C44 LVDS_IBG Y5 VSS
AR20 VCCA_SM C46 NC Y6 H_D#_34
Y7 H_D#_38
Y8 VSS
Y9 H_D#_41
142 Datasheet
16.3 Standard GMCH Package Information
The GMCH comes in an FCBGA package, which consists of a silicon die mounted face
down on an organic substrate populated with solder balls on the bottom side.
Capacitors may be placed in the area surrounding the die.
Caution: Because the die-side capacitors are electrically conductive, and only slightly shorter
than the die height, care should be taken to avoid contacting the capacitors with
electrically conductive materials. Doing so may short the capacitors and possibly
damage the device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out area,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.
Dimensions are in millimeters. Unless otherwise specified, interpret the dimensions and
tolerances in accordance with ASME Y14.5-1994.
Tolerances:
X: 0.1
XX: 0.05
Angles: 1.0 degrees
Package parameters: 34 mm x 34 mm, 0.7-mm ball pitch
Solder resist opening: 430 microns
Package thickness changed to 2.2730.210 and ball diameter changed to
0.3500.100. These dimensions have been updated in Figure 25.
Note: This change to mechanical specification does not impact any mechanical/ thermal/
manufacture design of the customer.
Datasheet 143
Figure 25. Mobile Intel 4 Series Express Chipset Drawing

144 Datasheet
16.4 Intel GS45 Express Chipset Ballout Diagrams
Figure 26. Ballout Diagram (Top View) Upper Left Quadrant
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
BL
VSS_SCB NC NC NC VSS
SB_DQ_2
4
VSS
SB_DQ_2
6
VSS
SB_MA_1
4
VSS VSS
SM_RCO
MP_VOL
VCC_SM
BK
NC NC VSS
SB_DQ_1
9
SB_DQ_2
2
SB_DQ_2
9
SB_DQS_
3
SB_DQ_3
0
SB_BS_2
SB_MA_1
1
SB_MA_7
SM_RCO
MP_VOH
VCC_SM VCC_SM
BJ
SB_DQS#
_2
SB_DM_2
SB_DQ_2
3
SB_DQ_2
5
SB_DM_3 SA_BS_2
SB_DQ_3
1
SB_MA_8 SA_MA_5 SB_MA_1 VSS VCC_SM
BH
NC
SB_DQ_2
1
SB_DQS_
2
SB_DQ_1
8
SB_DQ_2
8
SB_DQ_2
7
SB_DQS#
_3
SB_MA_9
SB_MA_1
2
SB_MA_5
SA_MA_1
2
SA_MA_7 VCC_SM VCC_SM
BG
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC_SM
BF
SB_DQ_1
6
VCC_SM
_LF
SA_DQ_1
8
SA_DQ_1
9
SA_DQ_1
6
SA_DQ_2
6
SA_DQ_2
4
SA_DQ_2
7
SA_DQ_3
0
SB_MA_4 SB_MA_6 SA_MA_9 VCC_SM VCC_SM
BE
NC
SB_DQ_2
0
SB_DQ_1
7
SA_DQ_2
1
SA_DQ_2
3
SA_DQS_
2
SA_DQ_2
9
SA_DQ_3
1
SA_DM_3
SB_CKE_
0
VCC_SM
SA_CKE_
1
SA_MA_2 VCC_SM
BD
VSS
SB_DQ_1
4
SA_DQ_9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC_SM VCC_SM
BC
SB_DQ_1
5
SB_DQ_1
1
SM_VRE
F
SA_DQ_1
2
SA_DQ_1
7
SA_DQS#
_2
SA_DQ_2
0
SA_DQS_
3
SA_DQ_2
5
SB_CKE_
1
SA_CKE_
0
SB_CK#_
0
SA_MA_3 VCC_SM
BB
SB_DQS#
_1
SB_DQ_1
0
SA_DM_1 VSS SA_DM_2 VSS VSS
SA_DQ_2
8
VCC_SM
_LF
VCC_SM SA_MA_6 SA_CK_0 VCC_SM VCC_SM
BA
VSS
SB_DQS_
1
VSS
SA_DQ_1
1
SA_DQ_1
4
SA_DQS_
1
SA_DQ_2
2
SA_DQS#
_3
VSS
SM_DRA
MRST#
VSS SB_CK_0
SA_CK#_
0
VCC_SM
AY
SB_DM_1 SB_DQ_9
SA_DQ_1
5
VSS VSS VSS VSS PWROK
SM_PWR
OK
VSS VSS VSS VCC_SM
AW
SB_DQ_1
3
SB_DQ_8 VSS
SA_DQ_1
0
SA_DQ_8
SA_DQS#
_1
RSVD
CL_PWR
OK
VSS VSS VCC_SM VCC_SM VCC_SM VSS
AV
SB_DQ_3
SB_DQ_1
2
SA_DQ_6 VSS
SA_DQ_1
3
VSS
AU
VSS SB_DQ_7 VSS SA_DQ_3 SA_DQ_1
VCC_SM
_LF
VSS VSS VSS VSS VSS VSS VSS VSS
VCCA_S
M_CK
VCCA_S
M_CK
VCCA_S
M_CK
AT
SB_DQS#
_0
SB_DQ_6 SA_DM_0 VSS SA_DQ_2
ME_J TAG
_TDO
VCC VCC
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VSS_NCT
F
VCCA_S
M_CK_N
CTF
VCCA_S
M_CK_N
CTF
VCCA_S
M_CK_N
CTF
AR
SB_DQ_2
SB_DQS_
0
VSS
SA_DQS#
_0
SA_DQS_
0
SA_DQ_4 VSS VCC VSS
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VSS_NCT
F
VCCA_S
M_CK_N
CTF
VCCA_S
M_CK_N
CTF
VCCA_S
M_CK_N
CTF
AP
SB_DQ_0 SB_DM_0 SA_DQ_7 VSS SA_DQ_0
ME_J TAG
_TDI
AN
VSS SB_DQ_5 VSS SA_DQ_5
ME_J TAG
_TMS
ME_J TAG
_TCK
VCC_DMI VCC VSS
VCC_NC
TF
VCC_NC
TF
VCC VSS VSS VSS VSS VSS
AM
SB_DQ_4 SB_DQ_1 VSS VSS VSS VCC_DMI VSS VCC
VCC_NC
TF
VCC_NC
TF
VCC VCC VCC VCC VCC VCC
AL
CL_VREF CL_RST# VSS
DMI_RXN
_1
DMI_RXN
_3
DMI_RXP
_3
VCC_DMI VSS VCC
VCC_NC
TF
VCC_NC
TF
VSS VCC VCC VCC VCC VCC
AK
CL_DATA CL_CLK
DMI_RXP
_1
VSS VSS VSS
AJ
VSS VSS VSS
DMI_TXN
_1
DMI_TXN
_2
DMI_TXP
_2
VCCA_P
EG_BG
VCC VCC
VSS_NCT
F
VCC_NC
TF
VCC VCC VCC VCC VSS VCC
AH
DMI_RXN
_2
DMI_RXP
_2
DMI_TXP
_1
VSS VSS VSS VCC VCC
VSS_NCT
F
VCC_NC
TF
VCC VCC VCC VCC
VCC_AX
G
VCC_AX
G
AG
DMI_RXN
_0
DMI_RXP
_0
VSS
DMI_TXN
_0
DMI_TXN
_3
DMI_TXP
_3
VCCA_P
EG_PLL
VSS VCC
VCC_NC
TF
VCC_NC
TF
VSS VCC VSS
VCC_AX
G
VCC_AX
G
VCC_AX
G
Datasheet 145
Figure 27. Ballout Diagram (Top View) Upper Right Quadrant
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VCC_SM
SM_RCO
MP
VCC_SM
_CK
VSS VCC_SM VSS SA_WE# VSS
SB_DQ_3
7
VSS NC NC NC VSS_SCB
BL
SM_RCO
MP#
VCC_SM
_CK
VCC_SM
_CK
SA_CAS#
SA_CS#_
0
SA_CS#_
1
SB_WE# SB_BS_1
SB_DQ_3
2
SB_DQS#
_4
SB_DQ_3
4
NC NC
BK
VCC_SM VSS
VCC_SM
_CK
SA_BS_1
SA_ODT_
1
SA_ODT_
0
SB_MA_0 SB_BS_0
SB_MA_1
3
SB_DQ_3
6
VSS
SB_DQ_3
9
BJ
SA_MA_4 SB_MA_2 SA_RAS#
SM_REX
T
SA_MA_1
3
SB_MA_1
0
SB_CAS# SB_DM_4
SB_DQ_3
3
SB_DQS_
4
SB_DQ_3
5
VSS NC
BH
VCC_SM
SA_MA_1
1
VSS VSS VSS VSS VSS VSS VSS VSS
SA_DQ_4
3
SB_DQ_3
8
SB_DQ_4
0
BG
VSS VCC_SM SA_MA_1 RSVD RSVD
SA_DQ_3
9
SA_DQ_3
5
SA_DQ_4
7
SA_DQ_4
0
SA_DQ_4
2
VSS
SB_DQ_4
1
SB_DQ_4
5
BF
VCC_SM
SA_MA_1
4
SB_CS#_
0
SB_RAS# RSVD
SB_ODT_
1
SA_DQ_3
4
SA_DQ_3
8
SA_DQ_3
3
VCC_SM
_LF
SA_DM_5
SB_DQ_4
4
VSS NC
BE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SA_DQ_4
6
SB_DQ_4
2
SB_DM_5
BD
VCC_SM
SA_CK#_
1
SA_MA_0 SA_BS_0
SB_CS#_
1
SB_ODT_
0
SA_DQ_3
7
SA_DQS_
4
SA_DQ_4
1
SA_DQ_4
5
SA_DQ_4
4
VSS
SB_DQS#
_5
VSS
BC
SA_MA_8
SB_CK#_
1
VSS RSVD RSTIN# VCC_SM
SA_DQ_3
6
SA_DM_4
SA_DQS_
5
VSS
SA_DQ_4
9
SB_DQ_4
6
SB_DQS_
5
BB
VCC_SM SA_CK_1 SB_CK_1
SA_MA_1
0
VCC_SM
_LF
SB_MA_3
SA_DQ_3
2
SA_DQS#
_4
SA_DQS#
_5
SA_DQS#
_6
SA_DQS_
6
VSS
SB_DQ_4
3
SB_DQ_4
8
BA
VCC_SM VSS VSS VSS VSS VSS VSS VSS VSS VSS
SA_DQ_5
1
SB_DQ_4
7
SB_DM_6
AY
VCC_SM
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
SA_DQ_5
3
SA_DQ_5
5
SA_DQ_5
0
VSS
SB_DQS#
_6
VSS
AW
VSS SA_DM_6 VSS
SA_DQ_4
8
SB_DQ_5
3
SB_DQS_
6
AV
VCCA_S
M_CK
VSS
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VCCA_S
M
VSS
SA_DQ_5
4
VCC_SM
_LF
SA_DQ_6
3
VSS
SB_DQ_5
4
SB_DQ_5
0
AU
VCCA_S
M_CK_N
CTF
VSS_NCT
F
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M
VCCA_S
M
SA_DQ_6
1
SA_DQ_5
2
VSS
SA_DQ_5
7
SB_DQ_5
2
SB_DQ_5
1
AT
VCCA_S
M_CK_N
CTF
VSS_NCT
F
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M_NCTF
VCCA_S
M
VCCA_S
M
VSS
SA_DQ_5
6
SA_DM_7
SA_DQ_6
0
VSS
SB_DQ_5
5
VSS
AR
VSS VSS VSS
SA_DQ_5
8
SB_DQ_5
7
SB_DQ_4
9
AP
VSS VSS VSS VSS VSS
VSS_NCT
F
VSS_NCT
F
VSS VSS VSS RSVD
SA_DQS#
_7
SA_DQS_
7
VSS
SB_DQS#
_7
SB_DQ_5
6
AN
VCC VCC VCC
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VSS RSVD VSS
SA_DQ_6
2
SB_DQ_6
1
SB_DQS_
7
AM
VCC VCC VSS
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VSS RSVD
VCC_SM
_LF
SA_DQ_5
9
VSS
SB_DQ_5
8
VSS
AL
VSS RSVD VSS H_D#_56
SB_DQ_6
0
SB_DQ_6
3
AK
VSS VCC
VCC_AX
G
VCC_AX
G
VCC_AX
G
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VSS
HPLL_CL
K#
H_D#_58 H_D#_62 VSS SB_DM_7
SB_DQ_5
9
AJ
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VCCD_H
PLL
HPLL_CL
K
VSS H_D#_59 H_D#_61
SB_DQ_6
2
AH
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G
VSS
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS
VCC_AX
G
VCC_AX
G_SENS
E
VSS H_D#_53 H_D#_54 VSS
H_DINV#
_3
VSS
AG
146 Datasheet
Figure 28. Ballout Diagram (Top View) Lower Right Quadrant
H_D#_60
VCCA_H
PLL
VSS H_D#_57
H_DSTB
N#_3
H_DSTBP
#_3
AF
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G
VSS
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS
VCC_AX
G
VSS_AX
G_SENS
E
H_D#_55 H_D#_63 H_D#_49 VSS H_D#_52
VCCA_M
PLL
AE
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VSS H_D#_42 H_D#_45 VSS H_D#_51 H_D#_48 H_D#_50
AD
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VSS VSS H_D#_32 H_D#_33 H_D#_41 VSS H_D#_40 VSS
AC
VSS H_D#_38 VSS H_D#_36 H_D#_43 H_D#_47
AB
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G
VCC_AX
G
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VSS H_D#_46 H_D#_37
H_DINV#
_2
VSS
H_DSTB
N#_2
H_D#_39
AA
VCC_AX
G
VSS
VCC_AX
G
VSS
VCC_AX
G
VSS_NCT
F
VCC_AX
G_NCTF
VSS
VCC_AX
G
VTTLF H_D#_35 VSS H_D#_44 H_D#_34
H_DSTBP
#_2
Y
VCC_AX
G
VCC_AX
G
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS
VCC_AX
G
VSS H_D#_30 H_D#_17 H_D#_21 VSS H_D#_27 VSS
W
VSS H_D#_28 VSS H_D#_18 H_D#_25 H_D#_19
V
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VSS H_D#_31 H_D#_24 H_D#_29 VSS VSS H_D#_26
U
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G
VCC_AX
G
VTT VTT VTT VTT VTT VTT
T
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G
VSS VTT VTT VTT VTT VTT VTT VTT
R
VSS H_D#_20 VSS H_D#_16 H_D#_23 VTTLF
P
VSS VCC_AXF VSS VSS VSS VSS VSS H_D#_11 H_D#_22
H_DINV#
_1
VSS
H_DSTB
N#_1
VSS
N
VSS VCC_AXF VCC_AXF VSS VSS VSS VSS VSS H_D#_9 VSS H_D#_10 H_D#_14
H_DSTBP
#_1
M
CFG_5 CFG_4 CFG_17 H_A#_25 H_A#_26 H_AVREF H_A#_3
H_REQ#_
1
H_D#_2
H_DINV#
_0
H_D#_12 VSS
H_DSTBP
#_0
H_D#_8
L
CFG_0 CFG_15 H_A#_29 H_A#_31
H_DVRE
F
H_A#_14 VTTLF H_D#_7 H_D#_6 VSS H_D#_13 H_D#_15
H_DSTB
N#_0
K
TVA_DAC CFG_3 CFG_9 H_A#_20 H_A#_19 H_A#_24 H_A#_10
H_REQ#_
0
H_CPUR
ST#
RSVD H_D#_0 VSS H_D#_3 VSS
J
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS H_D#_1 H_D#_4
H_DRDY
#
H
TVC_DA
C
CFG_2 CFG_1 H_A#_27 H_A#_23 H_A#_8
H_REQ#_
4
H_REQ#_
3
H_DPWR
#
H_CPUSL
P#
H_RS#_2 VSS H_D#_5 NC
G
TVA_RTN CFG_6 H_A#_33 H_A#_32 H_A#_30 H_A#_15 H_A#_7 RSVD H_ADS# H_HITM#
PM_DPR
STP#
H_RS#_0 H_RS#_1
F
TVB_DAC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H_DEFE
R#
VSS
E
CFG_8 CFG_7 H_A#_22 H_A#_28 H_A#_18 H_A#_11 H_A#_13 H_A#_6 TSATN# H_TRDY# H_DBSY#
H_RCOM
P
VSS_SCB
D
RSVD CFG_16 CFG_12 H_A#_17
H_ADSTB
#_1
H_A#_12 H_A#_5
H_REQ#_
2
H_BREQ
#
H_BNR# H_HIT# VSS
C
CFG_10 CFG_13 CFG_14 H_A#_34 H_A#_21 H_A#_16 H_A#_4 H_A#_9 VSS H_BPRI#
H_SWIN
G
VSS_SCB
B
HDA_SD
O
VSS CFG_11 VSS H_A#_35 VSS
H_ADSTB
#_0
VSS H_LOCK# VSS NC VSS_SCB
A
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Datasheet 147
Figure 29. Ballout Diagram (Top View) Lower Left Quadrant
AF
PEG_RX#
_15
PEG_RX_
15
DMI_TXP
_0
VSS
PEG_TX#
_14
VSS
AE
VSS VSS VSS
PEG_RX#
_14
PEG_TX_
14
VSS
VCCD_P
EG_PLL
VSS VCC
VCC_NC
TF
VCC_NC
TF
VSS VCC VCC
VCC_AX
G
VCC_AX
G
VCC_AX
G
AD
PEG_TX#
_15
PEG_TX_
15
PEG_RX_
14
VSS
PEG_RX#
_12
VSS VCC VCC
VSS_NCT
F
VCC_NC
TF
VCC VCC VCC
VCC_AX
G
VCC_AX
G
VSS
AC
PEG_RX#
_13
PEG_RX_
13
VSS
PEG_TX#
_13
PEG_RX_
12
VSS
VCC_PE
G
VCC VCC
VSS_NCT
F
VCC_NC
TF
VCC VCC VSS
VCC_AX
G
VCC_AX
G
VSS
AB
PEG_RX#
_11
PEG_RX_
11
PEG_TX_
13
VSS
PEG_TX#
_10
VCC_PE
G
AA
VSS VSS VSS
PEG_RX_
8
PEG_TX_
10
VSS
VCC_PE
G
VSS VCC
VCC_NC
TF
VCC_NC
TF
VSS VCC VCC
VCC_AX
G
VCC_AX
G
VCC_AX
G
Y
PEG_TX#
_12
PEG_TX_
12
PEG_RX#
_8
VSS
PEG_TX#
_9
VCC_PE
G
VCC VCC
VCC_NC
TF
VCC_NC
TF
VSS VCC VSS
VCC_AX
G
VCC_AX
G
VSS
W
PEG_TX_
11
PEG_TX#
_11
VSS
PEG_RX#
_10
PEG_TX_
9
VSS VSS VCC VSS
VCC_NC
TF
VCC_NC
TF
VCC VCC
VCC_AX
G
VCC_AX
G
VCC_AX
G
VSS
V
PEG_RX_
9
PEG_RX#
_9
PEG_RX_
10
VSS
PEG_RX#
_7
VSSA_LV
DS
U
VSS VSS VSS
PEG_TX#
_7
PEG_RX_
7
PEG_CO
MPI
VCCA_LV
DS
VCCA_LV
DS
VSS
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VCC_NC
TF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
T
PEG_TX#
_8
PEG_TX_
8
PEG_TX_
7
VSS
PEG_TX#
_5
PEG_CO
MPO
VCC_TX_
LVDS
VSS
VCC_NC
TF
VCC_NC
TF
VSS_NCT
F
VCC_NC
TF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
R
PEG_TX_
6
PEG_TX#
_6
VSS PEG_CLK
PEG_TX_
5
VSS VSS VSS VSS
VCC_NC
TF
VCC_NC
TF
VSS_NCT
F
VCC_NC
TF
VSS_NCT
F
VCC_AX
G_NCTF
VCC_AX
G_NCTF
VSS_NCT
F
P
PEG_RX#
_6
PEG_RX_
6
PEG_CLK
#
VSS
PEG_TX#
_2
LVDS_VR
EFH
N
VSS VSS VSS
PEG_RX#
_5
PEG_TX_
2
VSS VSS VSS VSS VCC
VCCD_Q
DAC
VCCD_T
VDAC
VSS VSS
M
PEG_RX_
4
PEG_RX#
_4
PEG_RX_
5
VSS
VCCD_LV
DS
VSS VSS VSS VSS VSS
VSSA_DA
C_BG
VSS VSS
L
PEG_TX#
_4
PEG_TX_
4
VSS
VCCA_D
PLLB
PEG_TX#
_0
VCCD_LV
DS
RSVD RSVD
PM_EXT_
TS#_1
L_CTRL_
DATA
L_DDC_D
ATA
CFG_18
VCCA_D
AC_BG
VSS
K
PEG_RX#
_2
VSS VSS VSS
LVDS_VR
EFL
VSS
ICH_SYN
C#
VSS
L_CTRL_
CLK
DPRSLP
VR
CFG_20 CFG_19
VCCA_TV
_DAC
THERMT
RIP#
J
PEG_RX_
2
VSS VSS
PEG_RX_
3
PEG_TX_
0
VCCA_D
PLLA
RSVD RSVD
PM_EXT_
TS#_0
L_DDC_C
LK
PM_SYN
C#
CRT_HS
YNC
VCCA_C
RT_DAC
CRT_BLU
E
H
PEG_TX#
_3
PEG_TX_
3
PEG_RX#
_3
VSS
LVDS_VB
G
VSS VSS VSS VSS VSS VSS VSS VSS VSS
G
NC VSS VSS
PEG_RX#
_1
LVDSA_D
ATA_1
LVDSA_D
ATA#_0
LVDSB_D
ATA_2
LVDSA_D
ATA#_2
GFX_VR_
EN
GFX_VID
_1
GFX_VID
_4
GFX_VID
_0
CRT_VSY
NC
CRT_GR
EEN
F
PEG_TX_
1
PEG_TX#
_1
LVDS_IB
G
PEG_RX_
1
LVDSA_D
ATA#_1
LVDSA_D
ATA_0
LVDSB_D
ATA#_2
LVDSA_D
ATA_2
GFX_VID
_2
GFX_VID
_3
DDPC_C
TRLCLK
DDPC_C
TRLDATA
CRT_RE
D
VSS
E
VSS
PEG_RX_
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CRT_IRT
N
D
NC
PEG_RX#
_0
DPLL_RE
F_SSCLK
#
LVDSB_D
ATA#_3
LVDSA_C
LK#
LVDSB_C
LK#
DPLL_RE
F_CLK#
LVDSB_D
ATA_0
L_BKLT_
CTRL
CRT_DD
C_CLK
TV_DCO
NSEL_1
CRT_TV
O_IREF
RSVD HDA_SDI
C
VSS VSS VSS
LVDSA_D
ATA#_3
VSS
LVDSB_D
ATA_1
VSS
L_BKLT_
EN
CRT_DD
C_DATA
VCC_HV
CLKREQ
#
HDA_BCL
K
B
VSS_SCB NC
DPLL_RE
F_SSCLK
LVDSB_D
ATA_3
LVDSA_C
LK
LVDSB_C
LK
DPLL_RE
F_CLK
LVDSB_D
ATA#_0
SDVO_C
TRLCLK
L_VDD_E
N
TV_DCO
NSEL_0
VSS
HDA_RS
T#
HDA_SY
NC
A
VSS_SCB NC NC NC VSS
LVDSA_D
ATA_3
VSS
LVDSB_D
ATA#_1
VSS
SDVO_C
TRLDATA
VSS VCC_HV
VCC_HD
A
VSS
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
148 Datasheet
16.5 Intel GS45 Express Chipset Package Information
The Intel GS45 Express Chipset (SFF GMCH) comes in an FCBGA package, which
consists of a silicon die mounted face down on an organic substrate populated with
solder balls on the bottom side. Capacitors may be placed in the area surrounding the
die.
Caution: Because the die-side capacitors are electrically conductive, and only slightly shorter
than the die height, care should be taken to avoid contacting the capacitors with
electrically conductive materials. Doing so may short the capacitors and possibly
damage the device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out area,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.
Dimensions are in millimeters. Unless otherwise specified, interpret the dimensions and
tolerances in accordance with ASME Y14.5-1994.
Tolerances:
X: 0.1
XX: 0.05
Angles: 1.0 degrees
Package parameters: 1363 FCBGA, 27 mm x 25 mm, 0.593-mm minimum ball
pitch
Solder resist opening: 335 microns
Outgoing coplanarity (max): 0.2 mm (8 mils)
Datasheet 149
Figure 30. Intel GS45 Express Chipset Drawing
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150 Datasheet
Table 34. Intel GS45 Chipset Pinlist (Sheet 1 of 13)
A11 H_LOCK# AT46 SA_DQ_2 D14 H_A#_13
A13 VSS AT48 VSS D16 H_A#_11
A15 H_ADSTB#_0 AT50 SA_DM_0 D18 H_A#_18
A17 VSS AT52 SB_DQ_6 D20 H_A#_28
A19 H_A#_35 AT54 SB_DQS#_0 D22 H_A#_22
A21 VSS AT6 SA_DQ_57 D24 CFG_7
A23 CFG_11 AT8 VSS D26 CFG_8
A25 VSS AU1 SB_DQ_50 D28 HDA_SDI
A27 HDA_SDO AU11 SA_DQ_54 D30 RSVD
A29 VSS AU13 VSS D32 CRT_TVO_IREF
A31 VCC_HDA AU15 VCCA_SM D34 TV_DCONSEL_1
A33 VCC_HV AU16 VCCA_SM D36 CRT_DDC_CLK
A35 VSS AU18 VCCA_SM D38 L_BKLT_CTRL
A37 SDVO_CTRLDATA AU19 VCCA_SM D4 H_RCOMP
A39 VSS AU21 VCCA_SM D40 LVDSB_DATA_0
A4 VSS_SCB AU22 VCCA_SM D42 DPLL_REF_CLK#
A41 LVDSB_DATA#_1 AU24 VCCA_SM D44 LVDSB_CLK#
A43 VSS AU25 VSS D46 LVDSA_CLK#
A45 LVDSA_DATA_3 AU27 VCCA_SM_CK D48 LVDSB_DATA#_3
A47 VSS AU28 VCCA_SM_CK D50 DPLL_REF_SSCLK#
A49 NC AU29 VCCA_SM_CK D52 PEG_RX#_0
A52 NC AU3 SB_DQ_54 D55 NC
A54 NC AU31 VCCA_SM_CK D6 H_DBSY#
A55 VSS_SCB AU32 VSS D8 H_TRDY#
A7 NC AU34 VSS E11 VSS
A9 VSS AU35 VSS E13 VSS
AA1 H_D#_39 AU37 VSS E15 VSS
AA11 H_D#_46 AU38 VSS E17 VSS
AA13 VSS AU40 VSS E19 VSS
AA15 VCC_AXG AU41 VSS E21 VSS
AA18 VCC_AXG_NCTF AU45 VCC_SM_LF E25 VSS
AA19 VSS_NCTF AU47 SA_DQ_1 E27 TVB_DAC
AA21 VCC_AXG AU49 SA_DQ_3 E29 CRT_IRTN
AA25 VSS AU53 SB_DQ_7 E33 VSS
Datasheet 151
AA28 VCC_AXG AU7 SA_DQ_63 E37 VSS
AA29 VCC_AXG AU9 VCC_SM_LF E39 VSS
AA3 H_DSTBN#_2 AV10 SA_DM_6 E41 VSS
AA31 VCC_AXG AV12 VSS E43 VSS
AA32 VCC AV2 SB_DQS_6 E45 VSS
AA34 VCC AV4 SB_DQ_53 E47 VSS
AA35 VSS AV44 VSS E49 VSS
AA37 VCC_NCTF AV46 SA_DQ_13 E5 H_DEFER#
AA38 VCC_NCTF AV48 VSS E51 PEG_RX_0
AA40 VCC AV50 SA_DQ_6 E53 VSS
AA41 VSS AV52 SB_DQ_12 E7 VSS
AA43 VCC_PEG AV54 SB_DQ_3 E9 VSS
AA45 VSS AV6 SA_DQ_48 F10 H_ADS#
AA47 PEG_TX_10 AV8 VSS F12 RSVD
AA49 PEG_RX_8 AW1 VSS F14 H_A#_7
AA5 VSS AW11 SA_DQ_53 F16 H_A#_15
AA51 VSS AW14 VCCA_SM F18 H_A#_30
AA53 VSS AW16 VCCA_SM F2 H_RS#_1
AA55 VSS AW18 VCCA_SM F20 H_A#_32
AA7 H_DINV#_2 AW20 VCCA_SM F22 H_A#_33
AA9 H_D#_37 AW22 VCCA_SM F24 CFG_6
AB10 H_D#_38 AW24 VCCA_SM F26 TVA_RTN
AB12 VSS AW26 VCC_SM F28 VSS
AB2 H_D#_47 AW28 VSS F30 CRT_RED
AB4 H_D#_43 AW3 SB_DQS#_6 F32 DDPC_CTRLDATA
AB44 VCC_PEG AW30 VCC_SM F34 DDPC_CTRLCLK
AB46 PEG_TX#_10 AW32 VCC_SM F36 GFX_VID_3
AB48 VSS AW34 VCC_SM F38 GFX_VID_2
AB50 PEG_TX_13 AW36 VSS F4 H_RS#_0
AB52 PEG_RX_11 AW38 VSS F40 LVDSA_DATA_2
AB54 PEG_RX#_11 AW40 CL_PWROK F42 LVDSB_DATA#_2
AB6 H_D#_36 AW42 RSVD F44 LVDSA_DATA_0
AB8 VSS AW45 SA_DQS#_1 F46 LVDSA_DATA#_1
AC1 VSS AW47 SA_DQ_8 F48 PEG_RX_1
AC11 H_D#_32 AW49 SA_DQ_10 F50 LVDS_IBG
AC13 VSS AW5 VSS F52 PEG_TX#_1
AC15 VSS AW51 VSS F54 PEG_TX_1
152 Datasheet
AC16 VCC_AXG AW53 SB_DQ_8 F6 PM_DPRSTP#
AC18 VCC_AXG_NCTF AW55 SB_DQ_13 F8 H_HITM#
AC19 VCC_AXG_NCTF AW7 SA_DQ_50 G1 NC
AC21 VCC_AXG AW9 SA_DQ_55 G11 H_DPWR#
AC22 VCC_AXG AY10 VSS G13 H_REQ#_3
AC24 VCC_AXG AY13 VSS G15 H_REQ#_4
AC25 VCC_AXG AY15 VSS G17 H_A#_8
AC27 VCC_AXG AY17 VSS G19 H_A#_23
AC28 VSS AY19 VSS G21 H_A#_27
AC29 VCC_AXG AY2 SB_DM_6 G23 CFG_1
AC3 H_D#_40 AY21 VSS G25 CFG_2
AC31 VCC_AXG AY23 VSS G27 TVC_DAC
AC32 VSS AY25 VSS G29 CRT_GREEN
AC34 VCC AY27 VCC_SM G3 H_D#_5
AC35 VCC AY29 VCC_SM G31 CRT_VSYNC
AC37 VCC_NCTF AY31 VSS G33 GFX_VID_0
AC38 VSS_NCTF AY33 VSS G35 GFX_VID_4
AC40 VCC AY35 VSS G37 GFX_VID_1
AC41 VCC AY37 SM_PWROK G39 GFX_VR_EN
AC43 VCC_PEG AY39 PWROK G41 LVDSA_DATA#_2
AC45 VSS AY4 SB_DQ_47 G43 LVDSB_DATA_2
AC47 PEG_RX_12 AY41 VSS G45 LVDSA_DATA#_0
AC49 PEG_TX#_13 AY43 VSS G47 LVDSA_DATA_1
AC5 VSS AY46 VSS G49 PEG_RX#_1
AC51 VSS AY48 VSS G5 VSS
AC53 PEG_RX_13 AY50 SA_DQ_15 G51 VSS
AC55 PEG_RX#_13 AY52 SB_DQ_9 G53 VSS
AC7 H_D#_41 AY54 SB_DM_1 G55 NC
AC9 H_D#_33 AY6 SA_DQ_51 G7 H_RS#_2
AD10 H_D#_45 AY8 VSS G9 H_CPUSLP#
AD12 H_D#_42 B10 VSS H10 VSS
AD15 VSS B12 H_A#_9 H12 VSS
AD16 VCC_AXG B14 H_A#_4 H14 VSS
AD18 VCC_AXG_NCTF B16 H_A#_16 H16 VSS
AD19 VCC_AXG_NCTF B18 H_A#_21 H18 VSS
AD2 H_D#_50 B2 VSS_SCB H2 H_DRDY#
AD21 VCC_AXG B20 H_A#_34 H20 VSS
AD22 VCC_AXG B22 CFG_14 H22 VSS
Datasheet 153
AD27 VCC_AXG B28 HDA_SYNC H28 VSS
AD28 VSS B30 HDA_RST# H30 VSS
AD29 VCC_AXG B32 VSS H32 VSS
AD31 VCC_AXG B34 TV_DCONSEL_0 H34 VSS
AD32 VCC B36 L_VDD_EN H36 VSS
AD34 VCC B38 SDVO_CTRLCLK H38 VSS
AD35 VCC B40 LVDSB_DATA#_0 H4 H_D#_4
AD37 VCC_NCTF B42 DPLL_REF_CLK H40 VSS
AD38 VSS_NCTF B44 LVDSB_CLK H42 VSS
AD4 H_D#_48 B46 LVDSA_CLK H44 VSS
AD40 VCC B48 LVDSB_DATA_3 H46 LVDS_VBG
AD41 VCC B50 DPLL_REF_SSCLK H48 VSS
AD44 VSS B54 NC H50 PEG_RX#_3
AD46 PEG_RX#_12 B55 VSS_SCB H52 PEG_TX_3
AD48 VSS B6 H_SWING H54 PEG_TX#_3
AD50 PEG_RX_14 B8 H_BPRI# H6 H_D#_1
AD52 PEG_TX_15 BA1 SB_DQ_48 H8 VSS
AD54 PEG_TX#_15 BA11 SA_DQS#_5 J1 VSS
AD6 H_D#_51 BA13 SA_DQS#_4 J11 H_CPURST#
AD8 VSS BA15 SA_DQ_32 J13 H_REQ#_0
AE1 VCCA_MPLL BA17 SB_MA_3 J15 H_A#_10
AE11 H_D#_55 BA19 VCC_SM_LF J17 H_A#_24
AE13 VSS_AXG_SENSE BA21 SA_MA_10 J19 H_A#_19
AE15 VCC_AXG BA23 SB_CK_1 J21 H_A#_20
AE16 VSS BA25 SA_CK_1 J23 CFG_9
AE18 VCC_AXG_NCTF BA27 VCC_SM J25 CFG_3
AE19 VCC_AXG_NCTF BA29 VCC_SM J27 TVA_DAC
AE21 VSS BA3 SB_DQ_43 J29 CRT_BLUE
AE22 VCC_AXG BA31 SA_CK#_0 J3 H_D#_3
AE24 VCC_AXG BA33 SB_CK_0 J31 VCCA_CRT_DAC
AE25 VSS BA35 VSS J33 CRT_HSYNC
AE27 VCC_AXG BA37 SM_DRAMRST# J35 PM_SYNC#
AE28 VCC_AXG BA39 VSS J37 L_DDC_CLK
AE29 VCC_AXG BA41 SA_DQS#_3 J39 PM_EXT_TS#_0
AE3 H_D#_52 BA43 SA_DQ_22 J41 RSVD
AE31 VCC_AXG BA45 SA_DQS_1 J43 RSVD
154 Datasheet
AE32 VCC BA47 SA_DQ_14 J45 VCCA_DPLLA
AE34 VCC BA49 SA_DQ_11 J47 PEG_TX_0
AE35 VSS BA5 VSS J49 PEG_RX_3
AE37 VCC_NCTF BA51 VSS J5 VSS
AE38 VCC_NCTF BA53 SB_DQS_1 J51 VSS
AE40 VCC BA55 VSS J53 VSS
AE41 VSS BA7 SA_DQS_6 J55 PEG_RX_2
AE43 VCCD_PEG_PLL BA9 SA_DQS#_6 J7 H_D#_0
AE45 VSS BB10 SA_DQS_5 J9 RSVD
AE47 PEG_TX_14 BB12 SA_DM_4 K10 H_D#_6
AE49 PEG_RX#_14 BB14 SA_DQ_36 K12 H_D#_7
AE5 VSS BB16 VCC_SM K14 VTTLF
AE51 VSS BB18 RSTIN# K16 H_A#_14
AE53 VSS BB2 SB_DQS_5 K18 H_DVREF
AE55 VSS BB20 RSVD K2 H_DSTBN#_0
AE7 H_D#_49 BB22 VSS K20 H_A#_31
AE9 H_D#_63 BB24 SB_CK#_1 K22 H_A#_29
AF10 VCCA_HPLL BB26 SA_MA_8 K24 CFG_15
AF12 H_D#_60 BB28 VCC_SM K26 CFG_0
AF2 H_DSTBP#_3 BB30 VCC_SM K28 THERMTRIP#
AF4 H_DSTBN#_3 BB32 SA_CK_0 K30 VCCA_TV_DAC
AF44 VSS BB34 SA_MA_6 K32 CFG_19
AF46 PEG_TX#_14 BB36 VCC_SM K34 CFG_20
AF48 VSS BB38 VCC_SM_LF K36 DPRSLPVR
AF50 DMI_TXP_0 BB4 SB_DQ_46 K38 L_CTRL_CLK
AF52 PEG_RX_15 BB40 SA_DQ_28 K4 H_D#_15
AF54 PEG_RX#_15 BB42 VSS K40 VSS
AF6 H_D#_57 BB44 VSS K42 ICH_SYNC#
AF8 VSS BB46 SA_DM_2 K44 VSS
AG1 VSS BB48 VSS K46 LVDS_VREFL
AG11 VSS BB50 SA_DM_1 K48 VSS
AG13 VCC_AXG_SENSE BB52 SB_DQ_10 K50 VSS
AG15 VCC_AXG BB54 SB_DQS#_1 K52 VSS
AG16 VSS BB6 SA_DQ_49 K54 PEG_RX#_2
AG18 VCC_AXG_NCTF BB8 VSS K6 H_D#_13
AG19 VCC_AXG_NCTF BC1 VSS K8 VSS
AG21 VSS BC11 SA_DQ_41 L1 H_D#_8
AG22 VCC_AXG BC13 SA_DQS_4 L11 H_D#_2
Datasheet 155
AG24 VCC_AXG BC15 SA_DQ_37 L13 H_REQ#_1
AG25 VSS BC17 SB_ODT_0 L15 H_A#_3
AG27 VCC_AXG BC19 SB_CS#_1 L17 H_AVREF
AG28 VCC_AXG BC21 SA_BS_0 L19 H_A#_26
AG29 VCC_AXG BC23 SA_MA_0 L21 H_A#_25
AG3 H_DINV#_3 BC25 SA_CK#_1 L23 CFG_17
AG31 VCC_AXG BC27 VCC_SM L25 CFG_4
AG32 VSS BC29 VCC_SM L27 CFG_5
AG34 VCC BC3 SB_DQS#_5 L29 VSS
AG35 VSS BC31 SA_MA_3 L3 H_DSTBP#_0
AG37 VCC_NCTF BC33 SB_CK#_0 L31 VCCA_DAC_BG
AG38 VCC_NCTF BC35 SA_CKE_0 L33 CFG_18
AG40 VCC BC37 SB_CKE_1 L35 L_DDC_DATA
AG41 VSS BC39 SA_DQ_25 L37 L_CTRL_DATA
AG43 VCCA_PEG_PLL BC41 SA_DQS_3 L39 PM_EXT_TS#_1
AG45 DMI_TXP_3 BC43 SA_DQ_20 L41 RSVD
AG47 DMI_TXN_3 BC45 SA_DQS#_2 L43 RSVD
AG49 DMI_TXN_0 BC47 SA_DQ_17 L45 VCCD_LVDS
AG5 VSS BC49 SA_DQ_12 L47 PEG_TX#_0
AG51 VSS BC5 VSS L49 VCCA_DPLLB
AG53 DMI_RXP_0 BC51 SM_VREF L5 VSS
AG55 DMI_RXN_0 BC53 SB_DQ_11 L51 VSS
AG7 H_D#_54 BC55 SB_DQ_15 L53 PEG_TX_4
AG9 H_D#_53 BC7 SA_DQ_44 L55 PEG_TX#_4
AH10 HPLL_CLK BC9 SA_DQ_45 L7 H_D#_12
AH12 VCCD_HPLL BD10 VSS L9 H_DINV#_0
AH15 VCC_AXG BD12 VSS M10 H_D#_9
AH16 VCC_AXG BD14 VSS M13 VSS
AH18 VCC_AXG_NCTF BD16 VSS M15 VSS
AH19 VCC_AXG_NCTF BD18 VSS M17 VSS
AH2 SB_DQ_62 BD2 SB_DM_5 M19 VSS
AH21 VCC_AXG BD20 VSS M2 H_DSTBP#_1
AH24 VCC_AXG BD24 VSS M23 VCC_AXF
AH25 VCC_AXG BD26 VSS M25 VCC_AXF
AH27 VCC_AXG BD28 VCC_SM M27 VSS
AH28 VCC_AXG BD30 VCC_SM M29 VSS
156 Datasheet
AH31 VCC BD34 VSS M33 VSSA_DAC_BG
AH32 VCC BD36 VSS M35 VSS
AH35 VCC BD4 SB_DQ_42 M39 VSS
AH37 VCC_NCTF BD40 VSS M4 H_D#_14
AH38 VSS_NCTF BD42 VSS M41 VSS
AH4 H_D#_61 BD44 VSS M43 VSS
AH40 VCC BD46 VSS M46 VCCD_LVDS
AH44 VSS BD50 SA_DQ_9 M50 PEG_RX_5
AH46 VSS BD52 SB_DQ_14 M52 PEG_RX#_4
AH48 VSS BD54 VSS M54 PEG_RX_4
AH50 DMI_TXP_1 BD6 SA_DQ_46 M6 H_D#_10
AH52 DMI_RXP_2 BD8 VSS M8 VSS
AH54 DMI_RXN_2 BE1 NC N1 VSS
AH6 H_D#_59 BE11 SA_DQ_33 N11 H_D#_11
AH8 VSS BE13 SA_DQ_38 N14 VSS
AJ1 SB_DQ_59 BE15 SA_DQ_34 N16 VSS
AJ11 HPLL_CLK# BE17 SB_ODT_1 N18 VSS
AJ13 VSS BE19 RSVD N20 VSS
AJ15 VCC_AXG BE21 SB_RAS# N22 VSS
AJ16 VCC_AXG BE23 SB_CS#_0 N24 VCC_AXF
AJ18 VCC_AXG_NCTF BE25 SA_MA_14 N26 VSS
AJ19 VSS_NCTF BE27 VCC_SM N28 VSS
AJ21 VCC_AXG BE29 VCC_SM N3 H_DSTBN#_1
AJ22 VCC_AXG BE3 VSS N30 VSS
AJ24 VCC_AXG BE31 SA_MA_2 N32 VCCD_TVDAC
AJ25 VCC BE33 SA_CKE_1 N34 VCCD_QDAC
AJ27 VSS BE35 VCC_SM N36 VCC
AJ28 VCC BE37 SB_CKE_0 N38 VSS
AJ29 VSS BE39 SA_DM_3 N40 VSS
AJ3 SB_DM_7 BE41 SA_DQ_31 N42 VSS
AJ31 VCC BE43 SA_DQ_29 N45 VSS
AJ32 VCC BE45 SA_DQS_2 N47 PEG_TX_2
AJ34 VCC BE47 SA_DQ_23 N49 PEG_RX#_5
AJ35 VCC BE49 SA_DQ_21 N5 VSS
AJ37 VCC_NCTF BE5 SB_DQ_44 N51 VSS
AJ38 VSS_NCTF BE51 SB_DQ_17 N53 VSS
Datasheet 157
AJ40 VCC BE53 SB_DQ_20 N55 VSS
AJ41 VCC BE55 NC N7 H_DINV#_1
AJ43 VCCA_PEG_BG BE7 SA_DM_5 N9 H_D#_22
AJ45 DMI_TXP_2 BE9 VCC_SM_LF P10 H_D#_20
AJ47 DMI_TXN_2 BF10 SA_DQ_40 P12 VSS
AJ49 DMI_TXN_1 BF12 SA_DQ_47 P2 VTTLF
AJ5 VSS BF14 SA_DQ_35 P4 H_D#_23
AJ51 VSS BF16 SA_DQ_39 P44 LVDS_VREFH
AJ53 VSS BF18 RSVD P46 PEG_TX#_2
AJ55 VSS BF2 SB_DQ_45 P48 VSS
AJ7 H_D#_62 BF20 RSVD P50 PEG_CLK#
AJ9 H_D#_58 BF22 SA_MA_1 P52 PEG_RX_6
AK10 RSVD BF24 VCC_SM P54 PEG_RX#_6
AK12 VSS BF26 VSS P6 H_D#_16
AK2 SB_DQ_63 BF28 VCC_SM P8 VSS
AK4 SB_DQ_60 BF30 VCC_SM R1 VTT
AK44 VSS BF32 SA_MA_9 R11 VTT
AK46 VSS BF34 SB_MA_6 R13 VTT
AK48 VSS BF36 SB_MA_4 R15 VSS
AK50 DMI_RXP_1 BF38 SA_DQ_30 R16 VCC_AXG
AK52 CL_CLK BF4 SB_DQ_41 R18 VCC_AXG_NCTF
AK54 CL_DATA BF40 SA_DQ_27 R19 VSS_NCTF
AK6 H_D#_56 BF42 SA_DQ_24 R21 VCC_AXG_NCTF
AK8 VSS BF44 SA_DQ_26 R22 VCC_AXG_NCTF
AL1 VSS BF46 SA_DQ_16 R24 VSS_NCTF
AL11 RSVD BF48 SA_DQ_19 R25 VCC_AXG_NCTF
AL13 VSS BF50 SA_DQ_18 R27 VCC_AXG_NCTF
AL15 VCC_AXG BF52 VCC_SM_LF R28 VSS_NCTF
AL16 VCC_AXG BF54 SB_DQ_16 R29 VCC_AXG_NCTF
AL18 VCC_AXG_NCTF BF6 VSS R3 VTT
AL19 VCC_AXG_NCTF BF8 SA_DQ_42 R31 VCC_AXG_NCTF
AL21 VCC_AXG BG11 VSS R32 VSS_NCTF
AL22 VCC_AXG BG13 VSS R34 VCC_NCTF
AL24 VSS BG15 VSS R35 VSS_NCTF
AL25 VCC BG17 VSS R37 VCC_NCTF
AL27 VCC BG19 VSS R38 VCC_NCTF
AL28 VCC BG21 VSS R40 VSS
AL29 VCC BG23 VSS R41 VSS
158 Datasheet
AL3 SB_DQ_58 BG25 SA_MA_11 R43 VSS
AL31 VCC BG27 VCC_SM R45 VSS
AL32 VCC BG29 VCC_SM R47 PEG_TX_5
AL34 VCC BG3 SB_DQ_40 R49 PEG_CLK
AL35 VSS BG31 VSS R5 VTT
AL37 VCC_NCTF BG33 VSS R51 VSS
AL38 VCC_NCTF BG35 VSS R53 PEG_TX#_6
AL40 VCC BG37 VSS R55 PEG_TX_6
AL41 VSS BG39 VSS R7 VTT
AL43 VCC_DMI BG41 VSS R9 VTT
AL45 DMI_RXP_3 BG43 VSS T10 VTT
AL47 DMI_RXN_3 BG45 VSS T12 VTT
AL49 DMI_RXN_1 BG47 VSS T15 VCC_AXG
AL5 VSS BG49 VSS T16 VCC_AXG
AL51 VSS BG5 SB_DQ_38 T18 VCC_AXG_NCTF
AL53 CL_RST# BG51 VSS T19 VSS_NCTF
AL55 CL_VREF BG53 VSS T2 VTT
AL7 SA_DQ_59 BG7 SA_DQ_43 T21 VCC_AXG_NCTF
AL9 VCC_SM_LF BG9 VSS T22 VCC_AXG_NCTF
AM10 RSVD BH1 NC T24 VSS_NCTF
AM12 VSS BH10 SB_DQ_33 T25 VCC_AXG_NCTF
AM15 VCC_AXG BH12 SB_DM_4 T27 VCC_AXG_NCTF
AM16 VCC_AXG BH14 SB_CAS# T28 VSS_NCTF
AM18 VCC_AXG_NCTF BH16 SB_MA_10 T29 VCC_AXG_NCTF
AM19 VCC_AXG_NCTF BH18 SA_MA_13 T31 VCC_AXG_NCTF
AM2 SB_DQS_7 BH20 SM_REXT T32 VCC_AXG_NCTF
AM21 VCC_AXG BH22 SA_RAS# T34 VCC_NCTF
AM22 VCC_AXG BH24 SB_MA_2 T35 VSS_NCTF
AM24 VCC BH26 SA_MA_4 T37 VCC_NCTF
AM25 VCC BH28 VCC_SM T38 VCC_NCTF
AM27 VCC BH30 VCC_SM T4 VTT
AM28 VCC BH32 SA_MA_7 T40 VSS
AM29 VCC BH34 SA_MA_12 T41 VCC_TX_LVDS
AM31 VCC BH36 SB_MA_5 T44 PEG_COMPO
AM32 VCC BH38 SB_MA_12 T46 PEG_TX#_5
AM34 VCC BH4 VSS T48 VSS
AM35 VCC BH40 SB_MA_9 T50 PEG_TX_7
AM37 VCC_NCTF BH42 SB_DQS#_3 T52 PEG_TX_8
Datasheet 159
AM38 VCC_NCTF BH44 SB_DQ_27 T54 PEG_TX#_8
AM4 SB_DQ_61 BH46 SB_DQ_28 T6 VTT
AM40 VCC BH48 SB_DQ_18 T8 VTT
AM41 VSS BH50 SB_DQS_2 U1 H_D#_26
AM44 VCC_DMI BH52 SB_DQ_21 U11 H_D#_31
AM46 VSS BH55 NC U13 VSS
AM48 VSS BH6 SB_DQ_35 U15 VCC_AXG
AM50 VSS BH8 SB_DQS_4 U16 VCC_AXG
AM52 SB_DQ_1 BJ11 SB_MA_13 U18 VCC_AXG_NCTF
AM54 SB_DQ_4 BJ13 SB_BS_0 U19 VCC_AXG_NCTF
AM6 SA_DQ_62 BJ15 SB_MA_0 U21 VCC_AXG_NCTF
AM8 VSS BJ17 SA_ODT_0 U22 VCC_AXG_NCTF
AN1 SB_DQ_56 BJ19 SA_ODT_1 U24 VCC_AXG_NCTF
AN11 RSVD BJ21 SA_BS_1 U25 VCC_AXG_NCTF
AN13 VSS BJ23 VCC_SM_CK U27 VCC_AXG_NCTF
AN15 VSS BJ25 VSS U28 VCC_AXG_NCTF
AN16 VSS BJ27 VCC_SM U29 VCC_AXG_NCTF
AN18 VSS_NCTF BJ29 VCC_SM U3 VSS
AN19 VSS_NCTF BJ31 VSS U31 VCC_AXG_NCTF
AN21 VSS BJ33 SB_MA_1 U32 VSS_NCTF
AN22 VSS BJ35 SA_MA_5 U34 VCC_NCTF
AN24 VSS BJ37 SB_MA_8 U35 VCC_NCTF
AN25 VSS BJ39 SB_DQ_31 U37 VCC_NCTF
AN27 VSS BJ41 SA_BS_2 U38 VCC_NCTF
AN28 VSS BJ43 SB_DM_3 U40 VSS
AN29 VSS BJ45 SB_DQ_25 U41 VCCA_LVDS
AN3 SB_DQS#_7 BJ47 SB_DQ_23 U43 VCCA_LVDS
AN31 VSS BJ49 SB_DM_2 U45 PEG_COMPI
AN32 VSS BJ5 SB_DQ_39 U47 PEG_RX_7
AN34 VSS BJ51 SB_DQS#_2 U49 PEG_TX#_7
AN35 VCC BJ7 VSS U5 VSS
AN37 VCC_NCTF BJ9 SB_DQ_36 U51 VSS
AN38 VCC_NCTF BK1 NC U53 VSS
AN40 VSS BK10 SB_DQ_32 U55 VSS
AN41 VCC BK12 SB_BS_1 U7 H_D#_29
AN43 VCC_DMI BK14 SB_WE# U9 H_D#_24
AN45 ME_JTAG_TCK BK16 SA_CS#_1 V10 H_D#_28
AN47 ME_JTAG_TMS BK18 SA_CS#_0 V12 VSS
160 Datasheet
AN49 SA_DQ_5 BK2 NC V2 H_D#_19
AN5 VSS BK20 SA_CAS# V4 H_D#_25
AN51 VSS BK22 VCC_SM_CK V44 VSSA_LVDS
AN53 SB_DQ_5 BK24 VCC_SM_CK V46 PEG_RX#_7
AN55 VSS BK26 SM_RCOMP# V48 VSS
AN7 SA_DQS_7 BK28 VCC_SM V50 PEG_RX_10
AN9 SA_DQS#_7 BK30 VCC_SM V52 PEG_RX#_9
AP10 VSS BK32 SM_RCOMP_VOH V54 PEG_RX_9
AP12 VSS BK34 SB_MA_7 V6 H_D#_18
AP2 SB_DQ_49 BK36 SB_MA_11 V8 VSS
AP4 SB_DQ_57 BK38 SB_BS_2 W1 VSS
AP44 ME_JTAG_TDI BK40 SB_DQ_30 W11 H_D#_30
AP46 SA_DQ_0 BK42 SB_DQS_3 W13 VSS
AP48 VSS BK44 SB_DQ_29 W15 VCC_AXG
AP50 SA_DQ_7 BK46 SB_DQ_22 W16 VSS
AP52 SB_DM_0 BK48 SB_DQ_19 W18 VCC_AXG_NCTF
AP54 SB_DQ_0 BK50 VSS W19 VCC_AXG_NCTF
AP6 SA_DQ_58 BK54 NC W21 VCC_AXG
AP8 VSS BK55 NC W22 VSS
AR1 VSS BK6 SB_DQ_34 W24 VCC_AXG
AR11 SA_DQ_56 BK8 SB_DQS#_4 W25 VCC_AXG
AR13 VSS BL1 VSS_SCB W27 VCC_AXG
AR15 VCCA_SM BL11 SB_DQ_37 W28 VSS
AR16 VCCA_SM BL13 VSS W29 VCC_AXG
AR18 VCCA_SM_NCTF BL15 SA_WE# W3 H_D#_27
AR19 VCCA_SM_NCTF BL17 VSS W31 VCC_AXG
AR21 VCCA_SM_NCTF BL19 VCC_SM W32 VCC_AXG
AR22 VCCA_SM_NCTF BL2 NC W34 VCC
AR24 VCCA_SM_NCTF BL21 VSS W35 VCC
AR25 VSS_NCTF BL23 VCC_SM_CK W37 VCC_NCTF
AR27
VCCA_SM_CK_NCT
F
BL25 SM_RCOMP W38 VCC_NCTF
AR28
VCCA_SM_CK_NCT
F
BL27 VCC_SM W40 VSS
AR29
VCCA_SM_CK_NCT
F
BL29 VCC_SM W41 VCC
AR3 SB_DQ_55 BL31 SM_RCOMP_VOL W43 VSS
AR31
VCCA_SM_CK_NCT
F
BL33 VSS W45 VSS
Datasheet 161
AR32 VSS_NCTF BL35 VSS W47 PEG_TX_9
AR34 VCC_NCTF BL37 SB_MA_14 W49 PEG_RX#_10
AR35 VCC_NCTF BL39 VSS W5 VSS
AR37 VCC_NCTF BL4 NC W51 VSS
AR38 VCC_NCTF BL41 SB_DQ_26 W53 PEG_TX#_11
AR40 VSS BL43 VSS W55 PEG_TX_11
AR41 VCC BL45 SB_DQ_24 W7 H_D#_21
AR43 VSS BL47 VSS W9 H_D#_17
AR45 SA_DQ_4 BL49 NC Y10 H_D#_35
AR47 SA_DQS_0 BL52 NC Y12 VTTLF
AR49 SA_DQS#_0 BL54 NC Y15 VCC_AXG
AR5 VSS BL55 VSS_SCB Y16 VSS
AR51 VSS BL7 NC Y18 VCC_AXG_NCTF
AR53 SB_DQS_0 BL9 VSS Y19 VSS_NCTF
AR55 SB_DQ_2 C11 H_BREQ# Y2 H_DSTBP#_2
AR7 SA_DQ_60 C13 H_REQ#_2 Y21 VCC_AXG
AR9 SA_DM_7 C15 H_A#_5 Y22 VSS
AT10 SA_DQ_52 C17 H_A#_12 Y24 VCC_AXG
AT12 SA_DQ_61 C19 H_ADSTB#_1 Y25 VSS
AT15 VCCA_SM C21 H_A#_17 Y27 VCC_AXG
AT16 VCCA_SM C23 CFG_12 Y28 VSS
AT18 VCCA_SM_NCTF C25 CFG_16 Y29 VCC_AXG
AT19 VCCA_SM_NCTF C27 RSVD Y31 VCC_AXG
AT2 SB_DQ_51 C29 HDA_BCLK Y32 VSS
AT21 VCCA_SM_NCTF C31 CLKREQ# Y34 VCC
AT22 VCCA_SM_NCTF C33 VCC_HV Y35 VSS
AT24 VCCA_SM_NCTF C35 CRT_DDC_DATA Y37 VCC_NCTF
AT25 VSS_NCTF C37 L_BKLT_EN Y38 VCC_NCTF
AT27
VCCA_SM_CK_NCT
F
C39 VSS Y4 H_D#_34
AT28
VCCA_SM_CK_NCT
F
C41 LVDSB_DATA_1 Y40 VCC
AT29
VCCA_SM_CK_NCT
F
C43 VSS Y41 VCC
AT31
VCCA_SM_CK_NCT
F
C45 LVDSA_DATA#_3 Y44 VCC_PEG
AT32 VSS_NCTF C47 VSS Y46 PEG_TX#_9
AT34 VCC_NCTF C49 VSS Y48 VSS
AT35 VCC_NCTF C5 VSS Y50 PEG_RX#_8
162 Datasheet

AT37 VCC_NCTF C51 VSS Y52 PEG_TX_12
AT38 VCC_NCTF C7 H_HIT# Y54 PEG_TX#_12
AT4 SB_DQ_52 C9 H_BNR# Y6 H_D#_44
AT40 VCC D1 VSS_SCB Y8 VSS
AT41 VCC D10 TSATN#
AT44 ME_JTAG_TDO D12 H_A#_6
Datasheet 163
(G)MCH Register Description
17 (G)MCH Register Description
17.1 Register Terminology
For general terminology, refer to the Terminology Section in volume 1.
Abbreviation Definition
RO
Read Only Bit(s). Writes to these bits have no effect. This may be a status
bit or a static value.
RS/WC
Read Set/Write Clear Bit(s).
The first time the bit is read with an enabled byte, it returns the value 0, but
a side-effect of the read is that the value changes to 1. Any subsequent
reads with enabled bytes return a 1 until a 1 is written to the bit. When the
bit is read, but the byte is not enabled, the state of the bit does not change,
and the value returned is irrelevant, but will match the state of the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the
bit, its value becomes 0, until the next byte-enabled read. When the bit is
written, but the byte is not enabled, there is no effect.
R/W
Read/Write Bit(s). These bits can be read and written by software.
Hardware may only change the state of this bit by reset.
R/WC
Read/Write Clear Bit(s). These bits can be read. Internal events may set
this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and
a write of 0 has no effect.
R/WC/S
Read/Write Clear/Sticky Bit(s). These bits can be read. Internal events
may set this bit. A software write of 1 clears (sets to 0) the corresponding
bit(s) and a write of 0 has no effect. Bits are not cleared by warm reset,
but will be reset with a cold/complete reset (for PCI Express* related bits a
cold reset is Power Good Reset as defined in the PCI Express spec).
R/W/B
Read/Write/Blind Bit(s). These bits can be read and written by software.
Additionally there is a selector bit which, when set, changes what may be
read from these bits. The value written is always stored in a hidden register.
When the selector bit indicates that the written value should not be read,
some other status is read from this bit. When the selector bit indicates that
the written value should be read, the value in the hidden register is read
from this bit.
R/W/K
Read/Write/Key Bit(s). These bits can be read and written by software.
Additionally this bit, when set, prohibits some other bit field(s) from being
writeable (bit fields become Read Only).
R/W/L
Read/Write/Lockable Bit(s). These bits can be read and written by
software. Additionally there is a Key bit (which is marked R/W/K or R/W/L/
K) that, when set, prohibits this bit field from being writeable (bit field
becomes Read Only).
R/W/L/K
Read/Write/Lockable/Key Bit(s). These bits can be read and written by
software. Additionally this bit is a Key bit that, when set, prohibits this bit
field and/or some other specified bit fields from being writeable (bit fields
become Read Only).
R/W/S
Read/Write/Sticky Bit(s). These bits can be read and written by
software. Bits are not cleared by warm reset, but will be reset with a cold/
complete reset (for PCI Express related bits a cold reset is Power Good
Reset as defined in the PCI Express spec).
(G)MCH Register Description
164 Datasheet

R/WSC
Read/Write Self Clear Bit(s). These bits can be read and written by
software. When the bit is 1, hardware may clear the bit to 0 based upon
internal events, possibly sooner than any subsequent software read could
retrieve a 1.
R/WSC/L
Read/Write Self Clear/Lockable Bit(s). These bits can be read and
written by software. When the bit is 1, hardware may clear the bit to 0
based upon internal events, possibly sooner than any subsequent software
read could retrieve a 1. Additionally there is a bit (which is marked R/W/K
or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit
field becomes Read Only).
R/WO
Write Once Bit(s). Once written by software, bits with this attribute
become Read Only. These bits can only be cleared by a Reset.
W
Write Only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Abbreviation Definition
Datasheet 165
(G)MCH Configuration Process and Registers
18 (G)MCH Configuration Process
and Registers
18.1 Platform Configuration Structure
From a configuration standpoint, the DMI is logically PCI Bus 0. As a result, all devices
internal to the (G)MCH and the ICH appear to be on PCI Bus 0. The systems primary
PCI expansion bus is physically attached to the ICH and, from a configuration
perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and
therefore has a programmable PCI bus number. The PCI Express X16 graphics attach
appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a
device resident on PCI Bus 0.
Note: A physical PCI Bus 0 does not exist. DMI and the internal devices in the (G)MCH and
ICH logically constitute PCI Bus 0 to configuration software. This is shown in Figure 1.
The (G)MCH contains the following PCI devices. The Configuration Registers for these
devices are mapped as devices residing on PCI Bus 0.
Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI Bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling control),
configuration for the DMI, and other (G)MCH-specific registers.
Device 1: Host-PCI Express Bridge. Logically, this appears as a virtual PCI-to-PCI
bridge residing on PCI Bus 0 and is compliant with PCI Express Specification, Rev.
1.0. Device 1 contains the standard PCI-to-PCI bridge registers and the standard
PCI Express/PCI configuration registers (including the PCI Express memory address
mapping). It also contains Isochronous and Virtual Channel controls in the PCI
Express extended configuration space.
Device 2: Internal Graphics Control. Logically, this appears as a PCI device
residing on PCI Bus 0. Physically, Device 2 contains the configuration registers for
3D, 2D, and display functions.
Device 3: Internal Embedded Processor. This is the management engine built-in to
Mobile Intel 4 Series Express Chipsets for supporting embedded function beyond
the host system. It will appear on the PCI configuration bus as a new device.
166 Datasheet
18.2 Configuration Mechanisms
The CPU is the originator of configuration cycles so the FSB is the only interface in the
platform where these configuration mechanisms are used. Internal to the (G)MCH
transactions received through both configuration mechanisms are translated to the
same format.
Figure 1. Conceptual Platform PCI Configuration Diagram

CPU
PCI Configuration Window
in I/O Space
Host-PCI Express Bridge
Bus 0
Device 1
Bus 0
Direct Media Interface
Direct Media Interface
DMI PCI
Bridge (P2)
PBus 0
Device 30
Fcn 0
DRAM Controller
Interface Device
Bus 0
fi
Device 0
LPC Device
Bus 0
Device 31
Fcn 0
GMCH
ICH
Internal Graphics
Configuration Registers
Bus0 Device2
Embedded
Processor
Bus 0 Device3
Datasheet 167
Figure 2. Chipset Configuration Paths and Transaction Types

Internal
Registers
M
C
H

B
a
c
k
b
o
n
e
Internal
Config
Bus
Internal
Config
Bus
MCH
ICH
x16
M
a
i
n

M
e
m
o
r
y

S
u
b
s
y
s
t
e
m
CPU
F
S
BPCI Configuration Access Mechanism (using I/O CF8h/CFCh)
PCI Express Enhanced Configuration Access Mechanism
PCI Express Cfg* type TLPs
Internal
Registers
I
C
H

B
a
c
k
b
o
n
e
ICH
Backbone
ICH
Backbone
ICH
x1
D
M
I
x1
x1
x1
PCI Express TLPs
(CfgRd0, CfgWr0,
CfgRd1, CfgWr1)
PCI Bus
Standard PCI protocol
(using appropriate IDSEL & AD lines)
PCI Express TLPs
(CfgRd0, CfgWr0,
CfgRd1, CfgWr1)
168 Datasheet
18.2.1 Standard PCI Configuration Mechanism
A detailed description of the mechanism for translating CPU I/O bus cycles to
configuration cycles is described below.
The PCI specification defines a slot-based configuration space that allows each device
to contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the CPU. Configuration space is supported by a
mapping mechanism implemented within the (G)MCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at
I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
though 0CFFh). To reference a configuration register a DW I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,
the function within the device and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration
cycle. CONFIG_DATA then becomes a window into the 4 bytes of configuration space
specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will
result in the (G)MCH translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
The (G)MCH is responsible for translating and routing the CPUs I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA Registers to internal (G)MCH Configuration
Registers, DMI or PCI Express.
18.2.2 Logical PCI Bus 0 Configuration Mechanism
The (G)MCH decodes the Bus Number (Bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS Register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within
the (G)MCH is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity
within the (G)MCH is hardwired as Device 1 on PCI Bus 0. Device 2 contains the control
registers for the Integrated Graphics Controller. The ICH decodes the Type 0 access and
generates a configuration access to the selected internal device.
18.2.3 Primary PCI and Downstream Configuration Mechanism
If the bus number in the CONFIG_ADDRESS is non-zero, and falls outside the range
claimed by the Host-PCI Express bridge (not between the upper bound of the bridge
devices Subordinate Bus Number Register and the lower bound of the bridge devices
Secondary Bus Number Register), the (G)MCH will generate a Type 1 DMI configuration
Cycle. A [1:0] of the DMI request packet for the Type 1 configuration cycle will be 01.
Bits 31:2 of the CONFIG_ADDRESS Register will be translated to the A [31:2] field of
the DMI request packet of the configuration cycle as shown below. This DMI
configuration cycle will be sent over the DMI.
If the cycle is forwarded to the ICH via the DMI, the ICH compares the non-zero bus
number with the Secondary Bus Number and Subordinate Bus Number Registers of its
PCI-to-PCI bridges to determine if the configuration cycle is meant for Primary PCI, one
of the ICHs devices, the DMI, or a downstream PCI bus.
Datasheet 169
Figure 3. DMI Type 0 Configuration Address Translation
CONFIG_ADDRESS
DMI Type 0 Configuration Address Extension
CONFIG_ADDRESS
DMI Type 1 Configuration Address Extension
18.2.4 PCI Express* Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3-compatible region, which consists of the
first 256 bytes of a logical devices configuration space and a PCI Express extended
region which consists of the remaining configuration space.
The PCI-compatible region can be accessed using either the mechanism defined in the
previous Standard PCI Configuration Mechanism or using the PCI Express Enhanced
Configuration Mechanism described in this section. The extended configuration
registers may only be accessed using the PCI Express Enhanced Configuration
Mechanism. To maintain compatibility with PCI configuration addressing mechanisms,
system software must access the extended configuration space using 32-bit operations
(32-bit aligned) only. These 32-bit operations include byte enables allowing only
appropriate bytes within the dword to be accessed. Locked transactions to the PCI
Express memory mapped configuration address space are not supported. All changes
made using either access mechanism are equivalent.
The PCI Express enhanced configuration mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCIEXBAR, which
defines the base address for the block of addresses below top 4 GB for the
configuration space associated with buses, devices and functions that are potentially a
3
1
2
8
2
7
2
4
2
3
1
6
1
5
1
1
1
0
8 7 2 1 0
1 Reserved 0 0
Device
Number
Function Register Number x x
3
1
2
8
2
7
2
4
2
3
1
6
1
5
1
1
1
0
8 7 2 1 0
Reserved
Device
Number
Function Register Number 0 0
3
1
2
8
2
7
2
4
2
3
1
6
1
5
1
1
1
0
8 7 2 1 0
1 Reserved 0 Bus Number
Device
Number
Function Register Number x x
3
1
2
8
2
7
2
4
2
3
1
6
1
5
1
1
1
0
8 7 2 1 0
Reserved Bus Number
Device
Number
Function Register Number 0 1
170 Datasheet
part of the PCI Express root complex hierarchy. In the PCIEXBAR register there exist
controls to limit the size of this reserved memory mapped space. 256 MB is the amount
of address space required to reserve space for every bus, device, and function that
could possibly exist. Options for 128 MB and 64 MB exist in order to free up those
addresses for other uses. In these cases, the number of buses and all of their
associated devices and functions are limited to 128 or 64 buses, respectively.
The PCI Express configuration transaction header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
As with PCI devices, each device is selected based on decoded address information that
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function and
extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS):
1. Use the PCI-compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing 1 to Bit 0 of the PCIEXBAR register.
2. Use the PCI-compatible configuration mechanism to write an appropriate PCI
Express base address into the PCIEXBAR register.
3. Calculate the host address of the register you wish to set using (PCI Express Base
+ (bus number x 1 MB) + (device number x 32 KB) + (function number x 4 KB) +
(1 B x offset within the function) = host address).
4. Use a memory write or memory read cycle to the calculated host address to write
or read that register.
Figure 4. Memory Map to PCI Express Device Configuration Space

Bus 0
Bus 1
Bus 255
Device 0
Device 1
0
0xFFFFF
0x1FFFFF
0xFFFFFFF
0x7FFF
0xFFFF
0xFFFFF
Located by
PCI Express Base
Address
Device 31
Function 0
Function 1
0xFFF
0x1FFF
0x7FFF
Function 7
PCI Compatible
Conf iguration
Space Header
0x3F
0xFFF
PCI Express
Extended
Conf iguration
Space
PCI Compatible
Conf iguration
Space
0xFF
Datasheet 171
18.3 Routing Configuration Accesses
The (G)MCH supports two PCI related interfaces: DMI and PCI Express Graphics. The
(G)MCH is responsible for routing PCI and PCI Express configuration cycles to the
appropriate device that is an integrated part of the (G)MCH or to one of these two
interfaces. Configuration cycles to the ICH internal devices and Primary PCI (including
downstream devices) are routed to the ICH via DMI. Configuration cycles to both the
PCI Express Graphics PCI-compatibility configuration space and the PCI Express
Graphics extended configuration space are routed to the PCI Express Graphics port
device or associated link.
Figure 5. (G)MCH Configuration Cycle Flowchart
DWI/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
GMCH Generates
Type 1 Access
to PCI Express
MCH allows cycleto
go to DMI resulting
in Master Abort
Bus# > SEC BUS
Bus# SUBBUS
in GMCH Dev 1
Bus# = 0
Device# = 1 &
Dev # 1 Enabled
& Function# = 0
Device# = 0 &
Function# = 0
Device# = 2 &
(Function# = 0 & Dev#
2 Func# 0 Enabled) OR
(Function# = 1 & Dev#
2 Funcs# 0 and 1
GMCH Generates
DMI Type 1
ConfigurationCycle
Bus# =
SECONDARYBUS
in GMCH Dev 1
GMCH Generates
DMI Type 0
Configuration Cycle
GMCH Claims
GMCH Claims
GMCH Claims
Yes
No
Yes
Yes
No
No
Yes
Yes
Yes
No
No
No
No
Device# = 0
GMCH Generates
Type 0 Access
to PCI Express
Yes
Enabled)
172 Datasheet
18.3.1 Internal Device Configuration Accesses
The (G)MCH decodes the Bus Number (Bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device.
If the targeted PCI Bus 0 device exists in the (G)MCH and is not disabled, the
configuration cycle is claimed by the appropriate device.
18.3.2 Bridge Related Configuration Accesses
Configuration accesses on PCI Express graphics or DMI are PCI Express Configuration
TLPs:
Bus Number [7:0] is Header Byte 8 [7:0]
Device Number [4:0] is Header Byte 9 [7:3]
Function Number [2:0] is Header Byte 9 [2:0]
And special fields for this type of TLP:
Extended Register Number [3:0] is Header Byte 10 [3:0]
Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express Specification for more information on both the PCI 2.3-compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
18.3.2.1 PCI Express Graphics Configuration Accesses
When the bus number of a Type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device 1 Secondary Bus Number, a PCI
Express Type 0 Configuration TLP is generated on the PCI Express graphics link
targeting the device directly on the opposite side of the link. This should be Device 0 on
the bus number assigned to the PCI Express graphics link (likely Bus 1).
The device on other side of link must be Device 0. The (G)MCH will Master Abort any
Type 0 Configuration access to a non-zero device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the bus number of a Type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge devices Subordinate Bus Number Register and the lower bound of the
bridge devices Secondary Bus Number Register) but doesn't match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express graphics link.
PCI Express Configuration Writes:
Internally the host interface unit will translate writes to PCI Express extended
configuration space to configuration writes on the backbone.
Writes to extended space are posted on the FSB, but non-posted on the PCI
Express graphics or DMI (i.e., translated to configuration writes).
Datasheet 173
18.3.2.2 DMI Configuration Accesses
Accesses to disabled (G)MCH internal devices, bus numbers not claimed by the Host-
PCI Express graphics bridge, or PCI Bus 0 devices not part of the (G)MCH will
subtractively decode to the ICH and consequently be forwarded over the DMI via a PCI
Express configuration TLP.
If the bus number is zero, the (G)MCH will generate a Type 0 Configuration Cycle TLP
on DMI. If the bus number is non-zero, and falls outside the range claimed by the Host-
PCI Express graphics bridge, the (G)MCH will generate a Type 1 Configuration Cycle TLP
on DMI.
The ICH routes configurations accesses in a manner similar to the (G)MCH. The ICH
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
ICH compares the non-zero bus number with the Secondary Bus Number and
Subordinate Bus Number Registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the ICH, but remain unclaimed by any
device or bridge will result in a master abort.
18.3.2.3 Configuration Retry
For both PCI Express graphics and DMI, any configuration request (read or write) that
receives a Configuration Request Retry Completion Status (CRS) will be reissued as a
new transaction. The CRS terminates the original request TLP, but the (G)MCH will
synthesize a subsequent request. The new configuration TLP which gets reissued due
to CRS will have a new Sequence Number, but the TLP fields (tag, address, data,
attributes, requestor ID, etc.) will be the same as the original TLP.
While this is happening, no completion will be sent to the originator of the configuration
cycle (the CPU). A completion will not be sent to the CPU until the (G)MCH receives a
successful completion, an Unsupported Request or Completer Abort completion, or the
completion times out (if completion timeout is enabled).
This mechanism mimics the behavior on a legacy PCI bus, where any request that is
retried will retry indefinitely.
No devices in the ICH ever return CRS. The (G)MCH is the only root complex device
that handles CRS. The ICH just forwards to the (G)MCH all completions independent of
completion status.
18.4 (G)MCH Register Introduction
The (G)MCH internal registers (I/O Mapped, Configuration, and PCI Express Extended
Configuration registers) are accessible by the Host CPU. The registers that reside within
the lower 256 bytes of each device can be accessed as byte, word (16-bit), or dword
(32-bit) quantities, with the exception of CONFIG_ADDRESS which can only be
accessed as a dword. All multi-byte numeric fields use little-endian ordering (i.e.,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in dword (32-bit) quantities.
Some of the (G)MCH registers described in this section contain reserved bits. These
bits are labeled Reserved. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
174 Datasheet
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, or write
operation for the configuration address register.
In addition to reserved bits within a register, the (G)MCH contains address locations in
the configuration space of the Host Bridge entity that are marked either Reserved or
Intel Reserved. The (G)MCH responds to accesses to Reserved address locations by
completing the host cycle. When a Reserved register location is read, a zero value is
returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved
registers have no effect on the (G)MCH. Reads to Intel Reserved registers may return a
non-zero value.
Warning: Registers that are marked as Intel Reserved must not be modified by system software.
Writes to Intel Reserved registers may cause system failure.
Upon a Full Reset, the (G)MCH sets all of its internal configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options. The default state represents the minimum functionality feature set
required to successfully bring up the system. Hence, it does not represent the optimal
system configuration. It is the responsibility of the system initialization software
(usually BIOS) to properly determine the DRAM configurations, operating parameters
and optional system features that are applicable, and to program the (G)MCH registers
accordingly.
18.5 I/O Mapped Registers
The (G)MCH contains two registers that reside in the CPU I/O address space the
configuration address (CONFIG_ADDRESS) register and the configuration data
(CONFIG_DATA) register. The configuration address register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
18.5.1 CONFIG_ADDRESSConfiguration Address Register
I/O Address: 0CF8h Accessed as a dword
Size: 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a dword. A byte or
word reference will pass through the configuration address register and DMI onto the
PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the bus number,
device number, function number, and register number for which a subsequent
configuration access is intended.
Datasheet 175
Bit Access
Default
Value
Description
31 R/W 0b
Configuration Enable (CFGE): When this bit is set to 1,
accesses to PCI configuration space are enabled. If this bit
is reset to 0, accesses to PCI configuration space are
disabled.
30:24 RO 00h Reserved
23:16 R/W 00h
Bus Number: If the bus number is programmed to 00h,
the target of the configuration cycle is a PCI Bus 0 agent. If
this is the case and the (G)MCH is not the target (i.e., the
device number is >=3 and not equal to 7), then a DMI Type
0 configuration cycle is generated.
If the bus number is non-zero, and does not fall within the
ranges enumerated by Device 1s Secondary Bus Number
or Subordinate Bus Number Register, then a DMI Type 1
configuration cycle is generated.
If the bus number is non-zero and matches the value
programmed into the Secondary Bus Number Register of
Device 1, a Type 0 PCI configuration cycle will be generated
on PCI Express graphics.
If the bus number is non-zero, greater than the value in
the Secondary Bus Number Register of Device 1 and less
than or equal to the value programmed into the
Subordinate Bus Number Register of Device 1 a Type 1 PCI
configuration cycle will be generated on PCI Express
graphics.
This field is mapped to Byte 8 [7:0] of the request header
format during PCI Express* configuration cycles and
A[23:16] during the DMI Type 1 configuration cycles.
15:11 R/W 00h
Device Number: This field selects one agent on the PCI
bus selected by the bus number. When the bus number
field is 00 the (G)MCH decodes the Device Number field.
The (G)MCH is always Device 0 for the Host bridge entity,
Device 1 for the Host-PCI Express entity. Therefore, when
the bus number equals 0 and the device number equals 0,
1, 2 or 7 the internal (G)MCH devices are selected.
format during PCI Express and DMI configuration cycles.
10:8 R/W 000b
Function Number: This field allows the configuration
registers of a particular function in a multi-function device
to be accessed. The (G)MCH ignores configuration cycles to
its internal devices if the function number is not equal to 0
or 1.
7:2 R/W 00h
Register Number: This field selects one register within a
particular bus, device, and function as specified by the
other fields in the Configuration Address Register.
1:0 RO 00b Reserved
176 Datasheet
18.5.2 CONFIG_DATAConfiguration Data Register
I/O Address: 0CFCh
Size: 32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.

Bit Access
Default
Value
Description
31:0 R/W 0000 0000h
Configuration Data Window (CDW): If Bit 31 of
CONFIG_ADDRESS is 1, any I/O access to the
CONFIG_DATA register will produce a configuration
transaction using the contents of CONFIG_ADDRESS to
determine the bus, device, function, and offset of the
register to be accessed.
Datasheet 177
Host Bridge Device 0 Configuration Registers (D0:F0)
19 Host Bridge Device 0
Configuration Registers (D0:F0)
Caution: Address locations that are not listed are considered Reserved registers locations. Reads
to Reserved registers may return non-zero values. Writes to reserved locations may
cause system failures.
19.1 Device 0 Configuration Registers
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Vendor Identification VID 0 1 8086h RO
Device Identification DID 2 3 2A40h RO
PCI Command PCICMD 4 5 0006h RO; R/W
PCI Status PCISTS 6 7 0090h RO; R/WC
Revision Identification RID 8 8 00h RO
Class Code CC 9 B 060000h RO
Master Latency Timer MLT D D 00h RO
Header Type HDR E E 00h RO
Subsystem Vendor
Identification
SVID 2C 2D 0000h R/WO
Subsystem Identification SID 2E 2F 0000h R/WO
Capabilities Pointer CAPPTR 34 34 E0h RO
Egress Port Base Address EPBAR 40 47
000000000
0000000h
RO; R/W/L; R/W
(G)MCH Memory Mapped
Register Range Base
MCHBAR 48 4F
000000000
0000000h
RO; R/W/L; R/W
(G)MCH Graphics Control
Register (Device 0)
GGC 52 53 0030h RO; R/W/L
Device Enable DEVEN 54 57 000043DBh RO; R/W/L
PCI Express Register Range
Base Address
PCIEXBAR 60 67
00000000E
0000000h
RO; R/W/L; R/W
MCH-ICH Serial Interconnect
Ingress Root Complex
DMIBAR 68 6F
000000000
0000000h
RO; R/W/L; R/W
Reserved 70 8F
Programmable Attribute Map 0 PAM0 90 90 00h RO; R/W/L
178 Datasheet
NOTES:
1. Since the MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented.
19.1.1 VID - Vendor Identification
B/D/F/Type: 0/0/0/PCI
Address Offset: 0-1h
Default Value: 8086h
Access: RO
Size: 16 bits
This register combined with the Device Identification Register uniquely identifies any
PCI device.
Legacy Access Control LAC 97 97 00h RO; R/W/L
Remap Base Address Register REMAPBASE 98 99 03FFh RO; R/W/L
Remap Limit Address Register REMAPLIMIT 9A 9B 0000h RO; R/W/L
System Management RAM
Control
SMRAM 9D 9D 02h RO; R/W/L; R/W
Extended System Management
RAM Control
ESMRAMC 9E 9E 38h
RO; R/W/L;
R/WC
Top of Memory TOM A0 A1 0001h RO; R/W/L
Top of Upper Usable DRAM TOUUD A2 A3 0000h R/W/L
Top of Low Used DRAM Register TOLUD B0 B1 0010h RO; R/W/L
Error Status ERRSTS C8 C9 0000h RO; R/WC/S
Error Command ERRCMD CA CB 0000h RO; R/W
Reserved CC CF
Scratchpad Data SKPD DC DF 00000000h
Capability Identifier CAPID0 E0 E9
000000000
000010A00
09h
Reserved F0 FF
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Bit Access
Default
Value
Description
15:0 RO 8086h
Vendor Identification Number (VID): PCI standard
identification for Intel.
Datasheet 179
19.1.2 DID - Device Identification
Default Value: 2A40h
Access: RO
Size: 16 bits
This register combined with the Vendor Identification Register uniquely identifies any
PCI device.
19.1.3 PCICMD - PCI Command
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
15:0 RO 2A40h
Device Identification Number (DID): Identifier assigned
to the (G)MCH core/primary PCI device.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
9 RO 0b
Fast Back-to-Back Enable (FB2B): Since Device 0 is
strictly a target, this bit is not implemented and is hardwired
to 0. Writes to this bit position have no effect.
8 R/W 0b
SERR Enable (SERRE): Global enable bit for Device 0
SERR messaging. The MCH does not have an SERR signal.
The MCH communicates the SERR condition by sending an
SERR message over MCH ICH Serial Interface (DMI) to the
ICH. If this bit is set to a 1, the MCH is enabled to generate
SERR messages over DMI for specific Device 0 error
conditions that are individually enabled in the ERRCMD
register. The error status is reported in the ERRSTS and
PCISTS registers. If SERRE is clear, then the SERR message
is not generated by the MCH for Device 0. Note that this bit
only controls SERR messaging for the Device 0. Device 1
has its own SERRE bits to control error reporting for error
conditions occurring on their respective devices. The control
bits are used in a logical OR manner to enable the SERR DMI
message mechanism.
7 RO 0b
Address/Data Stepping Enable (ADSTEP): Address/
data stepping is not implemented in the MCH, and this bit is
hardwired to 0. Writes to this bit position have no effect.
6 RO 0b
Parity Error Enable (PERRE): PERRB is not implemented
by the MCH and this bit is hardwired to 0. Writes to this bit
position have no effect.
180 Datasheet
19.1.4 PCISTS - PCI Status
Access: RO; R/WC
Size: 16 bits
5 RO 0b
VGA Palette Snoop Enable (VGASNOOP): The MCH does
not implement this bit and it is hardwired to a 0. Writes to
this bit position have no effect.
4 RO 0b
Memory Write and Invalidate Enable (MWIE): The MCH
will never issue memory write and invalidate commands.
This bit is therefore hardwired to 0. Writes to this bit
position will have no effect.
3 RO 0b
Special Cycle Enable (SCE): The MCH does not implement
this bit and it is hardwired to a 0. Writes to this bit position
have no effect.
2 RO 1b
Bus Master Enable (BME): The MCH is always enabled as
a master on DMI. This bit is hardwired to a 1. Writes to this
bit position have no effect.
1 RO 1b
Memory Access Enable (MAE): The MCH always allows
access to main memory. This bit is not implemented and is
hardwired to 1. Writes to this bit position have no effect.
0 RO 0b
I/O Access Enable (IOAE): This bit is not implemented in
the MCH and is hardwired to a 0. Writes to this bit position
have no effect.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): The MCH does not
implement this bit and it is hardwired to a 0. Writes to this
bit position have no effect.
14 R/WC 0b
Signaled System Error (SSE): This bit is set to 1 when the
MCH Device 0 generates an SERR message over DMI for any
enabled Device 0 error condition or Device 0 error conditions
are enabled in the PCICMD and ERRCMD registers. Device 0
error flags are read/reset from the PCISTS or ERRSTS
registers. Software clears this bit by writing a 1 to it.
13 R/WC 0b
Received Unsupported Request (RURS): This bit is set
when the MCH generates a DMI request that receives an
unsupported request completion. Software clears this bit by
writing a 1 to it.
12 R/WC 0b
Received Completion Abort Status (RCAS): This bit is
set when the MCH generates a DMI request that receives a
completion abort. Software clears this bit by writing a 1 to it.
Datasheet 181
11 RO 0b
Signaled Target Abort Status (STAS): The MCH will not
generate a Target Abort DMI completion packet or Special
Cycle. This bit is not implemented in the MCH and is
hardwired to a 0. Writes to this bit position have no effect.
10:9 RO 00b
DEVSEL Timing (DEVT): These bits are hardwired to 00.
Writes to these bit positions have no affect. Device 0 does
not physically connect to PCI_A. These bits are set to 00
(fast decode) so that optimum DEVSEL timing for PCI_A is
not limited by the MCH.
8 RO 0b
Master Data Parity Error Detected (DPD): PERR
signaling and messaging are not implemented by the MCH
therefore this bit is hardwired to 0. Writes to this bit position
have no effect.
7 RO 1b
Fast Back-to-Back (FB2B): This bit is hardwired to 1.
Writes to these bit positions have no effect. Device 0 does
not physically connect to PCI_A. This bit is set to 1
(indicating fast back-to-back capability) so that the optimum
setting for PCI_A is not limited by the MCH.
6:5 RO 00b Reserved
4 RO 1b
Capability List (CLIST): This bit is hardwired to 1 to
indicate to the configuration software that this device/
function implements a list of new capabilities. A list of new
capabilities is accessed via register CAPPTR at configuration
address offset 34h. Register CAPPTR contains an offset
pointing to the start address within configuration space of
this device where the AGP capability standard register
resides.
3:0 RO 0h Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
182 Datasheet
19.1.5 RID - Revision Identification
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
RID Definition: This register contains the revision number of the (G)MCH Device 0.
Following PCI Reset, the SRID value is selected to be read. When a write occurs to this
register, the write data is compared to the hardwired RID Select Key Value, which is
69h. If the data matches this key, a flag is set that enables the CRID value to be read
through this register.
19.1.6 CC - Class Code
Address Offset: 9-Bh
Access: RO
Size: 24 bits
Bit Access
Default
Value
Description
7:0 RO 00h
Revision Identification Number (RID): This is an 8-
bit value that indicates the revision identification number
for the MCH Device 0.
07h: B-3 stepping
Bit Access
Default
Value
Description
23:16 RO 06h
Base Class Code (BCC): This is an 8-bit value that
indicates the base class code for the MCH. This code has
the value 06h, indicating a bridge device.
15:8 RO 00h
Sub-Class Code (SUBCC): This is an 8-bit value that
indicates the category of bridge into which the MCH falls.
The code is 00h indicating a host bridge.
7:0 RO 00h
Programming Interface (PI): This is an 8-bit value
that indicates the programming interface of this device.
This value does not specify a particular register set layout
and provides no practical use for this device.
Datasheet 183
19.1.7 MLT - Master Latency Timer
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
19.1.8 HDR - Header Type
Address Offset: Eh
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
19.1.9 SVID - Subsystem Vendor Identification
Address Offset: 2C-2Dh
Access: R/WO
Size: 16 bits
This value is used to identify the vendor of the subsystem.
Bit Access
Default
Value
Description
7:0 RO 00h Reserved
Bit Access
Default
Value
Description
7:0 RO 00h
PCI Header (HDR): This field always returns 0 to indicate
that the MCH is a single-function device with standard header
layout. Reads and writes to this location have no effect.
Bit Access
Default
Value
Description
15:0 R/WO 0000h
Subsystem Vendor ID (SUBVID): This field should be
programmed during boot-up to indicate the vendor of the
system board. After it has been written once, it becomes
read only.
184 Datasheet
19.1.10 SID - Subsystem Identification
Address Offset: 2E-2Fh
Access: R/WO
Size: 16 bits
This value is used to identify a particular subsystem.
19.1.11 CAPPTR - Capabilities Pointer
Address Offset: 34h
Default Value: E0h
Access: RO
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Bit Access
Default
Value
Description
15:0 R/WO 0000h
Subsystem ID (SUBID): This field should be
programmed during BIOS initialization. After it has been
written once, it becomes read only.
Bit Access
Default
Value
Description
7:0 RO E0h
Pointer to the Offset of the First Capability ID
Register Block: In this case the first capability is the
product-specific Capability Identifier (CAPID0).
Datasheet 185
19.1.12 EPBAR - Egress Port Base Address
Access: R/W/L; RO; R/W
Size: 64 bits
This is the base address for the Egress Port Root Complex MMIO configuration space.
This window of addresses contains the Egress Port Root Complex Register set for the
PCI Express Hierarchy associated with the MCH. There is no physical memory within
this 4-KB window that can be addressed. The 4 KB reserved by this register does not
alias to any PCI 3.0-compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to EPBAREN
[Bit 0 of this register].
All the bits in this register are Intel TXT locked. In Intel TXT mode, R/W bits are RO.
Bit Access
Default
Value
Description
63:36 R/W 0000000h Reserved
35:12 R/W/L 000000h
Egress Port RCRB Base Address: This field corresponds
to bits 35 to 12 of the base address Egress port RCRB MMIO
configuration space.
BIOS will program this register resulting in a base address
for a 4-KB block of contiguous memory address space. This
register ensures that a naturally aligned 4-KB space is
allocated within total addressable memory space of 4 GB.
System Software uses this base address to program the
Egress Port RCRB and associated registers.
0 R/W/L 0b
EPBAR Enable (EPBAREN):
0 = EPBAR is disabled and does not claim memory.
1 = EPBAR memory mapped accesses are claimed and
decoded appropriately.
186 Datasheet
19.1.13 MCHBAR - (G)MCH Memory Mapped Register Range Base
Address Offset: 48-4Fh
Size: 64 bits
This is the base address for the MCH MMIO configuration space. There is no physical
memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any PCI 3.0 compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN
[Dev0, offset 54h, bit 28].
Bit Access
Default
Value
Description
35:14 R/W/L 000000h
(G)MCH Memory Map Base Address: This field
corresponds to Bits 35 to 14 of the base address
MCHBAR configuration space.
BIOS will program this register resulting in a base
address for a 16-KB block of contiguous memory
address space. This register ensures that a naturally
aligned 16-KB space is allocated within total
addressable memory space of 4 GB.
MCH register set.
0 R/W/L 0b
MCHBAR Enable (MCHBAREN):
0 = MCHBAR is disabled and does not claim any
memory.
1 = MCHBAR memory mapped accesses are claimed and
Datasheet 187
19.1.14 GGC - (G)MCH Graphics Control Register (Device 0)
Access: RO; R/W/L
Size: 16 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
11:8 R/W/L 0h
GSM Memory Size (GGMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the
Internal Graphics Translation Table. The BIOS ensures that
memory is pre-allocated only when Internal graphics is
enabled.
GSM is assumed to be a contiguous physical DRAM space
with DSM, and BIOS needs to allocate a contiguous memory
chunk. Hardware will drive the base of GSM from DSM only
using the GSM size programmed in the register.
0000 = No memory pre-allocated. GTT cycles (Mem and IO)
are not decoded.
0001 = No Intel Virtualization Technology (Intel VT)
mode, 1 MB of memory pre-allocated for GTT.
0011 = No Intel VT mode, 2 MB of memory pre-allocated for
GTT.
1001 = Intel VT mode, 2 MB of memory pre-allocated for 1
MB of Global GTT and 1 MB Shadow GTT.
1010 = Intel VT mode, 3 MB of memory pre-allocated for
1.5 MB of Global GTT and 1.5 MB Shadow GTT.
1011 = Intel VT mode, 4 MB of memory pre-allocated for 2
MB of Global GTT and 2 MB Shadow GTT. If Intel VT
for Directed I/O (Intel VT-d) is disabled, then only
No Intel VT mode values (0001 & 0011) will take
effect and setting this register to Intel VT mode.
values (1001, 1010 & 1011) will have the same
effect as with 0000 value.
NOTE: All unspecified encodings of this register field are
reserved, hardware functionality is not guaranteed if
used. This register is locked and becomes Read Only
when the D_LCK bit in SMRAM register is set.
188 Datasheet
7:4 R/W/L 0011b
Graphics Mode Select (GMS): This field is used to select
the amount of Main Memory that is pre-allocated to support
the Internal Graphics device in VGA (non-linear) and Native
(linear) modes. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled.
0000: No memory pre-allocated. Device 2 (IGD) does not
claim VGA cycles (Mem and IO), and the Sub-Class Code
field within Device 2 Function 0 Class Code register is 80.
0001 = Reserved.
0010 = Reserved.
0011 = Reserved.
0100 = Reserved.
0101 = DVMT (UMA) mode, 32 MB of memory pre-allocated
for frame buffer.
0110 = Reserved.
for frame buffer.
1000 = DVMT (UMA) mode, 128 MB of memory pre-
allocated for frame buffer.
for frame buffer.
NOTES:
1. This register is locked and becomes Read Only when
the D_LCK bit in the SMRAM register is set. This
register is also Intel TXT lockable.
2. Hardware does not clear or set any of these bits
automatically based on IGD being disabled/enabled.
3. BIOS Requirement: BIOS must not set this field to
0000 if IVD (Bit 1 of this register) is 0.
3:2 RO 00b Reserved
1 R/W/L 0b
IGD VGA Disable (IVD):
0 = Enable (Default). Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within Device 2 Class
Code Register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles
(Mem and IO), and the Sub-Class Code field within
Device 2 Function 0 Class Code Register is 80.
0 RO 0b Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 189
19.1.15 DEVEN - Device Enable
Default Value: 000043DBh
Access: RO; R/W/L
Size: 32 bits
Allows for enabling/disabling of PCI devices and functions that are within the MCH. This
table describes the behavior of all combinations of transactions to devices controlled by
this register.
Bit Access
Default
Value
Description
15 R/W/L 0b Reserved
13 RO 0b Reserved
12:11 RO 00b Reserved
10 RO 0b Reserved
9:6 R/W/L 1b Reserved
5 RO 0b Reserved
4 R/W/L 1b
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0 Device 2 Function 1 is disabled and hidden.
1 = Bus 0 Device 2 Function 1 is enabled and visible.
If Device 2 Function 0 is disabled and hidden, then Device 2
Function 1 is also disabled and hidden, independent of the
state of this bit.
3 R/W/L 1b
If this (G)MCH does not have internal graphics capability,
then Device 2 Function 0 is disabled and hidden,
independent of the state of this bit.
If this function is disabled, then memory decoding for the
Intel TXT Trusted Graphics Registers at 0xFED305xx also
needs to be disabled.
2 RO 0b Reserved
1 R/W/L 1b
PCI Express Graphics Port Enable (D1EN):
Default value is determined by the device capabilities, SDVO
presence HW strap and SDVO/PCI Express concurrent HW
strap. Device 1 is Disabled on Reset if the SDVO present
strap is sampled high and the SDVO/PCI Express concurrent
strap is sampled low.
0 RO 1b
Host Bridge: Bus 0 Device 0 Function 0 may not be disabled
and is therefore hardwired to 1.
190 Datasheet
19.1.16 PCIEXBAR - PCI Express Register Range Base Address
Default Value: 00000000E0000000h
Size: 64 bits
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the (G)MCH. There
is not actual physical memory within this 256-MB window that can be addressed. Each
PCI Express hierarchies requires a PCI Express BASE Register. The (G)MCH supports
one PCI Express hierarchy.
The 256 MB reserved by this register does not alias to any PCI 2.3-compliant memory
mapped space. For example MCHBAR reserves a 16-KB space and CHAPADR reserves a
4-KB space both outside of PCIEXBAR space. They cannot be overlayed on the space
reserved by PCIEXBAR for Devices 0 and 7, respectively.
On reset, this register is disabled and must be enabled by writing a 1 to PCIEXBAREN
[Dev0, Offset 54h, Bit 31].
If the PCI Express Base Address [Bits 35:28] were set to Fh, an overlap with the High
BIOS area, APIC and Intel TXT ranges would result. Software must guarantee that
these ranges do not overlap. The PCI Express Base Address cannot be less than the
maximum address written to the top of physical memory register (TOLUD). If a system
is populated with more than 3.5 GB, either the PCI Express enhanced access
mechanism must be disabled or the value in TOLUD must be reduced to report that
only 3.5 GB are present in the system to allow a value of Eh for the PCI Express Base
Address (assuming that all PCI 2.3-compatible configuration space fits above 3.75 GB).
Datasheet 191
(Sheet 1 of 2)
Bit Access
Default
Value
Description
35:28 R/W/L 00001110b
PCI Express* Base Address: This field corresponds to
bits 35 to 28 of the base address for PCI Express
enhanced configuration space. BIOS will program this
register resulting in a base address for a contiguous
memory address space; size is defined by Bits 3:1 of this
register. This base address shall be assigned on a
boundary consistent with the number of buses (defined by
the Length field in this register), above TOLUD and still
within total 36-bit addressable memory space. The
address bits decoded depend on the length of the region
defined by this register. The address used to access the
PCI Express configuration space for a specific device can
be determined as follows:
PCI Express Base Address + Bus Number x 1 MB + Device
Number x 32 KB + Function Number x4 KB The address
used to access the PCI Express configuration space for
Device 1 in this component would be PCI Express Base
Address + 0 x 1 MB + 1 x 32 KB + 0 x 4 KB = PCI Express
Base Address + 32 KB. Remember that this address is the
beginning of the 4-KB space that contains both the PCI
compatible configuration space and the PCI Express
extended configuration space. All the bits in this register
are locked in Intel TXT mode.
27 R/W/L 0b
128-MB Address Mask: This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask
(RO, read 0b), depending on the value of bits 2:1 in this
register.
26 R/W/L 0b
64-MB Base Address Mask: This bit is either part of the
PCI Express Base Address (R/W) or part of the Address
Mask (RO, read 0b), depending on the value of Bits 2:1 in
this register.
192 Datasheet
2:1 R/W/L 00b
Length: This field describes the length of this region -
Enhanced Configuration Space Region/Buses Decoded
00 = 256 MB (Buses 0-255). Bits 31:28 are decoded in
the PCI Express Base Address field.
01 = 128 MB (Buses 0-127). Bits 31:27 are decoded in
the PCI Express Base Address field.
10 = 64 MB (Buses 0-63). Bits 31:26 are decoded in the
PCI Express Base Address field.
11 = Reserved
0 R/W/L 0b
PCIEXBAR Enable (PCIEXBAREN):
0 = PCIEXBAR register is disabled. Memory read and
write transactions proceed as if there were no
PCIEXBAR register. PCIEXBAR Register Bits 31:28 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and
write transactions whose Address Bits 31:28 match
PCIEXBAR 31:28 will be translated to configuration
reads and writes within the (G)MCH. These
translation cycles are routed as shown in the tables
above.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 193
19.1.17 DMIBAR - MCH-ICH Serial Interconnect Ingress Root
Complex
Size: 64 bits
This is the base address for the DMI Root Complex MMIO configuration space. This
window of addresses contains the DMI Root Complex Register set for the PCI Express
Hierarchy associated with the MCH. There is no physical memory within this 4-KB
window that can be addressed. The 4 KB reserved by this register does not alias to any
PCI 3.0-compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to RCBAREN
[Dev0, Offset 54h, Bit 29].
Bit Access
Default
Value
Description
35:12 R/W/L 000000h
DMI Root Complex MMIO Register Set Base
Address: This field corresponds to Bits 35 to 12 of the
base address DMI RCRB MMIO configuration space.
address for a 4-KB block of contiguous memory address
space. This register ensures that a naturally aligned 4-KB
space is allocated within total addressable memory space
of 4 GB.
DMI RCRB registers.
0 R/W/L 0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory.
1 = DMIBAR memory mapped accesses are claimed and
194 Datasheet
19.1.18 TCSBAR - Trusted Configuration Register Range Base
Address
Access: R/W/L; RO
Size: 64 bits
This is the base address for the trusted configuration space. This window of addresses
contains the 4 KB of configuration space for each device/function that can potentially
be part of the PCI hierarchy associated with the (G)MCH. There is not actual physical
memory within this 256-MB/128-MB/64-MB window that can be addressed. Each PCI
Hierarchies requires a PCI Base register.
Bit Access
Default
Value
Description
63:36 R/W/L 0000000h Reserved
35:28 R/W/L 0Eh
Trusted Configuration Base Address: This field
corresponds to Bits 63 to 28 of the base address for TCS
configuration space. BIOS will program this register
resulting in a base address for a contiguous memory
address space; size is defined by Bits 2:1 of Dev0
Offsetx60 (PCIEXBAR). This base address shall be
assigned on a boundary consistent with the number of
buses (defined by the Length field in this register), above
TOLUD and still within total 36-bit addressable memory
space. The address bits decoded depend on the length of
the region defined by this register. The address used to
access the PCI Express configuration space for a specific
device can be determined as follows:
TCS Base Address + Bus Number x 1 MB + Device Number
x
32 KB + Function Number x 4 KB. Example: The address
used to access the PCI configuration space for Device 1 in
this component would be PCI Express Base Address + 0 x
1 MB + 1 x 32 KB + 0 x 4 KB = PCI Express Base Address
+ 32 KB. This address is the beginning of the 4-KB space
that contains both the PCI compatible configuration space
and the PCI Express extended configuration space. All the
bits in this register are locked in Intel TXT mode.
27 R/W/L 0b
128-MB Address Mask: This bit is either part of the TCS
Base Address (R/W) or part of the Address Mask (RO, read
0b), depending on the value of Bits 2:1 of Dev 0 Offsetx60
(PCIEXBAR).
26 R/W/L 0b
64-MB Address Mask: This bit is either part of the TCS
Base Address (R/W) or part of the Address Mask (RO, read
0b), depending on the value of Bits 2:1 of Dev0 Offsetx60
(PCIEXBAR).
Datasheet 195
19.1.19 PAM0 - Programmable Attribute Map 0
Address Offset: 90h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h-0FFFFFh.
The MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 640-KB to 1-MB address range. Seven Programmable Attribute Map
(PAM) Registers are used to support these features. Cacheability of these areas is
controlled via the MTRR registers in the P6 processor. Two bits are used to specify
memory attributes for each memory segment. These bits apply to both host accesses
and PCI initiator accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory.
Conversely, when RE = 0, the host read accesses are directed to PCI_A.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory.
Conversely, when WE = 0, the host write accesses are directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size. Accesses to the entire
PAM region (000C_0000h to 000F_FFFFh) from DMI and PCI Express Graphics Attach
Low Priority will be forwarded to main memory. The PAM read enable and write enable
bits are not functional for these accesses. A full set of PAM decode/attribute logic is not
being implemented. The MCH may hang if a PCI Express Graphics Attach or DMI
originated access to Read Disabled or Write Disabled PAM segments occur (due to a
possible IWB to non-DRAM).
For these reasons the following critical restriction is placed on the programming of the
PAM regions. At the time that a DMI or PCI Express Graphics Attach accesses to the
PAM region may occur, the targeted PAM segment must be programmed to be both
readable and writeable.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0F0000-0FFFFF Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0F0000 to 0FFFFF.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked in Intel TXT mode. (RO in Intel TXT mode)
3:0 RO 0h Reserved
196 Datasheet
Address Offset: 91h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h-0C7FFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0C4000-0C7FFF Attribute (HIENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0C4000 to 0C7FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
This register is locked in Intel TXT mode. (RO in Intel
TXT mode)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0C0000-0C3FFF Attribute (LOENABLE): This field
the BIOS area from 0C0000 to 0C3FFF.
01 = Read Only: All reads are serviced by DRAM. All writes
are forwarded to DMI.
serviced by DMI.
serviced by DRAM.
This register is locked in Intel TXT mode. (RO in Intel TXT
mode)
Datasheet 197
Address Offset: 92h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
0C8000h-0CFFFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0CC000-0CFFFF Attribute (HIENABLE): Reserved
serviced by DMI.
serviced by DRAM.
mode.)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0C8000-0CBFFF Attribute (LOENABLE): This field
the BIOS area from 0C8000 to 0CBFFF.
serviced by DMI.
serviced by DRAM.
mode.)
198 Datasheet
Address Offset: 93h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
0D0000h-0D7FFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0D4000-0D7FFF Attribute (HIENABLE): This field
the BIOS area from 0D4000 to 0D7FFF.
serviced by DMI.
serviced by DRAM.
TXT mode.)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0D0000-0D3FFF Attribute (LOENABLE): This field
the BIOS area from 0D0000 to 0D3FFF.
serviced by DMI.
serviced by DRAM.
mode.)
Datasheet 199
Address Offset: 94h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
0D8000h-0DFFFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0DC000-0DFFFF Attribute (HIENABLE): This field
the BIOS area from 0DC000 to 0DFFFF.
serviced by DMI.
serviced by DRAM.
mode.)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0D8000-0DBFFF Attribute (LOENABLE): This field
the BIOS area from 0D8000 to 0DBFFF.
serviced by DMI.
serviced by DRAM.
mode.)
200 Datasheet
Address Offset: 95h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
0E0000h-0E7FFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0E4000-0E7FFF Attribute (HIENABLE): This field
the BIOS area from 0E4000 to 0E7FFF.
serviced by DMI.
serviced by DRAM.
TXT mode.)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0E0000-0E3FFF Attribute (LOENABLE): This field
the BIOS area from 0E0000 to 0E3FFF.
serviced by DMI.
serviced by DRAM.
mode.)
Datasheet 201
Address Offset: 96h
Default Value: 00h
Access: RO; R/W/L
Size: 8 bits
0E8000h-0EFFFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 R/W/L 00b
0EC000-0EFFFF Attribute (HIENABLE): This field
the BIOS area from 0EC000 to 0EFFFF.
serviced by DMI.
serviced by DRAM.
mode.)
3:2 RO 00b Reserved
1:0 R/W/L 00b
0E8000-0EBFFF Attribute (LOENABLE): This field
the BIOS area from 0E8000 to 0EBFFF.
serviced by DMI.
serviced by DRAM.
mode.)
202 Datasheet
19.1.26 LAC - Legacy Access Control
Address Offset: 97h
Default Value: 00h
Access: R/W/L; RO
Size: 8 bits
This 8-bit register controls a fixed DRAM hole from 15-16 MB.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
7 R/W/L 0b
Hole Enable (HEN): This field enables a memory hole in
DRAM space. The DRAM that lies behind this space is not
remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
TXT mode.)
6:1 RO 00h Reserved
Datasheet 203
0 R/W/L 0b
MDA Present (MDAP): This bit works with the VGA
Enable bits in the BCTRL register of Device 1 to control the
routing of CPU initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit
should not be set if Device 1's VGA enable bit is not set.
If Device 1's VGA enable bit is not set, then accesses to IO
address range x3BCh-x3BFh are forwarded to DMI.
If the VGA enable bit is set and MDA is not present, then
accesses to IO address range x3BCh-x3BFh are forwarded
to PCI Express graphics if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are
forwarded to DMI.
MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O:3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh
(Including ISA addresses aliases, A[15:10] are not used
in decode).
Any I/O reference that includes the I/O locations listed
above, or their aliases, will be forwarded to DMI even if the
reference includes I/O locations not listed above.
The following table shows the behavior for all
combinations of MDA and VGA:
(Sheet 2 of 2)
Bit Access
Default
Value
Description
VGAEN MDAP Description
0 0
All references to MDA and VGA
space are routed to HI.
0 1 Illegal Combination
1 0
All VGA and MDA references are
routed to PCI Express Graphics
Attach.
1 1
All VGA references are routed to PCI
Express Graphics Attach. MDA
references are routed to the HI. This
register is locked in Intel TXT
mode. (RO in Intel TXT mode).
204 Datasheet
19.1.27 REMAPBASE - Remap Base Address Register
Default Value: 03FFh
Access: RO; R/W/L
Size: 16 bits
19.1.28 REMAPLIMIT - Remap Limit Address Register
Address Offset: 9A-9Bh
Access: RO; R/W/L
Size: 16 bits
Bit Access
Default
Value
Description
9:0 R/W/L 3FFh
Remap Base Address[35:26]: The value in this register
defines the lower boundary of the Remap window. The
Remap window is inclusive of this address. In the decoder
A[25:0] of the Remap Base Address are assumed to be
0's. Thus the bottom of the defined memory range will be
aligned to a 64-MB boundary.
When the value in this register is greater than the value
programmed into the Remap Limit register, the Remap
window is disabled. This field defaults to 3FFh.
These bits are locked in Intel TXT mode. They are also
locked in Intel Management Engine mode.
Bit Access
Default
Value
Description
9:0 R/W/L 000h
Remap Limit Address [35:26]: The value in this
register defines the upper boundary of the Remap
window. The Remap window is inclusive of this address. In
the decoder A[25:0] of the Remap Limit Address are
assumed to be F's. Thus the top of the defined range will
be one less than a 64-MB boundary.
When the value in this register is less than the value
programmed into the Remap Base register, the Remap
window is disabled. This field defaults to 00h.
These bits are locked in Intel TXT mode. They are also
locked in Intel Management Engine mode.
Datasheet 205
19.1.29 SMRAM - System Management RAM Control
Address Offset: 9Dh
Default Value: 02h
Access: RO; R/W/L; R/W
Size: 8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
7 RO 0b Reserved
6 R/W/L 0b
SMM Space Open (D_OPEN): (When D_OPEN=1 and
D_LCK=0, the SMM space DRAM is made visible even when
SMM decode is not active. This is intended to help BIOS
initialize SMM space. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
This register is locked in Intel TXT mode (RO in Intel TXT
mode). It also locks when D_LCK bit is set.
5 R/W 0b
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space
DRAM is not accessible to data references, even if SMM
decode is active. Code references may still access SMM
space DRAM. This will allow SMM software to reference
through SMM space to update the display even when SMM is
mapped over the VGA range. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
mode).
4 R/W/L 0b
SMM Space Locked (D_LCK): When D_LCK is set to a 1
then D_OPEN is reset to 0 and D_LCK, D_OPEN, G_SMRARE,
C_BASE_SEG, H_SMRAM_EN, GMS, TOLUD, TOM, TSEG_SZ
and TSEG_EN become read only. D_LCK can be set to 1 via a
normal configuration space write but can only be cleared by
a Full Reset. The combination of D_LCK and D_OPEN provide
convenience with security. The BIOS can use the D_OPEN
function to initialize SMM space and then use D_LCK to lock
down SMM space in the future so that no application
software (or BIOS itself) can violate the integrity of SMM
space, even if the program has knowledge of the D_OPEN
function.
This bit when set locks itself.
3 R/W/L 0b
Global SMRAM Enable (G_SMRARE): If set to a 1, then
Compatible SMRAM functions are enabled, providing 128 KB
of DRAM accessible at the A0000h address while in SMM
(ADSB with SMM decode). To enable Extended SMRAM
function this bit has be set to 1. Refer to the section on SMM
for more details.
206 Datasheet
19.1.30 ESMRAMC - Extended System Management RAM Control
Address Offset: 9Eh
Default Value: 38h
Access: R/W/L; R/WC; RO
Size: 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
Note: When Extended SMRAM is used, the maximum amount of DRAM accessible is limited to
256 MB.
2:0 RO 010b
Compatible SMM Space Base Segment (C_BASE_SEG):
This field indicates the location of SMM space. SMM DRAM is
not remapped. It is simply made visible if the conditions are
right to access SMM space, otherwise the access is
forwarded to DMI. Since the MCH supports only the SMM
space between A0000 and BFFFF, this field is hardwired to
010.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
7 R/W/L 0b
Enable High SMRAM (H_SMRAME): Controls the SMM
memory space location (i.e., above 1 MB or below 1 MB)
When G_SMRAME is 1 and H_SMRAME this bit is set to 1,
the high SMRAM memory space is enabled. SMRAM
accesses within the range 0FEDA0000h to 0FEDBFFFFh are
remapped to DRAM addresses within the range
000A0000h to 000BFFFFh.
6 R/WC 0b
Invalid SMRAM Access (E_SMERR): This bit is set when
CPU has accessed the defined memory ranges in Extended
SMRAM (High Memory and T-segment) while not in SMM
space and with the D-OPEN bit = 0. It is software's
responsibility to clear this bit. The software must write a 1
to this bit to clear it.
5 RO 1b
SMRAM Cacheable (SM_CACHE): This bit is forced to 1
by the MCH.
4 RO 1b
L1 Cache Enable for SMRAM (SM_L1): This bit is forced
to 1 by the MCH.
3 RO 1b
L2 Cache Enable for SMRAM (SM_L2): This bit is forced
to 1 by the MCH.
Datasheet 207
2:1 R/W/L 00b
TSEG Size (TSEG_SZ): Selects the size of the TSEG
memory block if enabled. Memory from the top of DRAM
space is partitioned away so that it may only be accessed
by the processor interface and only then when the SMM bit
is set in the request packet. Non-SMM accesses to this
memory region are sent to DMI when the TSEG memory
block is enabled.
00 = 1 MB Tseg. (TOLUD:Graphics Stolen Memory Size -
1M) to (TOLUD - Graphics Stolen Memory Size).
01 = 2 MB Tseg (TOLUD:Graphics Stolen Memory Size -
10 = 8 MB Tseg (TOLUD:Graphics Stolen Memory Size -
11 = Reserved.
0 R/W/L 0b
TSEG Enable (T_EN): Enabling of SMRAM memory for
Extended SMRAM space only. When G_SMRAME =1 and
TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
208 Datasheet
19.1.31 TOM - Top of Memory
Address Offset: A0-A1h
Access: RO; R/W/L
Size: 16 bits
This register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this register.
All the bits in this register are locked in Intel TXT mode. They are also locked in Intel
Management Engine mode.
Bit Access
Default
Value
Description
8:0 R/W/L 001h
Top of Memory: This register reflects the total amount of
populated physical memory. This is also the amount of
addressable physical memory when remapping is used
appropriate to ensure that no physical memory is wasted.
This is NOT necessarily the highest main memory address
(holes may exist in main memory address map due to
addresses allocated for memory mapped IO).
These bits correspond to address Bits 35:27 (128 MB
granularity). Bits 26:0 are assumed to be 0.
All the bits in this register are locked in Intel TXT mode.
They are also locked in Intel Management Engine mode
and when D_LCK bit is set in SMRAM register.
Datasheet 209
19.1.32 TOUUD - Top of Upper Usable DRAM
Access: R/W/L
Size: 16 bits
Configuration software must set this value to TOM minus all EP stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit 64-MB
aligned since reclaim limit is 64-MB aligned. Address Bits 19:0 are assumed to be
0_0000h for the purposes of address comparison. The Host interface positively decodes
an address towards DRAM if the incoming address is less than the value programmed in
this register and greater than or equal to 4 GB. All the bits in this register are locked in
Intel Management Engine mode and when D_LCK bit is set in SMRAM register.
Bit Access
Default
Value
Description
15:0 R/W/L 0000h
Top of Upper Usable DRAM (TOUUD): This register
contains Bits 35 to 20 of an address one byte above the
maximum DRAM memory above 4 G that is usable by the
operating system. Configuration software must set this
value to TOM minus all EP stolen memory if reclaim is
disabled. If reclaim is enabled, this value must be set to
reclaim limit 64-MB aligned since reclaim limit is 64-MB
aligned. Address Bits 19:0 are assumed to be 0_0000h for
the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming
address is less than the value programmed in this register
and greater than 4 GB.
210 Datasheet
19.1.33 TOLUD - Top of Low Used DRAM Register
Address Offset: B0-B1h
Access: R/W/L; RO
Size: 16 bits
This 16-bit register defines the Top of Low Usable DRAM. Graphics Stolen Memory and
TSEG are within DRAM space defined under TOLUD. From the Top of Low Usable DRAM,
(G)MCH claims 1 to 64 MB of DRAM for internal graphics if enabled and 1, 2 or 8 MB of
DRAM for TSEG if enabled. All the bits in this register are locked in Intel TXT mode.
They are also locked in Intel Management Engine mode, or when D_LCK bit is set in
SMRAM register.
Note: Even if the OS does not need any PCI space, TOLUD can only be programmed to FFh.
This ensures that addresses within 128 MB below 4 GB that are reserved for APIC and
Intel TXT will not become accessible to applications.
Bit Access
Default
Value
Description
15:4 R/W/L 001h
Top of Low Usable DRAM (TOLUD): This register
contains Bits 31 to 20 of an address one byte above the
maximum DRAM memory below 4 GB that is usable by the
operating system. Address Bits 31 down to 20
programmed to a 001h implies a minimum memory size
of 1 MB.
Configuration software must set this value to the smaller
of the following 2 choices:
1. Maximum amount memory in the system minus
Intel Management Engine stolen memory plus 1
byte or
2. The minimum address allocated for PCI memory.
Address Bits 19:0 are assumed to be 0_0000h for the
purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the
incoming address is less than that value programmed in
this register.
This register must not be set to 0000 0 b.
NOTE: The Top of Low Usable DRAM is the lowest address
above both Graphics Stolen memory and TSEG. BIOS
determines the base of Graphics Stolen Memory by
subtracting the Graphics Stolen Memory Size from TOLUD
and further decrements by TSEG size to determine the
base of TSEG.
NOTE:This register MUST be 64-MB aligned when reclaim
is enabled.
3:0 RO 0h Reserved
Datasheet 211
19.1.34 ERRSTS - Error Status
Address Offset: C8-C9h
Access: RO; R/WC/S
Size: 16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. A SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set
regardless of whether or not the SERR is enabled and generated. After the error
processing is complete, the error logging mechanism can be unlocked by clearing the
appropriate status bit by software writing a 1 to it.
All the bits in this register are locked in Intel TXT mode. They are also locked in Intel
Management Engine mode, or when D_LCK bit is set in SMRAM register.
Bit Access
Default
Value
Description
15 RO 0b Reserved
14 R/WC/S 0b Reserved
13 R/WC/S 0b Reserved
12 R/WC/S 0b
(G)MCH Software Generated Event for SMI: This
indicates the source of the SMI was a Device 2 Software
Event.
11 R/WC/S 0b
(G)MCH Thermal Sensor Event for SMI/SCI/SERR:
Indicates that a (G)MCH Thermal Sensor trip has occurred
and an SMI, SCI or SERR has been generated. The status bit
is set only if a message is sent based on Thermal event
enables in Error command, SMI command and SCI
command registers. A trip point can generate one of SMI,
SCI, or SERR interrupts (two or more per event is illegal).
Multiple trip points can generate the same interrupt, if
software chooses this mode, subsequent trips may be lost. If
this bit is already set, then an interrupt message will not be
sent on a new thermal sensor event.
10 RO 0b Reserved
9 R/WC/S 0b
LOCK to non-DRAM Memory Flag (LCKF): When this bit
is set to 1, the MCH has detected a lock operation to
memory space that did not map into DRAM.
8 R/WC/S 0b
Received Refresh Timeout Flag (RRTOF): This bit is set
when 1024 memory core refreshes are enqueued.
7 R/WC/S 0b
DRAM Throttle Flag (DTF):
0 = Software has cleared this flag since the most recent
throttling event.
1 = Indicates that a DRAM Throttling condition occurred.
6:0 RO 00h Reserved
212 Datasheet
19.1.35 ERRCMD - Error Command
Address Offset: CA-CBh
Access: RO; R/W
Size: 16 bits
This register controls the MCH responses to various system errors. Since the MCH does
not have an SERRB signal, SERR messages are passed from the MCH to the ICH over
DMI. When a bit in this register is set, a SERR message will be generated on DMI
whenever the corresponding flag is set in the ERRSTS register. The actual generation of
the SERR message is globally enabled for Device 0 via the PCI Command register.
Bit Access
Default
Value
Description
12 RO 0b Reserved
11 R/W 0b
SERR on (G)MCH Thermal Sensor Event (TSESERR):
0 = Reporting of this condition via SERR messaging is
disabled.
1 = The MCH generates a SERR DMI special cycle when Bit
11 of the ERRSTS is set. The SERR must not be
enabled at the same time as the SMI for the same
thermal sensor event.
10 RO 0b Reserved
9 R/W 0b
SERR on LOCK to non-DRAM Memory (LCKERR):
disabled.
1 = The MCH will generate a DMI SERR special cycle
whenever a CPU lock cycle is detected that does not
hit DRAM.
8 R/W 0b
SERR on DRAM Refresh Timeout (DRTOERR):
disabled.
1 = The (G)MCH generates an SERR DMI special cycle
when a DRAM Refresh timeout occurs.
7 R/W 0b
SERR on DRAM Throttle Condition (DTCERR):
disabled.
1 = The (G)MCH generates an SERR DMI special cycle
when a DRAM Read or Write Throttle condition occurs.
6:0 RO 00h Reserved
Datasheet 213
19.1.36 CAPID0 - Capability Identifier
Address Offset: E0-E9h
Default Value: 000000000000010A0009h
Access: RO
Size: 80 bits
(Sheet 1 of 4)
Bit Access
Default
Value
Description
79 RO 0b
Integrated TPM Disable (ITPMDIS):
0 = iTPM is enabled
1 = iTPM is disabled
(delivered through Intel Management Engine)
78 RO 0b Reserved
77 RO 0b Reserved
76 RO 0b Reserved
72 RO 0b Reserved
71 RO 0b Reserved
70 RO 0b Reserved
69 RO 0b Reserved
68 RO 0b Reserved
67 RO 0b Reserved
66 RO 0b Reserved
65:62 RO 0000b
Compatibility Device ID: Identifier assigned to the
(G)MCH core/primary PCI device.
61:58 RO 0111b
Compatibility Revision ID: This is a 4-bit value that
indicates the revision identification number for the (G)MCH
Device 0.
57 RO 0b
Intel Management Engine / EP Disable:
0 = Intel Management Engine Feature is enabled.
1 = Intel Management Engine Feature is disabled.
56 RO 0b
All Intel Active Management Technology (Intel
AMT) Disable:
0 = Intel AMT Feature is enabled.
1 = Intel AMT Feature is disabled.
55 RO 0b Reserved
54 RO 0b Reserved
53 RO 0b
Audio Disable:
0 = (G)MCH is capable of audio.
1 = (G)MCH is not capable of audio.
52 RO 0b Reserved
51 RO 0b Reserved
50 RO 0b Reserved
214 Datasheet
49 RO 0b
DDR2 Capability:
0 = (G)MCH is capable of supporting DDR2 SDRAM with
800 MHz and lower.
667 MHz and lower.
48 RO 0b
Intel Virtualization Technology (Intel VT) for
Directed I/O (Intel VT-d) Disable (VTDDIS):
Controls Intel VT-d capability.
0 = Intel VT-d is enabled
1 = Intel VT-d is disabled
47 RO 0b Reserved
46 RO 0b Reserved
45 RO 0b Reserved
44:42 RO 000b
GFX Software Capability ID:
Used to communicate (G)MCH variant information to the
Graphics Driver software
111 = PM45
001 = GM45
011 = GL40
100 = GS45, GS40
Others = Reserved
41 RO 0b Reserved
40 RO 0b Reserved
39 RO 0b Reserved
38 RO 0b Reserved
37 RO 0b
Chipset Intel TXT Disable: The purpose of Intel TXT
Disable is to mask all Intel TXT functionality in the chipset.
With Intel TXT disabled, the chipset will decode all cycles as
in previous chipsets.
0 = Intel TXT behaviors are allowed. Graphics Intel TXT
capability depends on separate Graphics Intel TXT
Disable field.
1 = Intel TXT behaviors are not allowed, including graphics
are not allowed.
(Delivered through Intel Management Engine)
36:35 RO 00b
Render Core Frequency Capability:
01 = Capable of 533-MHz Core or lower
00 = Reserved
34 RO 0b Reserved
(Sheet 2 of 4)
Bit Access
Default
Value
Description
Datasheet 215
33 RO 0b
Internal Graphics Disable:
0 = There is a graphics engine within this (G)MCH. Internal
Graphics Device (Device 2) is enabled and all of its
memory and I/O spaces are accessible. Configuration
cycles to Device 2 will be completed within the (G)MCH.
All non-SMM memory and IO accesses to VGA will be
handled based on Memory and IO enables of Device 2
and IO registers within Device 2 and VGA Enable of the
PCI to PCI bridge control register in Device 1 (if PCI
Express GFX attach is supported). A selected amount of
Graphics Memory space is pre-allocated from the main
memory based on Graphics Mode Select (GMS in the
(G)MCH Control Register). Graphics Memory is pre-
allocated above TSEG Memory.
1 = There is no graphics engine within this (G)MCH.
Internal Graphics Device (Device 2) and all of its
memory and I/O functions are disabled. Configuration
cycle targeted to Device 2 will be passed on to DMI. In
addition, All clocks to internal graphics logic are turned
off. All non-SMM memory and IO accesses to VGA will
be handled based on VGA Enable of the PCI to PCI
bridge control register in Device 1. DEVEN [4:3]
(Device 0, offset 54h) are forced to 00 have no
meaning. Device 2 Functions 0 and 1 are disabled and
hidden.
32 RO 0b
PCI Express Port Disable:
0 = There is a PCI Express GFX Attach on this (G)MCH.
Device 1 and associated memory spaces are accessible.
All non-SMM memory and IO accesses to VGA will be
handled based on VGA Enable of the PCI to PCI bridge
control register in Device 1 and VGA settings controlling
internal graphics VGA if internal graphics is enabled.
1 = There is no PCI Express GFX Attach on this (G)MCH.
Device 1 and associated memory and IO spaces are
disabled. In addition, Next_Pointer = 00h, VGA
memory and IO cannot decode to the PCI Express
interface. VGA memory and IO cannot decode to the
PCI Express interface. From a Physical Layer
perspective, all 16 lanes are powered down and the link
does not attempt to train.
31:30 RO 00b
DDR3 Capability:
1066 MHz and lower.
800 MHz and lower.
1x: (G)MCH is not capable of supporting DDR3 SDRAM.
(Sheet 3 of 4)
Bit Access
Default
Value
Description
216 Datasheet

29:28 RO 00b
FSB Capability:
This field controls which values are allowed in the FSB
Frequency Select Field of the Clocking Configuration
Register (MCHBAR Offset C00h). These values are
determined by the BSEL[2:0] frequency straps. Any
unsupported straps will render the (G)MCH host interface
inoperable.
00 = Reserved
01 = (G)MCH capable of up to FSB 1066 MHz
27:24 RO 1h
CAPID Version: This field has the value 0001b to identify
the first revision of the CAPID register definition.
23:16 RO 0Ah
CAPID Length: This field has the value 0Ah to indicate the
structure length (10 bytes).
15:8 RO 00h
Next Capability Pointer: This field is hardwired to 00h
indicating the end of the capabilities linked list.
7:0 RO 09h
CAP_ID: This field has the value 1001b to identify the
CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
(Sheet 4 of 4)
Bit Access
Default
Value
Description
Datasheet 217
Device 0 Memory Mapped I/O Register
20 Device 0 Memory Mapped I/O
Register
Note: All accesses to the Memory Mapped registers must be made as a single dword
(4 bytes) or less. Access must be aligned on a natural boundary.
20.1 Device 0 Memory Mapped I/O Registers
A variety of timing and control registers have been moved to MMR space of Device 0
due to space constraints.
To simplify the read/write logic to the SRAM, BIOS is required to write and read 32-bit
aligned dword. The SRAM includes a separate Write Enable for every dword.
The BIOS read/write cycles are performed in a memory mapped IO range that is setup
for this purpose in the PCI configuration space, via standard PCI range scheme.
20.1.1 Device 0 MCHBAR Chipset Control Registers
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
MEREMAPBAR Memory
ReMap Memory Register
Range Base Address
MEREMAPBAR 10 17
00000000000
00000h
RO; R/W
GFXREMAPBAR Memory
GFX ReMap Memory
Register Range Base
Address
GFXREMAPBAR 18 1F
00000000000
00000h
RO; R/W
VC0REMAPBAR Memory
VC0 ReMap Memory
Register Range Base
Address
VC0REMAPBAR 20 27
00000000000
00000h
RO; R/W
VC1REMAPBAR Memory
VC1 ReMap Memory
Register Range Base
Address
VC1REMAPBAR 28 2F
00000000000
00000h
RO; R/W
Reserved 30 33
PAVPC GMCH Graphics
Protected Audio Video Path
Control Register (Device 0)
PAVPC 34 37 00000000h RO; R/W
Reserved 38 FA
218 Datasheet
20.1.2 MEREMAPBAR - MEREMAPBAR Memory Intel
Management Engine REMAP Memory Register Range Base
Address
B/D/F/Type: 0/0/0/MCHBAR Chipset
Access: RO; R/W
Size: 64 bits
This is the base address for Intel Management Engine REMAP MMIO configuration
space. This window of addresses contains the Intel Management Engine ReMap
Register set. There is no physical memory within this 4-KB window that can be
addressed. The 4-KB reserved by this register does not alias to any PCI 2.2-compliant
memory mapped space.
The following BAR register will naturally gets locked when MCHBAR gets locked. The
access to this BAR registers is not allowed when Intel Management Engine is disabled
or when Intel VT-d is disabled.
Bit Access
Default
Value
Description
63:12 R/W
0000000
000000h
Intel Management Engine REMAP MMIO Register
Set Base Address: This field corresponds to Bits 63 to
12 of the base address Intel Management Engine REMAP
configuration space.
of 4 GB.
DMA REMAP registers for Intel Management Engine.
This register is locked based on Intel VT-d capability
(i.e., it becomes RO when Intel VT-d is disabled) or when
Intel Management Engine is disabled.
0 R/W 0b
Intel Management Engine REMAP MMIO Space
Enable (MEREMAPBAREN) (MEREMAPBAREN):
0 = MEREMAPBAR is disabled and does not claim any
memory.
1 = MEREMAPBAR memory mapped accesses are claimed
and decoded appropriately.
This register is locked based on Intel VT-d capability (i.e.,
it becomes RO when Intel VT-d is disabled) or when Intel
Management Engine is disabled.
Datasheet 219
20.1.3 GFXREMAPBAR - GFXREMAPBAR Memory GFX ReMap
Memory Register Range Base Address
Access: RO; R/W
Size: 64 bits
This is the base address for GFX ReMAP MMIO configuration space. This window of
addresses contains the GFX ReMap Register set. There is no physical memory within
this 4-KB window that can be addressed. The 4 KB reserved by this register does not
alias to any PCI 2.2 compliant memory mapped space.
The following BAR register will naturally lock when MCHBAR locks.
The accesses to this BAR registers are not allowed when IGD is disabled or when Intel
VT-d is disabled.
Bit Access
Default
Value
Description
63:12 R/W
0000000
000000h
GFX REMAP MMIO register set Base Address: This field
corresponds to Bits 63 to 12 of the base address GFX
REMAP configuration space.
for a 4-KB block of contiguous memory address space. This
DMA REMAP registers for GFX.
it becomes RO when Intel VT-d is disabled) or when IntGFX
is disabled
0 R/W 0b
GFX REMAP MMIO Space Enable (GFXREMAPBAREN):
0 = GFXREMAPBAR is disabled and does not claim any
memory.
1 = GFXREMAPBAR memory mapped accesses are claimed
This register is locked based on Intel VT-d capability (i.e., it
becomes RO when Intel VT-d is disabled) or when IntGFX is
disabled.
220 Datasheet
20.1.4 VC0REMAPBAR - VC0REMAPBAR Memory VC0 ReMap
Access: RO; R/W
Size: 64 bits
This is the base address for PCI Express graphics and DMI VC0 ReMAP MMIO
configuration space. This window of addresses contains the VC0 ReMap Register set.
There is no physical memory within this 4-KB window that can be addressed. The 4-KB
reserved by this register does not alias to any PCI 2.2-compliant memory mapped
space.
This BAR's registers will naturally lock when MCHBAR gets locks.
Bit Access
Default
Value
Description
63:12 R/W
0000000
000000h
VC0 REMAP MMIO register set Base Address: This
field corresponds to Bits 63 to 12 of the base address VC0
of 4 GB.
DMA REMAP registers for VC0.
This register is locked based on Intel VT-d capability
(i.e., it becomes RO when Intel VT-d is disabled).
0 R/W 0b
VC0 REMAP MMIO Space Enable
(VC0REMAPBAREN):
0 = VC0REMAPBAR is disabled and does not claim any
memory.
1 = VC0REMAPBAR memory mapped accesses are
claimed and decoded appropriately.
it becomes RO when Intel VT-d is disabled).
Datasheet 221
20.1.5 VC1REMAPBAR - VC1REMAPBAR Memory VC1 ReMap
Access: RO; R/W
Size: 64 bits
This is the base address for DMI VC1 ReMAP MMIO configuration space. This window of
addresses contains the VC1 ReMap Register set. There is no physical memory within
this 4-KB window that can be addressed. The 4-KB reserved by this register does not
alias to any PCI 2.2 compliant memory mapped space.
This BAR's registers will naturally get locked when MCHBAR gets locked.
Bit Access
Default
Value
Description
63:12 R/W
0000000
000000h
VC1 REMAP MMIO Register Set Base Address: This
field corresponds to Bits 63 to 12 of the base address VC1
for a 4-B block of contiguous memory address space. This
DMA REMAP registers for VC1.
it becomes RO when Intel VT-d is disabled).
0 R/W 0b
VC1 REMAP MMIO Space Enable (VC1REMAPBAREN):
0 = VC1REMAPBAR is disabled and does not claim any
memory.
1 = VC1REMAPBAR memory mapped accesses are claimed
This register is locked based on Intel VT-d capability (i.e., it
becomes RO when Intel VT-d is disabled).
222 Datasheet
20.1.6 PAVPC - GMCH Graphics Protected Audio Video Path
Control Register (Device 0)
B/D/F/Type: 0/0/0/MCHBAR
Access: RO; R/W/L;
Size: 32 bits
All the Bits in this register are LT locked. In LT mode R/W bits are RO.
Bit Access
Default
Value
Description
31:16 R/W/L 0000h
Protected Content Memory Write Once Base
(PCMWOBASE): This field is used to set the base of the
Write-Once Protected Content Memory space.
This corresponds to bits 31:16 of the system memory
address range, giving a 64-KB granularity. This value
MUST be above PCMBASE and below the top of stolen
memory.
This register is locked (becomes read-only) when PAVPE =
1b.
15:4 R/W/L 000h
Protected Content Memory Base (PCMBASE): This
field is used to set the base of Protected Content.Memory.
This corresponds to bits 31:20 of the system memory
address range, giving a 1-MB granularity. This value MUST
be at least 8 MB above the base and below the top of
stolen memory (unprotected VGA cycles can access 0-8
MB of stolen memory).
1b.
3 RO 0b Reserved
2 RO 0b
Protected Content Memory Write Once Status
(PCMWOST): This field reflects the status of the Write
Once PCM lock. It is set when the cyg_ci_wopcm internal
signal is pulsed, and reset on a system reset.
1 R/W/L 0b
Protected Audio Video Path Enable (PAVPE): This
field locks all of the bits in this register.
0 = PAVP path is disabled, and All PCM registers are R/W
(except PCME, which may be held to 0b by a fuse).
1 = PAVP path is enabled, and All PCM registers are read-
only (including PAVPE itself).
1b (i.e., it locks itself).
This register is read-only (stays at 0b) when the PAVP fuse
is set to disabled.
0 R/W/L 0b
Protected Content Memory Enable (PCME): This field
enables a Protected Content Memory within Graphics
Stolen Memory.
1b.
This register is read-only (stays at 0b) when the PAVP fuse
is set to disabled.
Datasheet 223
20.2 MCHBAR Arbitration
20.2.1 DCC - DRAM Channel Control
Access: RO; R/W; R/W/L
Size: 32 bits
This register controls how the DRAM channels work together. It affects how the CxDRB
registers are interpreted and allows them to steer transactions to the correct channel.
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
DRAM Channel Control DCC 200 203 00000000h RO; R/W; R/W/L
Reserved 204 243
(Sheet 1 of 2)
Bit Access
Default
Value
Description
23 RO 0b Reserved
22:21 R/W 00b
Bank Select for EMRS Commands: This field applies
only when the Mode Select (SMS) bits = 100, implying an
EMRS command.
00 = Bank 1 (BS[2:0] = 001), EMRS(1)
01 = Bank 2 (BS[2:0] = 010), EMRS(2)
10 = Bank 3 (BS[2:0] = 011), EMRS(3)
11 = Reserved
20 R/W 0b
Independent Dual Channel IC/SMS Enable:
0 = IC and SMS controls in DCC register control both
system memory channels.
1 = IC and SMS bits in C0/1DRC0 register control each
system memory channel independently.
19 R/W 0b Reserved
224 Datasheet
18:16 R/W 000b
Mode Select (SMS): These bits select the special
operational mode of the DRAM interface. The special
modes are intended for initialization at power up.
000 = Post Reset state. When the MCH exits reset, the
mode select field is cleared to 000.
001 = NOP Command Enable - All CPU cycles to DRAM
result in a NOP command on the DRAM interface.
010 = All Banks Pre-charge Enable - All CPU cycles to
DRAM result in an all banks precharge command
on the DRAM interface.
011 = Mode Register Set Enable - All CPU cycles to DRAM
result in a mode register set command on the
DRAM interface. Host address lines are mapped to
DRAM address lines in order to specify the
command sent.
100 = Extended Mode register set (EMRS)
101 = Initial ZQ calibration for DDR3 only
110 = CBR Refresh Enable:In this mode all CPU cycles to
DRAM result in a CBR cycle on the DRAM interface
111 = Normal operation
15 R/W 0b
SMS Exit Sequence Initiator: SMS Exit Sequence
Initiator
0 = SMS exit sequence handled by EP?
1 = BIOS initiates SMS exit sequence.
10 R/W/L 0b
Channel XOR Randomization Disable (CXRDIS):
When enabled, the DRAM Controller will try to spread page
accesses evenly among the channels by including more
address bits in the choice for which channel holds the
requested address.
0 = Channel XOR Randomization is enabled.
1 = Channel XOR Randomization is disabled
9 R/W/L 0b Reserved
8:2 RO
0000000
b
Reserved
1 R/W/L 0b
DRAM Addressing Mode Control (DAMC):
0 = Single-Channel/Dual-Channel Asymmetric
1 = Dual-Channel Interleaved
0 RO 0b Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 225
20.3 Device 0 MCHBAR Clock Controls
20.3.1 CLKCFG - Clocking Configuration
B/D/F/Type: 0/0/0/MCHBAR CLK
Access: RO; R/W
Size: 32 bits
Register Name
Register
Symbol
Register
Start
Register
End
Default Value Access
Clocking
Configuration
CLKCFG C00 C03 00040208h RO; R/W
Reserved C04 C17
Sticky Scratchpad
Data
SSKPD C1C C1D 0000h R/W/S
Reserved C20 C67
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31 R/W 0b Reserved
30 RO 0b Reserved
29 RO 0b Reserved
28 RO 0b Reserved
27 R/W 0b Reserved
26 RO 0b Reserved
25:23 R/W 000b Reserved
22 R/W 0b Reserved
21 R/W 0b Reserved
18 R/W 1b Reserved
17 R/W 0b Reserved
14 R/W 0b Reserved
13 RO 0b Reserved
12 R/W 0b Reserved
11 R/W 0b Reserved
10 R/W 0b Reserved
7 R/W 0h Reserved
226 Datasheet
20.3.2 SSKPD - Sticky Scratchpad Data
B/D/F/Type: 0/0/0/MCHBAR CLK
Address Offset: C1C-C1Dh
Access: R/W/S
Size: 16 bits
This register holds 16 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers. This Register is reset on PWROK.
6:4 R/W 000b
Memory Frequency Select. (MEMFREQSEL): The values
here refer to DDR frequencies.
100 = 667
101 = 800
110 = 1066
Others: Reserved.
3 R/W 1b Reserved
2:0 RO 000b
PSB Frequency Select. (PSBFREQSEL):
011 = FSB667
010 = FSB800
110 = FSB1066
Others = Reserved
Attempts to strap values beyond the configurable limit will
shut down the host PLL.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
15:0 R/W/S 0000h
Scratchpad Data (SCRATCHPAD): 1 WORD of data
storage.
Datasheet 227
20.4 Device 0 MCHBAR ACPI Power Management
Controls
20.4.1 C2C3TT - C2 to C3 Transition Timer
B/D/F/Type: 0/0/0/MCHBAR PM
Address Offset: F00-F03h
Access: RO; R/W
Size: 32 bits
Register Name
Register
Symbol
Register
Start
Register End Default Value Access
C2 to C3 Transition
Timer
C2C3TT F00 F03 00000000h RO; R/W
C3 to C4 Transition
Timer
C3C4TT F04 F07 00000000h RO; R/W
Reserved F08 F0E
Power Management
Configuration
PMCFG F10 F10 02h R/W
Self-Refresh Channel
Status
SLFRCS F14 F17 00000000h RO; R/WC
Reserved F20 FFF
Bit Access
Default
Value
Description
18:7 R/W 000h
C2 to C3 Transition Timer (C2C3TT): Dual purpose timer
in 128-core clock granularity.
Number of core clocks to wait between last snoop from PCI
Express graphics or DMI to a Req_C3 DMI message being
issued. Timer is activated only when the WAIT_C3 message
from DMI has been received when in C2.
000 = 128 host clocks
FFF = 524288 host clocks
6:0 RO 00h Reserved
228 Datasheet
20.4.2 C3C4TT - C3 to C4 Transition Timer
Access: RO; R/W
Size: 32 bits
20.4.3 PMCFG - Power Management Configuration
Address Offset: F10h
Default Value: 02h
Access: R/W
Size: 8 bits
BIOS Optimal Default 0h
This register bit field shall contain the default value unless otherwise indicated in the
BIOS Specification.
Bit Access
Default
Value
Description
18:7 R/W 000h
C3 to C4 Transition Timer (C34TT): 128 core clock
granularity.
Number of core clocks to wait between last snoop from
PCI Express graphics or DMI to a Req_C4 DMI message
being issued. Timer is activated only when the WAIT_C4
message from DMI has been received when in C3.
000 = 128 host clocks
FFF = 524288 host clocks
6:0 RO 00h Reserved
Datasheet 229
20.4.4 SLFRCS - Self-Refresh Channel Status
Access: RO; R/WC
Size: 32 bits
This register is reset by PWROK only.
20.5 Device 0 MCHBAR Thermal Management Controls
Bit Access
Default
Value
Description
1 R/WC 0b
Warm Reset Event Occurred (RST_EVNT):
Set by power management hardware when a
RESET_WARN message has been received on the DMI
link.
Cleared by the BIOS by writing a 1 in a warm reset
(Reset# asserted while PWROK is asserted) exit
sequence.
Note: In a non-Intel ME system, this bit will get cleared in
a cold reset. In an Intel ME system, this bit will always
retain its value.
0 R/WC 0b
Channels in Self-refresh:
Set by power management hardware after both memory
channels are placed in self refresh as a result of a Power
State or a Reset Warn sequence,
Cleared by Power management hardware before starting
self refresh exit sequence initiated by a power
management exit.
Cleared by the BIOS by writing a 1 in a warm reset
(Reset# asserted while PWROK is asserted) exit
sequence.
0 = Both Channels are not guaranteed to be in sElf
Refresh.
1 = Both Channels are in Self Refresh.
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Reserved 1000 1000
Thermal Sensor Control 1 TSC1 1001 1002 0000h R/W; R/W/L; R/WC
Thermal Sensor Status 1 TSS1 1004 1005 0000h RO
Thermometer Read 1 TR1 1006 1006 FFh RO
Thermometer Offset 1 TOF1 1007 1007 00h R/W
Relative Thermometer Read 1 RTR1 1008 1008 00h RO
230 Datasheet
Reserved 100B 100E
Thermal Sensor Temperature
Trip Point A1
TSTTPA1 1010 1013 00000000h RO; R/W/L; R/WO
Trip Point B1
TSTTPB1 1014 1017 00000000h R/W/L
Thermal Calibration Offset 1 TCO1 1018 1018 00h R/W/L
Reserved 101A 101B
Hardware Throttle Control 1
HWTHROT
CTRL1
101C 101C 00h RO; R/W/L; R/WO
Reserved 101D 101D
Thermal Interrupt Status 1 TIS1 101E 101F 0000h R/WC
Reserved 1040 1040
Thermal Sensor Control 2 TSC2 1041 1042 0000h R/W; R/W/L; R/WC
Thermal Sensor Status 2 TSS2 1044 1045 0000h RO
Thermometer Read 2 TR2 1046 1046 FFh RO
Thermometer Offset 2 TOF2 1047 1047 00h R/W
Relative Thermometer Read 2 RTR2 1048 1048 00h RO
Reserved 104B 104E
Trip Point A2
TSTTPA2 1050 1053 00000000h RO; R/W/L; R/WO
Trip Point B2
TSTTPB2 1054 1057 00000000h R/W/L
Thermal Calibration Offset 2 TCO2 1058 1058 00h R/W/L
Reserved 105A 105B
Hardware Throttle Control 2
HWTHROT
CTRL2
105C 105C 00h RO; R/W/L; R/WO
Reserved 105D 105D
Thermal Interrupt Status 2 TIS2 105E 105F 0000h R/WC
Thermometer Mode Enable
and Rate
TERATE 1070 1070 00h R/W
Thermal Sensor Rate Control TSRCTRL 1080 1080 06h R/W
In Use Bits IUB 10E0 10E3 00000000h RO; R/WC
Thermal Error Command TERRCMD 10E4 10E4 00h R/W
Thermal SMI Command TSMICMD 10E5 10E5 00h R/W
Thermal SCI Command TSCICMD 10E6 10E6 00h R/W
Thermal INTR Command TINTRCMD 10E7 10E7 00h R/W
External Thermal Sensor
Control and Status
EXTTSCS 10EF 10EF 00h RO; R/W/L; R/WO
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Datasheet 231
20.5.1 TSC1 - Thermal Sensor Control 1
B/D/F/Type: 0/0/0/MCHBAR Thermal
Access: R/W; R/W/L; R/WC
Size: 16 bits
This register controls the operation of the internal thermal sensor located in the hot
spot of graphics region.
Bit Access
Default
Value
Description
15 R/W/L 0b
ThermalSensorenable (TSE): This bit enables power to
the thermal sensor. Lockable via TCO Bit 7.
0 = Disabled
1 = Enabled
14 R/W 0b Reserved
13:10 R/W 0000b
Digital Hysteresis Amount (DHA): This bit determines
whether no offset, 1 LSB, 2... 15 is used for hysteresis for
the trip points.
0001 = 1 TR value added to each trip temperature when
tripped
0010 = 2 TR values added to each trip temperature when
tripped:
0110 = ~3.0 C (Recommended setting)
1110 = 14 TR value added to each trip temperature when
tripped
1111 = 15 TR values added to each trip temperature when
tripped
NOTE: TR = Temperature Read
9 R/W/L 0b Reserved
8 R/WC 0b
InUse (IU): Software semaphore bit. After a full MCH
RESET, a read to this bit returns a 0. After the first read,
subsequent reads will return a 1. A write of a 1 to this bit
will reset the next read value to 0. Writing a 0 to this bit has
no effect. Software can poll this bit until it reads a 0, and
will then own the usage of the thermal sensor. This bit has
no other effect on the hardware, and is only used as a
semaphore among various independent software threads
that may need to use the thermal sensor. Software that
reads this register but does not intend to claim exclusive
access of the thermal sensor must write a one to this bit if it
reads a 0, in order to allow other software threads to claim
it.
See also THERM Bit 15, which is an independent additional
semaphore bit.
7:0 RO 0h Reserved
232 Datasheet
20.5.2 TSS1 - Thermal Sensor Status 1
Access: RO
Size: 16 bits
This read only register provides trip point and other status of the thermal sensor.
Bit Access
Default
Value
Description
10 RO 0b
ThermometermodeOutputValid: A 1 indicates the
Thermometer mode is able to converge to a temperature
and that the TR register is reporting a reasonable
estimate of the thermal sensor temperature. A 0 indicates
the Thermometer mode is off, or that temperature is out
of range, or that the TR register is being looked at before
a temperature conversion has had time to complete.
9 RO 0b Reserved
8 RO 0b Reserved
7:6 RO 0h Reserved
5 RO 0b
CatastrophicTripIndicator (CTI): A 1 indicates that
the internal thermal sensor temperature is above the
catastrophic setting.
4 RO 0b
HotTripIndicator (HTI): A 1 indicates that the internal
thermal sensor temperature is above the Hot setting.
3 RO 0b
Aux3TripIndicator (A3TI): A 1 indicates that the
internal thermal sensor temperature is above the Aux3
setting.
2 RO 0b
setting.
1 RO 0b
setting.
0 RO 0b
setting.
Datasheet 233
20.5.3 TR1 - Thermometer Read 1
Address Offset: 1006h
Default Value: FFh
Access: RO
Size: 8 bits
This register generally provides the calibrated current temperature from the
thermometer circuit when the Thermometer mode is enabled. See the temperature
tables for the temperature calculations.
20.5.4 TOF1 - Thermometer Offset 1
Default Value: 00h
Access: R/W
Size: 8 bits
This register is used for programming the thermometer offset.
Bit Access
Default
Value
Description
7:0 RO FFh
ThermometerReading (TR): Provides the current counter
value. The current counter value corresponds to thermal
sensor temperature if TSS[Thermometer mode Output
Valid] = 1. This register has a straight binary encoding that
will range from 0 to FFh.
Bit Access
Default
Value
Description
7:0 R/W 00h
Thermomteroffset (TOF): This value is used to adjust the
current thermometer reading so that the TR value is not
relative to a specific trip or calibration point, and is positive
going for positive increases in temperature. The initial
default value is 00h and software must determine the
correct temperature adjustment that corresponds to a zero
reading by reading the fuses and referring to the
temperature tables, and then programming the computed
offset into this register.
234 Datasheet
20.5.5 RTR1 - Relative Thermometer Read 1
Default Value: 00h
Access: RO
Size: 8 bits
This register contains the relative temperature.
20.5.6 TSTTPA1 - Thermal Sensor Temperature Trip Point A1
Access: RO; R/W/L; R/WO
Size: 32 bits
This register:
1. Sets the target values for some of the trip points in thermometer mode.
2. Reports the relative thermal sensor temperature. See also TSTTPB.
Bit Access
Default
Value
Description
7:0 RO 00h
Relativethermometerreading (RTR1): In
Thermometer mode, this register reports the relative
temperature of the thermal sensor. Provides a two's
complement value of the thermal sensor relative to TOF.
TR and HTPS can both vary between 0 and 255. But RTR
will be clipped between 127 to keep it an 8-bit number.
See also TSS[Thermometer mode Output Valid].
In the Analog mode, the RTR field reports HTPS value.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31 R/WO 0b
Lock Bit forAux0, Aux1, Aux2 and Aux3 Trip Points
(AUXLOCK): This bit, when written to a 1, locks the Aux
x Trip point settings.
This lock is reversible. The reversing procedure is:
following sequence must be done in order without any
other configuration cycles in-between
write tsttpa1 04C1C202
It is expected that the Aux x Trip point settings can be
changed dynamically when this lock is not set.
Datasheet 235
20.5.7 TSTTPB1 - Thermal Sensor Temperature Trip Point B1
Access: R/W/L
Size: 32 bits
This register sets the target values for some of the trip points in the Thermometer
mode. See also TSTTPA1.
15:8 R/W/L 00h
Hot Trip Point Setting (HTPS): Sets the target value
for the Hot trip point. Lockable via TCO Bit 7.
7:0 R/W/L 00h
Catastrophic Trip Point Setting (CTPS): Sets the
target for the Catastrophic trip point.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
31:24 R/W/L 00h
Aux3Trippointsetting (A3TPS): Sets the target value for
the Aux3 trip point Lockable by TSTTPA1[31].
23:16 R/W/L 00h
15:8 R/W/L 00h
7:0 R/W/L 00h
236 Datasheet
20.5.8 TCO1 - Thermal Calibration Offset 1
Default Value: 00h
Access: R/W/L
Size: 8 bits
Bit Access
Default
Value
Description
7 R/W/L 0b
LockbitforCatastrophic (LBC): This bit, when written to
a 1, locks the Catastrophic programming interface,
including Bits 7:0 of TSTTPA[15-0], Bits 15 and 9 of TSC,
and Bits 10 and 8 of TST1.
This bit may only be set to a 0 by a hardware reset.
Writing a 0 to this bit has no effect.
6:0 R/W/L 00h
CalibrationOffset (CO): This field contains the current
calibration offset for the Thermal Sensor DAC inputs. The
calibration offset is a twos complement signed number
which is added to the temperature counter value to help
generate the final value going to the thermal sensor DAC.
This field is Read/Write and can be modified by Software
unless locked by setting Bit 7 of this register. The fuses
cannot be programmed via this register. Once this register
has been overwritten by software, the values of the TCO
fuses can be read using the Therm3 register. Note for TCO
operation: While this is a 7-bit field, the 7th bit is sign
extended to 9 bits for TCO operation.
The range of 00h to 3fh corresponds to 0 0000 0000 to 0
0011 1111.
The range of 41h to 7fh corresponds to 1 1100 001 (i.e,
negative 3fh) to 1 1111 1111 (i.e, negative 1),
respectively.
If TST[Direct DAC Test Enable] = 1, the values in this field
are sent directly to Bank B.
Datasheet 237
20.5.9 HWTHROTCTRL1 - Hardware Throttle Control 1
Address Offset: 101Ch
Default Value: 00h
Size: 8 bits
Bit Access
Default
Value
Description
7 R/W/L 0b
InternalThermalHardwareThrottlingEnablebit
(ITHTE): This bit is a master enable for internal thermal
sensor-based hardware throttling.
0 = Hardware actions via the internal thermal sensor are
disabled.
1 = Hardware actions via the internal thermal sensor are
enabled.
6:5 RO 00b Reserved:
4 R/W/L 0b
ThrottlingZoneSelection (TZS): This bit determines what
temperature zones will enable autothrottling. This register
applies to internal thermal sensor throttling. Lockable by Bit
0 of this register. See also the throttling registers in PCI
config space Device 0 which is used to enable or disable
throttling.
0 = Hot, Aux2, and Catastrophic.
1 = Hot and Catastrophic.
3 R/W/L 0b
HaltonCatastrophic (HOC): When this bit is set,
THRMTRIPB is asserted on catastrophic trip to bring the
platform down. A system reboot is required to bring the
system out of a halt from the thermal sensor. Once the
catastrophic trip point is reached, THRMTRIPB will stay
asserted even if the catastrophic trip deasserts before the
platform is shut down.
2 R/W/L 0b Reserved
1 R/W/L 0b Reserved
0 R/WO 0b
HardwareThrottlingLocKBit (HTL): This bit locks Bits
7:1 of this register. When this bit is set to a one, the
register bits are locked. It may only be set to a 0 by a
hardware reset. Writing a 0 to this bit has no effect.
238 Datasheet
20.5.10 TIS1 - Thermal Interrupt Status 1
Access: R/WC
Size: 16 bits
This register is used to report which specific error condition resulted in the D2F0 or
D2F1 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR
Thermal Event. SW can examine the current state of the thermal zones by examining
the TSS. Software can distinguish internal or external Trip Event by examining TSS.
(Sheet 1 of 3)
Bit Access
Default
Value
Description
13 R/WC 0b
WasCatastrophicThermalSensorInterruptEvent:
0 = No trip for this event
1 = Indicates that a Catastrophic Thermal Sensor trip
based on a higher to lower temperature transition
through the trip point.
Software must write a 1 to clear this status bit.
12 R/WC 0b
WasHotThermalSensorInterruptEvent:
0 = No trip for this event.
1 = Indicates that a Hot Thermal Sensor trip based on a
higher to lower temperature transition through the
trip point.
11 R/WC 0b
WasAux3ThermalSensorInterruptEvent (A3TSIE):
1 = Indicates that an Aux3 Thermal Sensor trip based on
a higher to lower temperature transition through the
trip point.
10 R/WC 0b
WasAux2ThermalSensorInterruptEvent:
trip pointSoftware must write a 1 to clear this status
bit.
9 R/WC 0b
trip point.
Datasheet 239
8 R/WC 0b
trip point.
7:6 RO 0h Reserved
5 R/WC 0b
CatastrophicThermalSensorInterruptEvent:
1 = Indicates that a Catastrophic Thermal Sensor trip
event occurred based on a lower to higher
temperature transition through the trip point.
4 R/WC 0b
HotThermalSensorInterruptEvent:
1 = Indicates that a Hot Thermal Sensor trip event
occurred based on a lower to higher temperature
transition through the trip point
3 R/WC 0b
Aux3ThermalSensorInterruptEvent (A3TSIE):
1 = Indicates that an Aux Thermal Sensor trip event
transition through the trip point.
2 R/WC 0b
Aux2ThermalSensorInterruptEvent:
1 = Indicates that an Aux Thermal Sensor trip event
1 R/WC 0b
1 = Indicates that an Aux1 Thermal Sensor trip event
(Sheet 2 of 3)
Bit Access
Default
Value
Description
240 Datasheet
20.5.11 TSC2 - Thermal Sensor Control 2
Access: R/W; R/W/L; R/WC
Size: 16 bits
This register controls the operation of the internal thermal sensor located in the
memory hot spot.
Bit settings for this register are identical to TSC1.
20.5.12 TSS2 - Thermal Sensor Status 2
Access: RO
Size: 16 bits
This read only register provides trip point and other status of the thermal sensor.
Bit settings for this register are identical to TSS1.
0 R/WC 0b
1 = Indicates that an Aux0 Thermal Sensor trip event
The following scenario is possible: An interrupt is initiated
on a rising temperature trip, the appropriate DMI cycles
are generated, and eventually the software services the
interrupt and sees a rising temperature trip as the cause
in the status bits for the interrupts. Assume that the
software then goes and clears the local interrupt status
bit in the TIS register for that trip event. It is possible at
this point that a falling temperature trip event occurs
before the software has had the time to clear the global
interrupts status bit. But since software has already
looked at the status register before this event happened,
software may not clear the local status flag for this event.
Therefore, after the global interrupt is cleared by S/W, S/
W must look at the instantaneous status in the TSS
register.
(Sheet 3 of 3)
Bit Access
Default
Value
Description
Datasheet 241
20.5.13 TOF2 - Thermometer Offset 2
Default Value: 00h
Access: R/W
Size: 8 bits
This register is used to program the thermometer offset.
Bit settings for this register are identical to TOF1.
20.5.14 RTR2 - Relative Thermometer Read 2
Default Value: 00h
Access: RO
Size: 8 bits
This register contains the relative temperature.
Bit settings for this register are identical to RTR1.
20.5.15 TR2 - Thermometer Read 2
Default Value: FFh
Access: RO
Size: 8 bits
This register generally provides the calibrated current temperature from the
thermometer circuit when the Thermometer mode is enabled. See the temperature
tables for the temperature calculations.
Bit settings for this register are identical to TR1.
20.5.16 TSTTPA2 - Thermal Sensor Temperature Trip Point A2
Size: 32 bits
This register:
1. Sets the target values for some of the trip points in thermometer mode.
2. Reports the relative thermal sensor temperature See also TSTTPB. Bit settings for
this register are identical to TSTTPA1.
242 Datasheet
20.5.17 TSTTPB2 - Thermal Sensor Temperature Trip Point B2
Access: R/W/L
Size: 32 bits
This register sets the target values for some of the trip points in the Thermometer
mode. See also TSTTPA.
Bit settings for this register are identical to TSTTPB1.
20.5.18 TCO2 - Thermal Calibration Offset 2
Default Value: 00h
Access: R/W/L
Size: 8 bits
Bit settings for this register are identical to TCO1.
20.5.19 HWTHROTCTRL2 - Hardware Throttle Control 2
Address Offset: 105Ch
Default Value: 00h
Size: 8 bits
Bit settings for this register are identical to HWTHROTCTRL1.
20.5.20 TIS2 - Thermal Interrupt Status 2
Access: R/WC
Size: 16 bits
This register is used to report which specific error condition resulted in the D2F0 or
D2F1 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR
Thermal Event. SW can examine the current state of the thermal zones by examining
the TSS. Software can distinguish internal or external Trip Event by examining TSS.
Bit settings for this register are identical to TIS1.
Datasheet 243
20.5.21 TERATE - Thermometer Mode Enable and Rate
Default Value: 00h
Access: R/W
Size: 8 bits
BIOS Specification.
20.5.22 TSRCTRL - Thermal Sensor Rate Control
Default Value: 06h
Access: R/W
Size: 8 bits
BIOS Specification.
20.5.23 IUB - In Use Bits
Address Offset: 10E0-10E3h
Access: RO; R/WC
Size: 32 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
24 R/WC 0b
InUseBit3 (IU3): Software semaphore bit. After a full
(G)MCH RESET, a read to this bit returns a 0. After the first
read, subsequent reads will return a 1. A write of a 1 to this
bit will reset the next read value to 0. Writing a 0 to this bit
has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the resource with which
software associates it. This bit has no other effect on the
hardware, and is only used as a semaphore among various
independent software threads that may need to use the
resource. When finished with the resource, software must
write a 1 to this bit to clear the semaphore.
244 Datasheet
16 R/WC 0b
read, subsequent reads will return a 1.
A write of a 1 to this bit will reset the next read value
to 0.
Software can poll this bit until it reads a 0, and will then
own the usage of the resource with which software
associates it. This bit has no other effect on the hardware,
and is only used as a semaphore among various
8 R/WC 0b
to 0.
7:1 RO 00h Reserved
0 R/WC 0b
to 0.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 245
20.5.24 TERRCMD - Thermal Error Command
Address Offset: 10E4h
Default Value: 00h
Access: R/W
Size: 8 bits
This register select which errors are generate a SERR DMI interface special cycle, as
enabled by ERRCMD [SERR Thermal Sensor event].The SERR and SCI must not be
enabled at the same time for the thermal sensor event.
Bit Access
Default
Value
Description
7:6 RO 0h Reserved
5 R/W 0b
SERRonCatastrophicThermalSensorEvent:
0 = Disable. Reporting of this condition via SERR
messaging is disabled.
1 = Does not mask the generation of a SERR DMI cycle on
a catastrophic thermal sensor trip.
4 R/W 0b
SERRonHotThermalSensorEvent:
a Hot thermal sensor trip.
3 R/W 0b
SERRonAux3ThermalSensorEvent (AUX3SERR):
a Aux3 thermal sensor trip.
2 R/W 0b
SERRonAux2ThermalSensorEvent:
1 R/W 0b
0 R/W 0b
246 Datasheet
20.5.25 TSMICMD - Thermal SMI Command
Default Value: 00h
Access: R/W
Size: 8 bits
This register selects specific errors to generate a SMI DMI cycle, as enabled by the SMI
Error Command Register[SMI on Thermal Sensor Trip].
Bit Access
Default
Value
Description
7:6 RO 0h Reserved
5 R/W 0b
SMIonCatastrophicThermalSensorTrip:
0 = Disable reporting of this condition via SMI messaging.
1 = Does not mask the generation of an SMI DMI cycle on
a catastrophic thermal sensor trip.
4 R/W 0b
SMIonHotThermalSensorTrip:
a Hot thermal sensor trip.
3 R/W 0b
SMIonAux3ThermalSensorTrip (AUX3SMI):
an Aux3 thermal sensor trip.
2 R/W 0b
SMIonAux2ThermalSensorTrip:
1 R/W 0b
0 R/W 0b
Datasheet 247
20.5.26 TSCICMD - Thermal SCI Command
Default Value: 00h
Access: R/W
Size: 8 bits
This register selects specific errors to generate a SCI DMI cycle, as enabled by the SCI
Error Command Register[SCI on Thermal Sensor Trip].The SCI and SERR must not be
enabled at the same time for the thermal sensor event.
Bit Access
Default
Value
Description
7:6 RO 0h Reserved
5 R/W 0b
SCIonCatastrophicThermalSensorTrip:
0 = Disable. Reporting of this condition via SCI messaging
is disabled.
1 = Does not mask the generation of an SCI DMI cycle on a
catastrophic thermal sensor trip.
4 R/W 0b
SCIonHotThermalSensorTrip:
is disabled.
Hot thermal sensor trip.
3 R/W 0b
SCIonAux3ThermalSensorTrip (AUX3SCI):
is disabled.
Aux3 thermal sensor trip.
2 R/W 0b
SCIonAux2ThermalSensorTrip:
is disabled.
1 R/W 0b
is disabled.
0 R/W 0b
is disabled.
248 Datasheet
20.5.27 TINTRCMD - Thermal INTR Command
Default Value: 00h
Access: R/W
Size: 8 bits
This register selects specific errors to generate an INT DMI cycle
Bit Access
Default
Value
Description
7:6 RO 0h Reserved
5 R/W 0b
INTRonCatastrophicThermalSensorTrip:
1 = A INTR DMI cycle is generated by (G)MCH
4 R/W 0b
INTRonHotThermalSensorTrip:
3 R/W 0b
INTRonAux3ThermalSensorTrip (AUX3INTR):
2 R/W 0b
INTRonAux2ThermalSensorTrip:
1 R/W 0b
0 R/W 0b
Datasheet 249
20.5.28 EXTTSCS - External Thermal Sensor Control and Status
Address Offset: 10EFh
Default Value: 00h
Size: 8 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
7 R/WO 0b
ExternalSensorEnable: Setting this bit to 1 locks the
lockable bits in this register. This bit may only be set to a
zero by a hardware reset. Once locked, writing a 0 to bit has
no effect.
EXTTS0 and EXTTS1 input signal pins are dedicated external
thermal sensor use. An asserted External Thermal Sensor
Trip signal can also cause a SCI, SMI, SERR or INTR
interrupt as well as the Internal Sensor. A 0 on the pins can
be used to trigger throttling.
If both internal sensor throttling and external write sensor
throttling are enabled, either can initiate throttling.
The AS0 and AS1 bits of this register allow control of what
action is triggered by external sensor trips. The (G)MCH
Throttling select bit controls the type of throttling action
that will happen, and the {AS0, AS1} bits control what trip
actions will result.
0 = External Sensor input is disabled.
1 = External Sensor input is enabled.
6 R/W/L 0b
ThrottlingTypeSelect (TTS): Lockable by EXTTSCS
[External Sensor Enable].
If External Thermal Sensor Enable = 1, then:
0 = DRAM throttling based on the settings in the Device 0
MCHBAR DRAM Throttling Control register.
1 = (G)MCH throttling, based on the settings in the Device
0 MCHBAR (G)MCH Throttling Control Register and the
Device 2 Graphics Render Throttle Control Register
[Catastrophic and Hot Hardware controlled Thermal
Throttle Duty Cycle] else.
5 R/W/L 0b
EXTTS1ActionSelect (AS1): Lockable by EXTTSCS
[External Sensor Enable].If External Thermal Sensor Enable
= 1, then:
0 = The external sensor trip functions same as a
Thermometer mode hot trip.
1 = The external sensor trip functions as a Thermometer
mode aux0 trip.
4 R/W/L 0b
EXTTS0ActionSelect (AS0): Lockable by EXTTSCS
[External Sensor Enable].
If External Thermal Sensor Enable = 1, then:
Thermometer mode catastrophic trip.
Thermometer mode hot trip.
250 Datasheet
20.6 MCHBAR Render Thermal Throttling
3 RO 0b
EXTTS0TripIndicator (S0TI): A 1 indicates that an
externally monitored temperature is exceeding the
programmed setting of an external thermal sensor.
2 RO 0b
EXTTS1TripIndicator (S1TI): A 1 indicates that an
externally monitored temperature is exceeding the
programmed setting of an external thermal sensor.
1:1 RO 0h Reserved
0 R/W/L 0b
External Thermal Sensor Signals Routing Control:
0 = Route all external sensor signals to affect internal
thermal sensor 1 registers, as appropriate.
1 = Route all external sensor signals to affect internal
thermal sensor 2 registers, as appropriate.
Register Name
Register
Symbol
Register
Start
Register End
Default
Value
Access
Reserved 1100 1101 0000h R/W
VID and Frequency
Relationship Table 1
VIDFREQ1 1110 1113 00000000h R/W
Reserved 1114 111F
Internal to External VID
Mapping Table 1
INTTOEXT1 1120 1123 00000000h RO; R/W
Mapping Table 2
INTTOEXT2 1124 1127 00000000h RO; R/W
Mapping Table 3
INTTOEXT3 1128 112B 00000000h RO; R/W
Reserved 112C 11AF
Thermal State Control THERMSTCTL 11B0 11B3 00000000h R/W
Render Standby State
Control
RSTDBYCTL 11B8 11BB 00000000h R/W
Reserved 11BC 11BF
VID Control VIDCTL 11C0 11C3 00000000h R/W
VID Control 1 VIDCTL1 11C4 11C7 00000000h R/W
Reserved 11C8 11E9
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 251
20.6.1 CRSTANDVID - Render Standby VID
Access: R/W
Size: 16 bits
This register contains the VIDs for Render Standby.
20.6.2 VIDFREQ1 - VID and Frequency Relationship Table 1
Access: R/W
Size: 32 bits
Bit Access
Default
Value
Description
11:8 R/W 0000b
Render Standby without Context Restore Voltage
VID (a.k.a. standby VCCMIN) (R2VID):The value in
this register corresponds to the internal VID mapping
7:4 RO 0h Reserved
Bit Access
Default
Value
Description
27:24 R/W 0000b VID Point -- P0 (VIDP0)
19:16 R/W 0000b P0 Frequency (P0FREQ)
11:8 R/W 0000b VID Point -- P1 (VIDP1)
7:4 RO 0h Reserved
252 Datasheet
20.6.3 INTTOEXT1 - Internal to External VID Mapping Table 1
Access: RO; R/W
Size: 32 bits
Access: RO; R/W
Size: 32 bits
Bit Access
Default
Value
Description
27:24 R/W 0000b
External Mapping for Internal Mapping 15 (MAP15):
External mapping for internal mapping 15
19:16 R/W 0000b External Mapping for Internal Mapping 14 (MAP14)
7:4 RO 0h Reserved
Bit Access
Default
Value
Description
27:24 R/W 0000h External Mapping for Internal Mapping 11 (MAP11)
7:4 RO 0h Reserved
Datasheet 253
Address Offset: 1128-112Bh
Access: RO; R/W
Size: 32 bits
20.6.6 THERMSTCTL - Thermal State Control
Address Offset: 11B0-11B3h
Access: R/W
Size: 32 bits
BIOS Specification
20.6.7 RSTDBYCTL - Render Standby State Control
Address Offset: 11B8-11BBh
Access: R/W
Size: 32 bits
Bit Access
Default
Value
Description
27:24 R/W 0h External Mapping for Internal Mapping 7 (MAP7)
7:4 RO 0h Reserved:
Bit Access
Default
Value
Description
31 R/W 0b Reserved
30 R/W 0b
RS2 Enable (RS2EN):
0 = RS2 not enabled
1 = RS2 enabled
254 Datasheet
20.6.8 VIDCTL - VID Control
Address Offset: 11C0-11C3h
Access: R/W
Size: 32 bits
20.6.9 VIDCTL1 - VID Control 1
Address Offset: 11C4-11C7h
Access: R/W
Size: 32 bits
BIOS Specification.
Bit Access
Default
Value
Description
31:24 R/W 00h
VID Up Time (VIDUPTIME):
0 = 255 s
1 = 1 s
255 = 255 s
23:16 R/W 00h
VID Down Time (VIDDNTIME):
0 = 255 s
1 = 1 s
255 = 255 s
Datasheet 255
20.7 Device 0 MCHBAR DRAM Controls
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register End
Default
Value
Access
Channel 0 DRAM Rank
Boundary 0/1
C0DRB01 1200 1203 00000000h RO; R/W
Reserved 1204 1207
Channel 0 DRAM Rank
0,1,2,3 Attribute
C0DRA 1208 120B 00000000h RO; R/W
Channel 0 DRAM Clock
Disable
C0DCLKDIS 120C 120F 00000000h RO; R/W
Reserved 1210 1213
Channel 0 DRAM Timing
Register 0
C0DRT0 1210 1213 34B10461h RO; R/W
Register 1
C0DRT1 1214 1217 11E08463h RO; R/W
Register 2
C0DRT2 1218 121B 2200105Fh RO; R/W
Register 3
C0DRT3 121C 121F 01056102h RO; R/W
Register 4
C0DRT4 1220 1223 28643C32h RO; R/W
Reserved 1224 122F
Channel 0 DRAM
Controller Mode 0
C0DRC0 1230 1233 4F000008h RO; R/W
Channel 0 DRAM
Controller Mode 1
C0DRC1 1234 1237 00000000h RO; R/W
Reserved 1238 123B
Channel 0 ODT Control. C0ODT 1248 124F
00828787200
02020h
RO; R/W
Reserved 1250 126F
Channel 0 GMCH
Throttling Event Weights
C0GTEW 1270 1273 00000000h R/W/L
Channel 0 GMCH
Throttling Event Control
C0GTC 1274 1277 00000000h RO; R/W/L
Channel 0 DRAM Rank
Throttling Passive Event
C0DTPEW 1278 127F
00000000000
00000h
RO; R/W/L
Channel 0 DRAM Rank
Throttling Active Event
C0DTAEW 1280 1287
00000000000
00000h
RO; R/W/L
Channel 0 DRAM
Throttling Control
C0DTC 1288 128B 00000000h RO; R/W/L
Reserved 128C 12B3
Channel 0 DRAM Thermal
Sensor Watch Dog Timer
C0DTWDT 12B4 12B7 00000000h RO; R/W/L
256 Datasheet
Channel 1 DRAM Rank
Boundary 0/1
C1DRB01 1300 1303 00000000h RO; R/W
Reserved 1304 1307
Channel 1 DRAM Rank
0,1,2,3 Attribute
C1DRA 1308 130B 00000000h RO; R/W
Channel 1 DRAM Clock
Disable
C1DCLKDIS 130C 130F 00000000h RO; R/W
Register 0
C1DRT0 1310 1313 34B10461h RO; R/W
Register 1
C1DRT1 1314 1317 11E08463h RO; R/W
Register 2
C1DRT2 1318 131B 2200105Fh RO; R/W
Register 3
C1DRT3 131C 131F 01056102h RO; R/W
Reserved 1320 132F
Channel 1 DRAM
Controller Mode 0
C1DRC0 1330 1333 4F000008h RO; R/W
Channel 1 DRAM
Controller Mode 1
C1DRC1 1334 1337 00000000h RO; R/W
Channel 1 DRAM
Controller Mode 2
C1DRC2 1338 133B 00000000h RO; R/W
Reserved 1348 136F
Channel 1 GMCH
Throttling Event Weights
C1GTEW 1370 1373 00000000h R/W/L
Channel 1 GMCH
Throttling Event Control
C1GTC 1374 1377 00000000h RO; R/W/L
Channel 1 DRAM Rank
Throttling Passive Event
C1DTPEW 1378 137F
00000000000
00000h
RO; R/W/L
Channel 1 DRAM Rank
Throttling Active Event
C1DTAEW 1380 1387
00000000000
00000h
RO; R/W/L
Channel 1 DRAM
Throttling Control
C1DTC 1388 138B 00000000h RO; R/W/L
Reserved 138C 13B3
Channel 1 DRAM Thermal
Sensor Watch Dog Timer
C1DTWDT 13B4 13B7 00000000h RO; R/W/L
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register End
Default
Value
Access
Datasheet 257
20.7.1 C0DRB01 - Channel 0 DRAM Rank Boundary 0/1
Access: RO; R/W
Size: 32 bits
The DRAM Rank Boundary Register defines the upper boundary address of each DRAM
rank with a granularity of 32. These registers are used to determine which chip select
will be active for a given address.
In all modes, if a SO-DIMM is single-sided, it appears as a populated rank and an
empty rank. A DRB must be programmed appropriately for each.
Bit Access
Default
Value
Description
24:16 R/W 000h
Channel 0 DRAM Rank 1 Boundary Address (DRB1):
This 9-bit value defines the upper and lower addresses for
each DRAM rank. Bits 7:2 are compared against Address
32:27 to determine the upper address limit of a particular
rank. Bits 1:0 must be 0s. Bit 8 may be programmed to a 1
in the highest DRB (DRB3) if 8 GB of memory are present.
8:0 R/W 000h
Channel 0 DRAM Rank 0 Boundary Address (DRB0):
This 9-bit value defines the upper and lower addresses for
each DRAM rank. Bits 7:2 are compared against Address
32:27 to determine the upper address limit of a particular
rank. Bits 1:0 must be 0s. Bit 8 may be programmed to a 1
in the highest DRB (DRB3) if 8 GB of memory are present.
258 Datasheet
20.7.2 C0DRA - Channel 0 DRAM Rank 0,1 Attribute
Access: RO; R/W
Size: 32 bits
The DRAM Rank Attribute Registers define the page sizes to be used when
accessing different ranks. These registers should be left with their default value (all
zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB
registers. Each byte of information in the CxDRA registers describes the page size of a
pair of ranks.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
24 RO 0b Reserved
21 RO 0b Reserved
20:19 R/W 00b
Rank 1 Bank Architecture:
00 = 4 Bank
01 = 8 Bank
10 = 16 Bank - Reserved
11 = Reserved
18 RO 0b Reserved
17:16 R/W 00b
Rank 0 Bank Architecture:
00 = 4 Bank
01 = 8 Bank
10 = 16 Bank - Reserved
11 = Reserved
15 RO 0b Reserved
11 RO 0b Reserved
7 RO 0b Reserved
6:4 R/W 000b
Channel 0 DRAM odd Rank 1 Attribute (DRA1): This
3-bit field defines the page size of the corresponding
rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB - Reserved
Others = Reserved
3 RO 0b Reserved
Datasheet 259
20.7.3 C0DCLKDIS - Channel 0 DRAM Clock Disable
Address Offset: 120C-120Fh
Access: RO; R/W
Size: 32 bits
This register can be used to disable the System Memory Clock signals to each SO-DIMM
slot, which can significantly reduce EMI and Power concerns for clocks that go to
unpopulated SO-DIMMs. Clocks can be enabled based on whether a slot is populated.
Since there are multiple clock signals assigned to each rank of a SO-DIMM, it is
important to clarify exactly which rank width field affects which clock signal.
2:0 R/W 000b
Channel 0 DRAM even Rank 0 Attribute (DRA0): This
3-bit field defines the page size of the corresponding
rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB - Reserved
Others = Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
2 R/W 0b Reserved
1 R/W 0b
SO-DIMM Clock Gate Enable Pair 1:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
0 R/W 0b
SO-DIMM Clock Gate Enable Pair 0:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
260 Datasheet
20.7.4 C0DRT0 - Channel 0 DRAM Timing Register 0
Default Value: 34B10461h
Access: RO; R/W
Size: 32 bits
This 32-bit register defines the timing parameters for all devices in this channel. The
BIOS programs this register with the least common denominator values for each
channel after reading configuration registers of each device in each channel.
(Sheet 1 of 5)
Bit Access
Default
Value
Description
31 RO 0b Reserved
30:26 R/W 0dh
Back-to-Back Write to Precharge Command
Spacing (Same Rank) (B2BWR2PCSB): This field
determines the number of clocks between write
command and a subsequent precharge command to the
same bank.
The minimum number of clocks is calculated based on
this formula:
DDR2 / DDR3: WL+ BL/2 + t WR
0h to 9h: Reserved
Ah to 13h: Allowed
25 RO 0b Reserved
24:20 R/W 0Bh
Back-to-Back Write to Read Command Spacing
(Same Rank): This field determines the number of
clocks between write command and a subsequent read
command to the same rank.
The minimum number of clocks is calculated based on
this formula:
DDR2 / DDR3: WL + BL/2 + t WTR
0h - 7h: Reserved
8h - Fh: Allowed
NOTE: Write to Read Command delay (tWTR). The tWTR
is a standard DDR timing parameter and is used to time a
RD command after a WR command to the same row.
Datasheet 261
17:15 R/W 010b
Back-to-Back Write-Read Command Spacing
(Different Rank):
This field determines the number of turnaround clocks on
the data bus that needs to be inserted between write
command and a subsequent read command.
The minimum spacing of commands is calculated based
on the formula:
Spacing = BL/2 + TA (wr-rd) + WL - CL
BL is the burst length and can be set to either 4 or 8
TA is the required write to read DQ turnaround on the
bus. Can be set to 1,2, or 3 CK using this register
CL is CAS Latency
WL is Write Latency
14 RO 0b Reserved
(Sheet 2 of 5)
Bit Access
Default
Value
Description
Encoding BL8 CMD Spacing
110 9
101 8
100 7
011 6
010 5
001 4
000 3
262 Datasheet
13:10 R/W 1h
Back-to-Back Read-Write Command Spacing: This
field determines the number of turnaround clocks
between the read command and a subsequent write
command. Same and different rank.
on the formula:
Spacing = CL + BL/2 + TA (wr-rd) - WL
BL is the burst length and can be set to either 4 or 8
TA is the required read to write DQ turnaround on the
bus. Can be set to 1,2,3, 4 CK for DDR2
CL is CAS Latency
WL is Write Latency
The bigger turnarounds are used in large configurations,
where the difference in total channel delay between the
fastest and slowest SO-DIMM is large.
9:8 RO 00b Reserved
(Sheet 3 of 5)
Bit Access
Default
Value
Description
Encoding BL8 CMD Spacing
0111 12
0110 11
0101 10
0100 9
0011 8
0010 7
0001 6
0000 5
Datasheet 263
7:5 R/W 011b
Back-to-Back Write Command Spacing (Different
Rank):
This field controls the turnaround time on the DQ bus for
WR-WR sequence to different ranks in one channel.
on the formula:
DDR2 and DDR3= BL/2 + TA
4:3 RO 00b Reserved
(Sheet 4 of 5)
Bit Access
Default
Value
Description
Encoding Turnaround
BL8 CMD
Spacing
100
4 turnaround
clocks on DQ
8
011
3 turnaround
clocks on DQ
7
010
2 turnaround
clocks on DQ
6
001
1 turnaround
clocks on DQ
5
000
0 turnaround
clocks on DQ
4
264 Datasheet
2:0 R/W 001b
Back-to-Back Read Command Spacing (Different
Rank):
This field controls the turnaround time on the DQ bus for
Rd-RD sequence to different ranks in one channel.
on the formula
DDR2 and DDR3= BL/2 + TA
(Sheet 5 of 5)
Bit Access
Default
Value
Description
Encoding Turnaround
BL8 CMD
Spacing
101
6 turnaround
clocks on DQ
10
100
5 turnaround
clocks on DQ
9
011
4 turnaround
clocks on DQ
8
010
3 turnaround
clocks on DQ
7
001
2 turnaround
clocks on DQ
6
000
1 turnaround
clocks on DQ
5
Datasheet 265
Access: RO; R/W
Size: 32 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
29:28 R/W 01b
Read to Precharge (tRTP): These bits control the number
of clocks that are inserted between a read command to a
row precharge command to the same rank.
25:21 R/W 0Fh
Activate to Precharge delay (tRAS): This bit controls
the number of DRAM clocks for tRAS. Minimum
recommendations are beside their corresponding
encodings.
18 R/W 0b
Precharge to Precharge Delay: Control Pre to Pre delay
between the different banks of the same rank.
0 = 1 Clock
1 = 2 Clocks
15 R/W 1b
Pre-All to Activate Delay (tRPALL): This is applicable
only to 8-bank architectures. Must be set to 1 if any Rank is
populated with 8-bank device technology.
0 = tRPALL = tRP
1 = tRPALL = tRP + 1
12:10 R/W 001b
Activate to Activate Delay (tRRD): Control Act to Act
delay between the different banks of the same rank. Trr is
specified in ns. 10 ns for 2-KB page size and 7.5 ns for
1-KB page size. BIOS should round up to the nearest
number of clocks and use the maximum applicable value.
000 = 2 Clocks
001 = 3 Clocks
010 = 4 Clocks
011 = 5 Clocks
100 = 6 Clocks
9:8 RO 00b Reserved
266 Datasheet
7:5 R/W 011b
DRAM RASB to CASB Delay (tRCD): This bit controls the
number of clocks inserted between a row activate command
and a read or write command to that row.
4:3 RO 00b Reserved
2:0 R/W 011b
DRAM RASB Precharge (tRP): This bit controls the
number of clocks that are inserted between a row
precharge command and an activate command to the same
rank.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Encoding tRCD
000 2 DRAM Clocks
001 3 DRAM Clocks
010 4 DRAM Clocks
011 5 DRAM Clocks
100 6 DRAM Clocks
101 7 DRAM Clocks
110 8 DRAM Clocks
111 Reserved.
Encoding tRP
000 2 DRAM Clocks
001 3 DRAM Clocks
010 4 DRAM Clocks
011 5 DRAM Clocks
100 6 DRAM clocks
101 7 DRAM clocks
110 8 DRAM clocks
111 Reserved
Datasheet 267
Default Value: 2200105Fh
Access: RO; R/W
Size: 32 bits
This register shall retain its default values or be programmed as per the (G)MCH BIOS
specification.
Access: RO; R/W
Size: 32 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
25:23 R/W 010b
CASB Latency (tCL): This value is programmable on SO-
DIMMs. The value programmed here must match the CAS
Latency of every SO-DIMM in the system.
20:13 R/W 2Bh
Refresh Cycle Time (tRFC): Refresh cycle time is
measured from a Refresh command (REF) until the first
Activate command (ACT) to the same rank, required to
perform a read or write.
6:3 RO 0h Reserved
Encoding DDR2 CL DDR3 CL
000 3 3
001 4 4
010 5 5
011 6 6
100 7 7
101 Reserved 8
268 Datasheet
20.7.8 C0DRC0 - Channel 0 DRAM Controller Mode 0
Default Value: 4F000008h
Access: RO; R/W
Size: 32 bits
2:0 R/W 010b
Write Latency (tWL):
For DDR2 this register is programmed to CL -1
For DDR3 WL is based on DDR freq.
000 - 2 - DDR2 - CL3
001 - 3 - DDR2 - CL4
010 - 4 - DDR2 - CL5
011 - 5 - DDR2 - CL6 or DDR3 - 800
100 - 6 - DDR2 - CL7
101 - 7 - DDR2 - CL8
Others Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31:30 RO 01b
Revision Number (REV): Reflects the revision number
of the format used for SDRAM DDR register definition.
29 RO 0b Reserved
28 RO 0b Reserved
27:24 R/W Fh
Rank Enable Bits (RANKEN): These bits should be set
to 1 to enable the corresponding rank to come out of Self
refresh. The setting of the bit is either done by the
Firmware or BIOS.
Only those ranks that are populated will be woken up.
Writing a 1 to a non-populated rank will not have any
effect.
[25] = Rank 1
[24] = Rank 0
19:18 RO 00b
DRB Granularity (DRBG): The value in the DRBG field
sets the meaning given to the values in the set of DRB
registers.
00: Numbers in DRB registers represent 32-MB quantities
Other: Reserved
17 RO 0h Reserved
16 R/W 0h Reserved
15 RO 0h Reserved
14 RO 0b Reserved
Datasheet 269
Access: RO; R/W
Size: 32 bits
10:8 R/W 000b
Refresh Mode Select (RMS): This field determines
whether refresh is enabled and, if so, at what rate
refreshes will be executed.
000 = Refresh disabled
010 = Refresh enabled. Refresh interval 7.8 sec
011 = Refresh enabled. Refresh interval 3.9 sec
Other = Reserved.
7:4 RO 0h Reserved
3 R/W 1b
Burst Length (BL): The burst length is the number of
QWORDS returned by a SO-DIMM per read command,
when not interrupted. This bit is used to select the DRAM
controller's Burst Length operation mode. It must be set
to match to the behavior of the SO-DIMM.
1 = Burst Length of 8
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31 R/W 0b
Address Swap/XOR Enable:
0 = Swap and XOR modes disabled.
1 = Swap or XOR mode enabled.
30 R/W 0b Reserved
29:28 R/W 00b
Address Swap/XOR Mode:
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
11 = XOR Enabled for Bank Select only
27 RO 0b Reserved
19:16 R/W 0h
CKE Tristate Enable Per Rank: Bit 16 corresponds to
Rank 0 and Bit 19 corresponds to rank3
0 = CKE is not tri-stated.
1 = CKE is tri-stated. This is set only if the rank is physically
not populated.
15 RO 0b Reserved
14 RO 0b Reserved
270 Datasheet
20.7.10 C0GTEW - Channel 0 GMCH Throttling Event Weights
Access: R/W/L
Size: 32 bits
13 RO 0b Reserved
12 R/W 0b Reserved
11 R/W 0b Reserved
10 RO 0b Reserved
9 R/W 0b Reserved
8 RO 0b Reserved
7 RO 0b Reserved
6 R/W 0b Reserved
5:4 RO 00b Reserved
3 R/W 0b Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Bit
31:24 R/W/L 00h
Read Weight ():
This value is input to the filter if in a given clock there is a
valid read command being issued on the memory bus.
23:16 R/W/L 00h
Write Weight ():
valid write command being issued on the memory bus.
15:8 R/W/L 00h
Command Weight ():
valid command other than a read or a write being issued
on the memory bus.
7:0 R/W/L 00h
Idle Weight ():
This value is input to the filter if in a given clock there is no
command being issued on the memory bus. If command
and address are tri-stated a value of 0 is input to the filter.
If command and address are under reduced drive strength
this value is divided by 2 and input to the filter.
Datasheet 271
20.7.11 C0GTC - Channel 0 GMCH Throttling Control
Access: RO; R/W/L
Size: 32 bits
Bit Access
Default
Value
Bit
21 R/W/L 0b
GMCH Bandwidth based throttling enable (GBTE):
0 = Bandwidth Threshold (WAB) is not used for throttling.
1 = Bandwidth Threshold (WAB) is used for throttling.
If both Bandwidth based and thermal sensor based throttling
modes are on and the thermal sensor trips, the WAT Thermal
threshold are used for throttling.
20 R/W/L 0b
GMCH Thermal Sensor trip enable ():
0 = GMCH throttling is not initiated when the GMCH thermal
sensor trips.
1 = GMCH throttling is initiated when the GMCH thermal
sensor trips and the Filter output is equal to or exceeds
thermal threshold WAT.
15:8 R/W/L 00h
WAB (): Threshold allowed per clock for bandwidth based
throttling. GMCH does not allow transactions to proceed on
the DDR bus if the output of the filter equals or exceeds this
value.
7:0 R/W/L 00h
WAT (): Threshold allowed per clock during thermal sensor
enabled throttling. GMCH does not allow transactions to
proceed on the DDR bus if the output of the filter equals or
exceeds this value.
272 Datasheet
20.7.12 C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event
Access: RO; R/W/L
Size: 64 bits
Programmable Event weights that are entered into the averaging filter. Each Event
weight is a normalized 8-bit value that the BIOS must program. The BIOS must
account for burst length and 2N rule considerations. It is also possible for BIOS to take
into account type loading variations of memory caused as a function of memory types
and population of ranks. (G)MCH implements four, independent filters, one per rank. All
bits in this register can be locked by the DTLOCK bit in the C0DTC register.
Bit Access
Default
Value
Description
47:40 R/W/L 00h
Additive Weight for ODT: This value is added to the
total weight of a Rank if ODT on that rank is asserted.
Note that this value should reflect whether the DRAMs
have been programmed for 75 or 150- termination.
39:32 R/W/L 00h
Weight for Any Open Page during Active
(WAOPDA): This value is input to the filter if, during the
present clock, the corresponding rank has any pages open
and is not in power down. The value programmed here is
IDD3N from the JEDEC.
31:24 R/W/L 00h
All Banks Precharge Active (ABPA): This value is input
to the filter if, during the present clock, the corresponding
rank has all banks precharged but is not in power down.
The value programmed here is IDD2N from the JEDEC
spec.
23:16 R/W/L 00h
Weight for Any Open Page during Power Down
(WAOPDPD): This value is input to the filter if, during
the present clock, the corresponding rank is in power
down with pages open. The value programmed here is
IDD3P from the JEDEC.
15:8 R/W/L 00h
All Banks Precharge Power Down (ABPPD): This
value is input to the filter if, during the present clock, the
corresponding rank has all banks percharged and is
powered down. The value programmed here is IDD2P
from the JEDEC spec.
7:0 R/W/L 00h
Self Refresh: This value is input to the filter if in a clock
the corresponding rank is in self refresh.
Datasheet 273
20.7.13 C0DTAEW - Channel 0 DRAM Rank Throttling Active Event
Access: RO; R/W/L
Size: 64 bits
Programmable Event weights that are input into the averaging filter. Each event weight
is a normalized 8-bit value that the BIOS must program. The BIOS must account for
burst length and 2N rule considerations. It is also possible for BIOS to take into account
type loading variations of memory caused as a function of memory types and
population of ranks. (G)MCH implements four, independent filters, one per rank. In the
clock (G)MCH asserts a command to the DRAM (via CS# assertion) based on the
command type the one of the weights specified in this register is added to the weight
specified in the previous register and input to the filter.
Bit Access
Default
Value
Description
63:56 RO 00h Read with AP
55:48 RO 00h Write with AP
47:40 R/W/L 00h Read
39:32 R/W/L 00h Write
31:24 R/W/L 00h Precharge All
23:16 R/W/L 00h Precharge
15:8 R/W/L 00h Activate
7:0 R/W/L 00h Refresh
274 Datasheet
20.7.14 C0DTC - Channel 0 DRAM Throttling Control
Access: RO; R/W/L
Size: 32 bits
Programmable Event weights are input into the averaging filter. Each Event weight is a
normalized 8-bit value that the BIOS must program. The BIOS must account for burst
length and 2N rule considerations. It is also possible for BIOS to take into account type
loading variations of memory caused as a function of memory types and population of
ranks.
Bit Access
Default
Value
Description
21 R/W/L 0b
(G)MCH Bandwidth-Based Throttling Enable:
0 = Bandwidth Threshold WAB (Weighted Avg.
Bandwidth) is not used for throttling.
If both Bandwidth-based and thermal sensor-based
throttling modes are on and the thermal sensor trips, the
WAT (Weighted Avg. Threshold) Thermal threshold are
used for throttling.
20 R/W/L 0b
(G)MCH Thermal Sensor Trip Enable:
0 = (G)MCH throttling is not initiated when the (G)MCH
thermal sensor trips.
1 = (G)MCH throttling is initiated when the (G)MCH
thermal sensor trips and the Filter output is equal to
or exceeds thermal threshold WAT.
19 RO 0b Reserved
15:8 R/W/L 00h
WAB: Threshold allowed per clock for bandwidth based
throttling. (G)MCH does not allow transactions to proceed
on the DDR bus if the output of the filter equals or
exceeds this value.
7:0 R/W/L 00h
WAT: Threshold allowed per clock during for thermal
sensor enabled throttling. (G)MCH does not allow
transactions to proceed on the DDR bus if the output of
the filter equals or exceeds this value.
Datasheet 275
20.7.15 TSWDT0 - GMCH Thermal Sensor Watch Dog Timer 0
Access: RO; R/W/L
Size: 32 bits
When thermal sensor is indicating thermally hot tripped and GMCH throttling is
enabled, this register allows the value in the TSWDT0 [Delta] field to affect the impact
of the C0GTC [WAT] throttling threshold whenever the TSWDT0 WDT times outs.
The thermal sensor lock bit locks the following register bits.
Bit Access
Default
Value
RST/PWR Description
31:29 R/W/L 000b Core Reserved
28:21 R/W/L 00h Core
Clamp (): This register contains the
lowest value that WATeff is allowed to
reach. Clamp must be a value no greater
than WAT.
20:16 R/W/L 00000b Core Reserved
15:3 RO 00h Core Reserved
2:0 R/W/L 0h Core Reserved
276 Datasheet
20.7.16 C0DTWDT - Channel 0 DRAM Thermal Sensor Watch Dog
Timer
Access: RO; R/W/L
Size: 32 bits
When external thermal sensor is indicating thermally hot tripped and DRAM throttling is
enabled, this register allows the value in the [Delta] field to affect the impact of the
CxDTC [WAT] throttling threshold whenever the WDT times outs. If the actual average
memory traffic is at a level less than the clamp value during the thermal trip, memory
traffic will not be affected.
The Thermal Sensor Lock bit locks the following register bits.
20.7.17 C1DRB01 - Channel 1 DRAM Rank Boundary 0/1
Access: RO; R/W
Size: 32 bits
Bit settings for this register are identical to C0DRB01.
20.7.18 C1DRA - Channel 1 DRAM Rank 0,1 Attribute
Access: RO; R/W
Size: 32 bits
Bit settings for this register are identical to C0DRA.
Bit Access
Default
Value
Description
28:21 R/W/L 00h
Clamp (Clamp): This register contains the lowest value
that WATeff is allowed to reach. Clamp must be a value no
greater than WAT.
7:3 RO 00h Reserved
Datasheet 277
20.7.19 C1DCLKDIS - Channel 1 DRAM Clock Disable
Access: RO; R/W
Size: 32 bits
Bit settings for this register are identical to C0DCLKDIS.
Access: RO; R/W
Size: 32 bits
Bit settings for this register are identical to C0DRT0.
Access: RO; R/W
Size: 32 bits
Access: RO; R/W
Size: 32 bits
Access: RO; R/W
Size: 32 bits
278 Datasheet
Default Value: 4F000008h
Access: RO; R/W
Size: 32 bits
Bit settings for this register are identical to C0DRC0.
Access: RO; R/W
Size: 32 bits
Access: RO; R/W
Size: 32 bits
Datasheet 279
20.7.27 C1GTEW - Channel 1 GMCH Throttling Event Weights.
Access: R/W/L
Size: 32 bits
Bit Access
Default
Value
Bit
31:24 R/W/L 00h
Read Weight (): This value is input to the filter if in a given
clock there is a valid read command being issued on the
memory bus.
23:16 R/W/L 00h
Write Weight (): This value is input to the filter if in a given
clock there is a valid write command being issued on the
memory bus.
15:8 R/W/L 00h
Command Weight (): This value is input to the filter if in a
given clock there is a valid command other than a read or a
write being issued on the memory bus.
7:0 R/W/L 00h
Idle Weight (): This value is input to the filter if in a given
clock there is no command being issued on the memory bus.
If command and address are tri-stated a value of 0 is input
to the filter. If command and address are under reduced
drive strength this value is divided by 2 and input to the
filter.
280 Datasheet
20.7.28 C1GTC - Channel 1 GMCH Throttling Control
Access: RO; R/W/L
Size: 32 bits
20.7.29 C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event
Access: RO; R/W/L
Size: 64 bits
Bit settings for this register are identical to C0DTPEW.
20.7.30 C1DTAEW - Channel 1 DRAM Rank Throttling Active Event
Access: RO; R/W/L
Size: 64 bits
Bit settings for this register are identical to C0DTAEW.
Bit Access
Default
Value
Bit
21 R/W/L 0b
GMCH Bandwidth-Based Throttling Enable (GBTE):
0 = Bandwidth Threshold (WAB) is not used for throttling.
If both bandwidth-based and thermal sensor based throttling
modes are on and the thermal sensor trips, the WAT Thermal
threshold are used for throttling.
20 R/W/L 0b
GMCH Thermal Sensor Trip Enable ():
0 = GMCH throttling is not initiated when the GMCH thermal
sensor trips.
1 = GMCH throttling is initiated when the GMCH thermal
sensor trips and the Filter output is equal to or exceeds
thermal threshold WAT.
15:8 R/W/L 00h
WAB (): Threshold allowed per clock for bandwidth based
throttling. GMCH does not allow transactions to proceed on
the DDR bus if the output of the filter equals or exceeds this
value.
7:0 R/W/L 00h
WAT (): Threshold allowed per clock during thermal sensor
enabled throttling. GMCH does not allow transactions to
proceed on the DDR bus if the output of the filter equals or
exceeds this value.
Datasheet 281
20.7.31 C1DTC - Channel 1 DRAM Throttling Control
Access: RO; R/W/L
Size: 32 bits
Bit settings for this register are identical to C0DTC.
20.7.32 TSWDT1 - GMCH Thermal Sensor Watch Dog Timer 1
Access: RO; R/W/L
Size: 32 bits
Bit settings for this register are identical to TSWDT0.
20.7.33 C1DTWDT - Channel 1 DRAM Thermal Sensor Watch Dog
Timer
Access: RO; R/W/L
Size: 32 bits
Bit settings for this register are identical to C0DTWDT.
282 Datasheet
20.8 DMI RCRB
This section describes the mapped register for DMI. The DMIBAR register provides the
base address or these registers.
This Root Complex Register Block (RCRB) controls (G)MCH ICH9M serial interconnect.
An RCRB is required for configuration and control of element that are located internal to
root complex that are not directly associated with a PCI Express device. The base
address of this space is programmed in DMIBAR in Device 0 config space.
All RCRB register spaces needs to remain organized as they are here. The Virtual
Channel capabilities (or at least the first PCI Express Extended Capability) must begin
at the 0h offset of the 4-K area pointed to by the associated BAR. This is a PCI Express
Specification 1.1 requirement.
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
DMI Virtual Channel Enhanced
Capability
DMIVCECH 0 3 04010002h RO
DMI Port VC Capability Register 1 DMIPVCCAP1 4 7 00000001h RO; R/WO
DMI Port VC Capability Register 2 DMIPVCCAP2 8 B 00000001h RO
DMI Port VC Control DMIPVCCTL C D 0000h RO; R/W
DMI VC0 Resource Capability DMIVC0RCAP 10 13 00000001h RO
DMI VC0 Resource Control DMIVC0RCTL0 14 17 800000FFh RO; R/W
DMI VC0 Resource Status DMIVC0RSTS 1A 1B 0002h RO
DMI VC1 Resource Capability DMIVC1RCAP 1C 1F 00008001h RO
DMI VC1 Resource Control DMIVC1RCTL1 20 23 01000000h RO; R/W
DMI VC1 Resource Status DMIVC1RSTS 26 27 0002h RO
Reserved 28 33
DMI Root Complex Link Declaration DMIRCLDECH 40 43 08010005h RO
DMI Element Self Description DMIESD 44 47 01000202h RO; R/WO
DMI Link Entry 1 Description DMILE1D 50 53 00000000h RO; R/WO
DMI Link Entry 1 Address DMILE1A 58 5F
0000000000
000000h
RO; R/WO
DMI Link Entry 2 Description DMILE2D 60 63 00000000h RO; R/WO
DMI Link Entry 2 Address DMILE2A 68 6F
0000000000
000000h
RO; R/WO
DMI Root Complex Internal Link
Control
DMIRCILCECH 80 83 00010006h RO
DMI Link Capabilities DMILCAP 84 87 00012C41h RO; R/WO
DMI Link Control DMILCTL 88 89 0000h RO; R/W
DMI Link Status DMILSTS 8A 8B 0001h RO
Reserved F0 33B
Datasheet 283
20.8.1 DMIVCECH - DMI Virtual Channel Enhanced Capability
B/D/F/Type: 0/0/0/DMIBAR
Access: RO
Size: 32 bits
Indicates DMI Virtual Channel capabilities.
20.8.2 DMIPVCCAP1 - DMI Port VC Capability Register 1
Access: RO; R/WO
Size: 32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit Access
Default
Value
Description
31:20 RO 040h
PointertoNextCapability (PNC): This field contains the
offset to the next PCI Express* capability structure in the
linked list of capabilities (Link Declaration Capability).
19:16 RO 1h
PCIExpressVirtualChannelCapabilityVersion
(PCIEVCCV): Hardwired to 1 to indicate compliances with
the 1.0 version of the PCI Express Specification.
15:0 RO 0002h
ExtendedCapabilityID (ECID): Value of 0002 h identifies
this linked list item (capability structure) as being for PCI
Express Virtual Channel registers.
Bit Access
Default
Value
Description
31:7 RO
0000000
h
Reserved
6:4 RO 000b
LowPriorityExtendedVCCount (LPEVCC): Indicates the
number of (extended) Virtual Channels in addition to the
default VC belonging to the low-priority VC (LPVC) group
that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
3 RO 0b Reserved
2:0 R/WO 001b
ExtendedVCCount (EVCC): Indicates the number of
(extended) Virtual Channels in addition to the default VC
supported by the device.
The Private Virtual Channel is not included in this count.
284 Datasheet
20.8.3 DMIPVCCAP2 - DMI Port VC Capability Register 2
Access: RO
Size: 32 bits
20.8.4 DMIPVCCTL - DMI Port VC Control
Address Offset: C-Dh
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
7:0 RO 01h
VCArbitrationCapability (VCAC): Indicates that the only
possible VC arbitration scheme is hardware fixed (in the
root complex). VC1 is the highest priority and VC0 is the
lowest priority.
Bit Access
Default
Value
Description
3:1 R/W 000b
VCArbitrationSelect (VCAS): This field will be
programmed by software to the only possible value as
indicated in the VC Arbitration Capability field. The value
000b when written to this field will indicate the VC
arbitration scheme is hardware fixed (in the root
complex). This field cannot be modified when more than
one VC in the LPVC group is enabled.
000 = Hardware fixed arbitration scheme, e.g., Round
Robin
Others = Reserved. See the PCI Express Specification for
more details
0 RO 0b ReservedforLoadVCArbitrationTable
Datasheet 285
20.8.5 DMIVC0RCAP - DMI VC0 Resource Capability
Access: RO
Size: 32 bits
20.8.6 DMIVC0RCTL0 - DMI VC0 Resource Control
Access: RO; R/W
Size: 32 bits
Controls the resources associated with PCI Express Virtual Channel 0.
Bit Access
Default
Value
Description
31:24 RO 00h ReservedforPortArbitrationTableOffset:
23 RO 0b Reserved
22:16 RO 00h ReservedforMaximumTimeSlots:
15 RO 0b
RejectSnoopTransactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set within
the TLP header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the
TLP header will be rejected as an Unsupported Request.
7:0 RO 01h
PortArbitrationCapability (PAC): Having only Bit 0 set
indicates that the only supported arbitration scheme for this
VC is non-configurable hardware-fixed.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31 RO 1b
VirtualChannel0Enable (VC0E): For VC0 this is
hardwired to 1 and read only as VC0 can never be disabled.
26:24 RO 000b
VirtualChannel0ID (VC0ID): Assigns a VC ID to the VC
resource. For VC0 this is hardwired to 0 and read only.
19:17 R/W 000b
PortArbitrationSelect (PAS): Configures the VC resource
to provide a particular Port Arbitration service. Valid value
for this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the
VC resource. Because only Bit 0 of that field is asserted.
This field will always be programmed to 1.
286 Datasheet
20.8.7 DMIVC0RSTS - DMI VC0 Resource Status
Access: RO
Size: 16 bits
Reports the Virtual Channel specific status.
7:1 R/W 7Fh
TrafficClass/VirtualChannel0Map (TCVC0M): Indicates
the TCs (Traffic Classes) that are mapped to the VC
resource. Bit locations within this field correspond to TC
values.
For example, when Bit 7 is set in this field, TC7 is mapped
to this VC resource. When more than one bit in this field is
set, it indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the TC/
VC Map of an enabled VC, software must ensure that no
new or outstanding transactions with the TC labels are
targeted at the given Link.
0 RO 1b
TrafficClass0/VirtualChannel0Map (TC0VC0M): Traffic
Class 0 is always routed to VC0.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
1 RO 1b
VirtualChannel0NegotiationPending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as
whenever the corresponding Virtual Channel is Disabled
or the Link is in the DL_Down state. It is cleared when the
link successfully exits the FC_INIT2 state. BIOS
Requirement: Before using a Virtual Channel, software
must check whether the VC Negotiation Pending fields for
that Virtual Channel are cleared in both Components on a
Link.
0 RO 0b Reserved
Datasheet 287
20.8.8 DMIVC1RCAP - DMI VC1 Resource Capability
Access: RO
Size: 32 bits
20.8.9 DMIVC1RCTL1 - DMI VC1 Resource Control
Access: RO; R/W
Size: 32 bits
Bit Access
Default
Value
Description
23 RO 0b Reserved
15 RO 1b
RejectSnoopTransactions (REJSNPT):
7:0 RO 01h
PortArbitrationCapability (PAC): Having only Bit 0 set
indicates that the only supported arbitration scheme for this
VC is non-configurable hardware-fixed.
288 Datasheet
Bit Access
Default
Value
Description
31 R/W 0b
VirtualChannel1Enable (VC1E):
0: Virtual Channel is disabled.
1: Virtual Channel is enabled. See exceptions below.
Software must use the VC Negotiation Pending bit to
check whether the VC negotiation is complete. When VC
Negotiation Pending bit is cleared, a 1 read from this VC
Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express port). A 0
read from this bit indicates that the Virtual Channel is
currently disabled.BIOS Requirement:
1. To enable a Virtual Channel, the VC Enable bits for that
Virtual Channel must be set in both Components on a
Link.
2. To disable a Virtual Channel, the VC Enable bits for that
Virtual Channel must be cleared in both Components
on a Link.
3. Software must ensure that no traffic is using a Virtual
Channel at the time it is disabled.
4. Software must fully disable a Virtual Channel in both
Components on a Link before re-enabling the Virtual
Channel.
26:24 R/W 001b
VirtualChannel1ID (VC1ID): Assigns a VC ID to the VC
resource. Assigned value must be non-zero. This field can
not be modified when the VC is already enabled.
19:17 R/W 000b
PortArbitrationSelect (PAS): Configures the VC
resource to provide a particular Port Arbitration service.
Valid value for this field is a number corresponding to one
of the asserted bits in the Port Arbitration Capability field
of the VC resource.
7:1 R/W 00h
TrafficClass/VirtualChannel1Map (TCVC1M):
Indicates the TCs (Traffic Classes) that are mapped to the
VC resource. Bit locations within this field correspond to
TC values.
For example, when Bit 7 is set in this field, TC7 is mapped
to this VC resource. When more than one bit in this field
is set, it indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the
TC/VC Map of an enabled VC, software must ensure that
no new or outstanding transactions with the TC labels are
0 RO 0b
TrafficClass0/VirtualChannel1Map (TC0VC1M):
Traffic Class 0 is always routed to VC0.
Datasheet 289
20.8.10 DMIVC1RSTS - DMI VC1 Resource Status
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:2 RO 0000h
Reserved: Reserved and Zero for future implementations.
Software must use 0 for writes to these bits.
1 RO 1b
VirtualChannel1NegotiationPending (VC1NP):
(initialization or disabling). Software may use this bit
when enabling or disabling the VC. This bit indicates the
status of the process of Flow Control initialization. It is
set by default on Reset, as well as whenever the
corresponding Virtual Channel is Disabled or the Link is
in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state. Before using a
Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are
cleared in both Components on a Link.
0 RO 0b Reserved
290 Datasheet
20.8.11 DMIRCLDECH - DMI Root Complex Link Declaration
Access: RO
Size: 32 bits
This capability declares links from the respective element to other elements of the root
complex component to which it belongs and to an element in another root complex
component. See the PCI Express Specification for link/topology declaration
requirements.
Bit Access
Default
Value
Description
31:20 RO 080h
PointertoNextCapability (PNC): This field contains the
offset to the next PCI Express capability structure in the
linked list of capabilities (Internal Link Control Capability).
19:16 RO 1h
LinkDeclarationCapabilityVersion (LDCV): Hardwired
to 1 to indicate compliances with the 1.0 version of the
PCI Express Specification.
15:0 RO 0005h
ExtendedCapabilityID (ECID): Value of 0005 h
identifies this linked list item (capability structure) as
being for PCI Express Link Declaration Capability.
Datasheet 291
20.8.12 DMIESD - DMI Element Self Description
Access: RO; R/WO
Size: 32 bits
Provides information about the root complex element containing this Link Declaration
Capability.
Bit Access
Default
Value
Description
31:24 RO 01h
PortNumber (PORTNUM): Specifies the port number
associated with this element with respect to the component
that contains this element. This port number value is
utilized by the egress port of the component to provide
arbitration to this Root Complex Element.
23:16 R/WO 00h
ComponentID (CID): Identifies the physical component
that contains this Root Complex Element.
BIOS Requirement: Must be initialized according to
guidelines in the PCI Express Isochronous/Virtual Channel
Support Hardware Programming Specification (HPS).
15:8 RO 02h
NumberofLinkEntries (NLE): Indicates the number of link
entries following the Element Self Description. This field
reports 2 (one for MCH egress port to main memory and
one to egress port belonging to ICH on other side of internal
link).
7:4 RO 0h Reserved
3:0 RO 2h
ElementType (ETYP): Indicates the type of the Root
Complex Element.
Value of 2 h represents an Internal Root Complex Link
(DMI).
292 Datasheet
20.8.13 DMILE1D - DMI Link Entry 1 Description
Access: R/WO; RO
Size: 32 bits
The first part of a Link Entry which declares an internal link to another Root Complex
Element.
Bit Access
Default
Value
Description
31:24 R/WO 00h
TargetPortNumber (TPN): Specifies the port number
associated with the element targeted by this link entry
(egress port of ICH). The target port number is with
respect to the component that contains this element as
specified by the target component ID.
This can be programmed by BIOS, but the default value
will likely be correct because the DMI RCRB in the ICH will
likely be associated with the default egress port for the
ICH meaning it will be assigned port number 0.
23:16 R/WO 00h
TargetComponentID (TCID): Identifies the physical
component that is targeted by this link entry. BIOS
Requirement: Must be initialized according to guidelines
in the PCI Express Isochronous/Virtual Channel Support
Hardware Programming Specification (HPS).
1 RO 0b
LinkType (LTYP): Indicates that the link points to
memory-mapped space (for RCRB).
The link address specifies the 64-bit base address of the
target RCRB.
0 R/WO 0b
LinkValid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Datasheet 293
20.8.14 DMILE1A - DMI Link Entry 1 Address
Access: RO; R/WO
Size: 64 bits
Second part of a Link Entry which declares an internal link to another Root Complex
Element.
20.8.15 DMILE2D - DMI Link Entry 2 Description
Access: RO; R/WO
Size: 32 bits
First part of a Link Entry which declares an internal link to another Root Complex
Element.
Bit Access
Default
Value
Description
63:32 RO 00000000h
Reserved: Reserved for Link Address high order 32
bits.
31:12 R/WO 00000h
LinkAddress (LA): Memory mapped base address of
the RCRB that is the target element (egress port of
ICH) for this link entry.
Bit Access
Default
Value
Description
31:24 RO 00h
TargetPortNumber (TPN): Specifies the port number
(Egress Port). The target port number is with respect to the
component that contains this element as specified by the
target component ID.
23:16 R/WO 00h
TargetComponentID (TCID): Identifies the physical or
logical component that is targeted by this link entry. BIOS
Requirement: Must be initialized according to guidelines in
the PCI Express Isochronous/Virtual Channel Support
1 RO 0b
LinkType (LTYP): Indicates that the link points to
memory-mapped space (for RCRB).
The link address specifies the 64-bit base address of the
target RCRB.
0 R/WO 0b
LinkValid (LV):
294 Datasheet
20.8.16 DMILE2A - DMI Link Entry 2 Address
Access: RO; R/WO
Size: 64 bits
Element.
20.8.17 DMIRCILCECH - DMI Root Complex Internal Link Control
Access: RO
Size: 32 bits
This capability contains controls for the Root Complex Internal Link known as DMI.
Bit Access
Default
Value
Description
63:32 RO 00000000h
Reserved: Reserved for Link Address high order 32
bits.
31:12 R/WO 00000h
LinkAddress (LA): Memory mapped base address of
the RCRB that is the target element (Egress Port) for
this link entry.
Bit Access
Default
Value
Description
31:20 RO 000h
PointertoNextCapability (PNC): This value terminates
the PCI Express extended capabilities list associated with
this RCRB.
19:16 RO 1h
LinkDeclarationCapabilityVersion (LDCV): Hardwired
to 1 to indicate compliances with the 1.0 version of the
PCI Express Specification.
15:0 RO 0006h
ExtendedCapabilityID (ECID): Value of 0006 h
being for PCI Express Internal Link Control Capability.
Datasheet 295
20.8.18 DMILCAP - DMI Link Capabilities
Default Value: 00012C41h
Access: RO; R/WO
Size: 32 bits
Indicates DMI specific capabilities.
20.8.19 DMILCTL - DMI Link Control
Access: RO; R/W
Size: 16 bits
Allows control of DMI.
Bit Access
Default
Value
Description
17:15 R/WO 010b Reserved
14:12 R/WO 010b Reserved
11:10 RO 11b
ActiveStateLinkPMSupport (ASLPMS):
11 = L0s & L1 entry supported.
9:4 RO 04h
MaxLinkWidth (MLW): Indicates the maximum number
of lanes supported for this link
3:0 RO 1h MaxLinkSpeed (MLS): Hardwired to indicate 2.5 Gb/s.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
7 R/W 0b
ExtendedSynch (EXTSYNC):
0 = Standard Fast Training Sequence (FTS).
1 = Forces extended transmission of 4096 FTS ordered sets
in the L0s state followed by a single SKP Ordered Set
prior to entering L0, and the transmission of 1024 TS1
ordered sets in the RecoveryRcvrLock state prior to
entering the RecoveryRcvrCfg state.This mode provides
external devices monitoring the link time to achieve bit
and symbol lock before the link enters L0 state and
resumes communication. This is a test mode only and
may cause other undesired side effects such as buffer
overflows or underruns.
296 Datasheet
20.8.20 DMILSTS - DMI Link Status
Access: RO
Size: 16 bits
Indicates DMI status.
2 R/W 0b Reserved
1:0 R/W 00b
ActiveStatePowerManagementSupport (ASPMS):
Controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
9:4 RO 00h
Negotiated Width (NWID): Indicates negotiated link
width. This field is valid only when the link is in the L0,
L0s, or L1 states (after link width negotiation is
successfully completed).
All other encodings are reserved.
3:0 RO 1h
Negotiated Speed (NSPD): Indicates negotiated link
speed.
1h:2.5 Gb/s
0h: Reserved
1h: X1
2h: X2
4h: X4
Datasheet 297
20.9 Egress Port (EP) RCRB
This Root Complex Register Block (RCRB) controls the port arbitration that is based on
the PCI Express Specification. Port arbitration is done for all PCI Express-based
isochronous requests (always on Virtual Channel 1) before being submitted to the main
memory arbiter. The base address of this space is programmed in the EPBAR in
Device-0 config space.
Register Name
Register
Symbol
Register
Start
Register
End
EP Virtual Channel Enhanced
Capability
EPVCECH 0 3 04010002h RO
EP Port VC Capability Register 1 EPPVCCAP1 4 7 00000401h RO; R/WO
EP Port VC Capability Register 2 EPPVCCAP2 8 B 00000001h RO
EP Port VC Control EPPVCCTL C D 0000h RO; R/W
EP VC 0 Resource Capability EPVC0RCAP 10 13 00000001h RO
EP VC 0 Resource Control EPVC0RCTL 14 17 800000FFh RO; R/W
EP VC 0 Resource Status EPVC0RSTS 1A 1B 0000h RO
EP VC 1 Resource Capability EPVC1RCAP 1C 1F 10008010h RO; R/WO
EP VC 1 Resource Control EPVC1RCTL 20 23 01080000h
RO; R/W;
R/W/S
EP VC 1 Resource Status EPVC1RSTS 26 27 0000h RO
EP VC 1 Maximum Number of
Time Slots
EPVC1MTS 28 2B 04050609h R/W
EP VC 1 Isoch Timing Control EPVC1ITC 2C 2F 00000000h RO; R/W
EP VC 1 Isoch Slot Time EPVC1IST 38 3F
00000000000000
00h
R/W
EP Root Complex Link
Declaration
EPRCLDECH 40 43 00010005h RO
EP Element Self Description EPESD 44 47 00000201h RO; R/WO
EP Link Entry 1 Description EPLE1D 50 53 01000000h RO; R/WO
EP Link Entry 1 Address EPLE1A 58 5F
00000000000000
00h
RO; R/WO
EP Link Entry 2 Description EPLE2D 60 63 02000002h RO; R/WO
EP Link Entry 2 Address EPLE2A 68 6F
00000000000080
00h
RO
Port Arbitration Table PORTARB 100 11F
00000000000000
00000000000000
00000000000000
00000000000000
00000000h
R/W
298 Datasheet
20.9.1 EPVCECH - EP Virtual Channel Enhanced Capability
B/D/F/Type: 0/0/0/EPBAR
Access: RO
Size: 32 bits
Indicates Egress Port Virtual Channel capabilities.
20.9.2 EPPVCCAP1 - EP Port VC Capability Register 1
Access: RO; R/WO
Size: 32 bits
Bit Access
Default
Value
Description
31:20 RO 040h
Pointer to Next Capability (PNC): This field contains
the offset to the next PCI Express capability structure in
the linked list of capabilities (Link Declaration Capability).
Bits [21:20] are reserved and software must mask them
to allow for future uses of these bits.
19:16 RO 1h
PCI Express Virtual Channel Capability Version
(PCIEVCCV): Hardwired to 1 to indicate compliances
with the PCI Express Specification.
15:0 RO 0002h
Extended Capability ID (ECID): Value of 0002h
being for PCI Express Virtual Channel registers.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
11:10 RO 01b
Port Arbitration Table Entry Size (PATES): Indicates
that the size of the Port Arbitration table entry is 2 bits.
9:8 RO 00b
Reference Clock (RC): Indicates the reference clock for
Virtual Channels that support time-based WRR Port
Arbitration.
00 = 100 ns
7 RO 0b Reserved
Datasheet 299
20.9.3 EPPVCCAP2 - EP Port VC Capability Register 2
Access: RO
Size: 32 bits
6:4 RO 000b
Low Priority Extended VC Count (LPEVCC): Indicates
the number of (extended) Virtual Channels in addition to
the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other
VC resources in a strict-priority VC Arbitration. The value
of 0 in this field implies strict VC arbitration.
3 RO 0b Reserved
2:0 R/WO 001b
Extended VC Count (EVCC): Indicates the number of
supported by the device.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
7:0 RO 01h
VC Arbitration Capability (VCAC): Indicates the VC
arbitration is fixed in the root complex. VC1 is the highest
priority, VCp (private VC) is next in priority, and VC0 is the
lowest priority.
300 Datasheet
20.9.4 EPPVCCTL - EP Port VC Control
Address Offset: C-Dh
Access: RO; R/W
Size: 16 bits
20.9.5 EPVC0RCAP - EP VC 0 Resource Capability
Access: RO
Size: 32 bits
Bit Access
Default
Value
Description
3:1 R/W 000b
VC Arbitration Select (VCAS): This field will be
indicated in the VC Arbitration Capability field. The value
complex). This field cannot be modified when more than
0 RO 0b Reserved for Load VC Arbitration Table
Bit Access
Default
Value
Description
23 RO 0b Reserved
15 RO 0b
Reject Snoop Transactions (RSNPT):
0 = Transactions with or without the No Snoop bit set
within the TLP header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within
the TLP header will be rejected as an Unsupported
Request.
7:0 RO 01h
Port Arbitration Capability (PAC): Indicates types of
Port Arbitration supported by this VC0 resource. The
default value of 01h indicates that the only port
arbitration capability for VC0 is non-configurable,
hardware-fixed arbitration scheme.
Datasheet 301
20.9.6 EPVC0RCTL - EP VC 0 Resource Control
Access: RO; R/W
Size: 32 bits
Controls the resources associated with Egress Port Virtual Channel 0.
Bit Access
Default
Value
Description
31 RO 1b
VC0 Enable (VC0E): For VC0 this is hardwired to 1 and
read only as VC0 can never be disabled.
26:24 RO 000b
VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For
VC0 this is hardwired to 0 and read only.
19:17 RO 000b
Port Arbitration Select (PAS): This field configures the
VC resource to provide a particular Port Arbitration service.
The value of 0h corresponds to the bit position of the only
asserted bit in the Port Arbitration Capability field.
7:1 R/W 7Fh
TC/VC0 Map (TCVC0M): Indicates the TCs (Traffic
Classes) that are mapped to the VC resource. Bit locations
within this field correspond to TC values. For example, when
Bit 7 is set in this field, TC7 is mapped to this VC resource.
When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to
remove one or more TCs from the TC/VC Map of an enabled
VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given
Link.
0 RO 1b
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always
routed to VC0.
302 Datasheet
20.9.7 EPVC0RSTS - EP VC 0 Resource Status
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
1 RO 0b
VC0 Negotiation Pending (VC0NP):
(initialization or disabling). For this default VC, this bit
indicates the status of the process of Flow Control
initialization. Before using a Virtual Channel, software
must check whether the VC Negotiation Pending fields
for that Virtual Channel are cleared in both
Components on a Link.
0 RO 0b Reserved
Datasheet 303
20.9.8 EPVC1RCAP - EP VC 1 Resource Capability
Access: RO; R/WO
Size: 32 bits
Bit Access
Default
Value
Description
31:24 RO 10h
Port Arbitration Table Offset (PATO): Indicates the
location of the Port Arbitration Table associated with the
Egress Port VC1. This field contains the zero-based offset of
the table in DQWORDS (16 bytes) from the base address of
the Virtual Channel Capability Structure. The default value
of 10h translates to the Port Arbitration Table beginning at
offset 100h.
23 RO 0b Reserved
22:16 R/WO 00h
Maximum Time Slots (MTS): Indicates the maximum
number of timeslots (minus one) that the VC resource is
capable of supporting when it is configured for time-based
WRR Port Arbitration. See the EP VC 1 Maximum Number of
Time Slots register from which system initialization software
will select the appropriate value for this field.
15 RO 1b
7:0 RO 10h
Port Arbitration Capability (PAC): Indicates types of
Port Arbitration supported by this VC1 resource.The default
value of 10h indicates that only Bit 4 is set, reporting as our
only port arbitration capability Time-Based Weighted Round
Robin (WRR) arbitration with 128 phases.
304 Datasheet
20.9.9 EPVC1RCTL - EP VC 1 Resource Control
Access: RO; R/W; R/W/S
Size: 32 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31 R/W 0b
VC1 Enable (VC1E): This bit will be ignored by the
hardware. The bit is R/W for specification compliance, but
writing to it will result in no behavior change in the
hardware (other than the bit value reflecting the written
value).
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions in note
below.
Software must use the VC Negotiation Pending bit to
check whether the VC negotiation is complete. When VC
Negotiation Pending bit is cleared, a 1 read from this VC
Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express port). A 0
read from this bit indicates that the Virtual Channel is
currently disabled.
NOTES:
1. To enable a Virtual Channel, the VC Enable bits for
that Virtual Channel must be set in both
2. To disable a Virtual Channel, the VC Enable bits for
that Virtual Channel must be cleared in both
3. Software must ensure that no traffic is using a
Virtual Channel at the time it is disabled.
4. Software must fully disable a Virtual Channel in
both Components on a Link before re-enabling the
Virtual Channel.
26:24 R/W 001b
VC1 ID (VC1ID): Assigns a VC ID to the VC resource.
Assigned value must be non-zero. This field cannot be
modified when the VC is already enabled.
19:17 R/W 100b
Port Arbitration Select (PAS): This field configures the
VC resource to provide a particular Port Arbitration
service. The default value of 4h corresponds to bit
position of the only asserted bit in the Port Arbitration
Capability field.
Datasheet 305
20.9.10 EPVC1RSTS - EP VC 1 Resource Status
Access: RO
Size: 16 bits
16 R/W/S 0b
Load Port Arbitration Table (LPAT): Software sets this
bit (writes a 1) to signal hardware to update the Port
Arbitration logic with new values stored in the Port
Arbitration Table.
Software uses the Port Arbitration Table Status bit to
confirm whether the new values of Port Arbitration Table
are completely latched by the arbitration logic. Clearing
this bit has no effect.
This bit always returns 0 when read.
7:1 R/W 00h
within this field correspond to TC values. For example,
when Bit 7 is set in this field, TC7 is mapped to this VC
resource.
When more than one bit in this field is set, it indicates
that multiple TCs are mapped to the VC resource. In order
to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or
outstanding transactions with the TC labels are targeted
at the given link.
0 RO 0b
routed to VC0.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
1 RO 0b
(initialization or disabling). For this non-default Virtual
Channel, software may use this bit when enabling or
disabling the VC. Before using a Virtual Channel,
software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in
both Components on a Link.
306 Datasheet
20.9.11 EPVC1MTS - EP VC 1 Maximum Number of Time Slots
Access: R/W
Size: 32 bits
The fields in this register reflect the maximum number of time slots supported by the
(G)MCH for time based arbitration in various configurations.
20.9.12 EPVC1ITC - EP VC 1 Isoch Timing Control
Access: RO; R/W
Size: 32 bits
This register reflects the number of common host clocks (Hclks) per Port Arbitration
Table phase.
20.9.13 EPVC1IST - EP VC 1 Isoch Slot Time
Access: R/W
Size: 64 bits
This register reflects the number of common host clocks per time slot.
0 RO 0b
Port Arbitration Table Status (PATS): Indicates the
coherency status of the Port Arbitration Table associated
with EP VC1.
0 = Hardware has finished loading values stored in the Port
Arbitration Table after software set the Load Port
Arbitration Table field.
1 = An entry in the Port Arbitration Table is being written to
by software.
Note that this bit will never be set to the value of 1 because
loading the Port Arbitration Table is Non-posted. It will not
complete on the FSB until the table loading is finished.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 307
20.9.14 EPRCLDECH - EP Root Complex Link Declaration
Access: RO
Size: 32 bits
This capability declares links from the respective element to other elements of the root
complex component to which it belongs. See the PCI Express Specification for link/
topology declaration requirements.
Bit Access
Default
Value
Description
31:20 RO 000h
Pointer to Next Capability (PNC): This value terminates
the PCI Express extended capabilities list associated with
this RCRB.
19:16 RO 1h
Link Declaration Capability Version (LDCV): Hardwired
to 1 to indicate compliances with the 1.0 version of the PCI
Express Specification.
15:0 RO 0005h
Extended Capability ID (ECID): Value of 0005 h
identifies this linked list item (capability structure) as being
for PCI Express Link Declaration Capability.
308 Datasheet
20.9.15 EPESD - EP Element Self Description
Access: RO; R/WO
Size: 32 bits
Capability.
Bit Access
Default
Value
Description
31:24 RO 00h
Port Number (PN): This field specifies the port number
associated with this element with respect to the
component that contains this element. Value of 00 h
indicates to configuration software that this is the default
egress port.
23:16 R/WO 00h
Component ID (CID): Identifies the physical component
15:8 RO 02h
Number of Link Entries (NLE): Indicates the number of
link entries following the Element Self Description. This
field reports 2 (one each for PCI Express graphics and
DMI).
7:4 RO 0h Reserved
3:0 RO 1h
Element Type (ET): Indicates the type of the Root
Complex Element. Value of 1 h represents a port to
system memory.
Datasheet 309
20.9.16 EPLE1D - EP Link Entry 1 Description
Access: RO; R/WO
Size: 32 bits
Element.
Bit Access
Default
Value
Description
31:24 RO 01h
Target Port Number (TPN): Specifies the port number
(DMI). The target port number is with respect to the
component that contains this element as specified by the
target component ID.
23:16 R/WO 00h
Target Component ID (TCID): Identifies the physical or
logical component that is targeted by this link entry. BIOS
Requirement: Must be initialized according to guidelines in
the PCI Express Isochronous/Virtual Channel Support
1 RO 0b
Link Type (LTYP): Indicates that the link points to
memory-mapped space (for RCRB). The link address
specifies the 64-bit base address of the target RCRB.
0 R/WO 0b
Link Valid (LV):
310 Datasheet
20.9.17 EPLE1A - EP Link Entry 1 Address
Access: RO; R/WO
Size: 64 bits
Element.
20.9.18 EPLE2D - EP Link Entry 2 Description
Access: RO; R/WO
Size: 32 bits
Element.
Bit Access
Default
Value
Description
63:32 RO 00000000h Reserved for Link Address High Order 32 Bits
31:12 R/WO 00000h
Link Address (LA): Memory mapped base address of
the RCRB that is the target element (DMI) for this link
entry.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31:24 RO 02h
(PCI Express graphics). The target port number is with
respect to the component that contains this element as
specified by the target component ID.
23:16 R/WO 00h
Target Component ID (TCID): Identifies the physical
or logical component that is targeted by this link entry. A
value of 0 is reserved. Component IDs start at 1. This
value is a mirror of the value in the Component ID field of
all elements in this component. BIOS Requirement: Must
be initialized according to guidelines in the PCI Express
Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
1 RO 1b
configuration space of the integrated device which
controls the x16 root port. The link address specifies the
configuration address (segment, bus, device, function) of
the target root port.
Datasheet 311
20.9.19 EPLE2A - EP Link Entry 2 Address
Access: RO
Size: 64 bits
Element.
20.9.20 PORTARB - Port Arbitration Table
Default Value: 0000000000000000000000000000000000000000
000000000000000000000000h
Access: R/W
Size: 256 bits
The Port Arbitration Table register is a read-write register array that is used to store the
arbitration table for Port Arbitration of the Egress Port VC resource.

0 R/WO 0b
Link Valid (LV):
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
63:28 RO
0000000
00h
Reserved for Configuration Space Base Address: Not
required if root complex has only one config space.
27:20 RO 00h Bus Number (BUSN)
19:15 RO 00001b
Device Number (DEVN): Target for this link is PCI
Express x16 port (Device 1).
14:12 RO 000b Function Number (FUNN)
312 Datasheet
Datasheet 313
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
21 PCI Express Graphics Device 1
Configuration Registers (D1:F0)
Device 1 contains the controls associated with the x16 root port that is the intended
attach point for external graphics. It is typically referred to as PCI Express graphics
port. It also functions as the virtual PCI-to-PCI bridge that was previously associated
with AGP.
When reading the PCI Express conceptual registers such as these, you may not get a
valid value unless the register value is stable.
The PCI Express Specification defines two types of reserved bits:
Reserved and Preserved: Reserved for future R/W implementations; software must
preserve value read for writes to these bits.
Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to these bits.
Note: Unless explicitly documented as Reserved and Zero, all bits marked as Reserved are
part of the Reserved and Preserved type which has historically been the typical
definition for Reserved.
Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first disable the link, then program the registers, then re-enable
the link (which will cause a full-retrain with the new settings).
21.1 PCI Express Graphics Device 1 Function 0
Configuration Registers
(Sheet 1 of 3)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Vendor Identification VID1 0 1 8086h RO
Device Identification DID1 2 3 2A41h RO
PCI Command PCICMD1 4 5 0000h RO; R/W
PCI Status PCISTS1 6 7 0010h RO; R/WC
Revision Identification RID1 8 8 00h RO
Class Code CC1 9 B 060400h RO
Cache Line Size CL1 C C 00h R/W
Header Type HDR1 E E 01h RO
Primary Bus Number PBUSN1 18 18 00h RO
Secondary Bus Number SBUSN1 19 19 00h R/W
Subordinate Bus Number SUBUSN1 1A 1A 00h R/W
I/O Base Address IOBASE1 1C 1C F0h RO; R/W
I/O Limit Address IOLIMIT1 1D 1D 00h RO; R/W
314 Datasheet
Secondary Status SSTS1 1E 1F 0000h R/WC; RO
Memory Base Address MBASE1 20 21 FFF0h RO; R/W
Memory Limit Address MLIMIT1 22 23 0000h RO; R/W
Prefetchable Memory Base
Address
PMBASE1 24 25 FFF1h RO; R/W
Prefetchable Memory Limit
Address
PMLIMIT1 26 27 0001h RO; R/W
Prefetchable Memory Base
Address
PMBASEU1 28 2B 0000000Fh R/W
Prefetchable Memory Limit
Address
PMLIMITU1 2C 2F 00000000h R/W
Capabilities Pointer CAPPTR1 34 34 88h RO
Interrupt Line INTRLINE1 3C 3C 00h R/W
Interrupt Pin INTRPIN1 3D 3D 01h RO
Bridge Control BCTRL1 3E 3F 0000h RO; R/W
Capabilities List Control CAPL 7F 7F 02h RO; R/W
Power Management
Capabilities
PM_CAPID1 80 83 C8039001h RO
Power Management Control/
Status
PM_CS1 84 87 00000000h
RO; R/W/S;
R/W
Subsystem ID and Vendor ID
Capabilities
SS_CAPID 88 8B 0000800Dh RO
Subsystem ID and
Subsystem Vendor ID
SS 8C 8F 00008086h R/WO
Message Signaled Interrupts
Capability ID
MSI_CAPID 90 91 A005h RO
Message Control MC 92 93 0000h RO; R/W
Message Address MA 94 97 00000000h RO; R/W
Message Data MD 98 99 0000h R/W
PCI Express Graphics
Capability List
PEG_CAPL A0 A1 0010h RO
Capabilities
PEG_CAP A2 A3 0141h RO; R/WO
Device Capabilities DCAP A4 A7 00008000h RO
Device Control DCTL A8 A9 0000h RO; R/W
Device Status DSTS AA AB 0000h RO; R/WC
Link Capabilities LCAP AC AF 02012D01h RO; R/WO
Link Control LCTL B0 B1 0040h RO; R/W
Link Status LSTS B2 B3 1001h RO
Slot Capabilities SLOTCAP B4 B7 00040040h R/WO; RO
Slot Control SLOTCTL B8 B9 01C0h RO; R/W
(Sheet 2 of 3)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Datasheet 315
21.1.1 VID1 - Vendor Identification
Access: RO
Size: 16 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
21.1.2 DID1 - Device Identification
Access: RO
Size: 16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Slot Status SLOTSTS BA BB 0000h RO; R/WC
Root Control RCTL BC BD 0000h RO; R/W
Root Status RSTS C0 C3 00000000h RO; R/WC
PCI Express Graphics Legacy
Control
PEGLC EC EF 00000000h RO; R/W
PCI Express Graphics CFG1 F0 F3 00010000h
Reserved F3 FB
PCI Express Graphics CFG2 FC FF 00000000h
(Sheet 3 of 3)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Bit Access
Default
Value
Description
15:0 RO 8086h
Vendor Identification (VID1): PCI standard identification
for Intel.
Bit Access
Default
Value
Description
15:0 RO 2A41h
Device Identification Number (DID1): Identifier
assigned to the (G)MCH Device 1.
316 Datasheet
21.1.3 PCICMD1 - PCI Command
Access: RO; R/W
Size: 16 bits

(Sheet 1 of 2)
Bit Access
Default
Value
Description
15:11 RO 00h Reserved:
10 R/W 0b
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt
messages.
1 = This device is prevented from generating interrupt
messages. Any INTA emulation interrupts already
asserted must be deasserted when this bit is set.
Only affects interrupts generated by the device (PCI
INTA from a PME or Hot Plug event) controlled by this
command register. It does not affect upstream MSIs,
upstream PCI INTA-INTD assert and deassert
messages.
9 RO 0b
Fast Back-to-Back Enable (FB2B): Not Applicable or
Implemented. Hardwired to 0.
8 R/W 0b
SERR Message Enable (SERRE1): Controls Device 1
SERR messaging. The (G)MCH communicates the SERRB
condition by sending an SERR message to the ICH. This
bit, when set, enables reporting of non-fatal and fatal
errors detected by the device to the Root Complex. Note
that errors are reported if enabled either through this bit
or through the PCI Express specific bits in the Device
Control Register.
0 = The SERR message is generated by the (G)MCH for
Device 1 only under conditions enabled individually
through the Device Control Register.
1 = The (G)MCH is enabled to generate SERR messages
which will be sent to the ICH for specific Device 1 error
conditions generated/detected on the primary side of
the virtual PCI to PCI bridge (not those received by
the secondary side). The status of SERRs generated is
reported in the PCISTS1 register.
7 RO 0b
Reserved: Not Applicable or Implemented. Hardwired to
0.
6 R/W 0b
Parity Error Enable (PERRE):
Controls whether or not the Master Data Parity Error bit in
the PCI Status register can be set.
0 = Master Data Parity Error bit in PCI Status register
cannot be set.
1 = Master Data Parity Error bit in PCI Status register can
be set.
5 RO 0b
VGA Palette Snoop (VGAPS): Not Applicable or
Datasheet 317
4 RO 0b
Memory Write and Invalidate Enable (MWIE): Not
Applicable or Implemented. Hardwired to 0.
3 RO 0b
Special Cycle Enable (SCE): Not Applicable or
2 R/W 0b
Bus Master Enable (BME): Controls the ability of the
PCI Express graphics port to forward Memory and IO
Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO
requests to its primary bus. Note that according to
the PCI Express Specification as MSI interrupt
messages are in-band memory writes, disabling the
bus master enable bit prevents this device from
generating MSI interrupt messages or passing them
from its secondary bus to its primary bus. Upstream
memory writes/reads, IO writes/reads, peer writes/
reads, and MSIs will all be treated as illegal cycles.
Writes are forwarded to memory address 0 with byte
enables deasserted. Reads will be forwarded to
memory address 0 and will return Unsupported
Request status (or Master abort) in its completion
packet.
1 = This device is allowed to issue requests to its primary
bus. Completions for previously issued memory read
requests on the primary bus will be issued when the
data is available.This bit does not affect forwarding of
Completions from the primary interface to the
secondary interface.
1 R/W 0b
Memory Access Enable (MAE):
0 = All of Device 1's memory space is disabled.
1 = Enable the Memory and Prefetchable memory
address ranges defined in the MBASE1, MLIMIT1,
PMBASE1, and PMLIMIT1 registers.
0 R/W 0b
IO Access Enable (IOAE):
0 = All of Device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the
IOBASE1, and IOLIMIT1 registers.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
318 Datasheet
21.1.4 PCISTS1 - PCI Status
Access: RO; R/WC
Size: 16 bits
This register reports the occurrence of error conditions associated with primary side of
the virtual Host-PCI Express bridge embedded within the (G)MCH.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): Not Applicable or
Implemented. Hardwired to 0. Parity (generating
poisoned TLPs) is not supported on the primary side of
this device (we don't do error forwarding).
14 R/WC 0b
Signaled System Error (SSE): This bit is set when this
Device sends an SERR due to detecting an ERR_FATAL or
ERR_NONFATAL condition and the SERR Enable bit in the
Command register is '1'. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do
not affect this field.
13 RO 0b
Received Master Abort Status (RMAS): Not Applicable
or Implemented. Hardwired to 0. The concept of a master
abort does not exist on primary side of this device.
12 RO 0b
Received Target Abort Status (RTAS): Not Applicable
or Implemented. Hardwired to 0. The concept of a target
11 RO 0b
Signaled Target Abort Status (STAS): Not Applicable
or Implemented. Hardwired to 0. The concept of a target
10:9 RO 00b
DEVSELB Timing (DEVT): This device is not the
subtractively decoded device on Bus 0. This bit field is
therefore hardwired to 00 to indicate that the device uses
the fastest possible decode.
8 RO 0b
Master Data Parity Error (PMDPE): There is no
scenario where this bit will get set. The PCI Express
Specification defines it as an R/WC, but for our
implementation an RO definition behaves the same way
and will meet all testing requirements.
7 RO 0b
Fast Back-to-Back (FB2B): Not Applicable or
6 RO 0b Reserved:
5 RO 0b
66-/60-MHz Capability (CAP66): Not Applicable or
Datasheet 319
21.1.5 RID1 - Revision Identification
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
4 RO 1b
Capabilities List (CAPL): Indicates that a capabilities
list is present. Hardwired to 1.
3 RO 0b
INTA Status (INTAS): Indicates that an interrupt
message is pending internally to the device. Only PME and
Hot Plug sources feed into this status bit (not PCI INTA-
INTD assert and deassert messages). The INTA Assertion
Disable bit, PCICMD1[10], has no effect on this bit.
Note that INTA emulation interrupts received across the
link are not reflected in this bit.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
7:0 RO 00h
Revision Identification Number (RID1): This is an 8-
for the (G)MCH Device 0.
07h: B-3 stepping
09h: CR A-1 Stepping
320 Datasheet
21.1.6 CC1 - Class Code
Access: RO
Size: 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register- specific programming interface.
21.1.7 CL1 - Cache Line Size
Address Offset: Ch
Default Value: 00h
Access: R/W
Size: 8 bits

Bit Access
Default
Value
Description
23:16 RO 06h
Base Class Code (BCC): Indicates the base class code
for this device. This code has the value 06h, indicating a
Bridge device.
15:8 RO 04h
Sub-Class Code (SUBCC): Indicates the sub-class code
for this device. The code is 04h indicating a PCI-to-PCI
bridge.
7:0 RO 00h
Programming Interface (PI): Indicates the
programming interface of this device. This value does not
specify a particular register set layout and provides no
practical use for this device.
Bit Access
Default
Value
Description
7:0 R/W 00h
Cache Line Size (Scratch pad): Implemented by PCI
Express devices as a read-write field for legacy
compatibility purposes but has no impact on any PCI
Express device functionality.
Datasheet 321
21.1.8 B/D/F/Type: 0/1/0/PCI
Address Offset: Eh
Default Value: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
21.1.9 PBUSN1 - Primary Bus Number
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that this virtual Host-PCI Express bridge is connected to PCI
Bus 0.
Bit Access
Default
Value
Description
7:0 RO 01h
Header Type Register (HDR): Returns 01 to indicate that
this is a single-function device with bridge header layout.
Bit Access
Default
Value
Description
7:0 RO 00h
Primary Bus Number (BUSN): Configuration software
typically programs this field with the number of the bus on
the primary side of the bridge. Since Device 1 is an internal
device and its primary bus is always 0, these bits are read
only and are hardwired to 0.
322 Datasheet
21.1.10 SBUSN1 - Secondary Bus Number
Address Offset: 19h
Default Value: 00h
Access: R/W
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the virtual
bridge i.e., to PCI Express Graphics. This number is programmed by the PCI
configuration software to allow mapping of configuration cycles to PCI Express
Graphics.
21.1.11 SUBUSN1 - Subordinate Bus Number
Address Offset: 1Ah
Default Value: 00h
Access: R/W
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express Graphics. This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to PCI Express Graphics.
Bit Access
Default
Value
Description
7:0 R/W 00h
Secondary Bus Number (BUSN): This field is
programmed by configuration software with the bus
number assigned to PCI Express Graphics.
Bit Access
Default
Value
Description
7:0 R/W 00h
Subordinate Bus Number (BUSN): This register is
programmed by configuration software with the number
of the highest subordinate bus that lies behind the Device
1 bridge. When only a single PCI device resides on the
PCI Express Graphics segment, this register will contain
the same value as the SBUSN1 register.
Datasheet 323
21.1.12 IOBASE1 - I/O Base Address
Address Offset: 1Ch
Default Value: F0h
Access: RO; R/W
Size: 8 bits
This register controls the CPU to PCI Express Graphics I/O access routing based on the
following formula: IO_BASE=<address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4-KB boundary.
21.1.13 IOLIMIT1 - I/O Limit Address
Address Offset: 1Dh
Default Value: 00h
Access: RO; R/W
Size: 8 bits
This register controls the CPU to PCI Express Graphics I/O access routing based on the
following formula: IO_BASE=< address =<IO_LIMIT.
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4-KB aligned address block.
Bit Access
Default
Value
Description
7:4 R/W Fh
I/O Address Base (IOBASE): Corresponds to A[15:12] of
the I/O addresses passed by bridge 1 to PCI Express
Graphics. BIOS must not set this register to 00h otherwise
0CF8h/0CFCh accesses will be forwarded to the PCI Express
hierarchy associated with this device.
3:0 RO 0h Reserved
Bit Access
Default
Value
Description
7:4 R/W 0h
I/O Address Limit (IOLIMIT): Corresponds to A[15:12]
of the I/O address limit of Device 1. Devices between this
upper limit and IOBASE1 will be passed to the PCI Express
hierarchy associated with this device.
3:0 RO 0h Reserved
324 Datasheet
21.1.14 SSTS1 - Secondary Status
Access: R/WC; RO
Size: 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express Graphics side) of the virtual PCI-PCI
bridge embedded within (G)MCH.
Bit Access
Default
Value
Description
15 R/WC 0b
Detected Parity Error (DPE): When set indicates that
the MCH received across the link (upstream) a Posted
Write Data Poisoned TLP (EP=1).
14 R/WC 0b
Received System Error (RSE): This bit is set when the
secondary side receives an ERR_FATAL or ERR_NONFATAL
message due to an error detected by the secondary side,
and the SERR Enable bit in the Bridge Control register is 1.
13 R/WC 0b
Received Master Abort (RMA): This bit is set when the
Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Unsupported Request
Completion Status.
12 R/WC 0b
Received Target Abort (RTA): This bit is set when the
Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Completer Abort
Completion Status.
11 RO 0b
Signaled Target Abort (STA): Not Applicable or
Implemented. Hardwired to 0. The (G)MCH does not
generate Target Aborts (the (G)MCH will never complete a
request using the Completer Abort Completion status).
10:9 RO 00b
DEVSELB Timing (DEVT): Not Applicable or
8 R/WC 0b
Master Data Parity Error (SMDPE): When set indicates
that the MCH received across the link (upstream) a Read
Data Completion Poisoned TLP (EP=1). This bit can only be
set when the Parity Error Enable bit in the Bridge Control
register is set.
7 RO 0b
Fast Back-to-Back (FB2B): Not Applicable or
6 RO 0b Reserved
5 RO 0b
66-/60-MHz Capability (CAP66): Not Applicable or
4:0 RO 00h Reserved
Datasheet 325
21.1.15 MBASE1 - Memory Base Address
Default Value: FFF0h
Access: RO; R/W
Size: 16 bits
This register controls the CPU to PCI Express Graphics non-prefetchable memory
access routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1-MB
boundary.
21.1.16 MLIMIT1 - Memory Limit Address
Access: RO; R/W
Size: 16 bits
This register controls the CPU to PCI Express Graphics non-prefetchable memory
access routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB
aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express Graphics address ranges (typically where control/status
memory-mapped I/O data structures of the graphics controller will reside) and PMBASE
and PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
Bit Access
Default
Value
Description
15:4 R/W FFFh
Memory Address Base (MBASE): Corresponds to
A[31:20] of the lower limit of the memory range that will be
passed to PCI Express Graphics.
3:0 RO 0h Reserved
326 Datasheet
Note: Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges
i.e., prevent overlap with each other and/or with the ranges covered with the main
memory. There is no provision in the (G)MCH hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not guaranteed.
21.1.17 PMBASE1 - Prefetchable Memory Base Address
Default Value: FFF1h
Access: RO; R/W
Size: 16 bits
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express Graphics prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit Access
Default
Value
Description
15:4 R/W 000h
Memory Address Limit (MLIMIT): Corresponds to
A[31:20] of the upper limit of the address range passed
to PCI Express Graphics.
3:0 RO 0h Reserved
Bit Access
Default
Value
Description
15:4 R/W FFFh
Prefetchable Memory Base Address (MBASE):
Corresponds to A[31:20] of the lower limit of the memory
range that will be passed to PCI Express graphics.
3:0 RO 1h
64-Bit Address Support: Indicates that the upper 32
bits of the prefetchable memory region base address are
contained in the Prefetchable Memory base Upper
Address register at 28h.
Datasheet 327
21.1.18 PMLIMIT1 - Prefetchable Memory Limit Address
Access: RO; R/W
Size: 16 bits
This register in conjunction with the corresponding Upper Limit Address register
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1-MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
Bit Access
Default
Value
Description
15:4 R/W 000h
Prefetchable Memory Address Limit (PMLIMIT):
Corresponds to A[31:20] of the upper limit of the address
range passed to PCI Express graphics.
3:0 RO 1h
64-bit Address Support: Indicates that the upper 32 bits
of the prefetchable memory region limit address are
contained in the Prefetchable Memory Base Limit Address
register at 2Ch
328 Datasheet
21.1.19 PMBASEU1 - Prefetchable Memory Base Address
Access: R/W
Size: 32 bits
The functionality associated with this register is present in the PCI Express graphics
design implementation.
This register in conjunction with the corresponding Upper Base Address register
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit Access
Default
Value
Description
31:4 R/W 0000000h
Reserved (MBASEU1): These registers are R/W for
compliance purposes only. They should never be
programmed to anything other than zeros.
3:0 R/W Fh
Prefetchable Memory Base Address (MBASEU):
Corresponds to A[35:32] of the lower limit of the
prefetchable memory range that will be passed to PCI
Express graphics.
Datasheet 329
21.1.20 PMLIMITU1 - Prefetchable Memory Limit Address
Access: R/W
Size: 32 bits
The functionality associated with this register is present in the PCI Express graphics
design implementation. This register in conjunction with the corresponding Upper Limit
Address register controls the CPU to PCI Express Graphics prefetchable memory access
routing based on the following formula:
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1-MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
Bit Access
Default
Value
Description
31:4 R/W 0000000h
Reserved (MLIMITU1): These registers are R/W for
compliance purposes only. They should never be
programmed to anything other than zeros.
3:0 R/W 0h
Prefetchable Memory Address Limit (MLIMITU):
Corresponds to A[35:32] of the upper limit of the
prefetchable Memory range that will be passed to PCI
Express graphics.
330 Datasheet
21.1.21 CAPPTR1 - Capabilities Pointer
Address Offset: 34h
Default Value: 88h
Access: RO
Size: 8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
21.1.22 INTRLINE1 - Interrupt Line
Address Offset: 3Ch
Default Value: 00h
Access: R/W
Size: 8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Bit Access
Default
Value
Description
7:0 RO 88h
First Capability (CAPPTR1): The first capability in the
list is the Subsystem ID and Subsystem Vendor ID
capability.
Bit Access
Default
Value
Description
7:0 R/W 00h
Interrupt Connection (INTCON): Used to communicate
interrupt line routing information.
BIOS Requirement: POST software writes the routing
information into this register as it initializes and
configures the system. The value indicates to which input
of the system interrupt controller this device's interrupt
pin is connected.
Datasheet 331
21.1.23 INTRPIN1 - Interrupt Pin
Address Offset: 3Dh
Default Value: 01h
Access: RO
Size: 8 bits
This register specifies which interrupt pin this device uses.
21.1.24 BCTRL1 - Bridge Control
Access: RO; R/W
Size: 16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express Graphics) as well as some bits that affect the overall behavior of the virtual
Host-PCI Express bridge embedded within (G)MCH, e.g., VGA-compatible address
ranges mapping.
Bit Access
Default
Value
Description
7:0 RO 01h
Interrupt Pin (INTPIN): As a single function device, the
PCI Express device specifies INTA as its interrupt pin.
01h=INTA.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
11 RO 0b
Discard Timer SERR Enable (DTSERRE): Not Applicable
or Implemented. Hardwired to 0.
10 RO 0b
Discard Timer Status (DTSTS): Not Applicable or
9 RO 0b
Secondary Discard Timer (SDT): Not Applicable or
8 RO 0b
Primary Discard Timer (PDT): Not Applicable or
7 RO 0b
Fast Back-to-Back Enable (FB2BEN): Not Applicable or
6 R/W 0b
Secondary Bus Reset (SRESET): Setting this bit triggers
a hot reset on the corresponding PCI Express Port. This will
force the LTSSM to transition to the Hot Reset state (via
Recovery) from L0, L0s, or L1 states.
332 Datasheet
5 RO 0b
Master Abort Mode (MAMODE): When acting as a
master, unclaimed reads that experience a master abort
returns all 1's and any writes that experience a master
abort completes normally and the data is thrown away.
Hardwired to 0.
4 R/W 0b
VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI
bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB. This
bit only has meaning if Bit 3 (VGA Enable) of this register is
also set to 1, enabling VGA I/O decoding and forwarding by
the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3 R/W 0b
VGA Enable (VGAEN): Controls the routing of CPU
initiated transactions targeting VGA compatible I/O and
memory address ranges. See the VGAEN/MDAP table in
Device 0, offset 97h[0].
2 R/W 0b
ISA Enable (ISAEN): Needed to exclude legacy resource
decode to route ISA resources to legacy decode path.
Modifies the response by the (G)MCH to an I/O access
issued by the CPU that target ISA I/O addresses. This
applies only to I/O addresses that are enabled by the
IOBASE and IOLIMIT registers.
0 = All addresses defined by the IOBASE and IOLIMIT for
CPU I/O transactions will be mapped to PCI Express
Graphics.
1 = (G)MCH will not forward to PCI Express Graphics any
I/O transactions addressing the last 768 bytes in each
1-KB block even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers. Instead
of going to PCI Express Graphics these cycles will be
forwarded to DMI where they can be subtractively or
positively claimed by the ISA bridge.
1 R/W 0b
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side
to primary side that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages
result in SERR message when individually enabled by
the Root Control register.
0 R/W 0b
Parity Error Response Enable (PEREN): Controls
whether or not the Master Data Parity Error bit in the
Secondary Status register is set when the MCH receives
across the link (upstream) a Read Data Completion
Poisoned TLP
0 = Master Data Parity Error bit in Secondary Status
register cannot be set.
1 = Master Data Parity Error bit in Secondary Status
register can be set.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 333
21.1.25 PM_CAPID1 - Power Management Capabilities
Default Value: C8039001h
Access: RO
Size: 32 bits
Bit Access
Default
Value
Description
31:27 RO 19h
PME Support (PMES): This field indicates the power states
in which this device may indicate PME wake via PCI Express
messaging. D0, D3hot & D3cold. This device is not required
to do anything to support D3hot & D3cold, it simply must
report that those states are supported. Refer to the PCI
Power Management 1.1 Specification for encoding
explanation and other power management details.
26 RO 0b
D2 Power State Support (D2PSS): Hardwired to 0 to
indicate that the D2 power management state is NOT
supported.
25 RO 0b
D1 Power State Support (D1PSS): Hardwired to 0 to
indicate that the D1 power management state is NOT
supported.
24:22 RO 000b
Auxiliary Current (AUXC): Hardwired to 0 to indicate that
there are no 3.3Vaux auxiliary current requirements.
21 RO 0b
Device Specific Initialization (DSI): Hardwired to 0 to
indicate that special initialization of this device is NOT
required before generic class device driver is to use it.
20 RO 0b Auxiliary Power Source (APS): Hardwired to 0.
19 RO 0b
PME Clock (PMECLK): Hardwired to 0 to indicate this
device does NOT support PMEB generation.
18:16 RO 011b
PCI PM CAP Version (PCIPMCV): Version: - A value of
011b indicates that this function complies with revision 1.2
of the PCI Power Management Interface Specification.
15:8 RO 90h
Pointer to Next Capability (PNC): This contains a pointer
to the next item in the capabilities list. If MSICH (CAPL[0] @
7Fh) is 0, then the next item in the capabilities list is the
Message Signaled Interrupts (MSI) capability at 90h. If
MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the
capabilities list is the PCI Express capability at A0h.
7:0 RO 01h
Capability ID (CID): Value of 01h identifies this linked list
item (capability structure) as being for PCI Power
Management registers.
334 Datasheet
21.1.26 PM_CS1 - Power Management Control/Status
Access: RO; R/W/S; R/W
Size: 32 bits
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31:16 RO 0000h
Reserved Not Applicable or Implemented. Hardwired to
0.
15 RO 0b
PME Status (PMESTS): Indicates that this device does
not support PMEB generation from D3cold.
14:13 RO 00b
Data Scale (DSCALE): Indicates that this device does
not support the power management data register.
12:9 RO 0h
Data Select (DSEL): Indicates that this device does not
support the power management data register.
8 R/W/S 0b
PME Enable (PMEE): Indicates that this device does not
generate PMEB assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.See
PM_CAP[15:11]
7:4 RO 0000b Reserved:
3 RO 0b
No Soft Reset (NSR): When set (1), this bit indicates
that devices transitioning from D3hot to D0 because of
PowerState commands do not perform an internal reset.
Configuration Context is preserved. Upon transition from
the D3hot to the D0 Initialized state, no additional
operating system intervention is required to preserve
Configuration Context beyond writing the PowerState bits.
When clear (0), devices do perform an internal reset upon
transitioning from D3hot to D0 via software control of the
PowerState bits. Configuration Context is lost when
performing the soft reset. Upon transition from the D3hot
to the D0 state, full re-initialization sequence is needed to
return the device to D0 Initialized. Regardless of this bit,
devices that transition from D3hot to D0 by a system or
bus segment reset will return to the device state D0
uninitialized with only PME context preserved if PME is
supported and enabled.
This bit is hardwired to 0.
2 RO 0b Reserved
Datasheet 335
21.1.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities
Default Value: 0000800Dh
Access: RO
Size: 32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
1:0 R/W 00b
Power State (PS): Indicates the current power state of
this device and can be used to set the device into a new
power state. If software attempts to write an unsupported
state to this field, write operation must complete normally
on the bus, but the data is discarded and no state change
occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the
target of PCI configuration transactions (for power
management control). This device also cannot generate
interrupts or respond to MMR cycles in the D3 state. The
device must return to the D0 state in order to be fully-
functional.
When the Power State is other than D0, the bridge will
Master Abort (i.e., not claim) any downstream cycles
(with exception of Type 0 config cycles). Consequently,
these unclaimed cycles will go down DMI and come back
up as Unsupported Requests, which the MCH logs as
Master Aborts in Device 0 PCISTS[13]. There is no
additional hardware functionality required to support
these power states.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
15:8 RO 80h
Pointer to Next Capability (PNC): This contains a pointer
to the next item in the capabilities list which is the PCI
Power Management capability.
7:0 RO 0Dh
Capability ID (CID): Value of 0Dh identifies this linked list
item (capability structure) as being for SSID/SSVID
registers in a PCI-to-PCI bridge.
336 Datasheet
21.1.28 SS - Subsystem ID and Subsystem Vendor ID
Access: R/WO
Size: 32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and hardware reset.
21.1.29 MSI_CAPID - Message Signaled Interrupts Capability ID
Default Value: A005h
Access: RO
Size: 16 bits
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH
(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and
instead go directly from the PCI PM capability to the PCI Express capability.
Bit Access
Default
Value
Description
31:16 R/WO 0000h
Subsystem ID (SSID): Identifies the particular
subsystem and is assigned by the vendor.
15:0 R/WO 8086h
Subsystem Vendor ID (SSVID): Identifies the
manufacturer of the subsystem and is the same as the
vendor ID which is assigned by the PCI Special Interest
Group.
Bit Access
Default
Value
Description
15:8 RO A0h
Pointer to Next Capability (PNC): This contains a
pointer to the next item in the capabilities list which is the
PCI Express capability.
7:0 RO 05h
Capability ID (CID): Value of 05h identifies this linked
list item (capability structure) as being for MSI registers.
Datasheet 337
21.1.30 MC - Message Control
Access: RO; R/W
Size: 16 bits
System software can modify bits in this register, but the device is prohibited from doing
so. If the device writes the same message multiple times, only one of those messages
is guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
Bit Access
Default
Value
Description
7 RO 0b
64-bit Address Capable (64AC): Hardwired to 0 to
indicate that the function does not implement the upper 32
bits of the Message Address register and is incapable of
generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32 bit-/4-GB
limit.
6:4 R/W 000b
Multiple Message Enable (MME): System software
programs this field to indicate the actual number of
messages allocated to this device. This number will be
equal to or less than the number actually requested. The
encoding is the same as for the MMC field below.
3:1 RO 000b
Multiple Message Capable (MMC): System software
reads this field to determine the number of messages being
requested by this device.
Value:Number of Messages Requested
000 = 1
All of the following are reserved in this implementation:
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
0 R/W 0b
MSI Enable (MSIEN): Controls the ability of this device to
generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME or HotPlug
messages. INTA will not be generated and INTA Status
(PCISTS1[3]) will not be set.
338 Datasheet
21.1.31 MA - Message Address
Access: RO; R/W
Size: 32 bits
21.1.32 MD - Message Data
Access: R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:2 R/W 00000000h
Message Address (MA): Used by system software to
assign an MSI address to the device. The device
handles an MSI by writing the padded contents of the
MD register to this address.
1:0 RO 00b
Force Dword Align (FDWA): Hardwired to 0 so that
addresses assigned by system software are always
aligned on a dword address boundary.
Bit Access
Default
Value
Description
15:0 R/W 0000h
Message Data (MD): Base message data pattern
assigned by system software and used to handle an MSI
from the device. When the device must generate an
interrupt request, it writes a 32-bit value to the memory
address specified in the MA register. The upper 16 bits are
always set to 0. The lower 16 bits are supplied by this
register.
Datasheet 339
21.1.33 PEG_CAPL - PCI Express Graphics Capability List
Access: RO
Size: 16 bits
Enumerates the PCI Express capability structure.
21.1.34 PEG_CAP - PCI Express Graphics Capabilities
Access: RO; R/WO
Size: 16 bits
Indicates PCI Express device capabilities.
Bit Access
Default
Value
Description
15:8 RO 00h
Pointer to Next Capability (PNC): This value terminates
the capabilities list. The Virtual Channel capability and any
other PCI Express specific capabilities that are reported via
this mechanism are in a separate capabilities list located
entirely within PCI Express extended configuration space.
7:0 RO 10h
Capability ID (CID): Identifies this linked list item
(capability structure) as being for PCI Express registers.
Bit Access
Default
Value
Description
13:9 RO 00h
Interrupt Message Number (IMN): Not Applicable or
8 R/WO 1b
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is
connected to an integrated component or is disabled.
1 = The PCI Express Link associated with this port is
connected to a slot. BIOS Requirement: This field must
be initialized appropriately if a slot connection is not
implemented.
7:4 RO 4h
Device/Port Type (DPT): Hardwired to 4h to indicate
root port of PCI Express Root Complex.
3:0 RO 1h
PCI Express Capability Version (PCIECV): Hardwired
to 1 as it is the first version.
340 Datasheet
21.1.35 DCAP - Device Capabilities
Access: RO
Size: 32 bits
Indicates PCI Express device capabilities
Bit Access
Default
Value
Description
31:16 RO 0000h
Reserved: Not Applicable or Implemented. Hardwired to
0.
15 RO 1b
Role-Based Error Reporting (RBER): Role-Based
Error Reporting This bit, when set, indicates that the
device implements the functionality originally defined in
the Error Reporting ECN for PCI Express Base
Specification, Revision 1.0a, and later incorporated into
PCI Express Base Specification, Revision 1.1. This bit
must be set by all devices conforming to the ECN, PCI
Express Base Specification, Revision 1.1, or subsequent
PCI Express Base Specification revisions.
14:6 RO
0000000
00b
Reserved
5 RO 0b
Extended Tag Field Supported (ETFS): Hardwired to
indicate support for 5-bit Tags as a Requestor.
4:3 RO 00b
Phantom Functions Supported (PFS): Not Applicable
or Implemented. Hardwired to 0.
2:0 RO 000b
Max Payload Size (MPS): Hardwired to indicate 128 B
max supported payload for Transaction Layer Packets
(TLP).
Datasheet 341
21.1.36 DCTL - Device Control
Access: RO; R/W
Size: 16 bits
Provides control for PCI Express device specific capabilities. The error reporting enable
bits are in reference to errors detected by this device, not error messages received
across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL,
ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command
Register.
Bit Access
Default
Value
Description
11 RO 0b Reserved for Enable No Snoop
7:5 R/W 000b
Max Payload Size (MPS):
000 = 128 B max supported payload for Transaction Layer
Packets (TLP). As a receiver, the Device must handle
TLPs as large as the set value; as transmitter, the
Device must not generate TLPs exceeding the set
value. All other encodings are reserved. Hardware
will actually ignore this field. It is writeable only to
support compliance testing.
4 RO 0b Reserved
3 R/W 0b
Unsupported Request Reporting Enable (URRE): When
set, Unsupported Requests will be reported.
NOTE: Reporting of error messages received by Root Port
is controlled exclusively by Root Control register.
2 R/W 0b
Fatal Error Reporting Enable (FERE): When set fatal
errors will be reported. For a Root Port, the reporting of
fatal errors is internal to the root. No external ERR_FATAL
message is generated.
1 R/W 0b
Non-Fatal Error Reporting Enable (NFERE): When set
non-fatal errors will be reported. For a Root Port, the
reporting of non-fatal errors is internal to the root. No
external ERR_NONFATAL message is generated.
Uncorrectable errors can result in degraded performance.
0 R/W 0b
Correctable Error Reporting Enable (CERE): When set
correctable errors will be reported. For a Root Port, the
reporting of correctable errors is internal to the root. No
external ERR_CORR message is generated.
342 Datasheet
21.1.37 DSTS - Device Status
Address Offset: AA-ABh
Access: RO; R/WC
Size: 16 bits
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Bit Access
Default
Value
Description
15:6 RO 000h
Reserved and Zero: For future R/WC/S
implementations; software must use 0 for writes to bits.
5 RO 0b
Transactions Pending (TP):
0 = All pending transactions (including completions for
any outstanding non-posted requests on any used
virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-
posted requests for all used Traffic Classes).
4 RO 0b Reserved
3 R/WC 0b
Unsupported Request Detected (URD): When set this
bit indicates that the Device received an Unsupported
Request. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal
Error Detected bit is set according to the setting of the
Unsupported Request Error Severity bit. In production
systems setting the Fatal Error Detected bit is not an
option as support for AER will not be reported.
2 R/WC 0b
Fatal Error Detected (FED): When set this bit indicates
that fatal error(s) were detected. Errors are logged in this
register regardless of whether error reporting is enabled
or not in the Device Control register. When Advanced
Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable
error mask register.
1 R/WC 0b
Non-Fatal Error Detected (NFED): When set this bit
indicates that non-fatal error(s) were detected. Errors are
logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
uncorrectable error mask register.
0 R/WC 0b
Correctable Error Detected (CED): When set this bit
indicates that correctable error(s) were detected. Errors
are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
correctable error mask register.
Datasheet 343
21.1.38 LCAP - Link Capabilities
Address Offset: AC-AFh
Default Value: 02012D01h
Access: RO; R/WO
Size: 32 bits
Indicates PCI Express device specific capabilities.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31:24 RO 02h
Port Number (PN): Indicates the PCI Express port number
for the given PCI Express link. Matches the value in Element
Self Description[31:24].
20 RO 0b
Data Link Layer Link Active Reporting Capable
(DLLLARC): For a Downstream Port, this bit must be set to
1b if the component supports the optional capability of
reporting the DL_Active state of the Data Link Control and
Management State Machine. For a hot-plug capable
Downstream Port (as indicated by the Hot-Plug Capable
field of the Slot Capabilities register), this bit must be set to
1b.
For upstream ports and components that do not support
this optional capability, this bit must be hardwired to 0b.
19 RO 0b
Surprise Down Error Reporting Capable (SDERC): For
a Downstream Port, this bit must be set to 1b if the
component supports the optional capability of detecting and
reporting a Surprise Down error condition. For Upstream
Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
18 RO 0b
Clock Power Management (CPM): A value of 1b in this
bit indicates that the component tolerates the removal of
any reference clock(s) when the link is in the L1 and L2/3
Ready link states. A value of 0b indicates the component
does not have this capability and that reference clock(s)
must not be removed in these link states.This capability is
applicable only in form factors that support clock request
(CLKREQ#) capability. For a multi-function device, each
function indicates its capability independently. Power
Management configuration software must only permit
reference clock removal if all functions of the multifunction
device indicate a 1b in this bit.
17:15 R/WO 010b
L1 Exit Latency (L1ELAT): Indicates the length of time
this Port requires to complete the transition from L1 to L0.
The value 010 b indicates the range of 2 s to less than
4 s.
BIOS Requirement: If this field is required to be any value
other than the default, BIOS must initialize it accordingly.
Both bytes of this register that contain a portion of this field
must be written simultaneously in order to prevent an
intermediate (and undesired) value from ever existing.
344 Datasheet
14:12 RO 010b
L0s Exit Latency (L0SELAT): Indicates the length of time
this Port requires to complete the transition from L0s to L0.
The actual value of this field depends on the common Clock
Configuration bit (LCTL[6]) and the Common and Non-
Common clock L0s Exit Latency values in PEGL0SLAT
(Offset 22Ch).
11:10 R/WO 11b Active State Link PM Support (ASLPMS)
9:4 RO 10h
Max Link Width (MLW): Indicates the maximum number
of lanes supported for this link.
3:0 RO 1h Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
000: Less than 64 ns
001: 64 ns to less than 128 ns
100: 512 ns to less than 1 s
101: 1 s to less than 2 s
110: 2 s - 4 s
111: More than 4 s
000: Less than 64 ns
100: 512 ns to less than 1 s
101: 1 s to less than 2 s
110: 2 s - 4 s
111: More than 4 s
Datasheet 345
21.1.39 LCTL - Link Control
Access: RO; R/W
Size: 16 bits
Allows control of PCI Express link.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
8 RO 0b
Enable Clock Power Management (ECPM): Applicable
only for form factors that support a Clock Request
(CLKREQ#) mechanism, this enable functions as follows
0b Clock power management is disabled and device must
hold CLKREQ# signal low
1b - When this bit is set to 1 the device is permitted to use
CLKREQ# signal to power manage link clock according to
protocol defined in appropriate form factor specification.
Default value of this field is 0b.
Components that do not support Clock Power Management
(as indicated by a 0b value in the Clock Power Management
bit of the Link Capabilities Register) must hardwire this bit
to 0b.
7 R/W 0b
Extended Synch (ES):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
exiting the L0s state and when in the Recovery state.
This mode provides external devices (e.g., logic
analyzers) monitoring the Link time to achieve bit and
symbol lock before the link enters L0 and resumes
communication. This is a test mode only and may cause
other undesired side effects such as buffer overflows or
underruns.
6 R/W 1b
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at
the opposite end of this Link are operating with
asynchronous reference clock.
1 = Indicates that this component and the component at
the opposite end of this Link are operating with a
distributed common reference clock.
The state of this bit affects the L0s Exit Latency reported in
LCAP[14:12] and the N_FTS value advertised during link
training.
See PEGL0SLAT at offset 22Ch.
346 Datasheet
5 R/W 0b
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical
Layer LTSSM from L0, L0s, or L1 states to the Recovery
state.
This bit always returns 0 when read.
This bit is cleared automatically (no need to write a 0).
4 R/W 0b
Link Disable (LD):
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the
Disabled state (via Recovery) from L0, L0s, or L1
states. Link retraining happens automatically on 0 to 1
transition, just like when coming out of reset.
Writes to this bit are immediately reflected in the value read
from the bit, regardless of actual Link state.
3 RO 0b
Read Completion Boundary (RCB): Hardwired to 0 to
indicate 64 byte.
2 R/W 0b Far-End Digital Loopback (FEDLB):
1:0 R/W 00b
Active State PM (ASPM): Controls the level of active state
power management supported on the given link.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
00 Disabled
01 L0s Entry Supported
10 Reserved
11 L0s and L1 Entry Supported
Datasheet 347
21.1.40 LSTS - Link Status
Access: RO
Size: 16 bits
Indicates PCI Express link status.
Bit Access
Default
Value
Description
13 RO 0b
Data Link Layer Link Active (Optional) (DLLLA): This
bit indicates the status of the Data Link Control and
Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise.This bit must be implemented
if the corresponding Data Link Layer Active capability bit is
implemented. Otherwise, this bit must be hardwired to 0b.
12 RO 1b
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of
the presence of a reference on the connector.
1 = The device uses the same physical reference clock that
the platform provides on the connector.
11 RO 0b
Link Training (LTRN): Indicates that the Physical Layer
LTSSM is in the Configuration or Recovery state, or that 1b
was written to the Retrain Link bit but Link training has not
yet begun. Hardware clears this bit when the LTSSM exits
the Configuration/Recovery state once Link training is
complete.
10 RO 0b
Undefined: The value read from this bit is undefined. In
previous versions of this specification, this bit was used to
indicate a Link Training Error. System software must ignore
the value read from this bit. System software is permitted
to write any value to this bit.
9:4 RO 00h
Negotiated Width (NW): Indicates negotiated link width.
This field is valid only when the link is in the L0, L0s, or L1
states (after link width negotiation is successfully
completed).
01h:X1
10h:X16
3:0 RO 1h
Negotiated Speed (NS): Indicates negotiated link speed.
1h:2.5 Gb/s All other encodings are reserved.
348 Datasheet
21.1.41 SLOTCAP - Slot Capabilities
Access: R/WO; RO
Size: 32 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit Access
Default
Value
Description
31:19 R/WO 0000h
Physical Slot Number (PSN): Indicates the physical
slot number attached to this Port. BIOS Requirement:
This field must be initialized by BIOS to a value that
assigns a slot number that is globally unique within the
chassis.
18 R/WO 1b
No Command Completed Support (NCCS): When set
to 1b, this bit indicates that this slot does not generate
software notification when an issued command is
completed by the Hot-Plug Controller. This bit is only
permitted to be set to 1b if the hot-plug capable port is
able to accept writes to all fields of the Slot Control
register without delay between successive writes.
17 RO 0b Reserved
16:15 R/WO 00b
Slot Power Limit Scale (SPLS): Specifies the scale
used for the Slot Power Limit Value.
14:7 R/WO 00h
Slot Power Limit Value (SPLV): In combination with
the Slot Power Limit Scale value, specifies the upper limit
on power supplied by slot. Power limit (in Watts) is
calculated by multiplying the value in this field by the
value in the Slot Power Limit Scale field. If this field is
written, the link sends a Set_Slot_Power_Limit message.
6 RO 1b
Hot-plug Capable (HPC): When set to 1b, this bit
indicates that this slot is capable of supporting hot-lug
operations.
5 RO 0b Reserved
4 RO 0b Reserved
3 RO 0b Reserved
2 RO 0b Reserved
1 RO 0b Reserved
0 RO 0b Reserved
00 1.0x
01 0.1x
10 0.01x
11
0.001xIf this field is written, the link sends
a Set_Slot_Power_Limit message.
Datasheet 349
21.1.42 SLOTCTL - Slot Control
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
12 RO 0b Reserved
11 RO 0b Reserved
10 RO 0b Reserved
9:8 RO 01b Reserved
7:6 RO 11b Reserved
5 R/W 0b
Hot-plug Interrupt Enable (HPIE): When set to 1b, this
bit enables generation of an interrupt on enabled hot-plug
events Default value of this field is 0b. If the Hot Plug
Capable field in the Slot Capabilities register is set to 0b,
this bit is permitted to be read-only with a value of 0b.
4 RO 0b Reserved
3 R/W 0b
Presence Detect Changed Enable (PDCE): When set to
1b, this bit enables software notification on a presence
detect changed event.
2 RO 0b Reserved
1 RO 0b Reserved
0 RO 0b Reserved
350 Datasheet
21.1.43 SLOTSTS - Slot Status
Address Offset: BA-BBh
Access: RO; R/WC
Size: 16 bits
Bit Access
Default
Value
Description
15:9 RO
0000000
b
Reserved
8 RO 0b Reserved
7 RO 0b Reserved
6 RO 0b
Presence Detect State (PDS): This bit indicates the
presence of an adapter in the slot, reflected by the logical
OR of the Physical Layer in-band presence detect
mechanism and, if present, any out-of-band presence
detect mechanism defined for the slot's corresponding
form factor. Note that the in-band presence detect
mechanism requires that power be applied to an adapter
for its presence to be detected. Consequently, form
factors that require a power controller for hot-plug must
implement a physical pin presence detect
mechanism.Defined encodings are:
0b Slot Empty
1b Card Present in slot
This register must be implemented on all Downstream
Ports that implement slots. For Downstream Ports not
connected to slots (where the Slot Implemented bit of the
PCI Express Capabilities Register is 0b), this bit must
return 1b.
5 RO 0b Reserved
4 RO 0b Reserved
3 R/WC 0b
Presence Detect Changed (PDC): This bit is set when
the value reported in Presence Detect State is changed.
2 RO 0b Reserved
1 RO 0b Reserved
0 RO 0b Reserved
Datasheet 351
21.1.44 RCTL - Root Control
Address Offset: BC-BDh
Access: RO; R/W
Size: 16 bits
Allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when our
device detects an error (reported in this device's Device Status register) or when an
error message is received across the link. Reporting of SERR as controlled by these bits
takes precedence over the SERR Enable in the PCI Command Register.
Bit Access
Default
Value
Description
3 R/W 0b
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME
messages.
1 = Enables interrupt generation upon receipt of a PME
message as reflected in the PME Status bit of the Root
Status Register. A PME interrupt is also generated if the
PME Status bit of the Root Status Register is set when
this bit is set from a cleared state.
2 R/W 0b
System Error on Fatal Error Enable (SEFEE): Controls
the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal
error is reported by any of the devices in the hierarchy
associated with this Root Port, or by the Root Port itself.
1 R/W 0b
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE): Controls the Root Complex's response to non-
fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-
fatal error is reported by any of the devices in the
hierarchy associated with this Root Port, or by the Root
Port itself.
0 R/W 0b
System Error on Correctable Error Enable (SECEE):
Controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a
correctable error is reported by any of the devices in the
hierarchy associated with this Root Port, or by the Root
Port itself.
352 Datasheet
21.1.45 RSTS - Root Status
Access: RO; R/WC
Size: 32 bits
Provides information about PCI Express Root Complex specific parameters.
Bit Access
Default
Value
Description
17 RO 0b
PME Pending (PMEP): Indicates that another PME is
pending when the PME Status bit is set. When the PME
Status bit is cleared by software; the PME is delivered by
hardware by setting the PME Status bit again and
updating the Requestor ID appropriately. The PME
pending bit is cleared by hardware if no more PMEs are
pending.
16 R/WC 0b
PME Status (PMES): Indicates that PME was asserted by
the requestor ID indicated in the PME Requestor ID field.
Subsequent PMEs are kept pending until the status
register is cleared by writing a 1 to this field.
15:0 RO 0000h
PME Requestor ID (PMERID): Indicates the PCI
requestor ID of the last PME requestor.
Datasheet 353
21.1.46 PEGLC - PCI Express Graphics Legacy Control
Address Offset: EC-EFh
Access: RO; R/W
Size: 32 bits
Controls functionality that is needed by Legacy (non-PCI Express aware) OS's during
run time.
21.1.47 PEGCFG1 - PCI Express Graphics Config 1
Access: RO; R/W
Size: 32 bits
This register must be left at its default value or programmed as defined by the (G)MCH
BIOS Specification.
Bit Access
Default
Value
Description
2 R/W 0b
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is
received.
1 = Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on
DMI). This enables the MCH to support PMEs on the PCI
Express graphics port under legacy OSs.
1 R/W 0b
Hot-Plug GPE Enable (HPGPE):
0 = Do not generate GPE Hot-Plug message when Hot-Plug
event is received.
1 = Generate a GPE Hot-Plug message when Hot-Plug
Event is received (Assert_HPGPE and Deassert_HPGPE
messages on DMI). This enables the MCH to support
Hot-Plug on the PCI Express graphics port under legacy
OSs.
0 R/W 0b
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/deassert
messages.
1 = Forward received GPE assert/deassert messages. These
general GPE message can be received via the PCI
Express graphics port from an external Intel device
(i.e., PxH) and will be subsequently forwarded to the
ICH (via Assert_GPE and Deassert_GPE messages on
DMI). For example, PxH might send this message if a
PCI Express device is hot plugged into a PxH
downstream port.
354 Datasheet
21.1.48 PEGCFG2 - PCI Express Graphics Config 2
Address Offset: FC-FFh
Access: RO; R/W
Size: 32 bits
This register must be left at its default value or programmed as defined by the (G)MCH
BIOS Specification.
21.2 PCI Express Graphics Device 1 Function 0
Extended Configuration Registers
Extended capability structures for PCI Express devices are located in PCI Express
extended configuration space and have different field definition than standard PCI
capability structures.
Register Name
Register
Symbol
Register
Start
Register
End
Virtual Channel Enhanced
Capability Header
VCECH 100 103 14010002h RO
Port VC Capability Register 1 PVCCAP1 104 107 00000000h RO
Port VC Capability Register 2 PVCCAP2 108 10B 00000001h RO
Port VC Control PVCCTL 10C 10D 0000h RO; R/W
VC0 Resource Capability VC0RCAP 110 113 00000000h RO
VC0 Resource Control VC0RCTL 114 117 800000FFh RO; R/W
VC0 Resource Status VC0RSTS 11A 11B 0002h RO
VC1 Resource Capability VC1RCAP 11C 11F 00000000h RO
VC1 Resource Control VC1RCTL 120 123 00000000h RO
VC1 Resource Status VC1RSTS 126 127 0000h RO
Root Complex Link Declaration
Enhanced
RCLDECH 140 143 00010005h RO
Element Self Description ESD 144 147 02000100h RO; R/WO
Link Entry 1 Description LE1D 150 153 00000000h RO; R/WO
Link Entry 1 Address LE1A 158 15F
00000000000000
00h
RO; R/WO
Sequence Status
PEGSSTS 218 21F
0000000000000F
FFh
RO
PCI Express Graphics Error
Status
PEGERRSTS 228 22B 00000000h RO
Datasheet 355
21.2.1 VCECH - Virtual Channel Enhanced Capability Header
B/D/F/Type: 0/1/0/MM
Access: RO
Size: 32 bits
Indicates PCI Express device Virtual Channel capabilities. Extended capability
structures for PCI Express devices are located in PCI Express extended configuration
space and have different field definitions than standard PCI capability structures.
21.2.2 PVCCAP1 - Port VC Capability Register 1
Access: RO
Size: 32 bits
Bit Access
Default
Value
Description
31:20 RO 140h
Pointer to Next Capability (PNC): The Link Declaration
capability is the next in the PCI Express extended
capabilities list.
19:16 RO 1h
PCI Express Virtual Channel Capability Version
(PCIEVCCV): Hardwired to 1 to indicate compliances with
the 1.0 version of the PCI Express Specification.
15:0 RO 0002h
Extended Capability ID (ECID): Value of 0002h identifies
this linked list item (capability structure) as being for PCI
Express Virtual Channel registers.
Bit Access
Default
Value
Description
31:7 RO
0000000
h
Reserved
6:4 RO 000b
Low Priority Extended VC Count (LPEVCC): Indicates
the number of (extended) Virtual Channels in addition to
the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
3 RO 0b Reserved
2:0 RO 000b
Extended VC Count (EVCC): Indicates the number of
supported by the device. BIOS Requirement: Set this field
to 000b for all configurations. VC1 is not a POR feature.
356 Datasheet
21.2.3 PVCCAP2 - Port VC Capability Register 2
Access: RO
Size: 32 bits
21.2.4 PVCCTL - Port VC Control
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:24 RO 00h
VC Arbitration Table Offset (VCATO): Indicates the
location of the VC Arbitration Table. This field contains the
zero-based offset of the table in DQWORDS (16 bytes)
from the base address of the Virtual Channel capability
Structure. A value of 0 indicates that the table is not
present (due to fixed VC priority).
7:0 RO 01h
VC Arbitration Capability (VCAC): Indicates that the
only possible VC arbitration scheme is hardware fixed (in
the root complex). VC1 is the highest priority. VC0 is the
lowest priority.
Bit Access
Default
Value
Description
3:1 R/W 000b
VC Arbitration Select (VCAS): This field will be
indicated in the VC Arbitration capability field. The value
complex). This field can not be modified when more than
0 RO 0b Reserved
Datasheet 357
21.2.5 VC0RCAP - VC0 Resource Capability
Access: RO
Size: 32 bits
21.2.6 VC0RCTL - VC0 Resource Control
Access: RO; R/W
Size: 32 bits
Bit Access
Default
Value
Description
23 RO 0b Reserved
15 RO 0b
14:0 RO 0000h
Reserved: The Port Arbitration capability is not valid for
root ports.
Bit Access
Default
Value
Description
31 RO 1b
VC0 Enable (VC0E): For VC0 this is hardwired to 1 and
read only as VC0 can never be disabled.
26:24 RO 000b
VC0 ID (VC0ID): Assigns a VC ID to the VC resource.
For VC0 this is hardwired to 0 and read only.
7:1 R/W 7Fh
within this field correspond to TC values. For example,
when Bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it
indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the
TC/VC Map of an enabled VC, software must ensure that
no new or outstanding transactions with the TC labels are
0 RO 1b
routed to VC0.
358 Datasheet
21.2.7 VC0RSTS - VC0 Resource Status
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
1 RO 1b
(initialization or disabling). This bit indicates the status
of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the
corresponding Virtual Channel is Disabled or the Link is
in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state. Before using a
Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are
cleared in both Components on a Link.
0 RO 0b Reserved
Datasheet 359
21.2.8 RCLDECH - Root Complex Link Declaration Enhanced
Access: RO
Size: 32 bits
This capability declares links from this element (PCI Express graphics) to other
elements of the root complex component to which it belongs. See the PCI Express
Specification for link/topology declaration requirements.
Bit Access
Default
Value
Description
31:20 RO 000h
Pointer to Next Capability (PNC): This is the last
capability in the PCI Express extended capabilities list
unless the partially implemented Advanced Error Reporting
capability is exposed. When the AER capability is exposed
by clearing the CAPL[1] bit then this field will point to the
AER capability at 1CO h which will be the last item in the
list.
19:16 RO 1h
Link Declaration Capability Version (LDCV): Hardwired
to 1 to indicate compliances with the 1.0 version of the PCI
Express Specification.
15:0 RO 0005h
Extended Capability ID (ECID): Value of 0005 h
identifies this linked list item (capability structure) as being
for PCI Express Link Declaration capability. See
corresponding Egress Port Link Declaration capability
registers for diagram of Link Declaration Topology.
360 Datasheet
21.2.9 ESD - Element Self Description
Access: RO; R/WO
Size: 32 bits
capability.
Bit Access
Default
Value
Description
31:24 RO 02h
Port Number (PN): Specifies the port number associated
with this element with respect to the component that
contains this element. This port number value is utilized by
the egress port of the component to provide arbitration to
this Root Complex Element.
23:16 R/WO 00h
Component ID (CID): Identifies the physical component
15:8 RO 01h
Number of Link Entries (NLE): Indicates the number of
link entries following the Element Self Description. This field
reports 1 (to Egress port only as we don't report any peer-
to-peer capabilities in our topology).
7:4 RO 0h Reserved
3:0 RO 0h
Element Type (ET): Indicates the type of the Root
Complex Element. Value of 0 h represents a root port.
Datasheet 361
21.2.10 LE1D - Link Entry 1 Description
Access: RO; R/WO
Size: 32 bits
Element.
21.2.11 LE1A - Link Entry 1 Address
Access: RO; R/WO
Size: 64 bits
Element.
Bit Access
Default
Value
Description
31:24 RO 00h
(Egress Port). The target port number is with respect to
the component that contains this element as specified by
the target component ID.
23:16 R/WO 00h
Target Component ID (TCID): Identifies the physical
or logical component that is targeted by this link entry.
1 RO 0b
memory-mapped space (for RCRB). The link address
specifies the 64-bit base address of the target RCRB.
0 R/WO 0b
Link Valid (LV):
Bit Access
Default
Value
Description
31:12 R/WO 00000h
Link Address (LA): Memory mapped base address of
the RCRB that is the target element (Egress Port) for this
link entry.
362 Datasheet
21.2.12 PEGSSTS - PCI Express Graphics Sequence Status
Default Value: 0000000000000FFFh
Access: RO
Size: 64 bits
PCI Express status reporting that is required by the PCI Express specification.
Bit Access
Default
Value
Description
59:48 RO 000h
Next Transmit Sequence Number (NTSN): Value of
the NXT_TRANS_SEQ counter. This counter represents the
transmit Sequence number to be applied to the next TLP
to be transmitted onto the Link for the first time.
43:32 RO 000h
Next Packet Sequence Number (NPSN): Packet
sequence number to be applied to the next TLP to be
transmitted or re-transmitted onto the Link.
27:16 RO 000h
Next Receive Sequence Number (NRSN): This is the
sequence number associated with the TLP that is expected
to be received next.
11:0 RO FFFh
Last Acknowledged Sequence Number (LASN): This
is the sequence number associated with the last
acknowledged TLP.
Datasheet 363
21.2.13 PEGERRSTS - PCI Express Graphics Error Status
Access: RO
Size: 32 bits
This register is used to report various error conditions. A message can be generated on
a zero-to-one transition of any of these flags (if enabled by the mask registers). These
bits are set regardless of whether or not the message is enabled and generated. After
the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a 1 to it.

Bit Access
Default
Value
Description
0 RO 0b
Illegal Isochronous Request Received (IIRR): If set,
indicates an illegal TBWRR VC1 Isochronous request was
receive. This bit is set when a TBWRR VC1 request takes
more than 1 time slot to process. This is determined from
the address and length information.If this bit is already
set, than an interrupt message will not be sent on a new
error event.
364 Datasheet
Datasheet 365
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
22 Internal Graphics Device 2
Configuration Register
(D2:F0-F1)
Device 2 contains registers for the internal graphics functions. The table below lists the
PCI configuration registers in order of ascending offset address.
Function 0 can be VGA compatible or not, this selected through Bit 1 of GGC register
(Device 0, offset 52h).
The following sections describe Device 2 PCI configuration registers and are applicable
only to (G)MCH variants supporting Integrated Graphics.
22.1 Internal Graphics Device 2 Configuration Register
Details (D2:F0)
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
PCI Status PCISTS2 6 7 0090h RO
Cache Line Size CLS C C 00h RO
Master Latency Timer MLT2 D D 00h RO
Reserved F F
Graphics Translation Table Range
Address
GTTMMADR 10 17
0000000000
000004h
RO; R/W
Graphics Memory Range Address GMADR 18 1F
0000000000
00000Ch
R/W; R/W/L
RO
I/O Base Address IOBAR 20 23 00000001h RO; R/W
Subsystem Vendor Identification SVID2 2C 2D 0000h R/WO
Subsystem Identification SID2 2E 2F 0000h R/WO
Video BIOS ROM Base Address ROMADR 30 33 00000000h RO
Capabilities Pointer CAPPOINT 34 34 90h RO
Interrupt Line INTRLINE 3C 3C 00h R/W
Interrupt Pin INTRPIN 3D 3D 01h RO
Minimum Grant MINGNT 3E 3E 00h RO
366 Datasheet
Maximum Latency MAXLAT 3F 3F 00h RO
Capabilities Pointer (to Mirror of
Dev0 CAPID)
MCAPPTR 44 44 48h RO
Mirror of Dev0 (G)MCH Graphics
Control
MGGC 52 53 0030h RO
Mirror of Dev0 DEVEN MDEVENdev0F0 54 57 0000001Bh RO
Software Scratch Read Write SSRW 58 5B 00000000h R/W
Base of Stolen Memory BSM 5C 63
0000000000
000000h
RO
Hardware Scratch Read Write HSRW 64 65 0000h R/W
Multi Size Aperture Control MSAC 66 66 02h RO; R/W
Message Signaled Interrupts
Capability ID
MSI_CAPID 90 91 D005h RO
Message Control MC 92 93 0000h RO; R/W
Message Address MA 94 97 00000000h RO; R/W
Message Data MD 98 99 0000h R/W
Reserved 9A CF
Power Management Capabilities
ID
PMCAPID D0 D1 0001h RO
Power Management Capabilities PMCAP D2 D3 0023h RO
Status
PMCS D4 D5 0000h RO; R/W
Reserved DA DC
Software SMI SWSMI E0 E1 0000h R/W
System Display Event Register ASLE E4 E7 00000000h R/W
Software SCI SWSCI E8 E9 0000h R/WO; R/W
Graphics Clock Frequency
Control
GCFC F0 F1 1606h RO; R/W
Reserved F2 F3
Legacy Backlight Brightness LBB F4 F7 00000000h R/W
Reserved F8 FB
ASL Storage ASLS FC FF 00000000h R/W
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Datasheet 367
Access: RO;
Size: 16 bits
PCI device.
Access: RO;
Size: 16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Bit Access
Default
Value
Description
15:0 RO 8086h
Bit Access
Default
Value
Description
15:0 RO 2A42h
assigned to the (G)MCH Device 2 Function 0.
368 Datasheet
Access: RO; R/W
Size: 16 bits
This 16-bit register provides basic control over the IGD ability to respond to PCI cycles.
The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to
main memory.
Bit Access
Default
Value
Description
10 R/W 0b
Interrupt Disable: This bit disables the device from
asserting INTx#.
0: Enable the assertion of this device's INTx# signal.
1: Disable the assertion of this device's INTx# signal.
DO_INTx messages will not be sent to DMI.
9 RO 0b
Fast Back-to-Back (FB2B): Not Implemented.
Hardwired to 0.
8 RO 0b
SERR Enable (SERRE): Not Implemented. Hardwired to
0.
7 RO 0b
Address/Data Stepping Enable (ADSTEP): Not
6 RO 0b
Parity Error Enable (PERRE): Not Implemented.
Hardwired to 0.
Since the IGD belongs to the category of devices that
does not corrupt programs or data in system memory or
hard drives, the IGD ignores any parity error that it
detects and continues with normal operation.
5 RO 0b
Video Palette Snooping (VPS): This bit is hardwired to
0 to disable snooping.
4 RO 0b
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write
and invalidate commands.
3 RO 0b
Special Cycle Enable (SCE): This bit is hardwired to 0.
The IGD ignores Special cycles.
2 R/W 0b
Bus Master Enable (BME):
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1 R/W 0b
Memory Access Enable (MAE): This bit controls the
IGD response to memory space accesses.
0 = Disable
1 = Enable
0 R/W 0b
I/O Access Enable (IOAE): This bit controls the IGD
response to I/O space accesses.
0 = Disable
1 = Enable
Datasheet 369
Access: RO;
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the IGD.
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): Since the IGD does not
detect parity, this bit is always hardwired to 0.
14 RO 0b
Signaled System Error (SSE): The IGD never asserts
SERR#, therefore this bit is hardwired to 0.
13 RO 0b
Received Master Abort Status (RMAS): The IGD never
gets a Master Abort, therefore this bit is hardwired to 0.
12 RO 0b
Received Target Abort Status (RTAS): The IGD never
gets a Target Abort, therefore this bit is hardwired to 0.
11 RO 0b
Signaled Target Abort Status (STAS): Hardwired to 0.
The IGD does not use target abort semantics.
10:9 RO 00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired to
00.
8 RO 0b
Master Data Parity Error Detected (DPD): Since Parity
Error Response is hardwired to disabled (and the IGD does
not do any parity detection), this bit is hardwired to 0.
7 RO 1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD
accepts fast back-to-back when the transactions are not to
the same agent.
6 RO 0b User Defined Format (UDF): Hardwired to 0.
5 RO 0b 66-MHz PCI Capable (66C): N/A - Hardwired to 0.
4 RO 1b
Capability List (CLIST): This bit is set to 1 to indicate that
the register at 34h provides an offset into the function PCI
Configuration Space containing a pointer to the location of
the first item in the list.
3 RO 0b
Interrupt Status: This bit reflects the state of the interrupt
in the device. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1,
will the devices INTx# signal be asserted. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this
bit.
370 Datasheet
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
Following PCI Reset the SRID value is selected to be read. When a write occurs to this
register the write data is compared to the hardwired RID Select Key Value which is 69h.
If the data matches this key a flag is set that enables the CRID value to be read
Access: RO;
Size: 24 bits
This register contains the device programming interface information related to the Sub-
Class Code and Base Class Code definition for the IGD. This register also contains the
Base Class Code and the function sub-class in relation to the Base Class Code.
Bit Access
Default
Value
Description
7:0 RO 00h
Revision Identification Number (RID): This is an 8-
for the (G)MCH.
07h: B-3 stepping
Bit Access
Default
Value
Description
23:16 RO 03h
indicates the base class code for the (G)MCH. This code
has the value 03h, indicating a Display Controller.
15:8 RO 00h
Sub-Class Code (SUBCC): Based on Device 0 GGC-GMS
bits and GGC-IVD bits.
00h = VGA compatible
80h = Non VGA (GMS = 000 or IVD = 1)
7:0 RO 00h
Programming Interface (PI):
00h = Hardwired as a Display controller.
Datasheet 371
22.1.7 CLS - Cache Line Size
Address Offset: Ch
Default Value: 00h
Access: RO;
Size: 8 bits
The IGD does not support this register as a PCI slave.
22.1.8 MLT2 - Master Latency Timer
Address Offset: Dh
Default Value: 00h
Access: RO;
Size: 8 bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
22.1.9 HDR2 - Header Type
Address Offset: Eh
Default Value: 80h
Access: RO;
Size: 8 bits
This register contains the Header Type of the IGD.
Bit Access
Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS): This field is hardwired to 0s. The
IGD as a PCI compliant master does not use the Memory
Write and Invalidate command and, in general, does not
perform operations based on cache line size.
Bit Access
Default
Value
Description
7:0 RO 00h Master Latency Timer Count Value: Hardwired to 0s.
Bit Access
Default
Value
Description
7 RO 1b
Multi Function Status (MFunc): Indicates if the device is
a Multi-Function Device. The Value of this register is
determined by Device 0, offset 54h, DEVEN[4]. If Device 0
DEVEN[4] is set, the Mfunc bit is also set.
6:0 RO 00h
Header Code (H): This is a 7-bit value that indicates the
Header Code for the IGD. This code has the value 00h,
indicating a Type 0 configuration space format.
372 Datasheet
22.1.10 GTTMMADR - Graphics Translation Table Range Address
Access: RO; R/W;
Size: 64 bits
This register requests allocation for combined Graphics Translation table and Memory
Mapped Range. 4 MB combined for MMIO and Global GTT table aperture (512 KB for
MMIO and 2 MB for GTT). GTT base address will be: base address from GTTMMADR + 2
MB, and the MMIO base address will be the same as base address from GTTMMADR.
Bit Access
Default
Value
Description
35:22 R/W 0000h
Memory Base Address: Set by the BIOS, these bits
correspond to address signals [35:22]. 4 MB combined for
MMIO and Global GTT table aperture (512 KB for MMIO
and 2 MB for GTT).
3 RO 0b
Prefetchable Memory: Hardwired to 0 to prevent
prefetching.
2 RO 1b
Memory Type:
0 = To indicate 32-bit base address
1 = To indicate 64-bit base address
1 RO 0b Reserved
0 RO 0b
Memory/IO Space: Hardwired to 0 to indicate memory
space.
Datasheet 373
22.1.11 GMADR - Graphics Memory Range Address
Default Value: 000000000000000Ch
Access: R/W; R/W/L; RO;
Size: 64 bits
IGD graphics memory base address is specified in this register.
Bit Access
Default
Value
Description
35:29 R/W 00h
Memory Base Address: Set by the OS, these bits
correspond to address signals [35:29].
28 R/W/L 0b
512-MB Address Mask: This bit is either part of the
Memory Base Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev2, Func0, Offset 66) for details. This bit is
locked in Intel TXT mode (RO in Intel TXT mode).
27 R/W/L 0b
256-MB Address Mask: This bit is either part of the
Memory Base Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev2, Func0, offset 66h) for details. This bit is
locked in Intel TXT mode (RO in Intel TXT mode).
26:4 RO 000000h
Address Mask: Hardwired to 0s to indicate at least
128-MB address range.
3 RO 1b
Prefetchable Memory: Hardwired to 1 to enable
prefetching.
2 RO 1b
Memory Type:
0 = To indicate 32-bit base address.
1 RO 0b Reserved
0 RO 0b
space.
374 Datasheet
22.1.12 IOBAR - I/O Base Address
Access: RO; R/W
Size: 32 bits
This register provides the base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address
Space. Bits 2:1 are fixed and return zero, Bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded.
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD Bit 0)
set. Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device 2 is
turned off or if Internal graphics is disabled. Note that access to this IO BAR is
independent of VGA functionality within Device 2. Also note that this mechanism in
available only through Function 0 of Device 2 and is not duplicated in Function 1.
22.1.13 SVID2 - Subsystem Vendor Identification
Access: R/WO
Size: 16 bits
Bit Access
Default
Value
Description
31:16 RO 0000h
Reserved Read as 0's, these bits correspond to address
signals [31:16].
15:3 R/W 0000h
IO Base Address: Set by the OS, these bits correspond
to address signals [15:3].
2:1 RO 00b
Memory Type: Hardwired to 0s to indicate 32-bit
address.
0 RO 1b Memory/IO Space: Hardwired to 1 to indicate IO space.
Bit Access
Default
Value
Description
15:0 R/WO 0000h
Subsystem Vendor ID: This value is used to identify the
vendor of the subsystem. This register should be
programmed by BIOS during boot-up. Once written, this
register becomes Read_Only. This register can only be
cleared by a Reset.
Datasheet 375
22.1.14 SID2 - Subsystem Identification
Access: R/WO
Size: 16 bits
22.1.15 ROMADR - Video BIOS ROM Base Address
Access: RO;
Size: 32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
22.1.16 CAPPOINT - Capabilities Pointer
Address Offset: 34h
Default Value: 90h
Access: RO;
Size: 8 bits
Bit Access
Default
Value
Description
15:0 R/WO 0000h
Subsystem Identification: This value is used to identify a
particular subsystem. This field should be programmed by
BIOS during boot-up. Once written, this register becomes
Read_Only. This register can only be cleared by a Reset.
Bit Access
Default
Value
Description
31:18 RO 0000h ROM Base Address: Hardwired to 0s
17:11 RO 00h
Address Mask: Hardwired to 0s to indicate 256-KB
address range.
0 RO 0b ROM BIOS Enable: 0 = ROM not accessible.
Bit Access
Default
Value
Description
7:0 RO 90h
Capabilities Pointer Value: This field contains an offset
into the function's PCI Configuration Space for the first item
in the New Capabilities Linked List which is the MSI
Capabilities ID register at address 90h or the Power
Management Capabilities ID registers at address D0h. The
value is determined by CAPL[0]
376 Datasheet
22.1.17 INTRLINE - Interrupt Line
Address Offset: 3Ch
Default Value: 00h
Access: R/W
Size: 8 bits
22.1.18 INTRPIN - Interrupt Pin
Address Offset: 3Dh
Default Value: 01h
Access: RO;
Size: 8 bits
22.1.19 MINGNT - Minimum Grant
Address Offset: 3Eh
Default Value: 00h
Access: RO;
Size: 8 bits
Bit Access
Default
Value
Description
7:0 R/W 00h
Interrupt Connection: Used to communicate interrupt
line routing information. POST software writes the routing
information into this register as it initializes and
configures the system. The value in this register indicates
which input of the system interrupt controller that the
devices interrupt pin is connected to.
Bit Access
Default
Value
Description
7:0 RO 01h
Interrupt Pin: As a single function device, the IGD
specifies INTA# as its interrupt pin.
01h:INTA#.
Bit Access
Default
Value
Description
7:0 RO 00h
Minimum Grant Value: The IGD does not burst as a PCI
compliant master.
Datasheet 377
22.1.20 MAXLAT - Maximum Latency
Address Offset: 3Fh
Default Value: 00h
Access: RO
Size: 8 bits
22.1.21 MCAPPTR - Capabilities Pointer (to Mirror of Dev0 CAPID)
Address Offset: 44h
Default Value: 48h
Access: RO
Size: 8 bits
22.1.22 MGGC - Mirror of Dev0 (G)MCH Graphics Control
Access: RO
Size: 16 bits
All the Bits in this register are Intel TXT locked. In Intel TXT mode R/W bits are RO.
Bit Access
Default
Value
Description
7:0 RO 00h
Maximum Latency Value: The IGD has no specific
requirements for how often it needs to access the PCI bus.
Bit Access
Default
Value
Description
7:0 RO 48h
Capabilities Pointer Value: In this case the first
capability is the product-specific capability Identifier
(CAPID0).
(Sheet 1 of 2)
Bit Access
Default
Value
Description
11:8 RO 0h Reserved
378 Datasheet
7:4 RO 0011b
Graphics Mode Select (GMS): This field is used to select
the amount of Main Memory that is pre-allocated to support
the Internal Graphics device in VGA (non-linear) and Native
(linear) modes. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled.
0000: No memory pre-allocated. Device 2 (IGD) does not
claim VGA cycles (Mem and IO), and the Sub-Class Code
field within Device 2 Function 0 Class Code register is 80.
0001 = Reserved.
0010 = Reserved.
0011 = Reserved.
0100 = Reserved.
for frame buffer.
0110 = Reserved.
for frame buffer.
for frame buffer.
NOTES:
1. This register is locked and becomes Read Only when
the D_LCK bit in the SMRAM register is set. This
register is also Intel TXT lockable.
automatically based on IGD being disabled/enabled.
3:2 RO 00b Reserved
1 RO 0b
and IO cycles, the Sub-Class Code within Device 2 Class
Code register is 00.
Device 2 Function 0 Class Code register is 80.
0 RO 0b Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 379
22.1.23 MDEVENdev0F0 - Mirror of Dev0 DEVEN
Default Value: 0000001Bh
Access: RO
Size: 32 bits
this register.
Bit Access
Default
Value
Description
7 RO 0b Reserved
6:5 RO 00b Reserved
4 RO 1b
If Device 2 Function 0 is disabled and hidden, then Device 2
Function 1 is also disabled and hidden independent of the
state of this bit.
3 RO 1b
If this (G)MCH does not have internal graphics capability
then Device 2 Function 0 is disabled and hidden
2 RO 0b Reserved
1 RO 1b
PCI Express Graphics Port Enable. (D1EN):
0 = Bus 0 Device 1 Function 0 is disabled and hidden. Also
gates PCI Express internal clock (lgclk) and asserts PCI
Express internal reset (lgrstB).
Default value is determined by the device capabilities,
SDVO presence HW strap and SDVO/PCI Express
concurrent HW strap. Device 1 is disabled on Reset if
PCI Express Port is disabled OR the SDVO present strap
is sampled high and the SDVO/PCI Express concurrent
strap is sampled low.
0 RO 1b
Host Bridge: Bus 0 Device 0 Function 0 may not be
disabled and is therefore hardwired to 1.
380 Datasheet
22.1.24 SSRW - Software Scratch Read Write
Access: R/W
Size: 32 bits

22.1.25 BSM - Base of Stolen Memory
Address Offset: 5C-63h
Access: RO
Size: 64 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From
the top of low used DRAM, (G)MCH claims 1 to 64 MB of DRAM for internal graphics if
enabled.
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
35:32 RO 0h Base of Stolen Memory
31:20 RO 000h
Base of Data Stolen Memory (BSM): This register
contains bits 31 to 20 of the base address of data stolen
DRAM memory. The host interface determines the base of
graphics stolen memory by subtracting the graphics
stolen memory size from TOLUD. See Device 0 TOLUD for
more explanation.
Datasheet 381
22.1.26 HSRW - Hardware Scratch Read Write
Access: R/W
Size: 16 bits
22.1.27 MSAC - Multi Size Aperture Control
Address Offset: 66h
Default Value: 02h
Access: RO; R/W
Size: 8 bits
This register determines the size of the graphics memory aperture in Function 0. By
default the aperture size is 256 MB. Only the System BIOS will write this register based
on pre-boot address allocation efforts, but the graphics may read this register to
determine the correct aperture size. System BIOS needs to save this value on boot so
that it can reset it correctly during S3 resume.
Bit Access
Default
Value
Description
15:0 R/W 0000h Scratchpad Bits
Bit Access
Default
Value
Description
7:4 R/W 0h Scratch Bits Only: Have no physical effect on hardware.
3 RO 0b Reserved
2:1 R/W 01b
Aperture Size (LHSAS):
11 = bits [28:27] of GMADR register are made Read only
and forced to zero, allowing only 512 MB of GMADR
01 = bit [28] of GMADR is made R/W and bit [27] of
GMADR is forced to zero allowing 256 MB of GMADR
00/10 = Illegal programming.
This bit is Intel TXT locked, becomes read-only when
trusted environment is launched.
0 RO 0b Reserved
382 Datasheet
22.1.28 MC - Message Control
Access: RO; R/W
Size: 16 bits
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
Bit Access
Default
Value
Description
7 RO 0b
64-bit Address Capable: Hardwired to 0 to indicate that
the function does not implement the upper 32 bits of the
Message Address register and is incapable of generating a
64-bit memory address. This may need to change in
future implementations when addressable system
memory exceeds the 32-bit/4-GB limit.
6:4 R/W 000b
Multiple Message Enable (MME): System software
programs this field to indicate the actual number of
messages allocated to this device. This number will be
equal to or less than the number actually requested. The
encoding is the same as for the MMC field below.
3:1 RO 000b
Multiple Message Capable (MMC): System software
reads this field to determine the number of messages
being requested by this device.
Value: Number of Messages Requested 000: 1
All of the following are reserved in this implementation:
0012
0 R/W 0b
MSI Enable (MSIEN): Controls the ability of this device
to generate MSIs.
010 4
011 8
100 16
101 32
110 Reserved.
111 Reserved.
Datasheet 383
22.1.29 MA - Message Address
Access: RO; R/W
Size: 32 bits
A read from this register produces undefined results.
22.1.30 MD - Message Data
Access: R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:2 R/W 00000000h
Message Address: Used by system software to assign an
MSI address to the device. The device handles an MSI by
writing the padded contents of the MD register to this
address.
1:0 RO 00b
Force Dword Align: Hardwired to 0 so that addresses
assigned by system software are always aligned on a dword
address boundary.
Bit Access
Default
Value
Description
15:0 R/W 0000h
Message Data: Base message data pattern assigned by
system software and used to handle an MSI from the
device.
When the device must generate an interrupt request, it
writes a 32-bit value to the memory address specified in
the MA register. The upper 16 bits are always set to 0. The
lower 16 bits are supplied by this register.
384 Datasheet
22.1.31 PMCAPID - Power Management Capabilities ID
Address Offset: D0-D1h
Access: RO
Size: 16 bits
22.1.32 PMCAP - Power Management Capabilities
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 00h
NEXT_PTR (NEXT_PTR): This contains a pointer to next
item in capabilities list. This is the final capability in the
list and must be set to 00h.
7:0 RO 01h
CAP_ID (CAP_ID): SIG defines this ID is 01h for power
management.
Bit Access
Default
Value
Description
15:11 RO 00h
PME Support (PME_SUPPORT): This field indicates the
power states in which the IGD may assert PME#.
Hardwired to 0 to indicate that the IGD does not assert
the PME# signal.
10 RO 0b
D2 (D2): The D2 power management state is not
supported. This bit is hardwired to 0.
9 RO 0b
D1 (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
8:6 RO 000b Reserved. (RSVD):
5 RO 1b
indicate that special initialization of the IGD is required
before generic class device driver is to use it.
4 RO 0b
Auxiliary Power Source (AUXPWRSRC): Hardwired to
0.
3 RO 0b
PME Clock (PMECLK): Hardwired to 0 to indicate IGD
does not support PME# generation.
2:0 RO 011b
Version (VER): A value of 011b indicates that this
function complies with revision 1.2 of the PCI Power
Management Interface Specification
Datasheet 385
22.1.33 PMCS - Power Management Control/Status
Access: RO; R/W
Size: 16 bits

Bit Access
Default
Value
Description
15 RO 0b
PME_Status (PME_STATUS): This bit is 0 to indicate that
IGD does not support PME# generation from D3 (cold).
12:9 RO 0h Reserved
8 RO 0b
PME_En (PME_EN): This bit is 0 to indicate that PME#
assertion from D3 (cold) is disabled.
7:4 RO 0h Reserved
3 RO 0b Reserved
2 RO 0b Reserved
1:0 R/W 00b
PowerState (PWR_STATE): This field indicates the
current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to write
an unsupported state to this field, write operation must
complete normally on the bus, but the data is discarded and
no state change occurs.
On a transition from D3 to D0 the graphics controller is
optionally reset to initial values. Behavior of the graphics
controller in supported states is detailed in the power
management section of the BIOS specification.
Bits[1:0] Power state
00 D0 Default
01 D1 Not Supported
10 D2 Not Supported
11 D3
386 Datasheet
22.1.34 SWSMI - Software SMI
Access: R/W
Size: 16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev#2F0address E0h-E1h must be reserved for this register.
22.1.35 ASLE - System Display Event Register
Access: R/W
Size: 32 bits
The exact use of these bytes including whether they are addressed as bytes, words, or
as a dword, is not pre-determined but subject to change by driver and System BIOS
teams (acting in unison).
Bit Access
Default
Value
Description
15:8 R/W 00h SW Scratch Bits (SW_SCRATCH)
7:1 R/W 00h
Software Flag (SFTWARE_FLAG): Used to indicate
caller and SMI function desired, as well as return result.
0 R/W 0b
(G)MCH Software SMI Event
((G)MCH_SOFT_SMI_EVENT): When Set this bit will
trigger an SMI. Software must write a 0 to clear this bit.
Bit Access
Default
Value
Description
31:24 R/W 00h
ASLE Scratch Trigger3 (ASLE_SCRATCH_3): When
written, this scratch byte triggers an interrupt when IEF
Bit 0 is enabled and IMR Bit 0 is unmasked. If written as
part of a 16-bit or 32-bit write, only one interrupt is
generated in common.
23:16 R/W 00h
ASLE Scratch Trigger2 (ASLE_SCRATCH_2): When
15:8 R/W 00h
ASLE Scratch Trigger 1 (ASLE_SCRATCH_1): When
7:0 R/W 00h
ASLE Scratch Trigger 0 (ASLE_SCRATCH_0): When
Datasheet 387
22.1.36 GCFC - Graphics Clock Frequency Control
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
15 RO 0b Reserved
14 R/W 0b
Gate Core Display Clock (GCRC):
0 = cdclk is running
1 = cdclk is gated
13 RO 0b Reserved
12 R/W 1b Reserved
7 RO 0b Reserved
6 R/W 0b Reserved
5 R/W 0b Reserved
4 R/W 0b Reserved
3:0 R/W 0110b
Graphics Core Render Clock Select (CRCLKFREQ)
1000 = 266 MHz
1001 = 320 MHz
1011 = 400 MHz
1101 = 533 MHz
1110 = Reserved
Others = Reserved
388 Datasheet
22.1.37 LBB - Legacy Backlight Brightness
Access: R/W
Size: 32 bits
This register can be accessed by either Byte, Word, or dword PCI config cycles. A write
to this register will cause the Backlight Event (Display B Interrupt) if enabled.
Bit Access
Default
Value
Description
31:24 R/W 00h
LBPC Scratch Trigger3 (LBPC_SCRATCH_3): When
written, this scratch byte triggers an interrupt when LBEE is
enabled in the Pipe B Status register and the Display B
Event is enabled in IER and unmasked in IMR etc. If written
as part of a 16-bit or 32-bit write, only one interrupt is
23:16 R/W 00h
15:8 R/W 00h
7:0 R/W 00h
Legacy Backlight Brightness (LBES): The value of zero
is the lowest brightness setting and 255 is the brightest. A
write to this register will cause a flag to be set (LBES) in the
PIPEBSTATUS register and cause an interrupt if Backlight
event in the PIPEBSTATUS register and cause an Interrupt if
Backlight Event (LBEE) and Display B Event is enabled by
software.
Datasheet 389
22.1.38 ASLS - ASL Storage
Address Offset: FC-FFh
Access: R/W
Size: 32 bits
This software scratch register only needs to be read/write accessible. The exact bit
register usage must be worked out in common between System BIOS and driver
software. For each device, the ASL control method with require two bits for _DOD
(BIOS detectable yes or no, VGA/NonVGA), one bit for _DGS (enable/disable
requested), and two bits for _DCS (enabled now/disabled now, connected or not).
22.2 Device 2 Function 1 PCI Configuration Registers
Bit Access
Default
Value
Description
31:0 R/W 00000000h
Software Controlled Usage to Support Device
Switching (SOFT_CTRL_DEV_SWITCH): R/W
according to a software controlled usage to support
device switching
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
PCI Status PCISTS2 6 7 0090h RO
Class Code Register CC 9 B 038000h RO
Master Latency Timer MLT2 D D 00h RO
Reserved F F
Memory Mapped Range Address MMADR 10 17
0000000000000
004h
RO; R/W
Subsystem Vendor Identification SVID2 2C 2D 0000h RO
Subsystem Identification SID2 2E 2F 0000h RO
Video BIOS ROM Base Address ROMADR 30 33 00000000h RO
Capabilities Pointer CAPPOINT 34 34 D0h RO
Minimum Grant MINGNT 3E 3E 00h RO
Maximum Latency MAXLAT 3F 3F 00h RO
Mirror of Dev0 Capability Pointer MCAPPTR 44 44 48h RO
390 Datasheet
Reserved 48 51
Mirror of Dev0 (G)MCH Graphics
Control
MGGC 52 53 0030h RO
Mirror of Dev0 DEVEN
MDEVENdev0
F0
54 57 0000001Bh RO
Software Scratch Read Write SSRW 58 5B 00000000h RO
Base of Stolen Memory BSM 5C 63
0000000000000
000h
RO
Hardware Scratch Read Write HSRW 64 65 0000h RO
Multi Size Aperture Control MSAC 66 66 02h RO
Reserved A8 CF
Power Management Capabilities
ID
PMCAPID D0 D1 0001h RO
Power Management Capabilities PMCAP D2 D3 0023h RO
Status
PMCS D4 D5 0000h RO; R/W
Reserved DA DC
Software SMI SWSMI E0 E1 0000h RO
System Display Event Register ASLE E4 E7 00000000h RO
Software SCI SWSCI E8 E9 0000h RO
Graphics Clock Frequency and
Gating Control
GCFGC F0 F1 1606h RO
Graphics Clock PLL Control GCPLLC F2 F3 0734h RO
Legacy Backlight Brightness LBB F4 F7 00000000h RO
Manufacturing ID MID2 F8 FB 00000F90h RO
ASL Storage ASLS FC FF 00000000h R/W
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Datasheet 391
Access: RO
Size: 16 bits
PCI device.
Access: RO
Size: 16 bits
This register is unique in Function 1 (the Function 0 DID is separate). This difference in
Device ID's is necessary for allowing distinct Plug and Play enumeration of Function 1
when both Function 0 and Function 1 have the same class code.
Bit Access
Default
Value
Description
15:0 RO 8086h
Bit Access
Default
Value
Description
15:0 RO 2A43h
assigned to the (G)MCH Device 2 Function 1.
392 Datasheet
Access: RO; R/W
Size: 16 bits
This 16-bit register provides basic control over the IGD ability to respond to PCI cycles.
The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to
main memory.
Bit Access
Default
Value
Description
10 RO 0b Reserved
9 RO 0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired
to 0.
8 RO 0b SERR Enable (SERRE): Not Implemented. Hardwired to 0.
7 RO 0b
Address/Data Stepping Enable (ADSTEP): Not
6 RO 0b
Parity Error Enable (PERRE): Not Implemented.
Hardwired to 0.
Since the IGD belongs to the category of devices that does
not corrupt programs or data in system memory or hard
drives, the IGD ignores any parity error that it detects and
continues with normal operation.
5 RO 0b
VGA Palette Snoop Enable (VGASNOOP): This bit is
hardwired to 0 to disable snooping.
4 RO 0b
Hardwired to 0. The IGD does not support memory write
and invalidate commands.
3 RO 0b
Special Cycle Enable (SCE): This bit is hardwired to 0.
The IGD ignores Special cycles.
2 R/W 0b
Bus Master Enable (BME): Set to 1 to enable the IGD to
function as a PCI compliant master. Set to 0 to disable IGD
bus mastering.
1 R/W 0b
Memory Access Enable (MAE): This bit controls the IGD
response to memory space accesses.
0 = Disable
1 = Enable
0 R/W 0b
I/O Access Enable (IOAE): This bit controls the IGD
response to I/O space accesses.
0 = Disable
1 = Enable
Datasheet 393
Access: RO
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the IGD.
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): Since the IGD does not
detect parity, this bit is always hardwired to 0.
14 RO 0b
Signaled System Error (SSE): The IGD never asserts
SERR#, therefore this bit is hardwired to 0.
13 RO 0b
Received Master Abort Status (RMAS): The IGD never
gets a Master Abort, therefore this bit is hardwired to 0.
12 RO 0b
Received Target Abort Status (RTAS): The IGD never
gets a Target Abort, therefore this bit is hardwired to 0.
11 RO 0b
Signaled Target Abort Status (STAS): Hardwired to 0.
The IGD does not use target abort semantics.
10:9 RO 00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired
to 00.
8 RO 0b
Master Data Parity Error Detected (DPD): Since
Parity Error Response is hardwired to disabled (and the
IGD does not do any parity detection), this bit is
hardwired to 0.
7 RO 1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD
accepts fast back-to-back when the transactions are not
to the same agent.
6 RO 0b User Defined Format (UDF): Hardwired to 0.
5 RO 0b 66-MHz PCI Capable (66C): N/A - Hardwired to 0.
4 RO 1b
Capability List (CLIST): This bit is set to 1 to indicate
that the register at 34h provides an offset into the
function PCI Configuration Space containing a pointer to
the location of the first item in the list.
3 RO 0b Interrupt Status: Hardwired to 0.
2:0 RO 0h Reserved
394 Datasheet
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
22.2.6 CC - Class Code Register
Access: RO
Size: 24 bits
This register contains the device programming interface information related to the Sub-
Class Code and Base Class Code definition for the IGD. This register also contains the
Base Class Code and the function sub-class in relation to the Base Class Code.
Bit Access
Default
Value
Description
7:0 RO 00h
Revision Identification Number (RID): This is an 8-bit
value that indicates the revision identification number for
the (G)MCH.
07h: B-3 stepping
Bit Access
Default
Value
Description
23:16 RO 03h
indicates the base class code for the (G)MCH. This code has
the value 03h, indicating a Display Controller.
15:8 RO 80h
Sub-Class Code (SUBCC):
80h = Non VGA
7:0 RO 00h
Programming Interface (PI):
00h = Hardwired as a Display controller.
Datasheet 395
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
The IGD does not support this register as a PCI slave.
22.2.8 MLT2 - Master Latency Timer
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
22.2.9 HDR2 - Header Type
Address Offset: Eh
Default Value: 80h
Access: RO
Size: 8 bits
This register contains the Header Type of the IGD.
Bit Access
Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS): This field is hardwired to 0s.
The IGD as a PCI-compliant master does not use the
Memory Write and Invalidate command and, in general,
does not perform operations based on cache line size.
Bit Access
Default
Value
Description
7:0 RO 00h Master Latency Timer Count Value: Hardwired to 0s.
Bit Access
Default
Value
Description
7 RO 1b
Multi Function Status (MFunc): Indicates if the device is
a Multi-Function Device. The Value of this register is
determined by Device 0, offset 54h, DEVEN[4]. If Device 0
DEVEN[4] is set, the Mfunc bit is also set.
6:0 RO 00h
Header Code (H): This is a 7-bit value that indicates the
Header Code for the IGD. This code has the value 00h,
indicating a Type 0 configuration space format.
396 Datasheet
22.2.10 BIST - Built In Self Test
Address Offset: Fh
Default Value: 00h
Access: RO
Size: 8 bits
This register is used for control and status of Built In Self Test (BIST).
22.2.11 MMADR - Memory Mapped Range Address
Access: RO; R/W
Size: 64 bits
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by Bits [35:20].
Bit Access
Default
Value
Description
7 RO 0b
BIST Supported: BIST is not supported. This bit is
hardwired to 0.
6:0 RO 00h Reserved
Bit Access
Default
Value
Description
35:20 R/W 0000h
Memory Base Address: Set by the OS, these bits
correspond to address signals [35:20].
19:4 RO 0000h
Address Mask: Hardwired to 0's to indicate 512-KB
address range (aligned to 1-M boundary).
3 RO 0b
Prefetchable Memory: Hardwired to 0 to prevent
prefetching.
2 RO 1b
Memory Type:
1 RO 0b Reserved
0 RO 0b
space.
Datasheet 397
22.2.12 SVID2 - Subsystem Vendor Identification
Access: RO
Size: 16 bits
22.2.13 SID2 - Subsystem Identification
Access: RO
Size: 16 bits
22.2.14 ROMADR - Video BIOS ROM Base Address
Access: RO
Size: 32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Bit Access
Default
Value
Description
15:0 RO 0000h
Subsystem Vendor ID: This value is used to identify the
vendor of the subsystem. This register should be
programmed by BIOS during boot-up. Once written, this
register becomes Read_Only. This register can only be
cleared by a Reset.
NOTE: This is a RO copy of the Dev2Fn0 value.
Bit Access
Default
Value
Description
15:0 RO 0000h
Subsystem Identification: This value is used to identify a
particular subsystem. This field should be programmed by
BIOS during boot-up. Once written, this register becomes
Read_Only. This register can only be cleared by a Reset.
NOTE: This is a RO copy of the Dev2Fxn0 value.
Bit Access
Default
Value
Description
31:18 RO 0000h ROM Base Address: Hardwired to 0.
17:11 RO 00h
Address Mask: Hardwired to 0s to indicate 256-KB
address range.
10:1 RO 000h Reserved Hardwired to 0s.
0 RO 0b ROM BIOS Enable: 0 = ROM not accessible.
398 Datasheet
22.2.15 CAPPOINT - Capabilities Pointer
Address Offset: 34h
Default Value: D0h
Access: RO
Size: 8 bits
22.2.16 MINGNT - Minimum Grant
Address Offset: 3Eh
Default Value: 00h
Access: RO
Size: 8 bits
22.2.17 MAXLAT - Maximum Latency
Address Offset: 3Fh
Default Value: 00h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO D0h
Capabilities Pointer Value (CPV): This field contains
an offset into the function's PCI Configuration Space for
the first item in the New Capabilities Linked List which is
the Power Management Capabilities ID registers at
address D0h.
Bit Access
Default
Value
Description
7:0 RO 00h
Minimum Grant Value: The IGD does not burst as a
PCI-compliant master.
Bit Access
Default
Value
Description
7:0 RO 00h
Maximum Latency Value: The IGD has no specific
requirements for how often it needs to access the PCI bus.
Datasheet 399
22.2.18 MCAPPTR - Mirror of Dev0 Capability Pointer
Address Offset: 44h
Default Value: 48h
Access: RO
Size: 8 bits
22.2.19 MGGC - Mirror of Dev0 (G)MCH Graphics Control
Access: RO
Size: 16 bits
All the bits in this register are Intel TXT locked. In Intel TXT mode R/W bits are RO.
Bit Access
Default
Value
Description
7:0 RO 48h
Capabilities Pointer Value: In this case the first
capability is the product-specific capability Identifier
(CAPID0).
(Sheet 1 of 2)
Bit Access
Default
Value
Description
11:8 RO 0h Reserved
400 Datasheet
7:4 RO 0011b
Graphics Mode Select (GMS): This field is used to
select the amount of Main Memory that is pre-allocated to
support the Internal Graphics device in VGA (non-linear)
and Native (linear) modes. The BIOS ensures that
memory is pre-allocated only when Internal graphics is
enabled.
0000 = No memory pre-allocated. Device 2 (IGD) does
not claim VGA cycles (Mem and IO), and the Sub-
Class Code field within Device 2 Function 0 Class
Code register is 80.
0001 = Reserved.
0010 = Reserved.
0011 = Reserved.
0100 = Reserved.
0110 = Reserved.
NOTES:
1. This register is locked and becomes Read Only
when the D_LCK bit in the SMRAM register is set.
This register is also Intel TXT lockable.
automatically based on IGD being disabled/
enabled.
3:2 RO 00b Reserved
1 RO 0b
and IO cycles, the Sub-Class Code within Device 2
Class Code register is 00.
Device 2 Function 0 Class Code register is 80.
0 RO 0b Reserved
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Datasheet 401
22.2.20 MDEVENdev0F0 - Mirror of Dev0 DEVEN
Default Value: 0000001Bh
Access: RO
Size: 32 bits
this register.
Bit Access
Default
Value
Description
7 RO 0b Reserved
6:5 RO 00b Reserved
4 RO 1b
If Device 2 Function 0 is disabled and hidden, then Device
2 Function 1 is also disabled and hidden independent of
the state of this bit.
3 RO 1b
If this (G)MCH does not have internal graphics capability
then Device 2 Function 0 is disabled and hidden
2 RO 0b Reserved
1 RO 1b
PCI Express* Graphics Port Enable. (D1EN):
Also gates PCI Express internal clock (lgclk) and
asserts PCI Express internal reset (lgrstB).
Default value is determined by the device capabilities,
SDVO presence HW strap and SDVO/PCI Express
concurrent HW strap. Device 1 is disabled on Reset if
PCI Express Port is disabled OR the SDVO present
strap is sampled high and the SDVO/PCI Express
concurrent strap is sampled low.
0 RO 1b
Host Bridge: Bus 0 Device 0 Function 0 may not be
disabled and is therefore hardwired to 1.
402 Datasheet
22.2.21 BSM - Base of Stolen Memory
Address Offset: 5C-63h
Access: RO
Size: 64 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From
the top of low used DRAM, (G)MCH claims 1 to 64 MB of DRAM for internal graphics if
enabled.
22.2.22 HSRW - Hardware Scratch Read Write
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
35:32 RO 0h Base of Stolen Memory:
31:20 RO 000h
Base of Stolen Memory (BSM): This register contains
Bits 31 to 20 of the base address of stolen DRAM memory.
The host interface determines the base of graphics stolen
memory by subtracting the graphics stolen memory size
from TOLUD. See Device 0 TOLUD for more explanation.
Bit Access
Default
Value
Description
Datasheet 403
22.2.23 MSAC - Multi Size Aperture Control
Address Offset: 66h
Default Value: 02h
Access: RO
Size: 8 bits
This register determines the size of the graphics memory aperture in Function 0. By
default, the aperture size is 256 MB. Only the System BIOS will write this register
based on pre-boot address allocation efforts, but the graphics may read this register to
determine the correct aperture size. System BIOS needs to save this value on boot so
that it can reset it correctly during S3 resume.
22.2.24 PMCAPID - Power Management Capabilities ID
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
7:4 RO 0h Scratch Bits Only: Have no physical effect on hardware.
3 RO 0b Reserved
2:1 RO 01b
Aperture Size (LHSAS):
11 = Bits [28:27] of GMADR register are made Read only
and forced to zero, allowing only 512 MB of GMADR
01 = Bit [28] of GMADR is made R/W and bit [27] of
GMADR is forced to zero allowing 256 MB of GMADR
00/10 = Illegal programming.
This bit is Intel TXT locked, becomes read-only when
trusted environment is launched.
0 RO 0b Reserved
Bit Access
Default
Value
Description
15:8 RO 00h
NEXT_PTR (NEXT_PTR): This contains a pointer to next
item in capabilities list. This is the final capability in the list
and must be set to 00h.
7:0 RO 01h
CAP_ID (CAP_ID): PCI-SIG defines this ID is 01h for
power management.
404 Datasheet
22.2.25 PMCAP - Power Management Capabilities
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:11 RO 00h
PME Support (PME_SUPPORT): This field indicates the
power states in which the IGD may assert PME#. Hardwired
to 0 to indicate that the IGD does not assert the PME#
signal.
10 RO 0b
D2 (D2): The D2 power management state is not
supported. This bit is hardwired to 0.
9 RO 0b
D1 (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
8:6 RO 000b Reserved. (RSVD):
5 RO 1b
indicate that special initialization of the IGD is required
before generic class device driver is to use it.
4 RO 0b
Auxiliary Power Source (AUX_PWR_SRC): Hardwired
to 0.
3 RO 0b
PME Clock (PME_CLK): Hardwired to 0 to indicate IGD
does not support PME# generation.
2:0 RO 011b
Version (VER): A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management
Interface Specification
Datasheet 405
22.2.26 PMCS - Power Management Control/Status
Access: RO; R/W
Size: 16 bits
Note: This register is not mirrored in Dev2 Func1 space (i.e., Dev2 Func1 PMCS is completely
independent register). Bits [1:0] power state of IGD - should be updated in both
Dev2 Func0 and Dev2 Func1.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
15 RO 0b
PME_Status (PME_STATUS): This bit is 0 to indicate
that IGD does not support PME# generation from D3
(cold).
14:13 RO 00b
Data Scale (Reserved): The IGD does not support data
register. This bit always returns 0 when read, write
operations have no effect.
12:9 RO 0h
Data_Select (Reserved): The IGD does not support
data register. This bit always returns 0 when read, write
8 RO 0b
PME_En (PME_EN): This bit is 0 to indicate that PME#
assertion from D3 (cold) is disabled.
7:4 RO 0h
Reserved (RSVD): Always returns 0 when read, write
3 RO 0b
No_Soft_reset (NOSOFTRESET): When set (1), this bit
indicates that devices transitioning from D
3hot
to D0
because of PowerState commands do no perform an
internal reset. Configuration Context is preserved. Upon
transition from D
3hot
to the D0 initialized state, no
additional operating system intervention is required to
preserve Configuration Context beyond writing the
PowerState bits.
When clear (0) devices do perform an internal reset upon
transitioning from D
3hot
to D0 via software control of the
performing the soft reset. Upon transition from the D
3hot

return the device to D0 initialized.
Regardless of this bit, devices that transition from D
3hot
to
D0 by a system or bus segment reset will return to the
device state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2 RO 0b
Reserved (RSVD): Always returns 0 when read, write
406 Datasheet
22.2.27 SWSMI - Software SMI
Access: R/W
Size: 16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev#2F0address E0h-E1h must be reserved for this register.
1:0 R/W 00b
PowerState (PWR_STATE): This field indicates the
current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to write
an unsupported state to this field, write operation must
complete normally on the bus, but the data is discarded
and no state change occurs.
On a transition from D3 to D0 the graphics controller is
optionally reset to initial values. Behavior of the graphics
controller in supported states is detailed in the power
management section of the BIOS specification
Bits [1:0] of PMCS register should be programmed in both
dev2 func0 and dev2 func1
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bits[1:0] Power state
00 D0 Default
01 D1 Not Supported
10 D2 Not Supported
11 D3
Bit Access
Default
Value
Description
15 RO 0b
SMI or SCI Event Select (SMISCISEL): If selected
event source is SMI, SMI trigger and associated scratch
bits accesses are performed via SWSMI register at offset
E0h. If SCI event source is selected, the rest of the bits in
this register provide SCI trigger capability and associated
SW scratch pad area.
14:1 RO 0000h
SW Scratch Bits (SW_SCRATCH): R/W bits not used by
hardware. Scratch.
0 RO 0b
(G)MCH Software SCI Event (GSSCIE): If SCI event is
selected (SMISCISEL = 1), on a 0 to 1 transition of
GSSCIE bit, (G)MCH will send a SCI message via DMI link
to ICH to cause the TCOSCI_STS bit in its GPE0 register to
be set to 1.
Software must write a 0 to clear this bit.
Datasheet 407
22.2.28 GCFGC - Graphics Clock Frequency and Gating Control
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15 RO 0b Reserved
14 R/W 0b
Gate Core Display Clock (GCRC):
0 = cdclk is running
1 = cdclk is gated
13 RO 0b Reserved
12 R/W 1b Reserved
7 RO 0b Reserved
6 R/W 0b Reserved
5 R/W 0b Reserved
4 R/W 0b Reserved
408 Datasheet
22.2.29 LBB - Legacy Backlight Brightness
Access: RO
Size: 32 bits
This register can be accessed by either byte, word, or dword PCI config cycles. A write
to this register will cause the Backlight Event (Display B Interrupt) if enabled.
Bit Access
Default
Value
Description
31:24 RO 00h
written, this scratch byte triggers an interrupt when LBEE
is enabled in the Pipe B Status register and the Display B
Event is enabled in IER and unmasked in IMR, etc. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
(Mirrored from Dev2 Func0)
23:16 RO 00h
15:8 RO 00h
7:0 RO 00h
Legacy Backlight Brightness (LBES): The value of
zero is the lowest brightness setting and 255 is the
brightest. A write to this register will cause a flag to be
set (LBES) in the PIPEBSTATUS register and cause an
interrupt if Backlight event in the PIPEBSTATUS register
and cause an Interrupt if Backlight Event (LBEE) and
Display B Event is enabled by software.
Datasheet 409
Intel Management Engine Subsystem PCI Device 3
23 Intel Management Engine
Subsystem PCI Device 3
23.1 Intel Management Engine Interface (Intel
MEI) PCI Device 3 Function 0
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Identifiers ID 0 3 2A448086h RO
Command CMD 4 5 0000h RO; R/W
Device Status STS 6 7 0010h RO
Header Type HTYPE E E 80h RO
Built-In Self Test BIST F F 00h RO
HECI MMIO Base Address HECI_MBAR 10 17
00000000000
00004h
RO; R/W
Sub System Identifiers SS 2C 2F 00000000h R/WO
Capabilities Pointer CAP 34 34 50h RO
Interrupt Information INTR 3C 3D 0100h RO; R/W
Minimum Grant MGNT 3E 3E 00h RO
Maximum Latency MLAT 3F 3F 00h RO
Host Firmware Status HFS 40 43 00000000h RO
PCI Power Management capability
ID
PID 50 51 8C01h RO
PCI Power Management
Capabilities
PC 52 53 C803h RO
PCI Power Management Control
and Status
PMCS 54 55 0008h R/WC; RO; R/W
Message Signaled Interrupt
Identifiers
MID 8C 8D 0005h RO
Message Control
MC 8E 8F 0080h RO; R/W
Message Address
MA 90 93 00000000h RO; R/W
410 Datasheet
23.1.1 ID - Identifiers
Access: RO
Size: 32 bits
23.1.2 CMD - Command
Access: RO; R/W
Size: 16 bits
Reserved 94 97
Message Data
MD 98 99 0000h R/W
HECI Interrupt Delivery Mode HIDM A0 A0 00h R/W
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Bit Access
Default
Value
Description
31:16 RO 2A44h
Device ID (DID): Indicates the device number assigned
by Intel.
15:0 RO 8086h
Vendor ID (VID): 16-bit field which indicates Intel is the
vendor, assigned by the PCI SIG.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
10 R/W 0b
Interrupt Disable (ID): Disables this device from
generating PCI line based interrupts. This bit does not
have any effect on MSI operation.
9 RO 0b
Fast Back-to-Back Enable (FBE): Not implemented,
hardwired to 0.
8 RO 0b SERR# Enable (SEE): Not implemented, hardwired to 0.
7 RO 0b
Wait Cycle Enable (WCC): Not implemented, hardwired
to 0.
6 RO 0b
Parity Error Response Enable (PEE): Not
implemented, hardwired to 0.
5 RO 0b
VGA Palette Snooping Enable (VGA): Not
implemented, hardwired to 0
Datasheet 411
4 RO 0b
3 RO 0b
Special Cycle Enable (SCE): Not implemented,
hardwired to 0.
2 R/W 0b
Bus Master Enable (BME): Controls the Intel MEI host
controller's ability to act as a system memory master for
data transfers. When this bit is cleared, Intel MEI bus
master activity stops and any active DMA engines return
to an idle condition. This bit is made visible to firmware
through the H_PCI_CSR register, and changes to this bit
may be configured by the H_PCI_CSR register to generate
an Intel MEI MSI.
When this bit is 0, Intel MEI is blocked from generating
MSI to the host CPU.
NOTE: This bit does not block Intel MEI accesses to Intel
Management Engine -UMA, i.e., writes or reads to
the host and Intel Management Engine circular
buffers through the read window and write window
registers still cause Intel Management Engine
backbone transactions to Intel Management
Engine -UMA.
1 R/W 0b
Memory Space Enable (MSE): Controls access to the
Intel MEI host controllers memory mapped register
space.
0 RO 0b
I/O Space Enable (IOSE): Not implemented, hardwired
to 0.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
412 Datasheet
23.1.3 STS - Device Status
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): Not implemented,
hardwired to 0.
14 RO 0b
Signaled System Error (SSE): Not implemented,
hardwired to 0.
13 RO 0b
Received Master-Abort (RMA): Not implemented,
hardwired to 0.
12 RO 0b
Received Target Abort (RTA): Not implemented,
hardwired to 0.
11 RO 0b
Signaled Target-Abort (STA): Not implemented,
hardwired to 0.
10:9 RO 00b
DEVSEL# Timing (DEVT): These bits are hardwired to
00.
8 RO 0b
Master Data Parity Error Detected (DPD): Not
7 RO 0b
Fast Back-to-Back Capable (FBC): Not implemented,
hardwired to 0.
6 RO 0b Reserved
5 RO 0b
66-MHz Capable (C66): Not implemented, hardwired to
0.
4 RO 1b
Capabilities List (CL): Indicates the presence of a
capabilities list, hardwired to 1.
3 RO 0b
Interrupt Status (IS): Indicates the interrupt status of
the device (1 = asserted).
Datasheet 413
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
Access: RO
Size: 24 bits
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO 00h
Revision ID (RID): Indicates stepping of the Intel MEI
host controller.
07h: B-3 stepping
Bit Access
Default
Value
Description
23:16 RO 07h
Base Class Code (BCC): Indicates the base class code of
the Intel MEI host controller device.
15:8 RO 80h
Sub Class Code (SCC): Indicates the sub class code of
7:0 RO 00h
Programming Interface (PI): Indicates the
programming interface of the Intel MEI host controller
device.
Bit Access
Default
Value
Description
7:0 RO 00h Cache Line Size (CLS): Not implemented, hardwired to 0.
414 Datasheet
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
23.1.8 HTYPE - Header Type
Address Offset: Eh
Default Value: 80h
Access: RO
Size: 8 bits
23.1.9 HECI_MBAR - Intel MEI MMIO Base Address
Access: RO; R/W
Size: 64 bits
Bit Access
Default
Value
Description
7:0 RO 00h
Master Latency Timer (MLT): Not implemented,
hardwired to 0.
Bit Access
Default
Value
Description
7 RO 1b
Multi-Function Device (MFD): Indicates the Intel MEI
host controller is part of a multi-function device.
6:0 RO 0000000b
Header Layout (HL): Indicates that the Intel MEI host
controller uses a target device layout.
Bit Access
Default
Value
Description
63:4 R/W
00000000
0000000h
Base Address (BA): Base address of register memory
space.
3 RO 0b
Prefetchable (PF): Indicates that this range is not
prefetchable
2:1 RO 10b
Type (TP): Indicates that this range can be mapped
anywhere in 64-bit address space.
0 RO 0b
Resource Type Indicator (RTE): Indicates a request
for register memory space.
Datasheet 415
23.1.10 SS - Sub System Identifiers
Access: R/WO
Size: 32 bits
23.1.11 CAP - Capabilities Pointer
Address Offset: 34h
Default Value: 50h
Access: RO
Size: 8 bits
23.1.12 INTR - Interrupt Information
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:16 R/WO 0000h
Subsystem ID (SSID): Indicates the sub-system
identifier. This field should be programmed by BIOS during
boot-up. Once written, this register becomes Read Only.
This field can only be cleared by PLTRST#.
15:0 R/WO 0000h
Subsystem Vendor ID (SSVID): Indicates the sub-
system vendor identifier. This field should be programmed
by BIOS during boot-up. Once written, this register
becomes Read Only. This field can only be cleared by
PLTRST#.
Bit Access
Default
Value
Description
7:0 RO 50h
Capability Pointer (CP): Indicates the first capability
pointer offset. It points to the PCI power management
capability offset.
Bit Access
Default
Value
Description
15:8 RO 01h
Interrupt Pin (IPIN): This indicates the interrupt pin the
Intel MEI host controller uses. The value of 01h selects
INTA# interrupt pin. Note: As Intel MEI is an internal device
in the (G)MCH, the INTA# pin is implemented as an INTA#
message to the ICH.
7:0 R/W 00h
Interrupt Line (ILINE): Software written value to indicate
which interrupt line (vector) the interrupt is connected to.
No hardware action is taken on this register.
416 Datasheet
23.1.13 HFS - Host Firmware Status
Access: RO
Size: 32 bits
23.1.14 PID - PCI Power Management Capability ID
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
31:0 RO 00000000h
Firmware Status Host Access (FS_HA): Indicates
current status of the firmware for the Intel MEI controller.
This field is the host's read only access to the FS field in
the Intel Management Engine Firmware Status AUX
register.
Bit Access
Default
Value
Description
15:8 RO 8Ch
Next Capability (NEXT): Indicates the location of the
next capability item in the list. This is the Message
Signaled Interrupts capability.
7:0 RO 01h
Cap ID (CID): Indicates that this pointer is a PCI power
management.
Datasheet 417
23.1.15 PC - PCI Power Management Capabilities
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:11 RO 11001b
PME_Support (PSUP): Indicates the states that can
generate PME#.
Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10 RO 0b
D2_Support (D2S): The D2 state is not supported for
the Intel MEI host controller.
9 RO 0b
D1_Support (D1S): The D1 state is not supported for
the Intel MEI host controller.
8:6 RO 000b
Aux_Current (AUXC): Reports the maximum Suspend
well current required when in the D3COLD state.
5 RO 0b
Device Specific Initialization (DSI): Indicates whether
device-specific initialization is required.
4 RO 0b Reserved
3 RO 0b
PME Clock (PMEC): Indicates that PCI clock is not
required to generate PME#.
2:0 RO 011b
Version (VS): Indicates support for Revision 1.2 of the
PCI Power Management Specification.
418 Datasheet
23.1.16 PMCS - PCI Power Management Control and Status
Access: R/WC; RO; R/W
Size: 16 bits

Bit Access
Default
Value
Description
15 R/WC 0b
PME Status (PMES): The PME Status bit in Intel MEI
space can be set to 1 by ARC FW performing a write into
AUX register to set PMES.
This bit is cleared by host CPU writing a 1 to it. ARC
cannot clear this bit. Host CPU writes with value 0 have
no effect on this bit. This bit is reset to 0 by MRST#
14:9 RO 000000b Reserved.
8 R/W 0b
PME Enable (PMEE): This bit is read/write, under
control of host S/W. It does not directly have an effect on
PME events. However, this bit is shadowed into AUX space
so ARC F/W can monitor it. The ARC F/W is responsible
for ensuring that F/W does not cause the PME-S bit to
transition to 1 while the PMEE bit is 0, indicating that host
S/W had disabled PME.
This bit is reset to 0 by MRST#
3 RO 1b Reserved
2 RO 0b Reserved
1:0 R/W 00b
Power State (PS): This field is used both to determine
the current power state of the Intel MEI host controller
and to set a new power state. The values are:
00 - D0 state
11 - D3HOT state
The D1 and D2 states are not supported for this Intel MEI
host controller. When in the D3HOT state, the HBAs
configuration space is available, but the register memory
spaces are not. Additionally, interrupts are blocked. This
field is visible to firmware through the H_PCI_CSR
register, and changes to this field may be configured by
the H_PCI_CSR register to generate an Intel Management
Engine MSI.
Datasheet 419
23.1.17 MID - Message Signaled Interrupt Identifiers
Access: RO
Size: 16 bits
23.1.18 MC - Message Signaled Interrupt Message Control
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 00h
Next Pointer (NEXT): Indicates the next item in the list.
This can be other capability pointers (such as PCI-X or PCI
Express) or it can be the last item in the list.
7:0 RO 05h Capability ID (CID): Capabilities ID indicates MSI.
Bit Access
Default
Value
Description
7 RO 1b
64-Bit Address Capable (C64): Specifies whether capable
of generating 64-bit messages.
6:4 RO 000b
Multiple Message Enable (MME): Not implemented,
hardwired to 0.
3:1 RO 000b
Multiple Message Capable (MMC): Not implemented,
hardwired to 0.
0 R/W 0b
MSI Enable (MSIE): If set, MSI is enabled and traditional
interrupt pins are not used to generate interrupts.
420 Datasheet
23.1.19 MA - Message Signaled Interrupt Message Address
Access: RO; R/W
Size: 32 bits
23.1.20 MD - Message Signaled Interrupt Message Data
Access: R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:2 R/W 00000000h
Address (ADDR): Lower 32 bits of the system specified
message address, always DW aligned.
MSI is not translated in Intel VT-d, therefore, in order
to avoid sending bad MSI with address bit [31:20] will be
masked internally to generate 12'hFEE regardless of
content in register. Register attribute remains as R/W.
1:0 RO 00b Reserved
Bit Access
Default
Value
Description
15:0 R/W 0000h
Data (Data): This 16-bit field is programmed by system
software if MSI is enabled. Its content is driven onto the
FSB during the data phase of the MSI memory write
transaction.
Datasheet 421
23.1.21 HIDM - Intel MEI Interrupt Delivery Mode
Address Offset: A0h
Default Value: 00h
Access: R/W
Size: 8 bits
This register is used to select interrupt delivery mechanism for Intel MEI to Host CPU
interrupts.
Bit Access
Default
Value
Description
7:2 RO 0h Reserved
1:0 R/W 00b
Intel MEI Interrupt Delivery Mode (HIDM): These bits
control what type of interrupt the Intel MEI will send. They
are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
422 Datasheet
23.2 Intel MEI PCI Device 3 Function 1
Register Name
Register
Symbol
Register
Start
Register
End
Identifiers ID 0 3 2A458086h RO
Command CMD 4 5 0000h RO; R/W
Device Status STS 6 7 0010h RO
Header Type HTYPE E E 80h RO
Built-In Self Test BIST F F 00h RO
HECI MMIO Base Address HECI_MBAR 10 17
0000000000000
004h
RO; R/W
Capabilities Pointer CAP 34 34 50h RO
Reserved 3E 3F
Host Firmware Status HFS 40 43 00000000h RO
Capability ID
PID 50 51 8C01h RO
Capabilities
PC 52 53 C803h RO
and Status
PMCS 54 55 0008h
RO; R/W; R/
WC
Identifiers
MID 8C 8D 0005h RO
Message Control
MC 8E 8F 0080h RO; R/W
Message Address
MA 90 93 00000000h RO; R/W
Message Data
MD 98 99 0000h R/W
HECI Interrupt Delivery Mode HIDM A0 A0 00h R/W
Datasheet 423
23.2.1 ID - Identifiers
Access: RO
Size: 32 bits
23.2.2 CMD - Command
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:16 RO 2A45h
Device ID (DID): Indicates what device number assigned
by Intel.
15:0 RO 8086h
Vendor ID (VID): 16-bit field which indicates Intel is the
vendor, assigned by the PCI SIG.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
10 R/W 0b
Interrupt Disable (ID): Disables this device from
generating PCI line based interrupts. This bit does not have
any effect on MSI operation.
9 RO 0b
Fast Back-to-Back Enable (FBE): Not implemented,
hardwired to 0.
8 RO 0b SERR# Enable (SEE): Not implemented, hardwired to 0.
7 RO 0b
Wait Cycle Enable (WCC): Not implemented, hardwired
to 0.
6 RO 0b
Parity Error Response Enable (PEE): Not implemented,
hardwired to 0.
5 RO 0b
VGA Palette Snooping Enable (VGA): Not implemented,
hardwired to 0
4 RO 0b
3 RO 0b
Special Cycle Enable (SCE): Not implemented, hardwired
to 0.
424 Datasheet
Access: RO
Size: 16 bits
2 R/W 0b
Bus Master Enable (BME): Controls the Intel MEI host
controller's ability to act as a system memory master for
data transfers. When this bit is cleared, Intel MEI bus
master activity stops and any active DMA engines return to
an idle condition. This bit is made visible to firmware
through the H_PCI_CSR register, and changes to this bit
may be configured by the H_PCI_CSR register to generate
an Intel Management Engine MSI.
When this bit is 0, Intel MEI is blocked from generating MSI
to the host CPU.
NOTE: This bit does not block Intel MEI accesses to Intel
Management Engine -UMA, i.e., writes or reads to the host
and Intel Management Engine circular buffers through the
read window and write window registers still cause Intel
Management Engine backbone transactions to Intel
Management Engine -UMA.
1 R/W 0b
Memory Space Enable (MSE): Controls access to the
Intel MEI host controllers memory mapped register space.
0 RO 0b
I/O Space Enable (IOSE): Not implemented, hardwired
to 0.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): Not implemented,
hardwired to 0.
14 RO 0b
Signaled System Error (SSE): Not implemented,
hardwired to 0.
13 RO 0b
Received Master-Abort (RMA): Not implemented,
hardwired to 0.
12 RO 0b
Received Target Abort (RTA): Not implemented,
hardwired to 0.
11 RO 0b
Signaled Target-Abort (STA): Not implemented,
hardwired to 0.
10:9 RO 00b DEVSEL# Timing (DEVT): These bits are hardwired to 00.
8 RO 0b
Master Data Parity Error Detected (DPD): Not
7 RO 0b
Fast Back-to-Back Capable (FBC): Not implemented,
hardwired to 0.
6 RO 0b Reserved
Datasheet 425
23.2.4 RID - Revision Identificatin
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
Access: RO
Size: 24 bits
5 RO 0b
66-MHz Capable (C66): Not implemented, hardwired
to 0.
4 RO 1b
Capabilities List (CL): Indicates the presence of a
capabilities list, hardwired to 1.
3 RO 0b
Interrupt Status (IS): Indicates the interrupt status of
the device (1 = asserted).
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
7:0 RO 00h
Revision ID (RID): Indicates stepping of the Intel MEI
host controller.
Bit Access
Default
Value
Description
23:16 RO 07h
Base Class Code (BCC): Indicates the base class code of
15:8 RO 80h
Sub Class Code (SCC): Indicates the sub class code of the
Intel MEI host controller device.
7:0 RO 00h
Programming Interface (PI): Indicates the programming
interface of the Intel MEI host controller device.
426 Datasheet
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
Address Offset: Eh
Default Value: 80h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS): Not implemented, hardwired
to 0.
Bit Access
Default
Value
Description
7:0 RO 00h
Master Latency Timer (MLT): Not implemented,
hardwired to 0.
Bit Access
Default
Value
Description
7 RO 1b
Multi-Function Device (MFD): Indicates the Intel MEI
host controller is part of a multi-function device.
6:0 RO 0000000b
Header Layout (HL): Indicates that the Intel MEI host
controller uses a target device layout.
Datasheet 427
23.2.9 BIST - Built-In Self Test
Address Offset: Fh
Default Value: 00h
Access: RO
Size: 8 bits
23.2.10 HECI_MBAR - Intel MEI MMIO Base Address
Access: RO; R/W
Size: 64 bits
This register allocates space for the Intel MEI memory mapped registers.
Bit Access
Default
Value
Description
7 RO 0b BIST Capable (BC): Not implemented, hardwired to 0.
Bit Access
Default
Value
Description
63:4 R/W
00000000
0000000h
Base Address (BA): Base address of register memory
space.
3 RO 0b
prefetchable
2:1 RO 10b
anywhere in 32-bit address space
0 RO 0b
Resource Type Indicator (RTE): Indicates a request for
register memory space.
428 Datasheet
Access: R/WO
Size: 32 bits
Address Offset: 34h
Default Value: 50h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
31:16 R/WO 0000h
Subsystem ID (SSID): Indicates the sub-system identifier.
This field should be programmed by BIOS during boot-up. Once
written, this register becomes Read Only. This field can only be
cleared by PLTRST#.
15:0 R/WO 0000h
Subsystem Vendor ID (SSVID): Indicates the sub-system
vendor identifier. This field should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only.
This field can only be cleared by PLTRST#.
Bit Access
Default
Value
Description
7:0 RO 50h
Capability Pointer (CP): Indicates the first capability pointer
offset. It points to the PCI power management capability offset.
Datasheet 429
Access: RO; R/W
Size: 16 bits
23.2.14 HFS - Host Firmware Status
Access: RO
Size: 32 bits
Bit Access
Default
Value
Description
15:8 RO 04h
Interrupt Pin (IPIN): This indicates the interrupt pin the
Intel MEI host controller uses. The value of 01h selects
INTA# interrupt pin.
NOTE: As Intel MEI is an internal device in the (G)MCH, the
INTA# pin is implemented as an INTA# message to the ICH.
7:0 R/W 00h
Interrupt Line (ILINE): Software written value to indicate
which interrupt line (vector) the interrupt is connected to.
No hardware action is taken on this register.
Bit Access
Default
Value
Description
31:0 RO 00000000h
Firmware Status Host Access (FS_HA): Indicates
current status of the firmware for the Intel MEI controller.
This field is the host's read only access to the FS field in the
Intel Management Engine Firmware Status AUX register.
430 Datasheet
23.2.15 PID - PCI Power Management capability ID
Access: RO
Size: 16 bits
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 8Ch
Next Capability (NEXT): Indicates the location of the next
capability item in the list. This is the Message Signaled
Interrupts capability.
7:0 RO 01h
management.
Bit Access
Default
Value
Description
15:11 RO 11001b
PME_Support (PSUP): Indicates the states that can generate
PME#.
Intel MEI can assert PME# from any D-state except D1 or D2
which are not supported by Intel MEI.
10 RO 0b
D2_Support (D2S): The D2 state is not supported for the Intel
MEI host controller.
9 RO 0b
D1_Support (D1S): The D1 state is not supported for the Intel
MEI host controller.
8:6 RO 000b
Aux_Current (AUXC): Reports the maximum Suspend well
current required when in the D3COLD state.
5 RO 0b
Device Specific Initialization (DSI): Indicates whether
4 RO 0b Reserved
3 RO 0b
PME Clock (PMEC): Indicates that PCI clock is not required to
generate PME#.
2:0 RO 011b
Version (VS): Indicates support for Revision 1.2 of the PCI
Power Management Specification.
Datasheet 431
23.2.17 PMCS - PCI Power Management Control an Status
Access: RO; R/W; R/WC
Size: 16 bits
Bit Access
Default
Value
Description
15 R/WC 0b
PME Status (PMES): The PME Status bit in Intel MEI space
can be set to 1 by ARC FW performing a write into AUX
register to set PMES.
This bit is cleared by host CPU writing a 1 to it.
ARC cannot clear this bit.
Host CPU writes with value 0 have no effect on this bit.
8 R/W 0b
PME Enable (PMEE): This bit is read/write, under control
of host SW. It does not directly have an effect on PME
events. However, this bit is shadowed into AUX space so
ARC FW can monitor it. The ARC FW is responsible for
ensuring that FW does not cause the PME-S bit to transition
to 1 while the PMEE bit is 0, indicating that host SW had
disabled PME.
3 RO 1b Reserved
2 RO 0b Reserved
1:0 R/W 00b
Power State (PS): This field is used both to determine the
current power state of the Intel MEI host controller and to
set a new power state. The values are:
00 - D0 state
11 - D3HOT state
The D1 and D2 states are not supported for this Intel MEI
host controller. When in the D3HOT state, the HBAs
configuration space is available, but the register memory
spaces are not. Additionally, interrupts are blocked. This
field is visible to firmware through the H_PCI_CSR register,
and changes to this field may be configured by the
H_PCI_CSR register to generate an Intel Management
Engine MSI.
432 Datasheet
23.2.18 MID - Message Signaled Interrupt Identifiers
Access: RO
Size: 16 bits
Access: RO; R/W
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 00h
Next Pointer (NEXT): Indicates the next item in the list.
This can be other capability pointers (such as PCI-X or PCI
Express) or it can be the last item in the list.
7:0 RO 05h Capability ID (CID): Capabilities ID indicates MSI.
Bit Access
Default
Value
Description
7 RO 1b
64-Bit Address Capable (C64): Specifies whether
capable of generating 64-bit messages.
6:4 RO 000b
Multiple Message Enable (MME): Not implemented,
hardwired to 0.
3:1 RO 000b
Multiple Message Capable (MMC): Not implemented,
hardwired to 0.
0 R/W 0b
MSI Enable (MSIE): If set, MSI is enabled and
traditional interrupt pins are not used to generate
interrupts.
Datasheet 433
Access: RO; R/W
Size: 32 bits
Access: R/W
Size: 16 bits
Bit Access
Default
Value
Description
31:2 R/W 00000000h
message address, always DW aligned.
MSI is not translated in Intel VT-d, therefore, in order to
avoid sending bad MSI with address bit [31:20] will be
masked internally to generate 12'hFEE regardless of
content in register. Register attribute remains as R/W.
1:0 RO 00b Reserved
Bit Access
Default
Value
Description
15:0 R/W 0000h
Data (Data): This 16-bit field is programmed by system
software if MSI is enabled. Its content is driven onto the
FSB during the data phase of the MSI memory write
transaction.
434 Datasheet
23.2.22 HIDM - Intel MEI Interrupt Delivery Mode
Address Offset: A0h
Default Value: 00h
Access: R/W
Size: 8 bits
This register is used to select interrupt delivery mechanism for Intel MEI to Host CPU
interrupts.
23.3 Intel Management Engine Interface PCI Device
3 Function 2 (AMT IDER)
Bit Access
Default
Value
Description
7:2 RO 0h Reserved
1:0 R/W 00b
Intel MEI Interrupt Delivery Mode (HIDM): These
bits control what type of interrupt the Intel MEI will send
when ARC writes to set the M_IG bit in AUX space. They
are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
(Sheet 1 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Identification ID 0 3 2A468086h RO
Command Register CMD 4 5 0000h RO; R/W
Device Status STS 6 7 00B0h RO
Class Codes CC 9 B 010185h RO
Reserved E F
Primary Command Block IO Bar PCMDBA 10 13 00000001h RO; R/W
Primary Control Block Base
Address
PCTLBA 14 17 00000001h RO; R/W
Secondary Command Block Base
Address
SCMDBA 18 1B 00000001h RO; R/W
Secondary Control Block base
Address
SCTLBA 1C 1F 00000001h RO; R/W
Legacy Bus Master Base Address LBAR 20 23 00000001h RO; R/W
Reserved 24 27
Datasheet 435
23.3.1 ID - Identification
Access: RO
Size: 32 bits
PCI device.
Reserved 30 33
Capabilities Pointer CAP 34 34 C8h RO
Minimum Grant MGNT 3E 3E 00h RO
Maximum Latency MLAT 3F 3F 00h RO
Capability ID
PID C8 C9 D001h RO
Capabilities
PC CA CB 0023h RO
and Status
PMCS CC CF 00000000h RO; R/W/V
Capability ID
MID D0 D1 0005h RO
Message Control
MC D2 D3 0080h RO; R/W
Message Address
MA D4 D7 00000000h RO; R/W
Message Upper Address
MAU D8 DB 00000000h RO; R/W
Message Data
MD DC DD 0000h R/W
(Sheet 2 of 2)
Register Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Bit Access
Default
Value
Description
31:16 RO 2A46h
Device ID (DID): Indicates device number assigned by
Intel.
15:0 RO 8086h
Vendor ID (VID): 16-bit field which indicates the
company vendor as Intel
436 Datasheet
23.3.2 CMD - Command Register
Access: RO; R/W
Size: 16 bits
Reset: Host System reset or D3->D0 transition of function
This register provides basic control over the device's ability to respond to and perform
Host system related accesses.
Bit Access
Default
Value
Description
10 R/W 0b
Interrupt Disable (ID): This disables pin-based INTx#
interrupts. This bit has no effect on MSI operation. When
set, internal INTx# messages will not be generated. When
cleared, internal INTx# messages are generated if there
is an interrupt and MSI is not enabled.
9 RO 0b Fast Back-to-Back Enable (FBE): Reserved
8 RO 0b
SERR# Enable (SEE): The PT function never generates
an SERR#
Reserved
7 RO 0b Wait Cycle Enable (WCC): Reserved
6 RO 0b
Parity Error Response Enable (PEE): No Parity
detection in PT functions.
Reserved
5 RO 0b VGA Palette Snooping Enable (VGA): Reserved
4 RO 0b
Reserved
3 RO 0b Special Cycle Enable (SCE): Reserved
2 R/W 0b
Bus Master Enable (BME): Controls the PT function's
ability to act as a master for data transfers. This bit does
not impact the generation of completions for split
transaction commands.
1 RO 0b
Memory Space Enable (MSE): PT function does not
contain target memory space.
0 R/W 0b
I/O Space enable (IOSE): Controls access to the PT
function's target I/O space
Datasheet 437
Access: RO
Size: 16 bits
This register is used by the function to reflect its PCI status to the host for the
functionality that it implements.
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): No parity error on its
interface
14 RO 0b
Signaled System Error (SSE): The PT function will never
generate an SERR#.
13 RO 0b Received Master-Abort Status (RMA): Reserved
12 RO 0b Received Target-Abort Status (RTA): Reserved
11 RO 0b
Signaled Target-Abort Status (STA): The PT Function
will never generate a target abort.
Reserved
10:9 RO 00b
DEVSEL# Timing Status (DEVT): Controls the device
select time for the PT function's PCI interface
8 RO 0b
Master Data Parity Error Detected) (DPD): PT function
(IDER), as a master, does not detect a parity error. Other PT
function is not a master and hence this bit is reserved also.
7 RO 1b Fast Back-to-Back Capable (RSVD): Reserved
6 RO 0b Reserved
5 RO 1b 66-MHz Capable (RSVD):
4 RO 1b
Capabilities List (CL): Indicates that there is a
capabilities pointer implemented in the device.
3 RO 0b
Interrupt Status (IS): This bit reflects the state of the
interrupt in the function. Setting of the Interrupt Disable bit
to 1 has no affect on this bit. Only when this bit is a 1 and
ID bit is 0 is the INTC interrupt asserted to the Host.
438 Datasheet
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
23.3.5 CC - Class Codes
Access: RO
Size: 24 bits
This register identifies the basic functionality of the device, i.e., IDE mass storage
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
This register defines the system cache line size in dword increments. Mandatory for
master which use the Memory-Write and Invalidate command.
Bit Access
Default
Value
Description
7:0 RO 00h Revision ID (RID)
Bit Access
Default
Value
Description
23:0 RO 010185h Programming Interface BCC SCC (PI BCC SCC)
Bit Access
Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS): All writes to system memory are
Memory Writes.
Datasheet 439
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
Address Offset: Eh
Default Value: < Not Defined >
Access: < Not Defined >
Size: 8 bits
Register is not implemented.
23.3.9 PCMDBA - Primary Command Block IO Bar
Access: RO; R/W
Size: 32 bits
Reset: Host system Reset or D3->D0 transition of the function
This 8-byte I/O space is used in Native Mode for the Primary Controller's Command
Block, i.e., BAR 0.
Bit Access
Default
Value
Description
7:0 RO 00h
Master Latency Timer (MLT): Not implemented since the
function is in MCH
Bit Access
Default
Value
Description
15:3 R/W 0000h
Base Address (BAR): Base Address of the BAR0 I/O space
(eight consecutive I/O locations).
2:1 RO 00b Reserved
0 RO 1b
I/O space.
440 Datasheet
23.3.10 PCTLBA - Primary Control Block Base Address
Access: RO; R/W
Size: 32 bits
Reset: Host system Reset or D3->D0 transition of the function
This 4-byte I/O space is used in Native Mode for the Primary Controller's Control Block,
i.e., BAR 1.
23.3.11 SCMDBA - Secondary Command Block Base Address
Access: RO; R/W
Size: 32 bits
Reset: Host System Reset or D3->D0 transition of the function
This 8-byte I/O space is used in Native Mode for the secondary Controller's Command
Block. Secondary Channel is not implemented and reads return 7F7F7F7F and all writes
are dropped.
Bit Access
Default
Value
Description
15:2 R/W 0000h
Base Address (BAR): Base Address of the BAR1 I/O
space (four consecutive I/O locations).
1 RO 0b Reserved
0 RO 1b
I/O space.
Bit Access
Default
Value
Description
15:3 R/W 0000h
Base Address (BAR): Base Address of the I/O space
2:1 RO 00b Reserved
0 RO 1b
for I/O space.
Datasheet 441
23.3.12 SCTLBA - Secondary Control Block Base Address
Access: RO; R/W
Size: 32 bits
Reset: Host System Reset or D3->D0 transition.
This 4-byte I/O space is used in Native Mode for Secondary Controller's Control block.
Secondary Channel is not implemented and reads return 7F7F7F7F and all writes are
dropped.
23.3.13 LBAR - Legacy Bus Master Base Address
Access: RO; R/W
Size: 32 bits
Reset: Host system Reset or D3->D0 transition
This Bar is used to allocate I/O space for the SFF-8038i mode of operation (a.k.a. Bus
Master IDE).
Bit Access
Default
Value
Description
15:2 R/W 0000h
Base Address (BAR): Base Address of the I/O space (four
consecutive I/O locations).
1 RO 0b Reserved
0 RO 1b
I/O space.
Bit Access
Default
Value
Description
15:4 R/W 000h
Base Address (BA): Base Address of the I/O space (16
consecutive I/O locations).
0 RO 1b
I/O space.
442 Datasheet
Access: R/WO
Size: 32 bits
Reset: Host System Reset.
These registers are used to uniquely identify the add-in card or the subsystem that the
device resides within.
Address Offset: 34h
Default Value: C8h
Access: RO
Size: 8 bits
This register is used to point to a linked list of new capabilities implemented by the
device.
Bit Access
Default
Value
Description
31:16 R/WO 0000h
Subsystem ID (SSID): This is written by BIOS. No
hardware action taken on this value.
15:0 R/WO 8086h
Subsystem Vendor ID (SSVID): This is written by
BIOS. No hardware action taken on this value.
Bit Access
Default
Value
Description
7:0 RO c8h
capability Pointer (CP): Indicates that the first
capability pointer offset is offset c8h (the power
management capability).
Datasheet 443
Access: RO; R/W
Size: 16 bits
Reset: Host System Reset or D3->D0 reset of the function.
See definitions in the registers below.
Default Value: D001h
Access: RO
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 03h
Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4
indicates that this function implements legacy interrupt on
INTA/INTB/INTC/INTD, respectively.
7:0 R/W 00h
Interrupt Line (ILINE): The value written in this register
tells which input of the system interrupt controller, the
device's interrupt pin is connected to. This value is used by
the OS and the device driver, and has no affect on the HW.
Function Value INTx
(2 IDE) 03h INTC
Bit Access
Default
Value
Description
15:8 RO D0h
Next Capability (NEXT): Its value of 0xD0 points to the
MSI capability
7:0 RO 01h
management
444 Datasheet
Access: RO
Size: 16 bits
This register implements the power management capabilities of the function.
Bit Access
Default
Value
Description
15:11 RO 00000b
PME Support (PME): Indicates no PME# in the PT
function.
10 RO 0b D2 Support (D2S): The D2 state is not supported.
8:6 RO 000b
Aux Current (AUXC): PME# from D3 (cold) state is not
supported, therefore this field is 000b.
5 RO 1b
Device Specific Initialization (DSI): Indicates that no
4 RO 0b Reserved
3 RO 0b
2:0 RO 011b
Version (VS): Indicates support for revision 1.2 of the
Datasheet 445
Address Offset: CC-CFh
Access: RO; R/W/V
Size: 32 bits
This register implements the PCI PM Control and Status Register to allow PM state
transitions and Wake up.
Note: The NSR bit of this register. All registers (PCI configuration and Device Specific) marked
with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a 1, the
D3->D0 transition will not reset the registers.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
31:16 RO 0h Reserved (RSVD)
15 RO 0b
PME Status (PMES): This bit is set when a PME event is
to be requested. Not supported
8 RO 0b PME Enable (PMEE): Not Supported
3 RO/V 0b
No Soft Reset (NSR): When set (1), this bit indicates
that devices transitioning from D3hot to D0 because of
the D3hot to the D0 Initialized state, no additional
operating system intervention is required to preserve
Configuration Context beyond writing the PowerState bits.
performing the soft reset. Upon transition from the D3hot
return the device to D0 Initialized.
Value in this bit is reflects chicken bit in Intel Management
Engine -AUX register x13900, bit [7] which is as follows:
When 0: Device performs internal reset
When 1: Device does not perform internal reset
2 RO 0b Reserved
446 Datasheet
23.3.20 MID - Message Signaled Interrupt Capability ID
Access: RO
Size: 16 bits
Message Signaled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a dword memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI-capable device.
1:0 R/W 00b
Power State (PS): This field is used both to determine
the current power state of the PT function and to set a
new power state. The values are:
00 D0 state
11 D3
HOT
state
When in the D3HOT state, the controller's configuration
space is available, but the I/O and memory spaces are
not. Additionally, interrupts are blocked. If software
attempts to write a '10' or '01' to these bits, the write will
be ignored.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
15:8 RO 00h
Next Pointer (NEXT): Value Indicates this is the last
item in the capabilities list.
7:0 RO 05h
Capability ID (CID): Capabilities ID value indicates
device is capable of generating an MSI.
Datasheet 447
Access: RO; R/W
Size: 16 bits
This register provides System Software control over MSI.
Access: RO; R/W
Size: 32 bits
Reset: Host system Reset or D3->D0 transition.
This register specifies the dword aligned address programmed by system software for
sending MSI.
Bit Access
Default
Value
Description
7 RO 1b
64-Bit Address Capable (C64): Capable of generating
64-bit and 32-bit messages.
6:4 R/W 000b
Multiple Message Enable (MME): These bits are R/W
for software compatibility, but only one message is ever
sent by the PT function.
3:1 RO 000b
Multiple Message Capable (MMC): Only one message
is required.
0 R/W 0b
MSI Enable (MSIE): If set MSI is enabled and traditional
Bit Access
Default
Value
Description
31:2 R/W 00000000h
message address, always DWORD-aligned.
1:0 RO 00b Reserved
448 Datasheet
23.3.23 MAU - Message Signaled Interrupt Message Upper Address
Address Offset: D8-DBh
Access: RO; R/W
Size: 32 bits
Upper 32 bits of the message address for the 64-bit address capable device.
Address Offset: DC-DDh
Access: R/W
Size: 16 bits
This 16-bit field is programmed by system software if MSI is enabled.
Bit Access
Default
Value
Description
3:0 R/W 0000b
Address (ADDR): Upper 4 bits of the system specified
message address.
Bit Access
Default
Value
Description
15:0 R/W 0000h
Data (DATA): This content is driven onto the lower word
of the data bus of the MSI memory write transaction
Datasheet 449
23.4 Device 3 Function 3 (AMT SOL Redirection)
Register Name
Register
Symbol
Register
Start
Register
End
Identification ID 0 3 2A478086h RO
Command Register CMD 4 5 0000h RO; R/W
Device Status STS 6 7 00B0h RO
Class Codes CC 9 B 070002h RO
Header Type HTYPE E E < Not Defined > < Not Defined >
Built In Self Test BIST F F < Not Defined > < Not Defined >
KT IO Block Base Address KTIBA 10 13 00000001h RO; R/W
KT Mem Block Base Address KTMBA 14 17 00000000h RO; R/W
Reserved RSVD 18 1B 00000000h RO
Reserved RSVD 1C 1F 00000000h RO
Reserved RSVD 20 23 00000000h RO
Reserved RSVD 24 28 0000000000h < Not Defined >
Reserved 30 33
Capabilities Pointer CAP 34 34 C8h RO
PCI Power Management Capability
ID
PID C8 C9 D001h RO
Capabilities
PC CA CB 0023h RO
and Status
PMCS CC CF 00000000h RO/V; RO; R/W
Capability ID
MID D0 D1 0005h RO
Message Control
MC D2 D3 0080h RO; R/W
Message Address
MA D4 D7 00000000h RO; R/W
Message Upper Address
MAU D8 DB 00000000h RO; R/W
Message Data
MD DC DD 0000h R/W
450 Datasheet
23.4.1 ID - Identification
Access: RO
Size: 32 bits
PCI device.
23.4.2 CMD - Command Register
Access: RO; R/W
Size: 16 bits
Reset: Host System reset or D3->D0 transition.
This register provides basic control over the device's ability to respond to and perform
Host system related accesses.
Bit Access
Default
Value
Description
31:16 RO 2A47h
Device ID (DID): Indicates device number assigned by
Intel.
15:0 RO 8086h
Vendor ID (VID): 16-bit field which indicates the company
vendor as Intel.
(Sheet 1 of 2)
Bit Access
Default
Value
Description
10 R/W 0b
Interrupt Disable (ID): This disables pin-based INTx#
interrupts. This bit has no effect on MSI operation. When
set, internal INTx# messages will not be generated. When
cleared, internal INTx# messages are generated if there is
an interrupt and MSI is not enabled.
9 RO 0b Fast Back-to-Back Enable (FBE): Reserved
8 RO 0b
SERR# Enable (SEE): The PT function never generates an
SERR#.
Reserved
7 RO 0b Wait Cycle Enable (WCC): Reserved
6 RO 0b
Parity Error Response Enable (PEE): No Parity detection
in PT functions.
Reserved
5 RO 0b VGA Palette Snooping Enable (VGA): Reserved
4 RO 0b
Reserved
Datasheet 451
Access: RO
Size: 16 bits
This register is used by the function to reflect its PCI status to the host for the
functionality that it implements.
3 RO 0b Special Cycle enable (SCE): Reserved
2 R/W 0b
Bus Master Enable (BME): Controls the KT function's
ability to act as a master for data transfers. This bit does
not impact the generation of completions for split
transaction commands. For KT, the only bus mastering
activity is MSI generation.
1 R/W 0b
Memory Space Enable (MSE): Controls Access to the PT
function's target memory space.
0 R/W 0b
I/O Space Enable (IOSE): Controls access to the PT
function's target I/O space
(Sheet 2 of 2)
Bit Access
Default
Value
Description
(Sheet 1 of 2)
Bit Access
Default
Value
Description
15 RO 0b
Detected Parity Error (DPE): No parity error on its
interface
14 RO 0b
Signaled System Error (SSE): The PT function will never
generate a SERR#.
13 RO 0b Received Master-Abort Status (RMA): Reserved
12 RO 0b Received Target-Abort Status (RTA): Reserved
11 RO 0b
Signaled Target-Abort Status (STA): The PT Function
will never generate a target abort.
Reserved
10:9 RO 00b
DEVSEL# Timing Status (DEVT): Controls the device
select time for the PT function's PCI interface
8 RO 0b
Master Data Parity Error Detected) (DPD): PT function
(IDER), as a master, does not detect a parity error. Other PT
function is not a master and hence this bit is reserved also.
7 RO 1b Fast Back-to-Back Capable (RSVD): Reserved
6 RO 0b Reserved
5 RO 1b 66-MHz Capable (RSVD)
4 RO 1b
Capabilities List (CL): Indicates that there is a capabilities
pointer implemented in the device.
452 Datasheet
Address Offset: 8h
Default Value: 00h
Access: RO
Size: 8 bits
23.4.5 CC - Class Codes
Access: RO
Size: 24 bits
This register identifies the basic functionality of the device, i.e., Serial Com port.
3 RO 0b
Interrupt Status (IS): This bit reflects the state of the
interrupt in the function. Setting of the Interrupt Disable bit
to 1 has no affect on this bit. Only when this bit is a 1 and
ID bit is 0 is the INTB interrupt asserted to the Host.
(Sheet 2 of 2)
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
7:0 RO 00h Revision ID (RID): Indicates stepping of the silicon.
Bit Access
Default
Value
Description
23:0 RO 070002h Programming Interface BCC SCC (PI BCC SCC)
Datasheet 453
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
This register defines the system cache line size in dword increments. Mandatory for
master which uses the Memory-Write and Invalidate command.
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
23.4.8 KTIBA - KT IO Block Base Address
Access: RO; R/W
Size: 32 bits
Base Address for the 8-byte IO space for KT.
Bit Access
Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS): All writes to system memory
are Memory Writes.
Bit Access
Default
Value
Description
7:0 RO 00h
Master Latency Timer (MLT): Not implemented since the
function is in MCH.
Bit Access
Default
Value
Description
15:3 R/W 0000h
Base Address (BAR): Base Address of the I/O space
2:1 RO 00b Reserved
0 RO 1b
I/O space.
454 Datasheet
23.4.9 KTMBA - KT Mem Block Base Address
Access: RO; R/W
Size: 32 bits
Base Address of Memory Mapped space.
Access: R/WO
Size: 32 bits
Reset: Host system Reset.
These registers are used to uniquely identify the add-in card or the subsystem that the
device resides within.
Bit Access
Default
Value
Description
31:12 R/W 00000h Base Address (BAR): Memory Mapped IO BAR
3 RO 0b
prefetchable
2:1 RO 00b
anywhere in 32-bit address space
0 RO 0b
for register memory space
Bit Access
Default
Value
Description
31:16 R/WO 0000h
Subsystem ID (SSID): This is written by BIOS. No
hardware action taken on this value
15:0 R/WO 8086h
Subsystem Vendor ID (SSVID): This is written by
BIOS. No hardware action taken on this value
Datasheet 455
Address Offset: 34h
Default Value: C8h
Access: RO
Size: 8 bits
This register is used to point to a linked list of new capabilities implemented by the
device.
Access: RO; R/W
Size: 16 bits
Reset: Host System Reset or D3->D0 reset of the function.
See individual registers below.
Bit Access
Default
Value
Description
7:0 RO c8h
Capability Pointer (CP): Indicates that the first capability
pointer offset is offset c8h (the power management
capability).
Bit Access Default Value Description
15:8 RO 02h
Interrupt Pin (IPIN): a value of 0x1/0x2/0x3/0x4
indicates that this function implements legacy interrupt
on INTA/INTB/INTC/INTD, respectively.
7:0 R/W 00h
Interrupt Line (ILINE): The value written in this
register tells which input of the system interrupt
controller the device's interrupt pin is connected to.
This value is used by the OS and the device driver, and
has no affect on the H/W.
Function Value INTx
(3 KT/Serial Port) 02h INTB
456 Datasheet
Default Value: D001h
Access: RO
Size: 16 bits
Access: RO
Size: 16 bits
This register implements the power management capabilities of the function.
Bit Access Default Value Description
15:8 RO D0h
Next Capability (NEXT): Its value of 0xD0 points to
the MSI capability.
7:0 RO 01h
Cap ID (CID): Indicates that this pointer is a PCI
power management.
Bit Access
Default
Value
Description
15:11 RO 00000b
PME Support (PME): Indicates no PME# in the PT
function.
10 RO 0b D2 Support (D2S): The D2 state is not Supported.
8:6 RO 000b
Aux Current (AUXC): PME# from D3 (cold) state is not
supported, therefore this field is 000b.
5 RO 1b
Device Specific Initialization (DSI): Indicates that no
4 RO 0b Reserved
3 RO 0b
2:0 RO 011b
Version (VS): Indicates support for revision 1.2 of the
Datasheet 457
Address Offset: CC-CFh
Access: RO/V; RO; R/W
Size: 32 bits
This register implements the PCI PM Control and Status Register to allow PM state
transitions and Wake up.
Note: The NSR bit of this register. All registers (PCI configuration and device specific) marked
with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a 1, the
D3->D0 transition will not reset the registers.
Bit Access
Default
Value
Description
31:16 RO 0h Reserved (RSVD)
15 RO 0b
PME Status (PMES): This bit is set when a PME event is to
be requested. Not supported.
8 RO 0b PME Enable (PMEE): Not supported.
7:4 RO 0h Reserved
3 RO/V 0b
No Soft Reset (NSR): When set (1), this bit indicates that
devices transitioning from D3hot to D0 because of
the D3hot to the D0 Initialized state, no additional operating
system intervention is required to preserve Configuration
Context beyond writing the PowerState bits.
performing the soft reset. Upon transition from the D3hot to
the D0 state, full re-initialization sequence is needed to
return the device to D0 Initialized.
Value in this bit is reflects chicken bit in Intel Management
Engine -AUX register x13900, bit [6] which is as follows:
When 0: Device performs internal reset
When 1: Device does not perform internal reset.
2 RO 0b Reserved
1:0 R/W 00b
Power State (PS): This field is used both to determine the
current power state of the PT function and to set a new
power state. The values are:
00 D0 state
11 D3
HOT
state
When in the D3HOT state, the controller's configuration
space is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked. If software attempts to
write a '10' or '01' to these bits, the write will be ignored.
458 Datasheet
23.4.16 MID - Message Signaled Interrupt Capability ID
Access: RO
Size: 16 bits
Message Signaled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a dword memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Access: RO; R/W
Size: 16 bits
Reset: Host System Reset or D3->D0 transition
This register provides System Software control over MSI.
Bit Access
Default
Value
Description
15:8 RO 00h
Next Pointer (NEXT): Value indicates this is the last
item in the list.
7:0 RO 05h
capability ID (CID): Value of Capabilities ID indicates
device is capable of generating MSI.
Bit Access
Default
Value
Description
7 RO 1b
64-Bit Address Capable (C64): Capable of generating
64-bit and 32-bit messages.
6:4 R/W 000b
Multiple Message Enable (MME): These bits are R/W
for software compatibility, but only one message is ever
sent by the PT function.
3:1 RO 000b
Multiple Message Capable (MMC): Only one message
is required.
0 R/W 0b
MSI Enable (MSIE): If set MSI is enabled and traditional
Datasheet 459
Access: RO; R/W
Size: 32 bits
This register specifies the dword aligned address programmed by system software for
sending MSI.
23.4.19 MAU - Message Signaled Interrupt Message Upper Address
Address Offset: D8-DBh
Access: RO; R/W
Size: 32 bits
Upper 32 bits of the message address for the 64-bit address capable device.
Bit Access
Default
Value
Description
31:2 R/W 00000000h
message address, always dword-aligned.
1:0 RO 00b Reserved
Bit Access
Default
Value
Description
3:0 R/W 0000b
Address (ADDR): Upper 4 bits of the system specified
message address
460 Datasheet
Address Offset: DC-DDh
Access: R/W
Size: 16 bits
This 16-bit field is programmed by system software if MSI is enabled.

Bit Access
Default
Value
Description
15:0 R/W 0000h
Data (DATA): This MSI data is driven onto the lower word
of the data bus of the MSI memory write transaction.

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