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FSM Design Using VHDL

This document contains lecture slides on finite state machine design using VHDL. It discusses sequential digital logic system design using state diagrams and graphs. It covers synchronous sequential design using state transfer diagrams or algorithmic state machines. The slides provide examples of Mealy and Moore machine descriptions in VHDL, including a 0110 sequence detector example to demonstrate state assignment and coding. The 0110 detector is modeled as both a Mealy and Moore machine in VHDL code.

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0% found this document useful (0 votes)
151 views19 pages

FSM Design Using VHDL

This document contains lecture slides on finite state machine design using VHDL. It discusses sequential digital logic system design using state diagrams and graphs. It covers synchronous sequential design using state transfer diagrams or algorithmic state machines. The slides provide examples of Mealy and Moore machine descriptions in VHDL, including a 0110 sequence detector example to demonstrate state assignment and coding. The 0110 detector is modeled as both a Mealy and Moore machine in VHDL code.

Uploaded by

rajivsharma1610
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Department of Engineering

10/1/2006 ECE 358: Introduction to VHDL Lecture 8-1


Lecture 08
Finite State Machine Design
Using VHDL
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-2
Today
Sequential digital logic system design
state diagram/state graph
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-3
Synchronous sequential
design
Most sequential systems are synchronous; that is
controlled by a clock.
State transfer diagram or Algorithmic state
machines (ASM) are used to design sequential
circuits.
Sequential circuits:
Mealy machine: output =func (current state, inputs)
Moore machine: output=func (current state)
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-4
Synchronous Design Summary
using VHDL
Draw a state graph and state table
Write VHDL code and implement in EDA
software package
Check and simulate your design
Download or fabricate
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-5
State assignment in VHDL
State encoding:
Binary state encoding
One-hot state encoding
Example: four states S0,S1,S2,S3
Binary state encoding: 00,01,10,11
One-hot state encoding: 1000,0100,0010,0001
Binary state encoding: CPLD
One-hot state encoding: FPGA, rich resources in
registers.
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-6
State assignment in VHDL
Binary state encoding
type STATE_TYPE is (S1, S2, S3, S4);
attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "00 01 10 11";
signal CURRENTSTATE, NEXTSTATE: STATE_TYPE;
One-hot state encoding
type STATE_TYPE is (S1, S2, S3, S4);
Attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100
1000";
signal CS, NS: STATE_TYPE;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-7
State machine VHDL code
TWO processes for Mealy Machine:
One process is used to model the state
registers to decide the next state
Second process models to update the next
state and output logic
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-8
State machine VHDL code
Two or Three processes for Moore
machine:
One process is used to model the state
registers to decide the next state
Second process models to update the next
state
Three process models the output logic
OR 2
nd
and 3
rd
combined into one process
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-9
FSM VHDL Design Example
0110 sequence detector,
Mealy machine no pattern
overlapping
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-10
0110 Detector Mealy FSM
No overlapping
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MEALY0110NV is
port (CLK,RST,X : in std_logic;
Z : out std_logic);
end entity MEALY0110NV;
architecture NOOV of MEALY0110NV
is
type STATE_TYPE is
(IDLE,S0,S01,S011);
signal CS,NS: STATE_TYPE;
begin
SEQ: process (CLK,RST) is
begin
if (rising_edge(CLK)) then
if (RST=1 ) then
CS<=IDLE;
else
CS <= NS;
end if;
end if;
end process SEQ;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-11
0110 Detector Mealy FSM
No overlapping
COM: process (CS,X) is
begin
Z<=0;
case CS is
when IDLE =>
if (X = 0') then
NS<=S0;
else
NS<=IDLE;
end if;
when S0 =>
if (X = 0') then
NS<=S0;
else
NS<=S01;
end if;
when S01=>
if (X = 0') then
NS<=S0;
else
NS<=S011;
end if;
when S011 =>
if (X = 0') then
NS<=IDLE;
Z<=1;
else
NS<=IDLE;
end if;
end case;
end process COM;
end architecture NOOV;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-12
0110 Detector Mealy FSM
No overlapping Simulation
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-13
0110 detector Moore Machine
0110 sequence detector, Moore machine no pattern
overlapping
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-14
0110 Detector Moore FSM
No overlapping
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MOORE0110NV is
port (CLK,RST,X : in std_logic;
Z : out std_logic);
end entity MOORE0110NV;
architecture NOOV of MOORE0110NV is
type STATE_TYPE is
(IDLE,S0,S01,S011,S0110);
signal CS,NS: STATE_TYPE;
begin
SEQ: process (CLK) is
begin
if (rising_edge(CLK)) then
if (RST=1 ) then
CS<=IDLE;
else
CS <= NS;
end if;
end if;
end process SEQ;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-15
0110 Detector Moore FSM
No overlapping with two processes
COM: process (CS,X) is
begin
Z<=0;
case CS is
when IDLE =>
if (X = 0') then
NS<=S0;
else
NS<=IDLE;
end if;
when S0 =>
if (X = 0') then
NS<=S0;
else
NS<=S01;
end if;
when S01=>
if (X = 0') then
NS<=S0;
else
NS<=S011;
end if;
when S011 =>
if (X = 0') then
NS<=S0110;
else
NS<=IDLE;
end if;
when S0110=>
Z<=1;
NS<=IDLE;
end case;
end process COM;
end architecture NOOV;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-16
0110 Detector Moore FSM
No overlapping Simulation
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-17
0110 Detector Moore FSM No overlapping
Another VHDL code style (three processes)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MOORE0110NV is
port (CLK,RST,X : in std_logic;
Z : out std_logic);
end entity MOORE0110NV;
architecture NOOV of MOORE0110NV is
type STATE_TYPE is
(IDLE,S0,S01,S011,S0110);
signal CS,NS: STATE_TYPE;
begin
SEQ: process (CLK) is
begin
if (rising_edge(CLK)) then
if (RST=1 ) then
CS<=IDLE;
else
CS <= NS;
end if;
end if;
end process SEQ;
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-18
0110 Detector Moore FSM
No overlapping
COM: process (CS,X) is
begin
case CS is
when IDLE =>
if (X = 0') then
NS<=S0;
else
NS<=IDLE;
end if;
when S0 =>
if (X = 0') then
NS<=S0;
else
NS<=S01;
end if;
when S01=>
if (X = 0') then
NS<=S0;
else
NS<=S011;
end if;
when S011 =>
if (X = 0') then
NS<=S0110;
else
NS<=IDLE;
end if;
when S0110=>
NS<=IDLE;
end case;
end process COM;
No output Z in
the COM
process
Department of Engineering
10/1/2006 ECE 358: Introduction to VHDL Lecture 8-19
0110 Detector Moore FSM
No overlapping
OUTPUTZ: process (CS) is
begin
case CS is
when
IDLE|S0|S01|S011=>
Z<=0;
when S0110=>
Z<=1;
end case;
end process OUTPUTZ;
end architecture NOOV;
Z<=1 when CS=S0110 else
0;
end architecture NOOV;
OR
3
rd
process defines the
output function

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