Scribd
Upload
106 views7 pages

13 Isa Io I-F

This document discusses address decoding and designing an ISA bus interface. It explains that address decoding identifies locations in memory or I/O space. A decoder circuit enables an address line if the address matches. Partial decoding is shown to activate for multiple addresses. A generic ISA bus interface diagram is presented with address decoding, control signals, and a device. Designing an output port is demonstrated connecting an address decoder and I/O device to the ISA bus lines to write to a specific port address.

Uploaded by

Fernando Galaz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
106 views7 pages

13 Isa Io I-F

This document discusses address decoding and designing an ISA bus interface. It explains that address decoding identifies locations in memory or I/O space. A decoder circuit enables an address line if the address matches. Partial decoding is shown to activate for multiple addresses. A generic ISA bus interface diagram is presented with address decoding, control signals, and a device. Designing an output port is demonstrated connecting an address decoder and I/O device to the ISA bus lines to write to a specific port address.

Uploaded by

Fernando Galaz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

EE3803 - Lecture 13

Designing An ISA Bus


IO Interface

EE3803-L13P01

Address Decoding
Address decoding is the way we can locate hardware devices at particular locations in the
address space (memory or port) of a microprocessor. Once again, this looks complicated,
but it really isn't if you take it in bits (pun intended).

Typically, an address decoder is a combinational circuit that enables an address select line
if an appropriate access condition exists.

Suppose we want to decode address FF03h:


A15
A14
A13
A12
A11
A10
A9
A8

= 1 If Addx is FF03h

A7

= 0 Otherwise

A6
A5
A4
A3
A2
A1
A0

EE3803-L13P02

Partial Address Decoding


Suppose I don't have a 16 input and gate. What if I only have a 14 input gate?

Consider what happens if I leave A15 and A14 disconnected:

A13
A12
A11
A10
A9
A8
A7

= 1 If Addx is FF03, BF03h, 7F03h, or 3F03h

A6

= 0 Otherwise

A5
A4
A3
A2
A1
A0

Hmmm. In this case there are four different addresses that will result in generating exactly
the same control signal!!!

Is that a good or a bad thing??

EE3803-L13P03

A Generic ISA-Bus Interface Card Design


The basic block diagram of an ISA-Bus interface includes buffers (to isolate the card from
the ISA Bus), Address and control decoding (to make sure the card responds to the desired
bus condition) and the stuff being controlled (memory or other devices).

Device

High
Address

Address

Decoder

Low Address

Control

IOR-, MEMR-, etc.

CE-

Addx

To/From
RD, WR, etc

Some
Physical
Thing!

Data

D0-D7 (or D0-D15)

Data

EE3803-L13P04

An ISA Bus Output Port


At this point, we know a lot about how the software architecture of the IBM PC works.
We've explored the whole operating system hierarchy and understand how to access
hardware elements.

We've also taken a quick look at the ISA Bus and at the idea of Address Decoding as a
method for locating hardware devices within the memory space of the computer.

Now, let's put it all together by building a (very) simple IO port!

I/O Interface

Address

Control

Address
Decoder

Device
Select

and
Status

Address

80x86

Information

Data
Control

Data

IO
Device

System
Under
Control

EE3803-L13P05

The ISA Bus Interface

Remember, when interfacing to the ISA (or any other) bus, we need to account
for all of the signals that are important for accomplishing our goal.

Let's look at that interface in more detail:

A15 - A1

AEN

Address
Decoder

Device
Select

A0
IORIOW-

IO
Device

D7 - D0

EE3803-L13P06

A Genuine Workable Output Port!


Suppose we want to design a system to write a byte to an Octal Flip-Flop which
drives an LED Display in response to a port write to 0FFFEh.

Address Decoder
A15 - A12

A11 - A8

A7 - A4

A3 - A1
A0

AEN
IOW-

D7 - D0

8-bit
Latch

IO Device

EE3803-L13P07

You might also like