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Instruction Encoding: - Thorne: Chapter 13 2 Appendix V B - Thorne: Chapter 13.2, Appendix V.B

On the Intel 8086, instructions are encoded in 1 to 6 bytes. The number of bytes used depends on the operation, operands, and addressing modes. Common addressing modes include register, immediate, direct, indirect, based, indexed, and base-index modes. Jump instructions modify the instruction pointer register to change the flow of execution. The target of a jump can be specified using absolute, relative, or register/memory indirect addressing.

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86 views10 pages

Instruction Encoding: - Thorne: Chapter 13 2 Appendix V B - Thorne: Chapter 13.2, Appendix V.B

On the Intel 8086, instructions are encoded in 1 to 6 bytes. The number of bytes used depends on the operation, operands, and addressing modes. Common addressing modes include register, immediate, direct, indirect, based, indexed, and base-index modes. Jump instructions modify the instruction pointer register to change the flow of execution. The target of a jump can be specified using absolute, relative, or register/memory indirect addressing.

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Mafuzal Hoque
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© © All Rights Reserved
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Instruction Encoding

Thorne: Chapter 132 AppendixV B Thorne : Chapter 13.2, Appendix V.B


Additional notes in : Instruction Encoding Note g
SYSC3006 1
Instruction Encoding Instruction Encoding
On the Intel 8086, an instruction is a sequenceof 1..6 bytes
A simple (and incomplete) model of an instruction is as follows
::
Opcode Operand Operand Operand Operand Operand
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
Opcode
Destination Operand, if neededSource if needed
Operand Operand Operand Operand Operand
Tells what kind of
i i instruction,
How many bytes
SYSC3006 2
Number of Bytes Depends on Number of Operands Number of Bytes Depends on Number of Operands
NOP
1001 0000
INC BX (Thorne, p 668)
0100 0001
ADD BX, 1(Thorne, p 667)
1000 0011 1100 0011
0000 0001 0000 0000
Immediate value: a word (little endian)
SYSC3006 3
Number of Bytes Depends on Addressing Modes Number of Bytes Depends on Addressing Modes
ADD BX, AX
00000001 11000011
BX | AX
ADD BX, 1
10000001 11000011 00000001
Register Immediate
00000000
ADD BL, 1
00000001
Register
10000000 11000011
Immediate
ADD BX, [1]
00000011 00011110
Direct
00000001 00000000
Direct
Register
Register
ADD BL, [1]
00000001 00000000 00000010 00011110
Direct Register
SYSC3006 4
Review Earlier Slides on Addressing Modes Review Earlier Slides on Addressing Modes
1) Register mode : operand is a register
2) Immediate mode : operandisaconstant 2) Immediate mode : operand is a constant
Constant valueis encoding as part of instruction
value is hard-coded (static)
C t t l i l d di t IR d i f t h Constant value is loaded into IR during fetch
Constant value obtained from IR during execution
3) Direct memory mode : operand is address offset of memory
variable
Constant address offset is encoded as part of instruction
Address offset is hard-coded (static) although contents ( ) g
of address may be dynamic
During execution, the address offset is implicitly
combined with DS
SYSC3006 5
Number of Bytes Depends on Addressing Modes
Indirect Addressing Modes
Number of Bytes Depends on Addressing Modes
Indirect Immediate
Assume : WORD PTR
ADD [BX], 1
10000001 00000111 00000001
Indirect Immediate
Based
00000000
Constant
Immediate
ADD [BX+2], 1
00000010
Based
10000001 01000111
Constant
00000001 00000000
Base-Index
Immediate
ADD [BX+SI], 1
BaseIndex
10000001 00000000 00000001 00000000
ADD [BX+SI+2], 1
00000010 10000001 01000000
Constant
00000001
Immediate
00000000
Base-Index with
SYSC3006 6
00000010 10000001 01000000 00000001 00000000
Review Earlier Slides on Addressing Modes
1) Indirect : Operand is an address offset held in a register
2) Based or Indexed Indirect : Operand is an address offset
heldinaregister andaconstant offset
[BX+2]
[BX]
held in a register and a constant offset
During fetch, constant offset is read in as part of
instruction
During execution CPU usestemporaryregister to During execution, CPU uses temporary register to
calculate BX +constant
It then accesses memory addressed by BX +constant
3) B I d O di dd ff t h ldi t i t
[BX SI]
3) Base-Index : Operand is an address offset held in two register
During execution, CPU calculates sum of 2 registers
It then accesses memory addressed by sum
[BX+SI]
4) Base-Index with Displacement : Like based-indexed mode,
except includes a constant too
During execution, CPU calculates sum of 3 values
[BX+SI+2]
SYSC3006 7
g ,
It then accesses memory addressed by sum
Instruction Encoding : J* Instruction Encoding : J
On all jump instructions, the target must supply a value that
will be used to modify the IP
1 Absolute addressing (Assembly code): Theinstruction 1. Absolute addressing (Assembly code): The instruction
contains a 16-bit constant value to replace the IP
Execution Semantics: IP :=new value
2 R l ti dd i (M hi d ) Th i t ti 2. Relative addressing (Machine code): : The instruction
contains a value to be added to IP (after the fetch!)
Execution Semantics : IP :=IP +value
If the value is positive, the jump is forward
If the value is negative, the jump is negative
3. Register/memory indirect addressing: The instruction g y g
specifies a register or memory location that contains the value
to be used to replace IP
Execution Semantics : IP :=mem[addrs]
SYSC3006 8
[ ]
IP :=register
Specifying Control Flow Targets (Intra-segment)
Question : What addressing modes is used below ?
JMP 1000h
JMP here
SYSC3006 9
JMP target Unconditional JUMP
Control is always transferred to specified (relative) target.
Relative Addressing Example: .LST file fragment Relative Addressing Example: .LST file fragment
address machine instruction ASM instruction
(memory contents)
0034H E9 10 02 J MP here
0037H . .
= JMP 247
Absolute
addressing
Relative
addressing
. . .
0247 here:
start of fetch: IP =0034H IR = ????????
after fetch: IP =0037H IR = E9 10 02
after execute: IP =0247H IR =E91002
(Little endian=0210h)
SYSC3006 10
after execute: IP =0247H IR = E9 10 02

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