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Programmer's Model: Thorne: Chapter 2 (Irvine, Edition IV: Chapter 2)

The document summarizes the programmer's model of a computer system based on the von Neumann architecture. It discusses key aspects like the instruction execution cycle, registers, control unit, system bus, and memory. The instruction execution cycle involves fetching an instruction from memory, decoding it, executing it using the execution unit which may require fetching operands from memory, and storing results back to memory. Memory contains both instructions and data and can be accessed via an address and data bus on the system bus.

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Mafuzal Hoque
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
56 views

Programmer's Model: Thorne: Chapter 2 (Irvine, Edition IV: Chapter 2)

The document summarizes the programmer's model of a computer system based on the von Neumann architecture. It discusses key aspects like the instruction execution cycle, registers, control unit, system bus, and memory. The instruction execution cycle involves fetching an instruction from memory, decoding it, executing it using the execution unit which may require fetching operands from memory, and storing results back to memory. Memory contains both instructions and data and can be accessed via an address and data bus on the system bus.

Uploaded by

Mafuzal Hoque
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Programmers Model

Thorne : Chapter 2
(Irvine, Edition IV : Chapter 2)
SYSC3006 1
Programmers Model
All modern microprocessors are based on the van Neumann model
System Bus (address, data, & control)
Bus
Interface
Unit (BIU)
Execution
Unit (EU)
Memory
Program
Storage
Output
Units
Input
Units
Central
Processing Unit
Unit (EU)
Storage
Data
Storage
SYSC3006 2
(CPU)
StoredProgramConcept >InstructionExecutionCycle Stored Program Concept -> Instruction Execution Cycle
Before Van Neumann : Program was stored externally, on tape or cards
A fundamental consequence of the Van NeumannModel:
Memorycontainsbothinstructionsanddata Memory contains both instructions and data
Instructions ARE data : Can be manipulated
Instructions must be read, executed; called the instruction execution cycle
Requires a unit to control the instruction execution cycle : CPU =control equ es u oco o e s uc o e ecu o cyc e: C U co o
unit
Briefly (for now) the instruction execution cycle is a sequence of operations
required to execute a single instruction. The control unit under a clock
commands commands
Control Unit (CU or BIU) to fetchthe next instruction from memory
BIU to decodethe fetched instruction
The execution unit (EU or ALU) to executethe instruction ( )
Execution of the instruction may require further fetches of data from
memory and/or storage of data to memory (ie. involvement of the
BIU)
What isreq iredtos pport theinstr ctione ec tionc cle?
SYSC3006 3
What is required to support the instruction execution cycle ?
Registers
Thorne: Registersareplaceswheredatacanbeprocessedparticularly Thorne: Registers are places where data can be processed particularly
quickly
Registers are internal storage places (ie. memory) connected to the
internal components of the CPU (eg. BIU, ALU)
Control Unit (CU)
Bus
Interface
System Bus (address, data, & control)
internal components of the CPU (eg. BIU, ALU)
Address
Fetch
Interface
Unit
(BIU)
PC
Register
Segment
Fetch
Decoder
Execution Unit (EU)
Memory
Program
Storage
Output
Units
Input
Units
Instruction Register (IR)
Status
Register
Segment
Registers
l i i ( )
Data
Storage
Working
Registers
Register
Arithmetic
Logic Unit
(ALU)
Clock
Unit
SYSC3006 4
Central Processing Unit (CPU)
*PC: Program Counter
(Instruction Pointer: IP)
Instructions
All activity within the microprocessor is initiated by the microprocessor
Includes all transfers to/from memory/input/output.
In the 8086 family: All activity must go through the microprocessors. y y g g p
Cant go from input directly to memory.
Cant go directly from one memory location to another memory location.
Two major categories of instructions j g
Register-memory instructions : Transfer information between
programmers registers and memory
Reads so that data can be used as inputs to the ALU in subsequent
instruction(s)
Writes so that results of ALU can be stored persistently
Register-to-Register
Typically to fetch two operands from the programmers registers to
be used as the two ALU inputs and storing the ALU output back in
one of the registers
Eg addition boolean
SYSC3006 5
Eg. addition, boolean
Defines what the computer can do
InstructionExecutionCycle InDetail Instruction Execution Cycle In Detail
For each machine instruction, the control unit uses the program
t (PC) ( l k i t ti i t IP) di t ti counter (PC) (also known as instruction pointer: IP) and instruction
queue (6 bytes) to do the following
Short name : Fetch-Execute Cycle
1 Fetch Phase : Readmemoryat theaddressgiveninthePC tocopythe 1. Fetch Phase : Read memory at the address given in the PC to copy the
instruction into the internal instruction queue.
2. Decode Phase: Determine the type of instruction and the
number/location of 0..2 operands. p
3. Execute Phase :
1. Fetch Operands : [If needed] Read memory to copy the data into an input
working register
2. Instruction Execution : Signal the ALU to perform the operation and
sends its data to its output working register and set the status flags
3. Store output operand: [If needed] Write to memory to store the data from
theALU output register.
SYSC3006 6
the ALU output register.
InstructionExecutionCycle Instruction Execution Cycle
The instruction execution cycle is the heartbeat of the computer.
It is all synchronized on the CPU clock.
Fetch Decode Fetch Execute Store Fetch Decode Fetch Execute Store
Execution Cycle
Instr Instr Operand Instr Result Instr Instr Operand Instr Result

Instruction Execution Phase


SYSC3006 7
What is the execution time of an instruction ?
Memory Memory
Central storage for both program instruction and data
Memory is persistent and changes only as a result of a write
Memory consists of a sequence of directly addressable byte locations.
Althoughmodernprocessorshavewider memory(16bit, 32bit, Although modern processors have wider memory (16 bit, 32 bit,
64 bit!), all memory is organized as 8-bit cells(bytes)
10101010b
0 (00b)
8 bit ll
1010 1010b
0000 1111b
0011 0011b
1100 1100b
( )
1 (01b)
2 (10b)
3 (11b)
8-bit cells
With 2-bit addresses
When we talk about wider memories, were talking about how they are
accessed by the processor.
SYSC3006 8
Memory
A memory location has two components: an addressand its contents.
Contents
Address Bus
Data Bus
Notation: m[addr] represents the contents of a memory location,
F l [20h] f t th t t f l ti t For example, m[20h] refers to the contentsof memory location at
20h.
Two
parameters
Two memory-related behaviours :
write(value, addr) and value =read( addr )
SYSC3006 9
Two buses
Memory and the System Bus
A memory location has two components: an addressand its contents.
You can read or write a memory location
System Bus (address, data, & control)
Consequently, the system bus has threecomponents .
Address bus : Contains the address of the memory location
Databus: Containsthedatabeingreador written Data bus : Contains the data being read or written
Control bus : Contains signals that control the flow of the data (read vs
write)
Data
Address
Control
SYSC3006 10
Control
What is a Memory Address ? (A programmers view) y ( p g )
11h
Address
00b
2-bit
Address Bus
CPU
Memory
Binary Address Contents
A0 11h
22h
33h
44h
Decoder
00b
01b
10b
11b
A1
In general computing, the memory cell (byte) is the smallest
addressablememory unit add essabe e o yu
You cannot address individual bits in a cell
What is the Address Space ?
For anaddressbuswithagivenwidth, what istherangeor For an address bus with a given width, what is the range or
capacity of this memory ? (A simple binary computation !)
2-bit address : 2
2
different addresses
20-bit addresses: 2
20
different addresses =1 Meg address space
SYSC3006 11
g p
(Hint : 1K =2
10
=1024)
What about the Data bus ?
2-bit
Memory
Binary Address Contents
11h
22h
33h
Address
Decoder
00b
01b
10b
Address Bus
CPU
y
A0
A1
(=0001 0001b)
(=0010 0010b)
(=0011 0011b)
44h 11b
8-bit Data
Bus D0
D7
(=0100 0100b)
Memory is viewed logically as an array of contiguous bytes but many
processors are 16-bit (and above), meaning
They have a 16-bit data bus y
They can read/write 16-bit contents all in oneread/write cycle.
A Memory Problem: How can binary values wider than 8-bits be
stored using 8-bit memory cells ?
SYSC3006 12
Solution : Use more than one consecutive memory locations
Endian Memory Schemes
New Problem: For 16-bit values, it will be stored in two memory
consecutive
b l b
16-bit
, y
locations but which location should hold which byte ?
consecutive
memory cells
msbyte lsbyte
16 bit
value
?
memory
t t dd
Little Endian (Intel)
lsbyte
msbyte lsbyte
contents address
msbyte
X
X +1
16-bit value
low @ low
high @ high
msbyte
memory
contents address
X
16-bit value
low@high
Big Endian (Motorola)
SYSC3006 13
msbyte
msbyte lsbyte
lsbyte
X
X +1
low @ high
high @ low
Little Endian Exercise
What is the byte at address 1201 ?
What is the word at address 1201 ?
What is the double-word at address 1201 ?
Add D
5Eh
1200h
Address Data
Memory
Address
73h
A2h
95h
0Ah
1201h
1202h
1203h
1204h
1202
1010 0010b
0Ah
1204h
Data is 8 bits
SYSC3006 14

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