Lecture 7

Input, Output and Traps

I/O basics

Keyboard input

Monitor output

Interrupt driven I/O

DMA

High-level I/O with Traps

CS Realities

Computers do more than just execute your program

I/O

Interrupts
I/O asics

!e"initions

Input

trans"er data "rom the outside #orld to the computer$

%ey&oard, mouse, scanner, &ar'code reader, etc(

Output

trans"er data "rom the computer to the outside$

monitor, printer, L)! display, etc(

*eripheral$ any I/O de+ice, including dis%s(

LC', supports only a %ey&oard and a monitor

!e+ice Registers

I/O Inter"ace

Through a set o" !e+ice Registers$

Status register -de+ice is &usy/idle/error.

!ata register -data to &e mo+ed to/"rom de+ice.

The de+ice registers ha+e to &e read/#ritten &y the C*/(

LC',

0!R$ %ey&oard data register

0SR$ %ey&oard status register

!!R$ display data register

!SR$ display status register

KBSR[15] - keyboard ready (new character
available)
KBDR[7:] - character ty!ed ("S#$$)
DSR[15] - %onitor ready
DDR[7:] - character to be di&!layed ("S#$$)
'#-(
KBSR
KBDR
DSR
DDR
1ddressing !e+ice Registers

Special I/O Instructions

Read or #rite to de+ice registers using speciali2ed I/O

instructions(

3emory 3apped I/O

/se existing data mo+ement instructions -Load 4 Store.(

3ap each de+ice register to a memory address -"ixed.(

C*/ communicates #ith the de+ice registers as i" they #ere

memory locations(

5rame &u""ers$ Large areas o" 3emory 3apped I/O "or +ideo
display

LC',

/ses memory mapped I/O$

)*+ KBSR Keyboard Stat,& Re-i&ter
)*+. KBDR Keyboard Data Re-i&ter
/*+0 DSR Di&!lay Stat,& Re-i&ter
/*+1 DDR Di&!lay Data Re-i&ter
/***+ 2#R 2achine #ontrol Re-i&ter
3emory'mapped Input
3emory'mapped Output
Synchroni2ing C*/ and I/O

*ro&lem

Speed mismatch &et#een C*/ and I/O

C*/ runs at up to 6 782, #hile all I/O is much slo#er

)xample$ 0ey&oard input is &oth slo# and irregular

9e need a protocol to %eep C*/ 4 0! synchroni2ed

T#o common approaches

*olling -handsha%e synchroni2ation.

C*/ chec%s the 0! Ready status &it

I" set, C*/ reads the data register and resets the Ready &it

Repeat

3a%es C*/'I/O interaction seem to &e synchronous

Interrupt'dri+en I/O

1n external de+ice is allo#ed to interrupt the C*/ and

demand attention

The C*/ attends to the de+ice in an orderly "ashion -more

later.
*olling +/s Interrupts -9ho:s dri+ing;.

*olling$ C*/ in charge

C*/ chec%s the ready &it o" status register -as per program
instructions.(

I" -0SR<=>? @@ =. then load 0!R<7$A? to a register(

I" the I/O de+ice is +ery slo#, C*/ is %ept &usy #aiting(

Interrupt$ peripheral in charge

)+ent triggered ' #hen the I/O de+ice is ready, it sets a

"lag called an interrupt

9hen an interrupt is set, the C*/ is "orced to an interrupt

service routine -ISR. #hich ser+ices the interrupting
de+ice

There can &e di""erent priority le+els o" interrupt

Speciali2ed instructions can mas an interrupt le+el

*olling 1lgorithm

Input -%ey&oard.

The C*/ loops chec%ing the Ready &it

9hen &it is set, a character is a+aila&le

C*/ loads the character #aiting in the %ey&oard data register

Output -monitor.

C*/ loops chec%ing the Ready &it

9hen &it is set, display is ready "or next character

C*/ stores a character in display data register

*olling details

0ey&oard

9hen %ey is struc%

1SCII code o" character is #ritten to 0!R<7$A?

-least signi"icant &yte o" data register.(

0SR<=>? -Ready it. is set to =(

0ey&oard is loc%ed until C*/ reads 0!R(

The C*/ sees Ready it, reads 0!R, and clears

the Ready it, unloc%ing the %ey&oard(

3onitor

9hen C*/ is ready to output a character

C*/ chec%s !SR<=>? -Ready it. until it is set to =

C*/ #rites character to !!R<7$A?

3onitor sets !SR<=>? to A #hile it is &usy

displaying
the character, then sets it &ac% to = to indicate readiness
"or next character(
Simple *olling Routines
START LDI R1, A ;Loop if Ready not set
BRzp START
LDI R0, B ;If set, load char to R0
BR N!T"TASK
A #$ILL %$00 ;Address of KBSR
B #$ILL %$0& ;Address of KBDR
Inp't a character fro( )ey*oard
START LDI R1, A ;Loop if Ready not set
BRzp START
STI R0, B ;If set, send char to DDR
BR N!T"TASK
A #$ILL %$0+ ;Address of DSR
B #$ILL %$0, ;Address of DDR
-'tp't a character to the (onitor
0ey&oard )cho$ com&ine the a&o+e
START LDI R1,KBSR ;Loop if KB not ready
BRzp START
LDI R0,KBDR ;.et character
/0- LDI R1,DSR ;Loop if (onitor not ready
BRzp /0-
STI R0,DDR ;Send character
BR N!T"TASK
KBSR #$ILL %$00 ;Address of KBSR
KBDR #$ILL %$0& ;Address of KBDR
DSR #$ILL %$0+ ;Address of DSR
DDR #$ILL %$0, ;Address of DDR
)xample$ *rint a string
LA R1, STR ;Load address of strin1
L--2 LDR R0, R1, 30 ;1et ne%t char to R0
BRz D-N ;strin1 ends 4ith 0
L2& LDI R5, DSR ;Loop 'ntil 6-N is ready
BRzp L2&
STI R0, DDR ;7rite ne%t character
ADD R1, R1, 31 ; Set address to ne%t char
BR L--2
STR #STRIN.8 9/har Strin19
D-N 0ALT
There:s got to &e a &etter #ayB

Later, #e #ill ta%e a closer loo% at interrupts that allo#

the computer to do other things #hile #aiting on I/O(
*ri+ileged Instructions

There are se+eral instructions that are &est executed &y a

supervisor program -OS. rather than a user program$

IO instructions

Loading o" memory'mapped registers

Resetting the cloc%

8alt
i(e( instructions #here one program can a""ect the &eha+ior o"
another(

The C*/ can &e designed to en"orce t#o modes o" operation$

/ser 3ode

*ri+ileged 3ode -a%a( super+isor, %ernel, monitor mode.

Only the super+isor program -OS. can execute pri+ileged

instructions(
TR1* Instructions

TR1*s insulate critical tas%s "rom the user

#ith or #ithout pri+ilege en"orcement

The TR1* mechanism$

1 set o" trap ser+ice routines or TSRs -part o" the C*/ OS.

9e ha+e already seen the &asic I/O SRs

1 ta&le o" the starting addresses o" these ser+ice routines

Located in a prede"ined &loc% o" memory C

C called the Trap Dector Ta&le or System Control loc%

In the LC',$ "rom xAAAA to xAA55 -only > currently in use.

The TR1* instruction

#hich loads the starting address o" the TSR into the *C

Return lin%

"rom the end o" the TSR &ac% to the original program(
LC', TR1* Routines

7)TC -TR1* xEA.

Read a single character "rom 0!(

9rite 1SCII code to RA<7$A?, clear

RA<=>$F?(

O/T -TR1* xE=.

9rite RA<7$A? to the monitor(

*/TS -TR1* xEE.

9rite a string to monitor -address o"

"irst character o" string is in RA.(

IG -TR1* xE,.

*rint a prompt to the monitor and read

a single character "rom 0!(

9rite 1SCII code to RA<7$A?, clear

RA<=>$F?, echo character to the monitor(

81LT -TR1* xE>.

*rint message to monitor 4 halt

execution(

*/TS* -TR1* xE6.

*rint pac%ed string to monitor -address

in RA.
3ra! vector table
TR1* Instructions

TR1*s insulate critical tas%s "rom the user

#ith or #ithout pri+ilege en"orcement

The TR1* mechanism$

1 set o" trap ser+ice routines or TSRs -part o" the C*/ OS.

9e ha+e already seen the &asic I/O SRs

1 ta&le o" the starting addresses o" these ser+ice routines

Located in a pre'de"ined &loc% o" memory C

C called the Trap Dector Ta&le or System Control loc%

In the LC',$ "rom xAAAA to xAA55 -only > currently in use.

The TR1* instruction

#hich loads the starting address o" the TSR into the *C

Return lin%

"rom the end o" the TSR &ac% to the original program(
TR1* )xample

Trap Dector Ta&le

Or System Control Loc%

In LC',

F &its speci"y one o" E>H

locations -xAAAA to xAA55.

The location contains the

address o" the TR1* ser+ice
routine(

TR1* 4 Interrupts

Similar mechanisms

1 TR1* is an
instruction -e+ent
internal to a
program.(

1n interrupt is
external to a
program -"rom an
I/O de+ice.

oth in+o%e a
super+isor ser+ice
routine(
Character Output TSR -O/T.
1 45R$6 /0( 7 Sy&te% call &tartin- addre&&
. S3 R18 SaveR1 7 R1 will be ,&ed 9or !ollin-
(
0 7 :rite the character
5 3ry:rite 'D$ R18 DSR 7 6et &tat,&
1 BR;! 3ry:rite 7 bit 15 < 1 <= di&!lay ready
7 :rite$t S3$ R8 DDR 7 :rite character in R
>
? 7 Ret,rn 9ro% 3R"@
" Ret,rn 'D R18 SaveR1 7 Re&tore re-i&ter&
B R+3 7 Ret,rn (act,ally A2@ R7)
# DSR 4*$'' )*+0 7 di&!lay &tat,& re-i&ter
D DDR 4*$'' )*+1 7 di&!lay data re-i&ter
+ SaveR1 4B'K: 1
* 4+BD
"'S5
1 45R$6 ).1
. 4*$'' )0(
81LT TSR

Clears the R/G latch 3CR<=>?$

1 45R$6 /*D7 7 Sy&te% call &tartin- addre&&
. S3 R8 SaveR 7 Save& re-i&ter& a99ected
( S3 R18 SaveR1 7 by ro,tine
0 S3 R78 SaveR7 7
5
1 7 @rint %e&&a-e that %achine i& haltin-
7 'D R8 "S#$$Bew'ine
> 3R"@ ).1 7 Set c,r&or to new line
? '+" R8 2e&&a-e 7 6et &tart o9 %e&&a-e
" 3R"@ ).. 7 and write it to %onitor
B 'D R8 "S#$$Bew'ine
# 3R"@ ).1
D
+ 7 #lear 2#R[15] to &to! the clock
* 'D$ R18 2#R 7 'oad 2# re-i&ter to R1
1 'D R8 2"SK 7 2"SK < )7*** (i4e4 bit 15 < )
11 "BDR8 R18 R 7 #lear bit 15 o9 co!y o9 2#R
1. S3$ R8 2#R 7 and load it back to 2#R
81LT TSR - cont(.
1( 7 Ret,rn 9ro% the C"'3 ro,tine
10 7 (how can thi& ever ha!!en8 i9 the clock i& &to!!ed on line 1.DD)
15 7
11 'D R78 SaveR7 7 Re&tore& re-i&ter&
17 'D R18 SaveR1 7 be9ore ret,rnin-
1> 'D R8 SaveR
1? R+3 7 A2@ R7
1"
1B 7 con&tant&
1# "S#$$Bew'ine 4*$'' )"
1D SaveR 4B'K: 1
1+ SaveR1 4B'K: 1
1* SaveR7 4B'K: 1
. 2e&&a-e 4S3R$B6E FCaltin- the %achineG
.1 2#R 4*$'' )***+
.. 2"SK 4*$'' )7***
.( 4+BD
3emory'mapped I/O re+isited
Interrupt'dri+en I/O

Iust one de+ice$

CPU
Memory
I/O
IRQ
IACK

9hen IRJ goes acti+e, jump to a special memory location$

the I!", or interrupt service routine# 5or no#, let:s say it
exists at address x=AAA(

1cti+ate I1C0 to tell the de+ice that the interrupt is &eing

ser+iced, and it can stop acti+ating the IRJ line(
7enerating the Interrupt

/sing the Status Register

The peripheral sets a Ready &it in SR<=>? -as #ith polling.

The C*/ sets an Interrupt )na&le &it in SR<=6?

These t#o &its are anded to set the Interrupt(

In this #ay, the C*/ has the "inal say in #ho gets to interrupt itB
*rocessing an interrupt$ one
de+ice

!e+ice generates an IRJ

C*/ signals I1C0 K LO0, I:m on it(M

S#itch to !upervisor Mode

C*/ sa+es its current state

$hat and how%

1ddress o" the ISR is loaded into the *C

&'(((

Continue K process the interrupt

9hen "inished, return to running program

How%
Super+isor 3ode

it => o" the *SR @ *ri+ileged -super+isor.

mode
*ri+ *riority G N *
=> =A K F E = A

Only the Operating System can access de+ice

addresses
$hy%
Interrupts and program state

9e need to sa+e the *C, the *SR, and all Registers

9e could reOuire that ISRs sa+e all rele+ant registers

-callee sa+e.

The callee #ould 1L91PS ha+e to sa+e the contents o" the
*C and *SR

In most computers these +alues -and possi&ly all register

contents. are stored on a stac%

Remem&er, there might &e nested interrupts, so simply

sa+ing them to a register or reser+ed memory location
might not #or%(
The Super+isor Stac%

The LC-3 has two stacks

The /ser stac%

/sed &y the programmer "or su&routine calls and other stac%
"unctions

The Super+isor stac%

/sed &y programs in super+isor mode -interrupt processing.

)ach stac% is in separate region o" memory

The stac% pointer "or the current stac% is al#ays RH(

I" the current program is in pri+ileged mode, RH points to

the Super+isor stac%, other#ise it points to the user stac%(

T#o special purpose registers, Sa+ed(SS* and Sa+ed(/S*,

are used to store the pointer currently not in use, so the
t#o stac%s can share push/pop su&routines #ithout
inter"ering #ith each other(
Sa+ing State

9hen the C*/ recei+es an IGT signal C

If the system was previously in User mode, the /ser

stac% pointer is sa+ed 4 the Super+isor stac% pointer is loaded

Sa+ed(/S* Q@ -RH.

RH Q@ -Sa+ed(SS*.

*C and *SR are pushed onto the Super+isor Stac%

Set the system to Super+isor mode

*SR<=>? Q@ A

Iump to the interrupt ser+ice routine

*rocessing an interrupt$ details

!e+ice generates in IRJ

C*/ signals I1C0 K LO0, I:m on it(M

C*/ sa+es its current state

)* and )!" are saved on the !upervisor !tac

S#itch to !upervisor Mode

*hange the ! bit in the )!" to (#

1ddress o" the ISR is loaded into the *C

+or now we assume ,ust one I!" - &'(((

Continue K process the interrupt

9hen "inished, return to running program

)op the )* and )!" .rom the !upervisor !tac

3ore than one de+ice

9ho sent the interrupt;

One #ay is to ha+e a uni"ied ISR that chec%s the status

&its o" e+ery de+ice in the system

This is a hy&rid method &et#een interrupt'dri+en I/O and

polling

ReOuires e+ery ne# de+ice to modi"y the ISR

The ISR #ill &e large and complex

CPU
Memory
I/O 1
IRQ
I/O 2 I/O 3 I/O 4
Dectored Interrupts

I" #e ha+e multiple de+ices, #e need a +ery large ISR

that %no#s ho# to deal #ith all o" themB

/sing vectored interrupts, #e can ha+e a di""erent ISR "or

each de+ice(

)ach I/O de+ice has a special register #here it %eeps a

special num&er called the interrupt vector#

The +ector tells the C*/ #here to loo% "or the ISR(
1 +ectored'interrupt de+ice
x8002
x8000
x8004
Input register
Output register
Device Controer
!t"tus register
x8006
Interrupt #ector
Register
67

When I trigger an interrupt, look up address number 67 in the

vector table, and jump to that address.
Initial state o" the ISR

Dectored interrupts

1long #ith the IGT signal, the I/O de+ice transmits an F'&it
+ector -IGTD.(

I" the interrupt is accepted, IGTD is expanded to a =H'&it

address$

The Interrupt Dector Ta&le resides in locations xA=AA to xA=55 and

holds the starting addresses o" the +arious Interrupt Ser+ice
Routines( -similar to the Trap Dector Ta&le and the Trap Ser+ice
Routines.

IGTD is an index into the Interrupt Dector Ta&le, i(e( the address o"
the rele+ant ISR is - xA=AA R Next-IGTD. .

The address o" the ISR is loaded into the *C

The *SR is set as "ollo#s$

*SR<=>? Q@ = -Super+isor mode.

*SR<E$A? Q@ AAA -no condition codes set.

Go# #e #ait #hile the interrupt is processed

Interrupt seOuence$ S= de+ice

!e+ice generates an IRJ

C*/ s#itches to SS* i" necessary -hard#are.

Current *C and *SR are sa+ed to the super+isor stac%

-hard#are.

S#itch to super+isor mode -S @ AT hard#are.

C*/ sends I1C0 , #hich is daisy chained to de+ice

-hard#are.

!e+ice sends its +ector num&er -hard#are.

Dector is loo%ed up in the interrupt +ector ta&le, and

address o" the ISR is loaded into the *C -hard#are.

ISR sa+es any registers that it #ill use -so"t#are.

ISR runs, then restores register +alues -so"t#are.

ISR executes RTI instruction, #hich restores *SR and *C

-so"t#are.

/ote that this restores previous supervisor/user mode

3ultiple de+ices$ priority

$hat happens i. another interrupt occurs while the

system is processing an interrupt%

*an devices be 0starved1 in this system%

*riority

)ach tas% has an assigned priority le+el

LC', has le+els *LA -lo#est. to *L7 -highest.(

I" a higher priority tas% reOuests access,

then a lo#er priority tas% #ill &e suspended(

Li%e#ise, each de+ice has an assigned priority

The highest priority interrupt is passed on to the C*/

only
i" it has higher priority than the currently executing tas%(

I" an IGT is present at the start o" the instruction

cycle,
then an extra step is inserted$

The C*/ sa+es its state in"ormation so that it can later

return to the current tas%(

The *C is loaded #ith the starting address o" the

Interrupt Ser+ice Routine

The 5)TC8 phase o" the cycle continues as normal(

*riority o" the current program

Remem&er those extra &its in the *SR;

*ri+ *riority G N *
=> =A K F E = A
!e+ice *riority
Returning "rom the Interrupt

The last instruction o" an ISR is RTI -ReTurn "rom Interrupt.

Return "rom Interrupt -opcode =AAA.

*ops *SR and *C "rom the Super+isor stac%

Restores the condition codes "rom *SR

I" necessary -i(e( i" the current pri+ilege mode is /ser.

restores the user stac% pointer to RH "rom Sa+ed(/S*

)ssentially this restores the state o" our program to

exactly the state it had prior to the interrupt

Continues running the program as i" nothing had happenedB

8o# does this ena&le multiprogramming en+ironments;

The entire interrupt seOuence

!e+ice generates an IRJ at a speci"ic *L

IF reOuesting *L S current process priority$

C*/ s#itches to SS* i" necessary -hard#are.

Current *C and *SR are sa+ed to the super+isor stac%

-hard#are.

S#itch to super+isor mode -S @ AT hard#are.

Set process priority to reOuested interrupt *L

C*/ sends I1C0 , #hich is daisy chained to de+ice

-hard#are.

!e+ice sends its +ector num&er -hard#are.

Dector is loo%ed up in the interrupt +ector ta&le, and

address o" the ISR is loaded into the *C -hard#are.

ISR sa+es any registers that it #ill use -so"t#are.

ISR runs, then restores register +alues -so"t#are.

ISR executes RTI instruction, #hich restores *SR and *C

-so"t#are.

/ote that this restores previous supervisor/user mode and

process priority
)xecution "lo# "or a nested
interrupt
Super+isor Stac% 4 *C during IGT
Interrupts$ Got just "or I/O

Interrupts are also used "or$

)rrors -di+ide &y 2ero, etc(.

TR1*s

Operating system e+ents -Ouanta "or multitas%ing,

etc(.

/ser generated e+ents -Ctrl'C, Ctrl'N, Ctrl'1lt'!el,

etc(.

Cand more(