2.

Analog layout design

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
Well structures
p substrate
n substrate
p- or n- substrate
p- substrate
n-well process
p-well process
Twin-well process
(The impurity concentration is
optimized.)
Triple-well process
(The wells can be electrically
isolated each other.)
p-well
n-well
p-well n-well
p-well n-well
n-well
2
Deep n-well (Triple-well process)
Triple well process Twin-well process
deep n-well
n-well
retrograde p-well
active
(MOSFET)
active
(MOSFET)
n-well
deep n-well
p-substrate
n-well
n-well
p
FOX FOX
p-substrate
n-well
p
FOX
FOX
active active
3
Shallow trench isolation (STI)
FOX: Field Oxide (Thickness = 100nm)
GOX: Gate Oxide (Thickness = several nm)
FOX FOX FOX
Active Active Field Field Field
GOX GOX
Si
SiO
2
MOSFET isolation isolation isolation MOSFET
VDD cannot invert the MOS interface.
4
Layout and cross section (Twin
well)
poly (G)
S D
contact
Contact
n-active
n-well
Wn
L
n
contact
p-substrate
n+ n+
Field Oxide
G
D
S B
p+
D
FOX
p-active
p-ch MOSFET
poly (G)
S D
n-active p-active
B
n-well
p+ p+
G
D
S B
n+
D
FOX FOX
L
p
B
Wp
n-ch MOSFET
5
Layout and cross section (Triple well)
poly (G)
S D
contact
Contact
n-active
n-well
Wn
L
n
contact
p-substrate
n+ n+
Field Oxide
G
D
S B
p+
D
FOX
p-active
poly (G)
S D
n-active p-active
B
n-well
p+ p+
G
D
S B
n+
D
FOX FOX
L
p
B
Wp
deep n-well
p-ch MOSFET n-ch MOSFET
6
Layers
Layer numbers are assigned to Well,
Active, Poly, Contact, Metal, Via, Silicide
Protect, and Dummy, respectively.
Some layer is automatically generated
from the pattern on the drawn layer.
ex. FOX and GOX is generated from the
pattern on the active layer.
poly
metal-1
contact
n-active (n+)
n-well
p-active (p+)
via-1
metal-2
Legend of layers
poly
p-sub
n+ p+
p+
n-well
contact layer
metal-1layer
via layer
metal-2 layer
Layout
Cross section
poly layer
p-active layer
n-active layer
n-well layer
FOX
7
Design Rules
Semiconductor foundry allows the designers to design only the layout
pattern on the top view.
The thickness of layers are fixed by the semiconductor foundry.
The designers have to design the layout according to design rules which
is fixed for each technology. The purpose of design rule is as follows.
Warranty of dimensional precision in micro fabrication
Warranty of precision on electrical characteristics
Prevention of latch-up
(NOTE)
triggered by parasitic bipolar-transistors
Design rule violation is automatically detected and reported in DRC
(Design Rule Check).
A semiconductor company accepts only the design that is passed the
specified design rules.
NOTE: Latch-up
The inadvertent creation of a low-impedance path between the power supply rails
of a CMOS circuit, triggering a parasitic pnpn or npnp structure.
8
Example of design rules (1)
2
2
2
1
1
p-active
2
2
poly-1
2
2
2
1
1
2
2
Metal-1
Via-1
contact
poly rule
min. width = 2
min. spacing 2
active (p+, n+) rule
min. width = 2
min. spacing to well = 2 (inside)
min. spacing to well = 1 (outside)
min. spacing to poly = 1
metal-1 rule
min. width = 2
min. spacing = 2
min. extension beyond contact = 1
min. extension beyond via-1 = 1
n-well
9
Geometry Rules
Example of design rules (2)
10
Minimum Density Rules Antenna Rules
(Process-Induced Damage Rules)
Fine featured processes utilize
CMP (Chemical-Mechanical
Polishing) to achieve planarity.
Effective CMP requires that the
variations in feature density on
a layer be restricted.
The "Antenna Rules" deal with process
induced gate oxide damage caused when
exposed poly-silicon and metal structures,
connected to a thin oxide transistor, collect
charge from the processing environment (e.g.,
reactive ion etch) and develop potentials
sufficiently large to cause Fowler Nordheim
current to flow through the thin oxide. The
rules require that the area of the polysilicon
and metal over field oxide divided by the area
of the transistor gate (thin oxide area) must be
less than Np (where Np is a limit that depends
on the process and on design targets).
S
G
S
F
(poly)
S
F
(M1)

Verifications of the layout design

DRC (Design Rule Check)
Detection of the design rule violation
ERC (Electrical Rule Check)
Detection of the open/short error
LVS (Layout VS Schematic)
Equivalence checking between layout and
schematic
The layout design checker has a batch processing mode and
interactive mode.
11
Influence on circuit performance of
the layout
Frequency response in high-frequency region
The parasitic resistance and the parasitic capacitance raise an
unintended pole and zero.
The long interconnect acts as a parasitic inductor or LC resonator.
Precision of the circuit operation
Common centroid layout of MOSFET, C, and R can improve the
production tolerance and mismatch.
Symmetric layout of interconnect can improves the production
tolerance and skew of the digital signal (delay) and analog signal
(phase lag).
Noise and jitter characteristics
The parasitic resistance, especially poly-Si, act as a thermal noise
source.
The parallel placement of interconnect raise a crosstalk of signals.
12
(1) Layout of the MOSFET
13
Layout sample of MOSFET
poly
metal-1
contact
n-active (n+)
n-well
p-active (p+)
via-1
metal-2
n-ch
p-ch
D
G
S
B
D
G
S
B
14
D
G
S
Parasitic of MOSFET
Long W: large time constant of gate poly-Si
Long W: large thermal noise of gate poly-Si
Long LD, LS: large parasitic capacitance and resistance of drain/source area
Few number of contact: Shift or fluctuation of substrate potential
L
W

R R
G

D
L W
j
C
Long W
LD
L
C
gs
WL
Parasitic
Gate resistance
(R

: sheet
resistance)
Drain junction
capacitance
Gate-Source capacitance
How can you design the MOSFET with larger W?
LS
B
S
L W
j
C
D
G
S
B
15
Fingered MOSFET
W/4
m
g
R
1
L
W

MOFET should be
sectioned to reduce
the gate resistance.
D
S
Abutment
High-performance MOSFET array
gs
ds
m
dV
dI
y g
21
g
m
: trans-conductance
This condition is
often met in the case
of W/L < 20.
W/L < 10 is
recommended.
Multiply = 4 (W/4 4)
Finger
B
G
16
Reduction of the drain junction
capacitance (single MOSFET)
D j DB
WL C C
D j DB
L
W
C C
2

L
D
W
D
S
G
D
S
S
L
D
W/2
C
j
= Capacitance of drain bottom pn junction per area (F/m
2
)
>
Abutment
17
Reduction of the drain junction
capacitance (series MOSFET)
min G j p
WSL C C
D j p
WL C C 2
D/S
D
S
W
C
j
= Capacitance of drain bottom pn junction per area (F/m
2
)
SL
Gmin
= minimum gate spacing
D
S
S
L
D
W
L
D
SL
Gmin
D
>
Abutment
18
Dummy gate
B
Dummy gate Dummy gate
The dummy pattern may be formed to reduce the production tolerance.
S
D
G
19
Interdigitated body contact
The body/well contact may be added to immobilize the
substrate/well potential in the very large MOSFET.
B
S
G
D
20
Layout of logic gate
High area utilization
Constant height of all cell
Horizontal runs of metal are used to
supply power (Rail), and vertical runs
of metal (or poly) are used to input
and to output the signals.
poly-1
n+ Metal-1
Contact
p+ Metal-2
Via-1
IN1
IN2 OUT
n-well
VDD
VSS
Outline box of the cell
2NAND
21
Matching layout
Matching layout is used to enhances the relative
precision of device pair (e.g. a differential pair, a
current mirror). (around 1%)
Use of The repeat of warp of the fundamental unit
The devices of the different shape and direction match very
poorly.
Use of the dummy pattern
Use of the common centroid pattern
Trimming is necessary if you expect more precise
matching.(less than 0.1%)
22
Distribution of GOX thickness
Fluctuation of V
th
and I
ds
several %
n+ n+
G
D S
Distribution of GOX thickness
n+ n+
G
D S
FOX FOX
Flux of O
2
Temperature and flow
distribution in the oxidation
furnace
GOX GOX
23
Common centroid layout
The fluctuation of the device characteristics may be
canceled using the common centroid.
1. The centroid of the matched devices should coincident.
2. The array should be symmetric around both the x and y-axis.
3. Each matched device should consist of an equal number of segments
oriented in either direction.
A B
A B
A B
A B
A B
A B
A B
A B A
B
B A B
A B A
4 segments
8 segments
16 segments
A B A B
4 segments
A
B
B
A
24
Segmentation and Placement for
common centroid layout
W/2
W
MOSFET A
MOSFET B
G
A
G
A
G
B
G
B
Dummy Dummy
Dummy Dummy
Distribution of device parameter
Matched
devices
D D
D D
S
S
25
Layout sample of a differential pair
G
1
G
2
G
2
S
12
S
12
D
2
D
2
D
1
Dummy Dummy
VSS VSS
G
1
G
2
D
1
D
2
S
12
VSS
poly-1
n+
Metal-1
Contact
p+
Metal-2
Via-1
26
(2) Layout of the passive devices
27
Example of the characteristics of
the passive device
Component Values Mismatch Temp.
Coefficient
Volt.
Coefficient
MOS Cap. 2.2 2.7
fF/m
2
0.05% 50 ppm/ 50 ppm/V
Poly2/Poly1
Cap.
0.8 1.0 fF/
m
2
0.05% 50 ppm/ 50 ppm/V
p+ Resister 80 150 / 0.4% 1500 ppm/ 200 ppm/V
p+ diff. Resistor 50 80 / 0.4% 1500 ppm/ 200 ppm/V
Poly Resistor 20 40 / 0.4% 1500 ppm/ 100 ppm/V
N-well Resister 1 k 2k / 1% 8000 ppm/ 10k ppm/V
The mismatch error on a chip is very small.
28
Structure of MIM capacitor
Poly Capacitor (Before 0.25m CMOS process)
MIM Capacitor (After 0.18m CMOS process)
Poly Capacitor
MIM Capacitor
P-substrate
N-well
N+
VDD
(Shield)
FOX(SiO
2

P-substrate
N-well
N+
VDD
(Shield)
FOX(SiO
2

Poly-1
Poly-2
Capacitor Metal
Metal-x
Metal-x+1
29
Layout sample of a MIM capacitor
Metal-4
Capacitor Metal (CM)
Metal-5
MIM Capacitor with the dummy CM
Metal-4
CM
Metal-5
VIA4
Dummy CM
Device model with parasitic

Dummy
(The dummy metal is automatically inserted, if the dummy is not
specify. The dummy metal may work as a parasitic capacitance.)
C
p
C
MIM
30
Structure of spiral inductor
Cross section
M1 VSS
(Shield)
M4
Top
FOX(SiO
2
)
Substrate
VIA4
Top metal or dedicated layer for
inductor is used.
The inductor is dissipative in the
chip area.
C
P
R
S
C
F
C
F
L
Device model with the parasitic
Top metal
Top Metal
Metal-1
Slit (prevent the
induction current)
Metal-4
31
Structure of the resistance
M1
M1
M1
FOX
N+
P+
N-well N-well
P-substrate P-substrate
P-substrate
N+
VDD
(Shield)
p+ resistor
poly resistor
n-well resistor
Active Active Active
N-well
VDD
(Shield)
N+
FOX FOX
Poly
Protect
Silicide
32
Layout sample of a poly resistor
Resistance Sheet R
W
L
R R
S
S
:

(recommended L/W > 5)

L
poly
Metal-1
Protect (non-silicide area)
W
p-select, n-select or high-resistance
Device model with the parasitic
33
Common centroid layout of a
resistor pair
R2
p+ diffusion Metal-1
R
R2
R
Dummy
Dummy
34
(3) Shielding and guard ring
35
Type of noise
Inherent noise
Noise resulting from the discrete and random movement of charge
in a device
Thermal noise, Flicker noise, shot noise
The noise floor depends on the circuit design quality
Quantization noise
Noise resulting from the finite digital word size
The SNR (signal-to-noise ratio) depends on the accuracy of ADC
and DAC.
Coupled noise (Crosstalk)
Noise resulting from the signals adjacent circuits deeding into each
other
The noise immunity depends on a layout.
36
Capacitive coupling Parasitic capacitance
Inductive coupling Parasitic inductance
Substrate current Parasitic resistance
Type of coupled noise
Circuit model
Electromagnetic model
37
Capacitive coupling
Vdig
Vsig
Vanalog
Cc
Cs
Rout
dig
sig
out c
V
V
R C j
SNR

1
Analog signal
Analog circuit
Analog circuit
Digital signal
38
Shielding of interconnects
GND
3W
W
Digital line
Analog line
Shielding plate
analog VSS
p-substrate
Signal
Digital circuit Analog circuit
Shielding line
p-substrate
39
Shielding of substrate
FOX
FOX
Cross section
p-substrate
Shield
n+ n+
n-well
Shield
Analog signal Capacitor
VDD VDD
Digital signal
Noise
(charge and discharge)
40
Guard ring
analog VSS
p-substrate
Analog circuit
p-guard ring
digital VSS
Digital circuit
(noise source)
n-guard ring
(termination of
electric field)
digital VDD
(absorption of
minority carrier)
41
Inductive coupling
The induction noise is in
proportion to the loop area S
of the signal and power line.
GND
Analog circuit
Digital signal current
I
1
(t)
Magnetic flux
t
I
1
(t)
I
2
(t)
I
2
(t)
S
Current
42
Translational symmetric layout
(In-phase circuit)
VDD VSS
Analog circuit
magnetic flux
The translational symmetry reduces
induced current.
VDD VSS
The mirror symmetry intensifies
the induced current.

magnetic flux
Analog circuit
43
Pin assignment
Digital Circuit
Analog Circuit
VDD
VSS
VDD
VSS
V
out
V
in
Adjacent placement
Adjacent placement
The analog input should be arranged in a perpendicular
direction on digital output and the power supply pin.
Increase the distance
44
Bypass capacitors on VDD, VSS
lines
VDD
p-substrateVSS
The noise in the VDD, VSS line is
bypassed through the bypass capacitors.
Small MOS capacitors
under the power line.
45
(4) ESD (Electrostatic Discharge)
Protection
46
Input Pad with ESD protection
Cross section Schematic
Input
Pad
CMOS
Circuit
VDD
VSS
p-substrate
FOX
FOX
n-well
p+ n+
Input Pad VDD VSS
NOTE: If the inductive load is used the output, the amplitude of the output
signal is larger than power supply voltage. In this case, the ESD protection
diode must be connected tandemly.
The ESD protection is required to prevent the damage of the GOX of
a MOSFET from the static charge buildup.
47
poly-1
metal-1
contact
n-active (n+)
n-well
p-active (p+)
via-1
metal-2
Layer
Pad
Input
VSS
VDD
Layout sample of pad ESD protection
48